Coreless closed-loop current sensing package structure and current sensing method

Abstract

This invention provides a coreless closed-loop current detection package structure and a current detection method. The coreless closed-loop current detection package structure includes: a primary frame, a carrier board, a feedback coil, and a detection chip for dynamically detecting the current in the primary frame; a main Hall sensor disposed inside the U-shaped structure of the primary frame for dynamically monitoring the magnetic field between the primary frame and the feedback coil; and a secondary Hall sensor disposed outside the U-shaped structure of the primary frame at a certain horizontal distance from the main Hall sensor for dynamically monitoring the magnetic field between the primary frame and the feedback coil and eliminating errors. The technical problem this invention aims to solve is how to reduce the size of the current detection module and improve the stability and anti-external magnetic interference capability of the Hall sensor, thereby providing a coreless closed-loop current detection package structure and a current detection method.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a coreless closed-loop current detection packaging structure and a current detection method. Background Technology

[0002] In existing technologies, closed-loop current detectors typically consist of a primary circuit, a magnetic ring (core), a Hall sensor, a feedback coil, and an amplifier. These closed-loop current detection modules suffer from drawbacks such as large size, poor stability, and weak resistance to external magnetic interference. Therefore, reducing the size of Hall sensors, improving their stability, and lowering costs have become pressing issues in the field of current detection. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to reduce the size of the current detection module and improve the stability and anti-external magnetic interference capability of the Hall sensor, and to provide a coreless closed-loop current detection packaging structure and current detection method.

[0004] This invention provides a coreless closed-loop current detection packaging structure, comprising: a primary frame, the primary frame including a U-shaped structure, through which current generates a magnetic field; a carrier plate, disposed on the surface of the primary frame, for isolating the primary frame and a feedback coil; a feedback coil, the feedback coil being a coreless coil, disposed above the carrier plate, for generating a magnetic field opposite to that of the primary frame; a detection chip, disposed between the primary frame and the feedback coil, for dynamically detecting the current in the primary frame by controlling the current of the feedback coil to generate an induced magnetic field that balances the magnetic field of the primary frame; a main Hall sensor, disposed inside the U-shaped structure of the primary frame, for dynamically monitoring the magnetic field between the primary frame and the feedback coil; and a secondary Hall sensor, disposed outside the U-shaped structure of the primary frame at a certain horizontal distance from the main Hall sensor, for dynamically monitoring the magnetic field between the primary frame and the feedback coil and eliminating errors.

[0005] Optionally, both the main Hall sensor and the secondary Hall sensor may be one of two types: an antimony Hall sensor or a gallium arsenide Hall sensor.

[0006] Optionally, the main Hall sensor is located at the center of the feedback coil; the secondary Hall sensor is located at the position covered by the feedback coil.

[0007] Optionally, the main Hall sensor is located at the center of the feedback coil; the secondary Hall sensor is located outside the feedback coil at a certain distance from the center of the feedback coil.

[0008] Optionally, the main Hall sensor and the secondary Hall sensor are positioned and fixed above or below the carrier plate.

[0009] Optionally, the distance from the center of the main Hall sensor to the inner edge of the original side frame U-shaped structure is 0-1mm; the distance from the center of the secondary Hall sensor to the outer edge of the original side frame U-shaped structure is 0-0.5mm.

[0010] Optionally, the circuit connection relationship between the main Hall sensor, the secondary Hall sensor, and the detection chip includes: the main Hall sensor includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the secondary Hall sensor includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the first input terminal and the third input terminal, the second input terminal and the fourth input terminal are respectively connected in parallel to the detection chip; the first output terminal and the third output terminal, the second output terminal and the fourth output terminal are respectively connected in series to the detection chip.

[0011] Optionally, the coreless closed-loop current detection module structure further includes a secondary side frame, which is electrically connected to the detection chip and the feedback coil, and is disposed below the carrier board.

[0012] Optionally, the circuit connection relationship between the main Hall sensor, the secondary Hall sensor, and the detection chip includes: the main Hall sensor includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the secondary Hall sensor includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the first input terminal and the third input terminal, the second input terminal and the fourth input terminal, the first output terminal and the third output terminal, and the second output terminal and the fourth output terminal are respectively connected in parallel to the detection chip.

[0013] This invention also provides a current detection method, wherein any of the above-mentioned coreless closed-loop current detection packaging structures is characterized by comprising: obtaining the output voltage value V of the main Hall sensor using the coreless closed-loop current detection packaging structure. 主OUT and the output voltage value V of the secondary Hall sensor 副OUT Calculate the differential voltage, V 差分OUT =V 主OUT -V 副OUT =k*(B 主磁 -(-B 副磁 ), where k is the Hall linear coefficient, B 主磁 The magnetic field strength in the sensing direction of the main Hall sensor, B 副磁 The magnetic field strength is in the sensitive direction of the secondary Hall sensor.

[0014] Optionally, the main Hall sensor and the secondary Hall sensor have opposite induced magnetic field directions and opposite output voltages.

[0015] The present invention also provides a current detection method, which adopts a coreless closed-loop current detection package structure with opposite polarities of the main Hall sensor and the secondary Hall sensor, comprising: obtaining the output voltage values ​​of the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal respectively using the coreless closed-loop current detection package structure; summing the output voltage values ​​of the first output terminal and the third output terminal, and the second output terminal and the third output terminal respectively, and taking the highest value as the output voltage value.

[0016] This invention provides a coreless closed-loop current detection packaging structure and current detection method, which reduces the size of the current detection module and improves the detection accuracy and reliability of the Hall sensor. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the specific embodiments of the invention, the drawings used in the specific embodiments of the invention will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a coreless closed-loop current detection packaging structure provided in an embodiment of the present invention;

[0019] Figure 2 This is a cross-sectional schematic diagram of a coreless closed-loop current detection packaging structure provided in an embodiment of the present invention;

[0020] Figure 3 This is a partial circuit diagram provided in one embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram showing the position of the Hall sensor of the present invention;

[0022] Figure 5 This is a cross-sectional schematic diagram of a coreless closed-loop current detection packaging structure provided in an embodiment of the present invention;

[0023] Figure 6 This is a partial circuit diagram provided for another embodiment of the present invention. Detailed Implementation

[0024] The coreless closed-loop current detection packaging structure and current detection method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0025] The technical problem to be solved by the present invention is how to reduce the size of the current detection module and improve the detection accuracy and reliability of the Hall sensor, and to provide a coreless closed-loop current detection packaging structure and current detection method.

[0026] Figure 1This is a schematic diagram of a coreless closed-loop current detection package structure according to an embodiment of the present invention. The dashed line indicates the location of the feedback coil 104. To clearly show the coreless closed-loop current detection package structure, the feedback coil 104 is rendered with a perspective effect, solely for the purpose of demonstrating the internal structure.

[0027] refer to Figure 1 The schematic diagram shown illustrates a coreless closed-loop current detection package structure. This coreless closed-loop current detection package structure includes: a primary frame 101, which includes a U-shaped structure 102; a carrier plate 103 disposed on the surface of the primary frame 101 to isolate the primary frame 101 from the feedback coil 104; a feedback coil 104, a coreless coil disposed above the carrier plate 103, to generate a magnetic field opposite to that of the primary frame 101; and a detection chip (not shown) disposed between the primary frame 101 and the feedback coil 104. An induced magnetic field is generated by regulating the current of the feedback coil 104 to balance the magnetic field of the primary side frame 101, thereby dynamically detecting the current in the primary side frame 101. A main Hall sensor 106 is disposed inside the U-shaped structure 102 of the primary side frame 101 and is used to dynamically monitor the magnetic field between the primary side frame 101 and the feedback coil 104. A secondary Hall sensor 107 is disposed outside the U-shaped structure 102 of the primary side frame, at a certain horizontal distance from the main Hall sensor 106, and is used to dynamically monitor the magnetic field between the primary side frame 101 and the feedback coil 104 and eliminate errors.

[0028] The coreless closed-loop current detection module structure also includes a secondary side frame 108, which is electrically connected to the detection chip and the feedback coil 104. The secondary side frame 108 is disposed below the carrier plate 103. Furthermore, a coil positioning structure (not shown) is also included above the carrier plate 103 for fixing the feedback coil 104.

[0029] Figure 2 This is a cross-sectional schematic diagram of a coreless closed-loop current sensing package structure according to an embodiment of the present invention. For further explanation of the coreless closed-loop current sensing package structure, please refer to... Figure 2 As shown.

[0030] In this embodiment, the main Hall sensor 106 is located at the center of the feedback coil 104; the secondary Hall sensor 107 is located at the position covered by the feedback coil 104. The position indicated by the dashed line OO' is the central axis of the feedback coil 104, that is, the main Hall sensor 106 is also located on the dashed line OO'.

[0031] Furthermore, a pad 109 is included below the main Hall sensor 106. The pad 109 raises the height of the main Hall sensor 106 to be closer to the center of the feedback coil 104, so as to reduce the error of the main Hall sensor 106.

[0032] To improve the accuracy of Hall sensor measurements, it should be placed where the current density is highest and the magnetic field is strongest. Therefore, the sensitive surface of the main Hall sensor 106 should be located inside the hole of the feedback coil 104, that is, above the lower end face of the feedback coil 104; if the sensitive surface of the main Hall sensor 106 should be located below the lower end face of the feedback coil 104, the distance from the lower end face of the feedback coil 104 should not exceed one Hall device height value.

[0033] In other embodiments of the present invention, the main Hall sensor is disposed at the center of the feedback coil; the secondary Hall sensor is disposed outside the feedback coil at a certain distance from the center of the feedback coil.

[0034] Furthermore, in this embodiment, the distance from the center of the main Hall sensor 106 to the inner edge of the original side frame U-shaped structure 102 is 0-1mm; the distance from the center of the secondary Hall sensor 107 to the outer edge of the original side frame U-shaped structure 102 is 0-0.5mm.

[0035] In this embodiment, the thickness of the carrier plate 103 is 0.03mm-0.25mm.

[0036] In this embodiment, the main Hall sensor 106 and the secondary Hall sensor 107 are disposed and fixed above the carrier plate 103; in other embodiments of the present invention, the main Hall sensor 106 and the secondary Hall sensor 107 may also be disposed and fixed below the carrier plate 103.

[0037] Furthermore, both the main Hall sensor 106 and the secondary Hall sensor 107 employ one of the following: an antimony Hall sensor or a gallium arsenide Hall sensor.

[0038] Figure 3 This is a partial circuit diagram provided for an embodiment of the present invention.

[0039] To illustrate the circuit connection relationship between the main Hall sensor, the secondary Hall sensor, and the detection chip, please refer to... Figure 3 As shown, it includes: a main Hall sensor including a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a secondary Hall sensor including a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the first input terminal and the third input terminal, the second input terminal and the fourth input terminal are respectively connected in parallel to the detection chip; the first output terminal and the third output terminal, the second output terminal and the fourth output terminal are respectively connected in series to the detection chip.

[0040] The chip supplies power to the main Hall sensor through the first and second input terminals, and to the secondary Hall sensor through the third and fourth input terminals. The power supply can be provided internally by the chip (direct chip power supply) or externally by other components (external direct power supply).

[0041] In this embodiment, terminal 1 of the main Hall sensor serves as the first input terminal, terminal 2 as the second input terminal, terminal 3 as the first output terminal, and terminal 4 as the second output terminal; terminal 1 of the secondary Hall sensor serves as the third input terminal, terminal 2 as the fourth input terminal, terminal 3 as the third output terminal, and terminal 4 as the fourth output terminal.

[0042] In this embodiment, terminals 1 and 3 of the main Hall sensor and the secondary Hall sensor are connected in parallel to terminals hall_1 and hall_3 of the detection chip; terminals 2 and 4 of the main Hall sensor and the secondary Hall sensor are connected in series to terminals hall_1 and hall_3 of the detection chip.

[0043] In other embodiments of the present invention, the first input terminal, the second input terminal, the third input terminal, the fourth input terminal, the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal are not fixedly set to the connection terminal numbers of the main Hall sensor and the sub-Hall sensor described above.

[0044] Among them, R1 and R2 are differential feedback sampling resistors, used for coarse adjustment and fine adjustment respectively; VOUT is the output terminal of the detection chip, VCC is the power supply terminal of the detection chip, VREF is the reference terminal, and CND is the common ground terminal.

[0045] In this embodiment, the detection chip uses integrated circuit ICs such as TI DRV411 and Senko XG211.

[0046] Figure 4 This is a schematic diagram showing the position of the Hall sensor of the present invention.

[0047] refer to Figure 4 As shown, in addition to the Hall sensor positions described in the above embodiments, the secondary Hall sensor can also be located at the bottom 41 of the feedback coil, the side 42 of the outer arc of the frame, and the outer 43 of the frame; the primary Hall sensor is located at the center 40 of the feedback coil 104. The distance from the outer arc of the frame at position 43 is 8mm-9mm.

[0048] The secondary Hall sensor, positioned in three different locations, provides differential functionality. In this embodiment, experiments were conducted under the conditions of a rated current of 10A for the primary frame and an external magnetic field of 22.5Gs. The output voltage values ​​of the primary Hall sensor at position 40 and the secondary Hall sensor at positions 41 (bottom of the feedback coil), 42 (outer arc of the frame), and 43 (outer frame) were compared. The output voltage value V of the primary Hall sensor was also compared. 主OUT and the output voltage value V of the secondary Hall sensor 副OUT The differential voltages obtained by taking the difference are -13mV, 90mV, and 107mV, respectively.

[0049] Furthermore, the secondary Hall sensor located at position 41 at the bottom of the feedback coil is affected by the magnetic field of the feedback coil and the magnetic field of the frame; the secondary Hall sensor located at position 42 next to the outer arc of the frame is affected by the magnetic field of the outer arc of the frame and the magnetic field of the small feedback coil; the secondary Hall sensor located at position 43 outside the frame is almost unaffected by the magnetic field of the feedback coil and the magnetic field of the frame.

[0050] Since both the main Hall sensor and the secondary Hall sensor are affected by the magnetic field generated by the change in the primary frame current, the main Hall sensor is located at the center of the feedback coil, and the magnetic field generated by the feedback coil compensates for the main Hall sensor's magnetic field. However, the secondary Hall sensor is farther from the center of the feedback coil, and its influence from the magnetic field generated by the feedback coil is negligible. Therefore, the feedback coil cannot simultaneously compensate for the secondary Hall sensor. Thus, the placement of the secondary Hall sensor must avoid the influence of the feedback coil's magnetic field. Furthermore, the complexity of the subsequent packaging process must also be considered.

[0051] Figure 5 This is a cross-sectional schematic diagram of a coreless closed-loop current detection packaging structure provided in an embodiment of the present invention.

[0052] Please refer to Figure 5 As shown, in this embodiment, the coreless closed-loop current detection packaging structure differs from the first embodiment of the present invention in that the main Hall sensor and the secondary Hall sensor are disposed and fixed below the carrier plate. The feedback coil 104 is directly disposed on the carrier plate 103, without the need for a coil positioning structure to fix the feedback coil 104; the main Hall sensor 106 and the secondary Hall sensor 107 are disposed and fixed below the carrier plate 103, respectively located in the gap between the primary side frame 101 and the secondary side frame 108.

[0053] The above technical solution adopts a differential structure of a main Hall sensor and a secondary Hall sensor for closed-loop power detection Hall sensor element, which can accurately measure and reduce errors, and has good performance in coreless current detection structure. Since there is no magnetic core in the coreless current detection structure, there is enough space to accommodate the main Hall sensor and the secondary Hall sensor, which can further reduce the size of the power detector, simplify the structure, reduce heat sources, facilitate smaller chip-level packaging and integration, and reduce costs.

[0054] The present invention also provides a current detection method, employing any of the above-mentioned coreless closed-loop current detection packaging structures, comprising: obtaining the output voltage value V of the main Hall sensor using the coreless closed-loop current detection packaging structure. 主OUT and the output voltage value V of the secondary Hall sensor 副OUT Calculate the differential voltage, V 差分OUT =V 主OUT -V 副OUT =k*(B 主磁 -(-B 副磁 ), where k is the Hall linear coefficient, B 主磁 The magnetic field strength in the sensing direction of the main Hall sensor, B 副磁 The magnetic field strength is in the sensitive direction of the secondary Hall sensor.

[0055] Since the magnetic fields in the sensing directions of both the main Hall sensor and the secondary Hall sensor are generated by the current in the sensing primary frame, the sensing magnetic fields of the main Hall sensor and the secondary Hall sensor located on both sides of the primary frame are in opposite directions, and their output voltages are opposite.

[0056] Furthermore, since the induced magnetic fields of the main Hall sensor and the secondary Hall sensor are in opposite directions, their output voltages are opposite. Therefore: V 差分OUT =V 主OUT -V 副OUT =k*(B 主磁 -(-B 副磁 ))=k*(B 主磁 +B 副磁 ); where k represents the coefficient of Hall induced magnetic field and output voltage, which is called the Hall linear coefficient; here V=k*B, which belongs to the inherent characteristics of Hall device.

[0057] This is because the primary current simultaneously generates opposite magnetic fields at the inner and outer edges of the frame throat, which are actually superimposed after differential measurement, thus improving measurement stability; V 差分OUT =V 主OUT -V 副OUT =k*(B 主磁 -(-B 副磁 ));

[0058] If there is a homogeneous stray magnet B above both Hall effect sensors杂磁 *sinθ, where θ represents the angle between the direction of the stray magnetism and the direction of Hall sensitivity, then V 差分OUT =k*((B 主磁 +B 杂磁 *sinθ)-(-B 副磁 +B 杂磁 *sinθ));

[0059] Simplifying and transforming to obtain V 差分OUT =k*(B 主磁 +B 副磁 ); that is, B 杂磁 *sinθ has been removed by the two Hall differential.

[0060] Therefore, it can be done through V 差分OUT =V 主OUT -V 副OUT The output voltage values ​​of the main Hall sensor and the secondary Hall sensor are differentially divided, V 差分OUT The voltage value after eliminating stray magnetic interference.

[0061] The aforementioned differential voltage is converted into a current value in the original edge frame 101 in real time through the calculation of the detection chip, thus completing the dynamic detection of the current.

[0062] The above technical solution adopts a differential structure for the Hall sensor element of closed-loop power detection, which has good performance in coreless power detection structure. It can reduce the size of the power detector, simplify the structure and reduce heat sources, and facilitate smaller chip-level packaging and integration, thereby reducing costs. The above current detection method uses a differential structure between a main Hall sensor and a secondary Hall sensor to suppress external magnetic interference during power detection and improve detection stability.

[0063] In one specific embodiment of the present invention, the main Hall sensor and the secondary Hall sensor have opposite polarities.

[0064] Figure 6 This is a partial circuit diagram provided for another embodiment of the present invention.

[0065] The circuit connection relationship between the main Hall sensor, the secondary Hall sensor, and the detection chip includes: the main Hall sensor includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the secondary Hall sensor includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the first input terminal and the third input terminal, the second input terminal and the fourth input terminal are respectively connected in parallel to the detection chip; the first output terminal and the third output terminal, the second output terminal and the fourth output terminal are respectively connected in series to the detection chip.

[0066] In this embodiment, terminal 1 of the main Hall sensor serves as the first input terminal, terminal 2 as the second input terminal, terminal 3 as the first output terminal, and terminal 4 as the second output terminal; terminal 1 of the secondary Hall sensor serves as the third input terminal, terminal 2 as the fourth input terminal, terminal 3 as the third output terminal, and terminal 4 as the fourth output terminal; terminals 1, 2, 3, and 4 of the main and secondary Hall sensors are connected in parallel to terminals hall_1, hall_2, hall_3, and hall_4 of the detection chip. The first, second, third, and fourth input terminals, as well as the first, second, third, and fourth output terminals, are not fixed to the connection terminal numbers of the main and secondary Hall sensors.

[0067] Furthermore, in other embodiments of the present invention, the connection terminals of the main Hall sensor and the secondary Hall sensor may not be in a one-to-one correspondence with the same serial number. For example, terminals 1, 2, 3, and 4 of the main Hall sensor may be connected in parallel to terminals 2, 3, 4, and 1 of the secondary Hall sensor, respectively, and then connected to terminals hall_1, hall_2, hall_3, and hall_4 of the detection chip (i.e., terminal 1 of the main Hall sensor and terminal 2 of the secondary Hall sensor are connected in parallel to terminal hall_1 of the detection chip; terminal 2 of the main Hall sensor and terminal 3 of the secondary Hall sensor are connected in parallel to terminal hall_2 of the detection chip; terminal 3 of the main Hall sensor and terminal 4 of the secondary Hall sensor are connected in parallel to terminal hall_3 of the detection chip; and terminal 4 of the main Hall sensor and terminal 1 of the secondary Hall sensor are connected in parallel to terminal hall_4 of the detection chip); or terminals 1, 2, 3, and 4 of the main Hall sensor may be connected in parallel to terminals 3, 4, 1, and 2 of the secondary Hall sensor, respectively, and then connected to terminals hall_1, hall_2, hall_3, and hall_4 of the detection chip, etc.

[0068] When the chip supplies power to the main Hall sensor and the secondary Hall sensor, the main Hall sensor is positive and the secondary Hall sensor is negative; or the main Hall sensor is negative and the secondary Hall sensor is positive.

[0069] The main Hall sensor and the secondary Hall sensor have opposite polarities. They can be Hall sensors with opposite polarities, or they can be the same Hall sensor installed in opposite directions to achieve the effect of opposite polarities.

[0070] The rotational power supply can be provided internally by the chip, i.e., using a direct chip power supply method; or it can be provided by other components connected to the chip, i.e., using an external direct power supply method, where power is supplied to the main Hall sensor and the secondary Hall sensor through the hall_1, hall_2, hall_3, and hall_4 terminals of the detection chip.

[0071] In one embodiment of the present invention, the rotating power supply, i.e., the detection chip, provides excitation voltages to the four terminals of the main Hall sensor and the secondary Hall sensor respectively through terminals hall_1, hall_2, hall_3, and hall_4, and switches the excitation voltages according to a certain cycle.

[0072] In this embodiment, the effect of canceling the interfering magnetic field and detecting the primary current can be achieved by switching the current.

[0073] This invention also provides a current detection method, employing a coreless closed-loop current detection package structure with opposite polarities of the main Hall sensor and the secondary Hall sensor, comprising: obtaining output voltage values ​​at a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal using the coreless closed-loop current detection package structure; summing the output voltage values ​​of the first output terminal and the third output terminal, and the second output terminal and the third output terminal, respectively, and taking the highest value as the output voltage value. The main Hall sensor and the secondary Hall sensor are spaced a certain distance apart, so that the secondary Hall sensor is not affected by the feedback coil.

[0074] The output voltage value is converted into a current value in the original frame 101 in real time through the calculation of the detection chip, thus completing the dynamic detection of the current.

[0075] This invention also provides a method for counteracting magnetic field interference. This method employs a coreless closed-loop current detection packaging structure with opposite polarities for the main Hall sensor and the secondary Hall sensor. The closer the spacing between the main Hall sensor and the secondary Hall sensor, the more pronounced the effect of counteracting magnetic field interference. For the coreless closed-loop current detection packaging structure described in the embodiment, refer to... Figure 1 As shown, the main Hall sensor 106 is preferably disposed at the center of the inner side of the original side frame 101 U-shaped structure 102; the secondary Hall sensor 107 is disposed on the outer side of the original side frame U-shaped structure 102, at a horizontal distance of 0.1 mm from the main Hall sensor 106.

[0076] Furthermore, the center line connecting the main Hall sensor and the secondary Hall sensor should be as parallel as possible to the direction of the external high current in order to counteract the magnetic field generated by the external current to the greatest extent.

[0077] In this example, the chip's zero-input principle can be achieved by rotating the voltage power supply to obtain the vector sum of the potential difference between the two Hall effect sensors in the same external magnetic field and the two sensors in opposite directions, thus realizing the anti-external magnetic field effect.

[0078] In this embodiment, the current detection method is applied to the above-mentioned coreless closed-loop current detection package structure. In other embodiments of the present invention, it is not limited to the above-mentioned coreless closed-loop current detection package structure, but can also be applied to other package structures or modules that use a main Hall sensor plus a secondary Hall sensor.

[0079] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A coreless closed-loop current detection packaging structure, characterized in that, include: The primary edge frame includes a U-shaped structure, and a magnetic field is generated when current passes through the primary edge frame. A carrier plate is disposed on the surface of the primary side frame to isolate the primary side frame and the feedback coil; A feedback coil, which is a coreless coil, is disposed above the carrier plate and is used to generate a magnetic field opposite to that of the original side frame; The detection chip is disposed between the primary side frame and the feedback coil. By adjusting the current of the feedback coil, an induced magnetic field is generated to balance the magnetic field of the primary side frame, and the current in the primary side frame is dynamically detected. The main Hall sensor is disposed inside the U-shaped structure of the primary side frame and is used to dynamically monitor the magnetic field between the primary side frame and the feedback coil. A secondary Hall sensor is disposed outside the U-shaped structure of the primary side frame, along the horizontal direction of the primary Hall sensor and located at a position covered by the feedback coil or at a certain position outside the feedback coil and a certain distance from the center of the feedback coil, so that the influence of the magnetic field of the feedback coil on the secondary Hall sensor is less than that on the primary Hall sensor. It is used to dynamically monitor the magnetic field between the primary side frame and the feedback coil and eliminate errors.

2. The coreless closed-loop current detection packaging structure according to claim 1, characterized in that, Both the main Hall sensor and the secondary Hall sensor employ one of the following: antimony Hall sensor or gallium arsenide Hall sensor.

3. The coreless closed-loop current detection packaging structure according to claim 1, characterized in that, The main Hall sensor and the secondary Hall sensor are positioned and fixed above or below the carrier plate.

4. The coreless closed-loop current detection packaging structure according to claim 1, characterized in that, The distance from the center of the main Hall sensor to the inner edge of the original side frame U-shaped structure is 0-1mm; the distance from the center of the secondary Hall sensor to the outer edge of the original side frame U-shaped structure is 0-0.5mm.

5. The coreless closed-loop current detection packaging structure according to claim 1, characterized in that, The circuit connections between the main Hall sensor, the secondary Hall sensor, and the detection chip include: The main Hall sensor includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the secondary Hall sensor includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the first and third input terminals, the second and fourth input terminals are respectively connected in parallel to the detection chip; the first and third output terminals, the second and fourth output terminals are respectively connected in series to the detection chip.

6. The coreless closed-loop current detection packaging structure according to claim 1, characterized in that, The coreless closed-loop current detection module structure also includes a secondary side frame, which is electrically connected to the detection chip and the feedback coil, and is located below the carrier board.

7. The coreless closed-loop current detection packaging structure according to claim 1, characterized in that, The main Hall sensor and the secondary Hall sensor have opposite polarities.

8. The coreless closed-loop current detection packaging structure according to claim 7, characterized in that, The circuit connection relationship between the main Hall sensor, the secondary Hall sensor, and the detection chip includes: the main Hall sensor includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the secondary Hall sensor includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the first input terminal and the third input terminal, the second input terminal and the fourth input terminal, the first output terminal and the third output terminal, and the second output terminal and the fourth output terminal are respectively connected in parallel to the detection chip.

9. A current detection method, employing the coreless closed-loop current detection packaging structure as described in any one of claims 1-6, characterized in that, include: The output voltage value V of the main Hall sensor is obtained by using a coreless closed-loop current sensing package structure. 主OUT and the output voltage value V of the secondary Hall sensor 副OUT ; Calculate the differential voltage, V 差分OUT =V 主OUT -V 副OUT =k*(B 主磁 -(-B 副磁 )), where k is the Hall linear coefficient, B 主磁 The magnetic field strength in the sensing direction of the main Hall sensor, B 副磁 The magnetic field strength is in the sensitive direction of the secondary Hall sensor.

10. The method according to claim 9, characterized in that, The main Hall sensor and the secondary Hall sensor have opposite induced magnetic field directions and opposite output voltages.

11. A current detection method, employing the coreless closed-loop current detection packaging structure as described in claim 8, comprising: The output voltage values ​​of the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal are obtained by adopting a coreless closed-loop current detection package structure. The output voltage values ​​of the first output terminal and the third output terminal, as well as the output voltage values ​​of the second output terminal and the third output terminal, are summed respectively, and the highest value is taken as the output voltage value.

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