Magnetoresistive random access memory element and method of making same

Abstract

A magnetic random access memory element and a method for fabricating the same are disclosed. The method for fabricating the magnetic random access memory element includes forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first upper electrode on the first MTJ, and forming a protective layer around the first MTJ. The protective layer includes a V-shape, and a valley of the V-shape is higher than a top surface of the first upper electrode.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a magnetoresistive random access memory (MAM) element. First, a first magnetic tunneling junction (MTJ) is formed on a substrate. Then, a first upper electrode is formed on the first MTJ. Next, a protective layer is formed around the first MTJ, wherein the protective layer comprises a V-shape and the valley point of the V-shape is higher than the top surface of the first upper electrode.

[0005] Another embodiment of the present invention discloses a magnetoresistive random access memory element, which mainly includes a first magnetic tunneling junction (MTJ) disposed on a substrate, a first upper electrode disposed on the MTJ, and a protective layer surrounding the first MTJ, wherein the protective layer comprises a V-shape and the valley point of the V-shape is higher than the top surface of the first upper electrode. Attached Figure Description

[0006] Figures 1 to 6 This is a schematic diagram of a method for fabricating an MRAM element according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: MRAM region

[0010] 16: Logical Area

[0011] 18: Interlayer dielectric layer

[0012] 20: Metal interconnect structure

[0013] 22: Metal interconnect structure

[0014] 24: Intermetallic dielectric layer

[0015] 26: Metal interconnects

[0016] 28: Stop Layer

[0017] 30: Intermetallic dielectric layer

[0018] 32: Metal interconnects

[0019] 34: Barrier Layer

[0020] 36: Metal layer

[0021] 38: MTJ stacked structure

[0022] 42: Lower electrode

[0023] 44: Fixed layer

[0024] 46: Barrier Layer

[0025] 48: Free Layer

[0026] 50: Upper electrode

[0027] 52:MTJ

[0028] 56: Covering layer

[0029] 58: Protective layer

[0030] 62: Intermetallic dielectric layer

[0031] 70: Metal interconnects

[0032] 72: Stop Layer

[0033] 74: Intermetallic Dielectric Layer

[0034] 76: Metal interconnects

[0035] 78: Stop Layer Detailed Implementation

[0036] Please refer to Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating an MRAM element according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0037] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0038] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0039] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0040] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0041] Subsequently, as Figure 2 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 52 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 52.

[0042] A masking layer 56 is then formed on the MTJ 52 and covers the surface of the inter-metal dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 56 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0043] Then as Figure 3 As shown, an atomic layer deposition (ALD) process is first performed to form a protective layer 58 covering each MTJ 52 and the intermetallic dielectric layer 30 of the logic region 16. An etch-back process is then performed to remove a portion of the protective layer 58 between the MRAM region 14 and the logic region 16, creating a V-shape on the top surface of the protective layer 58 between the two upper electrodes 50. Finally, another photolithography and etching process is used to remove the protective layer 58, the masking layer 62, and a portion of the intermetallic dielectric layer 30 of the logic region 16. In this embodiment, the protective layer 58 preferably comprises silicon oxide, but is not limited to this.

[0044] It should be noted that when the protective layer 58 is removed by the aforementioned etching process in this embodiment, the top surface of the remaining protective layer 58 is preferably higher than the top surfaces of the two upper electrodes 50 by a distance, for example, about 300 to 500 angstroms, and a V-shape is formed on the top surface of the protective layer 58 in the MRAM region 14. The V-shape is preferably located between the two MTJs 52 and the two upper electrodes 50, the valley point of the V-shape is higher than the top surface of the upper electrodes 50, and the angle of the V-shape is preferably greater than 110 degrees or more preferably greater than 120 degrees.

[0045] Subsequently, as Figure 4 As shown, an intermetallic dielectric layer 62 is first formed on the protective layer 58 using a process such as flowable chemical vapor deposition (FCVD). Then, a planarization process is performed, for example, using chemical mechanical polishing (CMP) to remove a portion of the intermetallic dielectric layer 62 between the MRAM region 14 and the logic region 16, so that the tops of the intermetallic dielectric layer 62 in the MRAM region 14 and the logic region 16 are approximately flush. In this embodiment, the intermetallic dielectric layer 62 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0046] Then as Figure 5As shown, a pattern transfer fabrication process is performed, for example, by using a patterned mask (not shown) to remove part of the intermetallic dielectric layer 62, part of the intermetallic dielectric layer 30, and part of the stop layer 28 of the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. Then, the contact holes are filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove part of the metal material to form contact plugs or metal interconnects 70 that electrically connect the metal interconnects 26 within the contact holes.

[0047] Subsequently, as Figure 6 As shown, a stop layer 72 is first formed in the MRAM region 14 and the logic region 16, covering the intermetallic dielectric layer 62 and the metal interconnects 70. An intermetallic dielectric layer 74 is then formed on the stop layer 72. One or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 74, the stop layer 72, the intermetallic dielectric layer 62, the protective layer 58, and the masking layer 56 in the MRAM region 14 and the logic region, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 76 in the MRAM region 14 and the logic region 16, connecting to the underlying MTJ 52 and the metal interconnects 70. Preferably, the metal interconnects 76 in the MRAM region 14 directly contact the underlying upper electrode 50, while the metal interconnects 76 in the logic region 16 contact the underlying metal interconnects 70. Next, another stop layer 78 is formed on the intermetal dielectric layer 70 and covers the metal interconnect 76.

[0048] In this embodiment, stop layer 72 and stop layer 78 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 76 disposed within the intermetallic dielectric layer 74 can be embedded within the intermetallic dielectric layer 74 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 76 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0049] Please refer to again Figure 6 , Figure 6 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 6 As shown, the semiconductor device includes multiple MTJs 52 disposed on the substrate 12 of the MRAM region 14, an upper electrode 50 disposed on each MTJ 52, a cover layer 56 disposed on the sidewalls of the MTJs 52 and the upper electrode 50, a protective layer 58 surrounding the MTJs 52, an intermetallic dielectric layer 62 disposed on the protective layer 58, a stop layer 72 disposed on the intermetallic dielectric layer 62, another intermetallic dielectric layer 74 disposed on the stop layer 72, and metal interconnects 76 disposed in the intermetallic dielectric layer 74, the stop layer 72, the intermetallic dielectric layer 62 and the protective layer 58 respectively and in contact with the upper electrode 50. In detail, the top surface of the upper electrode 50 is flush with the top surface of the cover layer 56, and the top surface of the protective layer 58 includes a V-shape. The V-shape is preferably located between the two MTJs 52 and the two upper electrodes 50. The valley of the V-shape is higher than the top surface of the upper electrode 50, the top surface of the cover layer 56, and the bottom surface of the metal interconnect 76, and the angle of the V-shape is preferably greater than 110 degrees or more preferably greater than 120 degrees. It should be noted that the protective layer 58 does not extend into the logic region 16 but is only located within the MRAM region 14. The intermetallic dielectric layer 62 next to the protective layer 58, in addition to contacting the underlying intermetallic dielectric layer 30, extends from the logic region 16 to the protective layer 58 in the MRAM region 14.

[0050] In summary, this invention primarily involves forming a protective layer on the MTJ after forming the MTJ and the top electrode. Then, selective etching is used to remove a portion of the protective layer, creating a V-shape on the surface of the protective layer between the two MTJs. Since the stacked protective layer is much higher than the top surface of the top electrode, when the protective layer is partially removed by etching, the top surface of the protective layer preferably forms a shallow V-shape with an angle greater than 110 degrees.

[0051] The valley point of the V-shape between the two MTJs or the top electrode is preferably higher than the bottom surface of the top electrode. According to a preferred embodiment of the present invention, controlling the top surface of the protective layer on both sides of the V-shape to be at a position higher than the top surface of the top electrode can avoid excessive erosion of the masking layer and protective layer on both sides of the top electrode by the etching process when forming the upper metal interconnect to the top electrode, thus affecting the device performance.

[0052] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a magnetoresistive random access memory element, characterized in that, Include: The first magnetic tunneling junction (MTJ) is formed on the substrate; A first upper electrode is formed on the first magnetic tunnel junction; The forming of a covering layer directly contacts the sidewall of the first magnetic tunnel junction; and A protective layer is formed around the first magnetic tunnel junction, wherein the protective layer directly contacts the cover layer and includes a V-shape, and the valley point of the V-shape is not located directly above the first upper electrode but is higher than the top surface of the first upper electrode. The top surface of the protective layer on one side of the V-shape is higher than the top surface of the first upper electrode. The protective layer and the cover layer are both single-layer structures.

2. The method of claim 1, further comprising: A first intermetallic dielectric layer is formed on the substrate; A first metal interconnect and a second metal interconnect are formed within the first metal inter-dielectric layer; The first magnetic tunnel junction is formed on the first metal interconnect and the second magnetic tunnel junction is formed on the second metal interconnect; The first upper electrode is formed on the first magnetic tunnel junction and the second upper electrode is formed on the second magnetic tunnel junction; The covering layer is formed on the first magnetic tunneling junction and the second magnetic tunneling junction; The protective layer is formed on the cover layer, and the V-shape of the protective layer is located between the first upper electrode and the second upper electrode; Remove portions of the protective layer, the shielding layer, and the first intermetallic dielectric layer; A second intermetallic dielectric layer is formed on the protective layer; as well as A third metal interconnect and a fourth metal interconnect are formed within the second metal inter-dielectric layer to connect the first upper electrode and the second upper electrode.

3. The method of claim 2, wherein the V-shape is disposed between the first upper electrode and the second upper electrode.

4. The method of claim 2, wherein the valley point of the V-shape is higher than the bottom surface of the third metal interconnect.

5. The method of claim 2, wherein the top surface of the first upper electrode is flush with the top surface of the cover layer.

6. The method of claim 1, wherein the V-angle is greater than 110 degrees.

7. A magnetoresistive random access memory element, characterized in that, Include: The first magnetic tunneling junction (MTJ) is located on the substrate; The first upper electrode is disposed on the first magnetic tunnel junction; The shielding layer directly contacts the sidewall of the first magnetic tunnel junction; and A protective layer surrounds the first magnetic tunnel junction, wherein the protective layer directly contacts the cover layer and includes a V-shape, and the valley point of the V-shape is not located directly above the first upper electrode but is higher than the top surface of the first upper electrode. The top surface of the protective layer on one side of the V-shape is higher than the top surface of the first upper electrode. The protective layer and the cover layer are both single-layer structures.

8. The magnetoresistive random access memory element as claimed in claim 7, further comprising: A first intermetallic dielectric layer is disposed on the substrate; The first metal interconnect and the second metal interconnect are disposed within the first metal inter-dielectric layer; The first magnetic tunneling junction is disposed on the first metal interconnect and the second magnetic tunneling junction is disposed on the second metal interconnect; The first upper electrode is disposed on the first magnetic tunnel junction and the second upper electrode is disposed on the second magnetic tunnel junction; The covering layer is disposed next to the first magnetic tunneling junction and the second magnetic tunneling junction; The protective layer is provided on the covering layer; A second intermetallic dielectric layer is disposed on the protective layer; as well as The third and fourth metal interconnects are disposed within the second metal inter-dielectric layer, connecting the first upper electrode and the second upper electrode.

9. The magnetoresistive random access memory element as claimed in claim 8, wherein the V-shape is disposed between the first upper electrode and the second upper electrode.

10. The magnetoresistive random access memory element of claim 8, wherein the valley of the V-shape is higher than the bottom surface of the third metal interconnect.

11. The magnetoresistive random access memory element of claim 8, wherein the top surface of the first upper electrode is flush with the top surface of the cover layer.

12. The magnetoresistive random access memory element of claim 7, wherein the V-angle is greater than 110 degrees.

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