Splicing display panel, splicing method thereof, and display device

Abstract

The present application provides a spliced ​​display panel, a splicing method thereof, and a display device. The spliced ​​display panel includes a driving backplane and a plurality of display components arranged in an array on the driving backplane. A first binding terminal on the display component is electrically connected to a corresponding LED chip. The driving backplane is provided with a second binding terminal bound to the first binding terminal and a third binding terminal electrically connected to a driving element and the second binding terminal. The driving element transmits a signal to the second binding terminal, the first binding terminal, and the LED chip in sequence through the third binding terminal to drive the LED chip to emit light. By arranging the driving element on the driving backplane in this way, the border of each display component can be reduced or eliminated, so that the splicing seam at the splicing point after the multiple display components are spliced ​​is reduced or eliminated, thereby solving the problem of large splicing seams at the splicing points of existing spliced ​​screens.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a spliced ​​display panel, a splicing method thereof, and a display device. Background Art

[0002] Spliced ​​screens are made up of multiple display screens, allowing them to be large enough to meet the large-scale demands of outdoor displays and other applications. Existing spliced ​​screens are mostly spliced ​​using printed circuit boards (PCBs). This splicing method is relatively simple, but the trace width and accuracy of PCBs are inferior to those of glass, making it difficult to meet the high-precision splicing requirements.

[0003] With the update and iteration of display technology, small-pitch, high-resolution Mini-LED or Micro-LED display products are gradually being introduced to the market. In order to meet the high-precision splicing requirements, splicing screens using Mini-LED or Micro-LED technology need to use glass-based splicing. Currently, the most commonly used glass-based splicing method is to use a set of driver ICs corresponding to one splicing unit, so that each splicing unit has a border. The presence of the border of each splicing unit will result in a large splicing seam at the splicing of the splicing screen, affecting the display quality. Summary of the Invention

[0004] The present application provides a spliced ​​display panel, a splicing method thereof, and a display device to alleviate the technical problem of large splicing seams at the splicing points of existing spliced ​​screens.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] An embodiment of the present application provides a spliced ​​display panel, which includes a driving backplane and a plurality of display components arranged in an array on the driving backplane;

[0007] Each of the display components includes a display substrate, a plurality of first binding terminals arranged on one side of the display substrate, and a plurality of LED chips arranged on the other side of the display substrate, wherein the first binding terminals are electrically connected to corresponding LED chips;

[0008] The driving backplane includes a first backplane and a second backplane arranged in a stacked manner, the first backplane is located on a side of the second backplane away from the display component, a plurality of second binding terminals are provided on the second backplane, a plurality of third binding terminals and driving elements electrically connected to the third binding terminals are provided on the first backplane, and the second binding terminals are electrically connected to the corresponding first binding terminals and the corresponding third binding terminals.

[0009] In the spliced ​​display panel provided in the embodiment of the present application, the driving element array is arranged on a side of the first backplane away from the second backplane.

[0010] In the spliced ​​display panel provided in an embodiment of the present application, the first backplane includes a first substrate and a first barrier layer located on the side of the first substrate close to the second backplane, the third binding terminal is located on the first substrate, and the first barrier layer is provided with a notch at a position corresponding to the third binding terminal to expose the third binding terminal; the first substrate is provided with a first opening at a position corresponding to the third binding terminal, and the driving element is electrically connected to the third binding terminal through the first opening.

[0011] In the spliced ​​display panel provided in an embodiment of the present application, the first backplane further includes a first auxiliary conductive layer, the first auxiliary conductive layer is filled in the first opening, and the driving element is electrically connected to the third binding terminal through the first auxiliary conductive layer.

[0012] In the spliced ​​display panel provided in an embodiment of the present application, the second backplane includes a second substrate, a connecting trace located on the side of the second substrate close to the display component, and a second blocking layer, the second blocking layer covers the connecting trace, the second binding terminal is located on the second blocking layer, and the connecting trace is connected to the corresponding second binding terminal and the third binding terminal.

[0013] In the spliced ​​display panel provided in an embodiment of the present application, the second backplane includes a second substrate and a driving function layer and a second blocking layer located on the side of the second substrate close to the display component, the second blocking layer is covered on the driving function layer, the second binding terminal is located on the second blocking layer, and the driving function layer is connected to the corresponding second binding terminal and the third binding terminal.

[0014] In the spliced ​​display panel provided in the embodiment of the present application, the display substrate includes:

[0015] substrate;

[0016] A driving circuit layer is provided on a side of the base substrate away from the driving backplane; the driving circuit layer is electrically connected to the first binding terminal;

[0017] The LED chip is located on a side of the driving circuit layer away from the base substrate and is electrically connected to the driving circuit layer.

[0018] In the spliced ​​display panel provided in an embodiment of the present application, the base substrate includes a third substrate and a third blocking layer located on a side of the third substrate away from the driving circuit layer, the first binding terminal is located on a side of the third blocking layer away from the third substrate, and the third blocking layer is provided with a second opening at a position corresponding to the first binding terminal, and the first binding terminal is located in the second opening.

[0019] The present invention also provides a method for splicing a spliced ​​display panel, which includes:

[0020] Providing a transfer substrate, on which a plurality of LED chips are arranged in an array;

[0021] Providing a plurality of display assemblies, each comprising a display substrate and a plurality of first binding terminals disposed on one side of the display substrate, sequentially transferring the LED chips on the transfer substrate to the other side of the display substrate of each display assembly, and electrically connecting the first binding terminals to the corresponding LED chips;

[0022] A driving backplane is provided, the driving backplane comprising a first backplane and a second backplane stacked together, the first backplane being located on a side of the second backplane away from the display assembly, the second backplane being provided with a plurality of second binding terminals, the first backplane being provided with a plurality of third binding terminals and driving elements electrically connected to the third binding terminals, the third binding terminals being further electrically connected to corresponding second binding terminals;

[0023] Multiple display components are spliced ​​on the driving backplane, and each second binding terminal is electrically connected to the corresponding first binding terminal, so that the driving element transmits the signal to the second binding terminal, the first binding terminal and the LED chip in sequence through the third binding terminal to drive the LED chip to emit light.

[0024] The present invention further provides a display device, comprising:

[0025] a housing forming a receiving cavity; and

[0026] As in one of the aforementioned embodiments, the spliced ​​display panel is disposed in the accommodating cavity.

[0027] The beneficial effects of the present application are as follows: in the spliced ​​display panel, splicing method thereof, and display device provided by the present application, the spliced ​​display panel includes a driving backplane and a plurality of display components arranged in an array on the driving backplane, each of the display components includes a display substrate, a plurality of first binding terminals arranged on one side of the display substrate, and a plurality of LED chips arranged on the other side of the display substrate, the first binding terminals are electrically connected to the corresponding LED chips, the driving backplane is provided with a second binding terminal bound to the first binding terminal and a third binding terminal electrically connected to the driving element and the second binding terminal, the driving element transmits the signal to the second binding terminal, the first binding terminal and the LED chip in sequence through the third binding terminal to drive the LED chip to emit light, and by arranging the driving element on the driving backplane in this way, the border of each display component can be reduced or eliminated, so that the splicing seam at the splicing point after the multiple display components are spliced ​​is reduced or eliminated, thereby solving the problem of large splicing seams at the splicing points of the existing splicing screens. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic top view of the structure of the spliced ​​display panel provided in an embodiment of the present application.

[0030] Figure 2 A schematic cross-sectional view of a spliced ​​display panel provided in an embodiment of the present application.

[0031] Figure 3 A schematic cross-sectional structure diagram of a driver backplane provided in an embodiment of the present application.

[0032] Figure 4 Schematic diagram of the arrangement of driving elements on the first backplane provided in an embodiment of the present application.

[0033] Figure 5 A schematic cross-sectional view of a display assembly according to an embodiment of the present application.

[0034] Figure 6 Another schematic cross-sectional structure diagram of the driver backplane provided in an embodiment of the present application.

[0035] Figure 7 A schematic flow chart of a method for splicing display panels provided in an embodiment of the present application.

[0036] Figure 8 A schematic cross-sectional view of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0038] Please refer to Figures 1 to 4 , Figure 1 A schematic diagram of a top view of the spliced ​​display panel provided in an embodiment of the present application is shown. Figure 2 A schematic cross-sectional view of a spliced ​​display panel provided in an embodiment of the present application is shown in FIG. Figure 3 A schematic cross-sectional view of a driver backplane provided in an embodiment of the present application is shown. Figure 4 This is a schematic diagram of the arrangement of the driving elements on the first backplane provided in an embodiment of the present application. Figure 5 A schematic cross-sectional structure diagram of a display assembly provided in an embodiment of the present application. The spliced ​​display panel 100 includes a display area AA and a non-display area NA located outside the display area AA. The spliced ​​display panel 100 also includes a driving backplane 1 and a plurality of display assemblies 2 arranged in an array on the driving backplane 1. The plurality of display assemblies 2 are located in the display area AA, and each of the display assemblies 2 includes a display substrate 20, a plurality of first binding terminals 10 arranged on one side of the display substrate 20, and a plurality of LED chips 30 arranged on the other side of the display substrate 20, wherein the first binding terminals 10 are electrically connected to the corresponding LED chips 30. The LED chips 30 include Mini-LED chips or Micro-LED chips. The one side of the display substrate 20 and the other side of the display substrate 20 refer to two opposite sides of the display substrate 20.

[0039] The driver backplane 1 is provided with a plurality of second binding terminals 40 and a driving element 50 electrically connected to the second binding terminals 40. Each second binding terminal 40 is electrically connected to a corresponding first binding terminal 10, thereby electrically connecting the LED chip 30 on the display substrate 20 to the driving element 50 on the driver backplane 1. The driving element 50 transmits signals to the first binding terminals 10 and the LED chip 30 in sequence through the second binding terminals 40, thereby driving the LED chip 30 on the display substrate 20 to emit light.

[0040] The driver element 50 includes a driver integrated circuit (IC) and other driver components. The driver element 50 is disposed on the side of the driver backplane 1 away from the display assembly 2. Placing the driver element 50 on the driver backplane 1 can reduce or eliminate the borders of each display assembly 2, thereby reducing or eliminating the seams at the joints of multiple display assemblies 2, thereby resolving the problem of large seams at the joints of existing spliced ​​screens.

[0041] The following will specifically describe the film structure of the display assembly 2 and the driving backplane 1 of the spliced ​​display panel 100:

[0042] Reference Figure 3 The driving backplane 1 includes a first backplane 11 and a second backplane 12 that are stacked. The first backplane 11 is located on the side of the second backplane 12 away from the display component 2. A plurality of second binding terminals 40 are provided on the second backplane 12. A plurality of third binding terminals 60 and a driving element 50 electrically connected to the third binding terminals 60 are provided on the first backplane 11. The second binding terminals 40 are electrically connected to the corresponding first binding terminals 10 and the corresponding third binding terminals 60.

[0043] Specifically, the first backplane 11 includes a first substrate 111 and a first barrier layer 112 located on a side of the first substrate 111 close to the second backplane 12. The third binding terminal 60 is located on the first substrate 111, and the first barrier layer 112 has a notch at a position corresponding to the third binding terminal 60 to expose the third binding terminal 60. The first substrate 111 has a first opening 1110 at a position corresponding to the third binding terminal 60. The driving element 50 is electrically connected to the third binding terminal 60 through the first opening 1110.

[0044] Furthermore, the first backplane 11 further includes a first auxiliary conductive layer 1111 , which is filled in the first opening 1110 , and the driving element 50 is electrically connected to the third binding terminal 60 through the first auxiliary conductive layer 1111 .

[0045] Optionally, the material of the first auxiliary conductive layer 1111 includes one or more of a conductive film, a conductive adhesive, a metal solder, a solder paste, a liquid metal, etc., wherein the conductive adhesive includes a polymer conductive adhesive or a conductive adhesive doped with conductive particles. Furthermore, the third binding terminal 60 can be made of a metal or alloy or metal laminate structure, metal oxide, or conductive oxide with strong oxidation resistance and low resistivity, such as MO, AL, or other metals.

[0046] Furthermore, the second backplane 12 includes a second substrate 121 and a connecting trace 123 and a second blocking layer 122 located on the side of the second substrate 121 close to the display component 2, the second blocking layer 122 covers the connecting trace 123, the second binding terminal 40 is located on the second blocking layer 122, and the connecting trace 123 is connected to the corresponding second binding terminal 40 and the third binding terminal 60.

[0047] Optionally, the second binding terminal 40 may also be made of metal or alloy or metal laminate structure, metal oxide, conductive oxide, etc. with strong oxidation resistance and low resistivity, such as MO, AL and other metals.

[0048] At the same time, the second binding terminal 40 is also electrically connected to the corresponding first binding terminal 10. Thus, the driving component 50 transmits signals to the second binding terminal 40, the first binding terminal 10 and the display substrate 20 in sequence through the third binding terminal 60 to drive the LED chip to emit light.

[0049] Optionally, the first barrier layer 112 and the second barrier layer 122 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON) to prevent unwanted impurities or contaminants (such as moisture and oxygen) from diffusing from the first substrate 111 or the second substrate 121 into devices that may be damaged by these impurities or contaminants. The first substrate 111 and the second substrate 121 may be made of a flexible thin film material such as polyimide (PI).

[0050] Furthermore, the driving elements 50 are arranged in an array on the side of the first back plate 11 away from the second back plate 12, so that the driving elements 50 are evenly distributed on the first back plate 11. Figure 4As shown. By placing the driver components 50 on the first backplane 11, the border of each display module 2 can be reduced or eliminated, thereby reducing or eliminating the seams at the joints of multiple display modules 2. Furthermore, the driver components 50 are evenly spaced on the first backplane 11 and positioned corresponding to the display area of ​​the display panel, thus avoiding IR drop issues caused by excessive wiring due to the concentration of driver components 50 on the bottom or side frames.

[0051] Next, the specific structure of the display component 2 is described:

[0052] Reference Figure 5 The display assembly 2 includes a display substrate 20, a plurality of first binding terminals 10 and a plurality of LED chips 30 disposed on opposite sides of the display substrate. The display substrate 20 includes a base substrate 13 and a driving circuit layer 21 disposed on the base substrate 13. The LED chips 30 are electrically connected to the driving circuit layer 21, and the driving circuit layer 21 is used to drive the LED chips 30 to emit light. The first binding terminals 10 can be made of metals or alloys or metal laminated structures, metal oxides, conductive oxides, etc. with strong oxidation resistance and low resistivity, such as MO, AL, etc., to ensure the stability of the first binding terminals 10 and the reliability of the connection with the driving backplane 1.

[0053] Optionally, the base substrate 13 includes a stacked third barrier layer 132, a third substrate 131, a fourth barrier layer 133, and a buffer layer 134. The first binding terminal 10 and the third barrier layer 132 are both located on a side of the third substrate 131 away from the driving circuit layer 21. Specifically, the first binding terminal 10 is located on a side of the third barrier layer 132 away from the third substrate 131. The third barrier layer 132 has a second opening 1321 at a position corresponding to the first binding terminal 10. The first binding terminal 10 is located within the second opening 1321, and the second opening 1321 exposes the first binding terminal 10.

[0054] The fourth barrier layer 133 and the buffer layer 134 are both located on a side of the third substrate 131 close to the driving circuit layer 21 . Specifically, the fourth barrier layer 133 covers the third substrate 131 , and the buffer layer 134 covers the fourth barrier layer 133 .

[0055] Optionally, the third barrier layer 132, the fourth barrier layer 133 and the buffer layer 134 can all be formed of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., to prevent unwanted impurities or contaminants (such as moisture, oxygen, etc.) from diffusing from the third substrate 131 to devices that may be damaged by these impurities or contaminants. The material of the third substrate 131 includes flexible thin film materials such as polyimide (PI). At the same time, the buffer layer 134 can also provide a flat top surface to facilitate the preparation of other film layer structures on the buffer layer 134. Of course, the substrate substrate 13 of the present application is not limited to this. The substrate substrate 13 of the present application may include more or less substrate film layers and barrier film layers.

[0056] The driving circuit layer 21 is arranged on the buffer layer 134, and the driving circuit layer 21 includes a first semiconductor layer 22, a first gate 23, a second gate 24, a first source 251, a first drain 252 and an insulating layer located between each layer. Specifically, it includes a first gate insulating layer 17 located between the first semiconductor layer 22 and the first gate 23, a second gate insulating layer 18 located between the first gate 23 and the second gate 24, and a first interlayer insulating layer 19 located between the second gate 24 and the first source 251.

[0057] Specifically, the first semiconductor layer 22 is disposed on the buffer layer 134, and the first semiconductor layer 22 includes a channel region and a source region and a drain region located on opposite sides of the channel region. The first gate insulating layer 17 covers the first semiconductor layer 22 and the buffer layer 134. The first gate 23 is disposed on the first gate insulating layer 17, and the first gate 23 is disposed corresponding to the channel region of the first semiconductor layer 22. The second gate insulating layer 18 covers the first gate 23 and the first gate insulating layer 17. The second gate 24 is disposed on the second gate insulating layer 18, and the second gate 24 is disposed corresponding to the first gate 23.

[0058] The first interlayer insulating layer 19 is covered on the second gate electrode 24 and the second gate insulating layer 18. The source electrode 251 and the drain electrode 252 are arranged on the first interlayer insulating layer 19, and the source electrode 251 and the drain electrode 252 are electrically connected to the source region and the drain region of the corresponding first semiconductor layer 22, respectively. It should be noted that the driving circuit layer 21 also includes a plurality of signal lines, and the signal lines include data lines 253, gate scanning lines, etc., wherein the data lines 253 are arranged in the same layer as the source electrode 251 and the drain electrode 252, and the gate scanning lines are arranged in the same layer as the first gate electrode 23 or the second gate electrode 24. However, the present application is not limited to this. The signal lines of the present application may also include VSS, VDD power lines and various other signal lines for display or non-display, and different signal lines are electrically connected to different first binding terminals 10 to obtain different signals. For example, the data line 253 is electrically connected to the corresponding first binding terminal 10 to obtain a source driving signal and provide it to the source 251 ; the gate scan line is electrically connected to the corresponding first binding terminal 10 to obtain a gate scan signal and provide it to the first gate 23 .

[0059] This embodiment takes the electrical connection between the data line 253 and the first binding terminal 10 as an example for explanation:

[0060] Specifically, continue to refer to Figure 5 The first interlayer insulating layer 19 is patterned to form a deep hole, which penetrates the first interlayer insulating layer 19, the second gate insulating layer 18, the first gate insulating layer 17, the buffer layer 134, the fourth barrier layer 133, the third substrate 131, the third barrier layer 132, and reaches the first binding terminal 10, thereby exposing a portion of the first binding terminal 10. The data line 253 is electrically connected to the first binding terminal 10 through the deep hole. At the same time, the data line 253 is also electrically connected to the source electrode 251 or the drain electrode 252, that is, the data line 253 is also electrically connected to the driving circuit layer 21, thereby achieving an electrical connection between the first binding terminal 10 and the driving circuit layer 21. This application takes the electrical connection between the data line 253 and the drain electrode 252 as an example.

[0061] It should be noted that "disposed in the same layer" in this application means that during the manufacturing process, a film layer formed of the same material is patterned to obtain at least two different features, and the at least two different features are disposed in the same layer. For example, in this embodiment, the data line 253 and the source electrode 251 are obtained by patterning the same conductive film layer, and thus the data line 253 and the source electrode 251 are disposed in the same layer.

[0062] At the same time, in order to provide a flat surface for the driving circuit layer 21, the driving circuit layer 21 further includes a planarization layer 27 covering the source electrode 251, the drain electrode 252, and the first interlayer insulating layer 19. Of course, the structure of the driving circuit layer 21 in the present application is not limited to that shown in this embodiment. The driving circuit layer 21 of the present application may also include more or fewer film layers, and the positional relationship of the film layers is also not limited to that shown in this embodiment. For example, the present application may also adopt a single-gate structure, and the single-gate structure may also be located below the first semiconductor layer 22 to form a bottom-gate structure.

[0063] Furthermore, the driving circuit layer 21 also includes a first electrode 261 located on the planarization layer 27. The first electrode 261 is electrically connected to the source electrode 251 and the drain electrode 252 through vias in the planarization layer 27. This embodiment uses the electrical connection between the first electrode 261 and the source electrode 251 as an example. The LED chip 30 is electrically connected to the first electrode 261 to achieve an electrical connection between the LED chip and the driving circuit layer 21. The driving circuit layer 21 is also electrically connected to the corresponding first binding terminal 10, thereby achieving an electrical connection between the first binding terminal 10 and the corresponding LED chip 30. Of course, to drive the LED chip 30 to emit light, the driving circuit layer 21 also includes a second electrode 262. Optionally, the second electrode 262 is provided on the same layer as the first electrode 261.

[0064] Specifically, the LED chip 30 has a first electrode 31 and a second electrode 32. The first electrode 31 is electrically connected to the first electrode 261, and the second electrode 32 is electrically connected to the second electrode 262. The first electrode 261 is an anode, and the second electrode 262 is a cathode. However, the present application is not limited to this. The first electrode 261 can also be a cathode, and the second electrode 262 can be an anode. Alternatively, the second electrode 262 can be disposed on a side of the LED chip 30 away from the driver circuit layer 21. In this case, the first electrode 31 and the second electrode 32 of the LED chip 30 are located on opposite sides of the LED chip 30.

[0065] To define the attachment position of the LED chip 30, the drive circuit layer 21 may further include a pixel definition layer 28 overlying the planarization layer 27. The pixel definition layer 28 has openings at positions corresponding to the first electrode 261 and the second electrode 262. The LED chip 30 may be placed within the openings and electrically connected to the drive circuit layer 21. To improve the reliability of the LED chip 30 and prevent failure of the LED chip 30 due to water and oxygen intrusion, the display assembly 2 also includes an encapsulation layer 29 overlying the LED chip 30 and the pixel definition layer 28.

[0066] In one embodiment, please refer to Figures 1 to 6 , Figure 6 Another cross-sectional structural diagram of a driving backplane provided in an embodiment of the present application. Unlike the above embodiment, the second backplane 12 includes a second substrate 121, a driving function layer 80 located on the side of the second substrate 121 close to the display assembly 2, and a second barrier layer 122. The second barrier layer 122 overlies the driving function layer 80. The second binding terminals 40 are located on the second barrier layer 122. The driving function layer 80 is connected to the corresponding second binding terminals 40 and the third binding terminals 60.

[0067] Specifically, the driving function layer 80 includes a plurality of driving transistors having a dual-gate structure. Specifically, the driving function layer 80 includes a second semiconductor layer 81 formed on the second substrate 121, a third gate insulating layer 62 covering the second semiconductor layer 81 and the second substrate 121, a third gate electrode 82 formed on the third gate insulating layer 62, a fourth gate insulating layer 63 covering the third gate electrode 82 and the third gate insulating layer 62, a fourth gate electrode 83 formed on the fourth gate insulating layer 63, a second interlayer insulating layer 64 covering the fourth gate electrode 83 and the fourth gate insulating layer 63, and a second source electrode 85 and a second drain electrode 84 formed on the second interlayer insulating layer 64. The second blocking layer 122 covers the second source electrode 85, the second drain electrode 84, and the second interlayer insulating layer 64.

[0068] The third gate 82 and the fourth gate 83 are both arranged corresponding to the channel region of the second semiconductor layer 81. The second source 85 and the second drain 84 are respectively electrically connected to the source region and the drain region of the second semiconductor layer 81. The second bonding terminal 40 is electrically connected to the second source 85 through a via in the second barrier layer 122. The second drain 84 is electrically connected to the third bonding terminal 60 through a first signal transfer line 86. The third bonding terminal 60 is also electrically connected to the driving element 50 through the first auxiliary conductive layer 1111.

[0069] In other embodiments, the driving function layer 80 may further include a driving transistor having a single-gate structure.

[0070] In this embodiment, the driving element 50 is arranged on the side of the first backplane 11 away from the second backplane 12, and the driving signal from the driving element 50 is transmitted to the display substrate 20 in sequence through the third binding terminal 60, the first signal adapter 86, the second drain 84, the second semiconductor layer 81, the second source 85, the second binding terminal 40 and the first binding terminal 10 to drive the LED chip 30 on the display substrate 20 to emit light.

[0071] In one embodiment, the driving function layer 80 can also be used to fabricate a GOA circuit, eliminating the need for a gate driver 50, thereby saving costs. Furthermore, fabricating the GOA circuit on the second backplane 12 can also reduce the border of the spliced ​​display panel 100.

[0072] In other embodiments, the structure of the driving function layer 80 is not limited to the above-mentioned structure. For other descriptions, please refer to the above-mentioned embodiment and will not be repeated here.

[0073] In one embodiment, the present application also provides a method for splicing display panels, please refer to Figures 1 to 7 , Figure 7 A schematic flow chart of a method for splicing display panels provided in an embodiment of the present application, the method comprising the following steps:

[0074] S301: providing a transfer substrate, on which a plurality of LED chips 30 are arranged in an array;

[0075] S302: Providing a plurality of display assemblies 2, each of the display assemblies 2 including a display substrate 20 and a plurality of first binding terminals 10 disposed on one side of the display substrate 20, sequentially transferring the LED chips 30 on the transfer substrate to the other side of the display substrate 20 of each display assembly 2, and electrically connecting the first binding terminals 10 to the corresponding LED chips 30;

[0076] The other side of the display substrate 20 refers to the side opposite to the first binding terminal 10. Specifically, the first binding terminal 10 is located on one side of the display substrate 20, and the LED chip 30 is located on the other side of the display substrate 20. The first binding terminal 10 and the LED chip 30 are located on opposite sides of the display substrate 20.

[0077] S303: Providing a driving backplane 1, the driving backplane 1 comprising a first backplane 11 and a second backplane 12 arranged in a stacked manner, wherein the first backplane 11 is located on a side of the second backplane 12 away from the display assembly 2, the second backplane 12 is provided with a plurality of second binding terminals 40, the first backplane 11 is provided with a plurality of third binding terminals 60 and a driving element 50 electrically connected to the third binding terminals 60, and the third binding terminals 60 are also electrically connected to corresponding second binding terminals 40;

[0078] S304: Splice multiple display components 2 on the driving backplane 1, so that each second binding terminal 40 is electrically connected to the corresponding first binding terminal 10, so that the driving element 50 transmits the signal to the second binding terminal 40, the first binding terminal 10 and the LED chip 30 in sequence through the third binding terminal 60, so as to drive the LED chip 30 to emit light.

[0079] It is understood that mass transfer technology is typically used in the LED chip 30 transfer process. However, this technology is limited by the area of ​​a single transfer. For large-scale tiled displays, multiple transfers are required to complete the entire transfer process. However, multiple transfers can lead to cumulative misalignment and lower yields. In this embodiment, the LED chips 30 on the transfer substrate are first transferred to a single, small-sized display assembly 2, and then multiple display assemblies 2 are spliced ​​onto the driver backplane 1. This eliminates the need for large-scale mass transfer and improves the transfer yield.

[0080] In one embodiment, see Figure 8 , Figure 8 The cross-sectional structure diagram of the display device provided in the embodiment of the present application is as follows: The display device 1000 comprises a housing 200 and a spliced ​​display panel 100 according to one of the above embodiments; the housing 200 is formed with a receiving cavity 201 , and the display panel 100 is disposed in the receiving cavity 201 .

[0081] According to the above embodiments, it can be seen that:

[0082] The present application provides a spliced ​​display panel, a splicing method thereof, and a display device, wherein the spliced ​​display panel includes a driving backplane and a plurality of display components arranged in an array on the driving backplane, each of the display components includes a display substrate, a plurality of first binding terminals arranged on one side of the display substrate, and a plurality of LED chips arranged on the other side of the display substrate, the first binding terminal being electrically connected to the corresponding LED chip, the driving backplane being provided with a second binding terminal bound to the first binding terminal and a third binding terminal electrically connected to a driving element and the second binding terminal, the driving element transmitting a signal to the second binding terminal, the first binding terminal, and the LED chip in sequence through the third binding terminal to drive the LED chip to emit light, and by arranging the driving element on the driving backplane in this way, the border of each display component can be reduced or eliminated, so that the splicing seam at the splicing point after the plurality of display components are spliced ​​is reduced or eliminated, thereby solving the problem of large splicing seams at the splicing points of the existing splicing screen.

[0083] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0084] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A spliced ​​display panel, characterized in that: It includes a driving backplane and a plurality of display components arranged in an array on the driving backplane; The display assembly includes a display substrate, a plurality of first binding terminals arranged on one side of the display substrate, and a plurality of LED chips arranged on the other side of the display substrate, wherein the first binding terminals are electrically connected to corresponding LED chips; The driving backplane includes a first backplane and a second backplane stacked together, the first backplane being located on a side of the second backplane away from the display assembly, a plurality of second binding terminals being provided in the second backplane, a plurality of third binding terminals and driving elements electrically connected to the third binding terminals being provided in the first backplane, and the second binding terminals being electrically connected to corresponding first binding terminals and corresponding third binding terminals; The first backplane includes a first substrate, the third binding terminal is located on the first substrate, the first substrate is provided with a first opening at a position corresponding to the third binding terminal, and the driving element is electrically connected to the third binding terminal through the first opening; The first backplane further includes a first auxiliary conductive layer, the first auxiliary conductive layer is filled in the first opening, and the driving element is electrically connected to the third binding terminal through the first auxiliary conductive layer; Wherein, the material of the first auxiliary conductive layer includes one or more of conductive film, conductive adhesive, metal solder, solder paste, and liquid metal; The second backplane includes a second substrate, a driving function layer and a second barrier layer located on a side of the second substrate close to the display assembly, the second barrier layer covers the driving function layer, the second binding terminals are located on the second barrier layer, and the driving function layer is connected to the corresponding second binding terminals and the third binding terminals; Wherein, the driving function layer is used to make a GOA circuit.

2. The spliced ​​display panel according to claim 1, wherein: The driving element array is arranged on a side of the first back plate away from the second back plate.

3. The spliced ​​display panel according to claim 2, wherein: The first backplane further includes a first barrier layer located on a side of the first substrate close to the second backplane, and the first barrier layer is provided with a notch at a position corresponding to the third binding terminal to expose the third binding terminal.

4. The spliced ​​display panel according to any one of claims 1 to 3, wherein: The display substrate comprises: substrate; A driving circuit layer is provided on a side of the base substrate away from the driving backplane; the driving circuit layer is electrically connected to the first binding terminal; The LED chip is located on a side of the driving circuit layer away from the base substrate and is electrically connected to the driving circuit layer.

5. The spliced ​​display panel according to claim 4, wherein: The substrate base includes a third substrate and a third barrier layer located on a side of the third substrate away from the driving circuit layer. The first binding terminal is located on a side of the third barrier layer away from the third substrate, and the third barrier layer is provided with a second opening at a position corresponding to the first binding terminal. The first binding terminal is located in the second opening.

6. A method for splicing display panels, characterized in that: include: Providing a transfer substrate, on which a plurality of LED chips are arranged in an array; Providing a plurality of display assemblies, each comprising a display substrate and a plurality of first binding terminals disposed on one side of the display substrate, sequentially transferring the LED chips on the transfer substrate to the other side of the display substrate of each display assembly, and electrically connecting the first binding terminals to the corresponding LED chips; A driving backplane is provided, the driving backplane comprising a first backplane and a second backplane stacked together, the first backplane being located on a side of the second backplane away from the display assembly, the second backplane being provided with a plurality of second binding terminals, the first backplane being provided with a plurality of third binding terminals and a driving element electrically connected to the third binding terminals, the third binding terminals being further electrically connected to corresponding second binding terminals; splicing a plurality of the display components onto the driving backplane, electrically connecting each of the second binding terminals to the corresponding first binding terminal, so that the driving element transmits signals to the second binding terminals, the first binding terminals, and the LED chip in sequence through the third binding terminal, thereby driving the LED chip to emit light; The first backplane includes a first substrate, the third binding terminal is located on the first substrate, the first substrate is provided with a first opening at a position corresponding to the third binding terminal, and the driving element is electrically connected to the third binding terminal through the first opening; The first backplane further includes a first auxiliary conductive layer, the first auxiliary conductive layer is filled in the first opening, and the driving element is electrically connected to the third binding terminal through the first auxiliary conductive layer; Wherein, the material of the first auxiliary conductive layer includes one or more of conductive film, conductive adhesive, metal solder, solder paste, and liquid metal; The second backplane includes a second substrate, a driving function layer and a second barrier layer located on a side of the second substrate close to the display assembly, the second barrier layer covers the driving function layer, the second binding terminals are located on the second barrier layer, and the driving function layer is connected to the corresponding second binding terminals and the third binding terminals; Wherein, the driving function layer is used to make a GOA circuit.

7. A display device, characterized in that: include: a housing forming a receiving cavity; and The spliced ​​display panel according to any one of claims 1 to 5, wherein the spliced ​​display panel is arranged in the accommodating cavity.

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