A low dynamic resistance enhancement mode GaN device

Abstract

The present invention discloses a low dynamic resistance enhanced GaN device. In the conventional enhanced HEMT enhanced device preparation process, an additional P-type doped GaN thin layer (i.e., p-GaN thin layer) is introduced by selectively etching the p-GaN epitaxial layer. The surface trap shielding effect and hole injection effect formed by the p-GaN thin layer in the device structure effectively suppress the ionization of traps in the device, and have a strong inhibitory effect on the current collapse effect. Therefore, the resistance degradation of the GaN device is improved, the dynamic stability of the device is improved, and the conduction characteristics of the device are optimized.

Description

Technical Field

[0001] The present invention relates to a GaN enhanced semiconductor device structure, and in particular to a low dynamic resistance enhanced GaN device, such as an enhanced GaN HEMT (high electron mobility transistor) device, and belongs to the field of power electronic devices. Background Art

[0002] When a high voltage is applied to the drain of a GaN device, the device's on-resistance will increase. This phenomenon is called the dynamic resistance degradation effect, which will affect the device's dynamic stability, degrade its on-characteristics, and limit the further development of GaN devices. Therefore, how to suppress the current collapse effect in GaN devices and improve the device's on-characteristics is a research hotspot for GaN devices.

[0003] In the prior art, Panasonic Electric Co., Ltd. proposed to introduce an additional layer of p-GaN structure connected to the drain in the drain region through selective etching to suppress the current collapse effect (see the literature: H. Okita, M. Hikita, A. Nishio, et al. Through Recess and Regrowth Gate Technology for Realizing Process Stability of GaN-Based Gate Injection Transistors [J]. IEEE Transactions on Electron Devices, 2017, 64 (3): 1026-1031.). In order to realize an enhancement-mode device, this technology needs to completely etch away the barrier layer in the gate region, and then epitaxially grow a thinner barrier layer after etching to form a two-dimensional electron gas channel in the gate region, which makes the device preparation process more complicated and the threshold voltage of the device difficult to accurately control. In addition, completely etching away the barrier layer will expose the channel layer to the etching gas, causing more damage and defects in the channel layer, and reducing the mobility of the two-dimensional electron gas.

[0004] In the prior art, a polarization superjunction field effect transistor with a long p-GaN gate was proposed by Japan's POWDEC (S.Hirata, F.Nakamura and H.Kawai, et al. 600V Switching Characteristics of GaN Polarization SuperJunction (PSJ) Transistors on Sapphire substrate. Autumn meeting of the Japanese Applied Physics, 2014) to improve the breakdown voltage of the device. However, the device is a depletion-type (normally open) device, which increases the complexity of circuit design and reduces system reliability in the circuit. Summary of the invention

[0005] In view of the problem of on-resistance degradation caused by the current collapse effect in existing GaN HEMT devices, the present invention first provides a novel enhanced GaN HEMT device structure to suppress the current collapse effect and increase the concentration of two-dimensional electron gas in the channel to improve the dynamic resistance degradation phenomenon. In order to enhance the suppression of the dynamic resistance degradation effect and simplify the process steps, the device structure of the present invention is as follows Figure 1 As shown in the figure, in the traditional HEMT enhancement device preparation process, an additional P-type doped GaN thin layer (i.e., p-GaN thin layer) is introduced by selectively etching the p-GaN epitaxial layer. The p-GaN thin layer covers the surface of the barrier layer and is connected to the p-GaN cap layer, which can shield the traps on the surface of the barrier layer. The p-GaN thin layer will inject holes into the device, ionizing traps in the composite device, and effectively suppress the current collapse effect. In the preparation process, there is no need to perform additional etching steps on the barrier layer, and accurate control of the threshold voltage is achieved.

[0006] Specifically, the technical solution of the present invention is as follows:

[0007] An enhancement mode GaN HEMT device, such as Figure 1 As shown, it includes a substrate and a buffer layer, a GaN channel layer and an AlGaN barrier layer stacked in sequence from bottom to top on the substrate, characterized in that a p-GaN cap layer and a p-GaN thin layer are formed by selectively etching a p-GaN epitaxial layer on the AlGaN barrier layer, and the p-GaN thin layer covers the surface of the AlGaN barrier layer and is connected to the p-GaN cap layer; the source and the drain are arranged on the upper surface of the AlGaN barrier layer, the gate is located on the upper surface of the p-GaN cap layer, and the gate and the p-GaN thin layer are located between the source and the drain.

[0008] The p-GaN layer in the enhanced GaN HEMT device structure of the present invention can raise the conduction band energy level at the two-dimensional electron gas channel, thereby realizing enhanced device technology, such as Figure 2 As shown in the figure, the distribution of the two-dimensional electron gas in the device without gate bias is shown. The two-dimensional electron gas in the area covered by the p-GaN layer in the device is completely depleted, making the device appear to be in the off state without external bias. At the same time, because the p-GaN thin layer covers the surface of the AlGaN barrier layer, it has a shielding effect on the surface traps of the AlGaN layer, which can weaken the trapping effect of the barrier layer surface traps on electrons and suppress the current collapse effect caused by the trapping of electrons by the barrier layer surface traps. In addition, Figure 3 As shown, when the gate-source voltage difference V GS When >0V, the p-GaN layer will inject holes into the device, and the holes will neutralize the negative charge centers in the device buffer layer, reducing the repulsive effect of the negative charge centers on the two-dimensional electron gas, thereby effectively inhibiting the degradation of dynamic conduction characteristics caused by the deep energy level negative charge centers in the buffer layer. The extended p-GaN thin layer is connected to the gate, so the p-GaN thin layer can play the same role as the gate, and can induce more two-dimensional electron gas under the barrier layer by applying a bias voltage to the gate, optimizing the conduction characteristics of the device and reducing the conduction loss of the device.

[0009] The p-GaN thin layer may cover the entire barrier layer surface or only cover the vicinity of the gate. The p-GaN thin layer may have a uniform thickness or vary in thickness in different regions. It may be in the shape of a long strip, a step, etc. when viewed from its longitudinal section.

[0010] The thickness of the p-GaN thin layer is preferably 1 nm to 400 nm, more preferably 100 nm, depending on different design requirements and preparation processes.

[0011] In one embodiment of the present invention, the p-GaN thin layer is connected to the drain through a metal electrode, and a Schottky contact is formed between the metal electrode and the p-GaN thin layer. When the device is turned off, the Schottky junction will be reverse biased to assist the p-GaN depletion and improve the voltage resistance performance of the device.

[0012] In another embodiment of the present invention, a p-GaN cap layer and a second gate thereon are additionally added between the source and the gate, and the switching of the common device is controlled by the second gate, thereby realizing a cascode structure.

[0013] The p-GaN thin layer can be introduced into various semiconductor devices, such as GaN LEDs, MIS structure enhanced HEMT devices, Schottky diodes, PN junction diodes and other GaN power devices, which are beneficial to improving the current collapse effect.

[0014] The present invention also provides a GaN diode, comprising a substrate and a buffer layer, a GaN channel layer and an AlGaN barrier layer stacked in sequence from bottom to top on the substrate, characterized in that a p-GaN cap layer and a p-GaN thin layer are formed by selectively etching a p-GaN epitaxial layer on the AlGaN barrier layer, the p-GaN thin layer covers the surface of the AlGaN barrier layer and is connected to the p-GaN cap layer; an anode and a cathode are arranged on the upper surface of the AlGaN barrier layer, a gate is located on the upper surface of the p-GaN cap layer, the gate and the p-GaN thin layer are located between the anode and the cathode, and the anode is electrically connected to the gate.

[0015] In the above-mentioned GaN diode, the shape, thickness, doping concentration and other parameters of the p-GaN thin layer vary in the same way as the p-GaN HEMT device, depending on different design requirements and preparation processes. Its longitudinal cross-sectional shape can be a long strip, a step shape, etc., and its thickness is preferably 1nm to 400nm.

[0016] Beneficial effects of the present invention:

[0017] The surface trap shielding effect and hole injection effect formed by the p-GaN thin layer in the novel device structure provided by the present invention effectively suppress the ionization of traps in the device, and have a strong inhibitory effect on the current collapse effect. Therefore, the resistance degradation of the GaN device is improved, the dynamic stability of the device is improved, and the conduction characteristics of the device are optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a two-dimensional cross-sectional view of the enhanced GaN HEMT device proposed in the present invention.

[0019] Figure 2 exhibit Figure 1 The figure shows the distribution of the two-dimensional electron gas in the device without an external bias. It can be seen that p-GaN will deplete the two-dimensional electron gas in the channel, thereby producing an enhancement-mode device.

[0020] Figure 3 yes Figure 1 Schematic diagram of the hole injection phenomenon stimulated by the p-GaN thin layer in the device shown.

[0021] Figure 4 It is a two-dimensional cross-sectional view of the device of the second embodiment of the present invention, and the p-GaN thin layer changes from a long strip to a step shape.

[0022] Figure 5 It is a two-dimensional cross-sectional view of the device of the third embodiment of the present invention, in which a new metal electrode is added between the p-GaN thin layer and the drain electrode to form a Schottky electrode contact with the p-GaN thin layer.

[0023] Figure 6It is a two-dimensional cross-sectional view of a device according to a fourth embodiment of the present invention. The device is a cascode structure, and a second gate is added to jointly control the switching of the device.

[0024] Figure 7 It is a two-dimensional cross-sectional view of the device of the fifth embodiment of the present invention, which is a GaN diode, in which the gate on the p-GaN layer of the device is connected to the anode. DETAILED DESCRIPTION

[0025] Embodiment 1: Enhanced-mode GaN HEMT device structure in the present invention

[0026] Figure 1 is a cross-sectional view of a GaN device according to a first embodiment of the present invention, such as Figure 1 As shown, the device includes a substrate 1 required for epitaxy, which can be a silicon substrate, a sapphire substrate and a silicon carbide substrate; a buffer layer 2 that can balance the stress in the epitaxy process, reduce the device leakage current and increase the breakdown voltage; a GaN channel layer 3 that provides a conductive channel; an AlGaN barrier layer 4 that generates a two-dimensional electron gas through a polarization effect; a p-GaN cap layer 5 that depletes the two-dimensional electron gas; a p-GaN thin layer 6 for shielding surface traps of the barrier layer and injecting holes into the negative charge center in the composite buffer layer; contact electrodes such as a gate 7, a drain 8, and a source 9, wherein the source and the drain are respectively prepared at both ends of the device by ohmic contact, and the gate is prepared on the p-GaN cap layer; and structures such as a passivation layer and a field plate that are necessary in traditional p-GaN devices, although not shown in the figure, corresponding structures are included in this example and other examples described later.

[0027] In addition, changes in parameters such as the length, thickness, and doping concentration of the extended p-GaN thin layer 6 are all within the scope of the present invention. The p-GaN thin layer 6 can cover the entire surface of the barrier layer, or only cover near the gate, and its length can vary. The thickness of the p-GaN thin layer 6 varies from 1nm to 400nm, with an optimal value of 100nm, depending on different design requirements and preparation processes. The doping concentration of the p-GaN thin layer 6 can vary within a reasonable range, which is related to the device threshold voltage design and doping process. It can be understood that without departing from the scope of the present invention, there may be other structures and other examples of changes. Furthermore, different examples, structures, and processes can be combined with each other.

[0028] The examples shown in the accompanying drawings can be used to manufacture the novel p-GaN HEMT device. However, the structure is not limited to this application mode. Any suitable semiconductor device can be manufactured according to the examples of the present invention, such as GaN LED, MIS structure enhanced HEMT device, Schottky diode, PN junction diode and other GaN power devices, which are all beneficial to improving the current collapse effect.

[0029] Embodiment 2: Enhanced-mode GaN HEMT device structure of the present invention

[0030] Figure 4 This is a cross-sectional view of a GaN device according to the second embodiment of the present invention. The GaN device of this embodiment is different from the first embodiment in that the p-GaN thin layer is changed from a long strip to a step shape. Other structures and effects are consistent with the first embodiment.

[0031] Embodiment 3: Enhanced-mode GaN HEMT device structure in the present invention

[0032] Figure 5 It is a cross-sectional view of the GaN device involved in the third example of the present invention. The GaN device of this example is different from the first and second examples. It has an additional metal electrode 10 connected to the drain 9 between the drain 9 and the p-GaN thin layer 6. The metal electrode 10 forms a Schottky contact with the p-GaN thin layer 6. When turned off, the Schottky junction will be reverse biased to assist the p-GaN depletion and improve the withstand voltage performance of the device. Other structures and effects are consistent with the first example.

[0033] Embodiment 4: Enhanced-mode GaN HEMT device structure of the present invention

[0034] Figure 6 It is a cross-sectional view of the GaN device cascode involved in the fourth example of the present invention. The GaN device of this example has an additional p-GaN cap layer 11 and a second gate 12 between the source 8 and the gate 7. The second gate 12 and the gate 7 are used to jointly control the switching of the device, and the external bias voltage of the gate 7 can also be kept unchanged to suppress the current collapse effect and induce more channel electrons.

[0035] Embodiment 5: GaN diode device structure in the present invention

[0036] Figure 7 It is a cross-sectional view of the GaN device involved in the fifth example of the present invention. The GaN device in this example is a diode, in which the drain 9 and the source 8 are replaced by the cathode 14 and the anode 13 of the diode. The anode 13 can be an ohmic contact or a Schottky contact, which depends on the design. The anode 13 is connected to the gate 7 through an external connection line 15 or other means.

Claims

1. An enhanced GaN HEMT device, comprising a substrate and a buffer layer, a GaN channel layer and an AlGaN barrier layer stacked sequentially from bottom to top on the substrate, characterized in that: A p-GaN cap layer and a p-GaN thin layer are formed by selectively etching a p-GaN epitaxial layer on an AlGaN barrier layer, wherein the p-GaN thin layer covers the surface of the AlGaN barrier layer and is connected to the p-GaN cap layer; a source electrode and a drain electrode are arranged on the upper surface of the AlGaN barrier layer, a gate electrode is arranged on the upper surface of the p-GaN cap layer, the gate electrode and the p-GaN thin layer are arranged between the source electrode and the drain electrode, and the p-GaN thin layer is arranged between the gate electrode and the drain electrode; when there is no gate bias, there is no two-dimensional electron gas under the p-GaN cap layer and the p-GaN thin layer; when a bias voltage is applied to the gate electrode, a two-dimensional electron gas is induced under the barrier layer below the p-GaN cap layer and the p-GaN thin layer; the p-GaN thin layer is connected to the drain electrode through a metal electrode, and a Schottky contact is formed between the metal electrode and the p-GaN thin layer.

2. The enhancement mode GaN HEMT device according to claim 1, characterized in that: The thickness of the p-GaN thin layer is uniform or changes in a step-like manner.

3. The enhancement mode GaN HEMT device according to claim 1, characterized in that: The thickness of the p-GaN thin layer is 1-400 nm.

4. The enhancement mode GaN HEMT device according to claim 1, characterized in that: Another p-GaN cap layer is placed between the source and the gate, with a second gate on top.

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