Single-chip optical transceiver

Abstract

This disclosure relates to single-chip optical transceivers. An optoelectronic device is disclosed, comprising a first semiconductor die having a first front surface and a first rear surface, and including at least one avalanche photodetector configured to output electrical pulses in response to photons incident on the first front surface. A second semiconductor die having a second front surface and a second rear surface, the second front surface being bonded to the first rear surface, and the second semiconductor die including a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and a transmitter drive circuit configured to drive a pulsed optical transmitter. A third semiconductor die having a third front surface and a third rear surface, the third front surface being bonded to the second rear surface, and the third semiconductor die including logic circuitry coupled to control the photodetector receiver analog circuitry and the transmitter drive circuitry, and to receive and process the electrical pulses output by the at least one avalanche photodetector.

Description

Technical Field

[0001] The present invention relates generally to optoelectronic devices and methods for manufacturing the same, and more specifically to integrated optical transceivers. Background Technology

[0002] Sensors used for direct time-of-flight (dToF) depth measurements typically consist of an array of one or more laser emitters (such as vertical-cavity surface-emitting lasers (VCSELs)) and single-photon detectors (such as single-photon avalanche diodes (SPADs)). One or more emitters direct light pulses toward the target scene, and the detectors output electrical pulses in response to incident photons reflected from the scene. The time span between the emitted light pulse and the resulting electrical pulse indicates the time of flight of the photon, thus indicating the distance to a point in the scene where the photon was reflected. Summary of the Invention

[0003] The embodiments of the present invention described below provide integrated optical transceivers and methods for manufacturing such transceivers.

[0004] Therefore, according to one embodiment of the present invention, an optoelectronic device is provided, comprising a first semiconductor die having a first front surface and a first rear surface, and including at least one avalanche photodetector configured to output an electrical pulse in response to a photon incident on the first front surface. A second semiconductor die having a second front surface and a second rear surface, the second front surface being bonded to the first rear surface, and the second semiconductor die including a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and an emitter drive circuit configured to drive a pulsed optical emitter. A third semiconductor die having a third front surface and a third rear surface, the third front surface being bonded to the second rear surface, and the third semiconductor die including logic circuitry coupled to control the photodetector receiver analog circuitry and the emitter drive circuitry, and to receive and process the electrical pulses output by the at least one avalanche photodetector.

[0005] In some embodiments, the first semiconductor die, the second semiconductor die, and the third semiconductor die comprise silicon dies. In some embodiments of these embodiments, the device comprises a III-V semiconductor die having a fourth front surface and a fourth rear surface, and includes an optical emitter coupled to be driven by emitter driving circuitry and configured to output optical pulses through the fourth front surface. In one embodiment, the optical emitter comprises a vertical-cavity surface-emitting laser (VCSEL). Additionally or alternatively, the first semiconductor die includes a first electrical contact located on the first front surface, and the III-V semiconductor die is mounted on the first front surface and includes a second electrical contact connected to the first electrical contact. In an alternative embodiment, the device includes a carrier substrate, wherein both the III-V semiconductor die and the third semiconductor die are mounted on the carrier substrate.

[0006] In the disclosed embodiments, the at least one avalanche photodetector includes a single-photon avalanche detector (SPAD). Alternatively or additionally, the at least one avalanche photodetector includes an array of multiple photodetectors.

[0007] In some embodiments, the first back surface is bonded to the second front surface via oxide bonding. In the disclosed embodiments, the second back surface and the third front surface include corresponding metal pads and are bonded together via hybrid bonding between the corresponding metal pads.

[0008] Additionally or alternatively, the logic circuit in the third die includes complementary metal-oxide-semiconductor (CMOS) logic components, while the driving circuit in the second die includes an n-type metal-oxide-semiconductor (NMOS) transistor or a p-type metal-oxide-semiconductor (PMOS) transistor.

[0009] Further or alternatively, the first semiconductor die includes a metal layer disposed between the at least one avalanche photodetector and the first rear surface and shielding the photodetector receiver analog circuitry from incident photons.

[0010] According to an embodiment of the present invention, a method for manufacturing an optoelectronic device is also provided. The method includes forming at least one avalanche photodetector in a first semiconductor die, the avalanche photodetector being configured to output electrical pulses in response to photons incident on a first front surface of the first semiconductor die. A second front surface of a second semiconductor die is bonded to a first rear surface of the first semiconductor die. A photodetector receiver analog circuit and an emitter driving circuit are formed in the second semiconductor die, the photodetector receiver analog circuit being coupled to the at least one avalanche photodetector, and the emitter driving circuit being configured to drive a pulsed optical emitter. A logic circuit is formed in a third semiconductor die. A third front surface of the third semiconductor die is bonded to a second rear surface of the second semiconductor die to couple the logic circuit to control the photodetector receiver analog circuit and the emitter driving circuit, and to receive and process the electrical pulses output by the at least one avalanche photodetector.

[0011] The invention will be more fully understood from the following detailed description of embodiments thereof, taken in conjunction with the accompanying drawings, in which: Attached Figure Description

[0012] Figure 1 This is a schematic cross-sectional view of an integrated optical transceiver according to one embodiment of the present invention;

[0013] Figure 2A and Figure 2B This is a schematic cross-sectional view illustrating details of an integrated optical transceiver according to an embodiment of the present invention;

[0014] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H This is a schematic cross-sectional view illustrating a series of manufacturing steps in the fabrication of a stacked optical transceiver chip according to an embodiment of the present invention; and

[0015] Figure 4A and Figure 4B These are schematic top and cross-sectional views of an optical transceiver device according to an embodiment of the present invention; and

[0016] Figure 5A and Figure 5B These are schematic top views and cross-sectional views of an optical transceiver device according to another embodiment of the present invention. Detailed Implementation

[0017] For mass-market applications of dToF depth sensing, the goal is to make the sensor as small and inexpensive as possible. To this end, for example, all driving and control functions should be integrated onto a single silicon chip along with an array of single-photon detectors (such as SPADs). Emitters (such as VCSELs) are typically fabricated on separate III-V semiconductor substrates (such as GaAs), but can be mounted on top of the silicon chip, for example, using VCSEL-on-silicon technology, or mounted adjacent to the silicon chip. The emitter (Tx) and detector (Rx) circuitry can then share circuit elements such as phase-locked loops (PLLs), temperature sensors, high-voltage bias circuitry, control and interface logic components, and memory, thereby reducing the overall chip area. However, creating such an integrated chip is challenging due to the need to integrate and accommodate the diverse requirements of optoelectronic devices, high-voltage driving components, and high-speed logic components.

[0018] The embodiments of the invention described herein solve this problem using three silicon wafers stacked and bonded together. After fabricating device components and bonding the wafers together, the bonded wafers are diced to produce multiple integrated transceiver chips. Therefore, each such chip comprises three semiconductor dies:

[0019] The first semiconductor die includes at least one avalanche photodetector that outputs an electrical pulse in response to photons incident on the front surface of the die. In embodiments described below, the first die includes a photodetector array, such as a SPAD, which enables the device to sense incoming photons with finer spatial resolution and / or a wider dynamic range.

[0020] • The front surface of the second semiconductor die is bonded, for example, by oxide bonding (also known as sequential bonding).

[0021] The second die is bonded to the rear surface of the first semiconductor die. The second die includes: a high-voltage circuit, including a photodetector receiver analog circuit coupled to a photodetector in the first die; and a transmitter drive circuit for driving a pulsed optical transmitter, such as a VCSEL.

[0022] The front surface of the third semiconductor die is bonded to the rear surface of the second semiconductor die, for example, through hybrid bonding between metal pads on both surfaces. The third die includes low-voltage logic circuitry that controls the analog circuitry of the photodetector receiver and the transmitter drive circuitry, and receives and processes electrical pulses output by the photodetector.

[0023] The terms "high voltage" and "low voltage" are used in a relative sense because the range of "high" and "low" voltage depends on the technology used. For example, considering currently available technology, the logic circuitry in the third die may include complementary metal-oxide-semiconductor (CMOS) logic components that operate in a voltage range of 0.7 volts to 3 volts; while the drive circuitry in the second die includes n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors with thick oxide layers that operate in a voltage range of 3 volts to 10 volts. Alternatively, higher or lower voltage ranges may be used. In any case, applying different circuitry techniques in the second and third dies enables the stacked chips to simultaneously perform both the high-voltage drive functions and high-speed logic functions involved in the operation of an optical transceiver.

[0024] In some implementations, the optical emitter is formed on a III-V semiconductor die, such as a GaAs die, which may be mounted on a portion of the front surface of a first (silicon) die or mounted on a carrier substrate together with the stacked chips. In either case, combining the detector (Rx) and emitter drive (Tx) functions in a single stacked chip of this type reduces the net die area in several ways:

[0025] • It eliminates the need for inter-die interface circuitry when implementing Rx and Tx drive functions on separate chips and reduces the complexity of logic components.

[0026] • Since many pads (such as clock, power, and control lines) can be shared by Rx and Tx circuits, the total number of pads in the device is reduced.

[0027] • Enables Rx and Tx drivers to share high-speed analog and digital circuitry, such as oscillators, phase-locked loops (PLLs), and / or delay-locked loops (DLLs).

[0028] Figure 1 This is a schematic cross-sectional view of an integrated optical transceiver 20 according to one embodiment of the present invention. The transceiver 20 includes an integrated circuit (IC) chip composed of three semiconductor dies 22, 24, and 26 (e.g., silicon dies) stacked and bonded together. The components of the transceiver 20 are conceptually shown in… Figure 1 It is shown in the figure and is not drawn to scale.

[0029] SPADs 28 in die 22 receive photons via corresponding microlenses 30 on the front surface 32 of die 22 and output electrical pulses in response to incident photons. (For convenience and clarity, in the context of this specification and the claims, the term "front" refers to the side of transceiver 20 that receives photons, while "rear" refers to the opposite side.) Although a single row of SPADs 28 is shown in the figures, die 22 may include smaller or larger numbers of SPADs, ranging from a single SPAD to a two-dimensional array 33, including tens, hundreds, or even thousands of SPADs. The rear surface 34 of die 22 is bonded to the front surface 36 of die 24, for example, by oxidation (sequential) bonding 38. The rear surface 40 of die 24 is bonded to the front surface 42 of die 26, for example, by hybrid bonding 44. For convenience and clarity, in the following description, the surfaces of the die (such as surfaces 32, 34, 36, 40, and 42) are oriented in an XY plane, wherein the Z-axis extends through the die in a vertical direction.

[0030] Die 24 includes a photodetector receiver (Rx) analog circuitry 48 coupled to SPAD 28, and an emitter (Tx) drive circuitry 50 driving a pulsed optical emitter (such as VCSEL 52). In the illustrated embodiment, die 22 also includes a reference SPAD 46 or a reference SPAD array, which is also driven by the Rx analog circuitry 48. The purpose of the reference SPAD 46 is further described below. The Rx analog circuitry 48 performs functions including biasing, quenching, and recharging SPADs 28 and 46, as known in the art. VCSEL 52 is fabricated on a III-V group semiconductor die 54, such as a GaAs die, which is then mounted on the front surface 32 of die 22 and attached to the Tx drive circuitry 50 via electrical contacts 56. Contacts 56 include, for example, suitable metal bumps that are connected to the Tx drive circuitry 50 via vias 58. The Tx driver circuit outputs short high-voltage electrical pulses, which causes the VCSEL 52 to emit short, high-intensity light pulses.

[0031] Die 26 includes Rx logic circuitry 60 that controls and receives signals from Rx analog circuitry 48, and Tx logic circuitry 62 that controls Tx drive circuitry 50. The positions and relative areas of Rx logic circuitry 60 and Tx logic circuitry 62 do not need to be matched with the positions and relative areas of the drive circuitry in die 24. Tx logic circuitry 62 controls the timing of the optical pulse sequence emitted by VCSEL 52. Rx logic circuitry 60 receives and processes electrical pulses output by SPAD 28 to count incident photons and measure their timing relative to outgoing optical pulses. Shared circuitry 64 in die 26 performs high-speed timing and digital logic functions shared by and coordinated between Rx logic circuitry 60 and Tx logic circuitry 62. Shared circuitry 64 may include, for example, one or more oscillators, PLLs and / or DLLs, as well as memory and input / output circuitry.

[0032] Figure 2A and Figure 2B An integrated optical transceiver (such as transceiver 20) is shown according to an embodiment of the present invention. Figure 1 Schematic cross-sectional views of the details. These two figures show segments through dies 22, 24, and 26, including the associated portions of the single SPAD 28 and Rx analog circuitry 48 and Rx logic circuitry 60. Unless otherwise stated, the two embodiments are very similar, and the following description applies to both embodiments.

[0033] SPAD 28 includes anode contacts 70 and cathode contacts 72, which are connected to the Rx analog circuitry 48 via metal vias 74. Each SPAD is isolated from its neighbors in the SPAD array by a metal-filled backside deep trench 76. The drive circuitry 48 includes high-voltage transistors 78, such as NMOS or PMOS thick oxide transistors with metal interconnects 80. Figure 2B In one embodiment, a metal layer 82 (e.g., a tungsten layer) extends across the back side of the die 22. The metal layer 82 can be used to enhance the sensitivity of the SPAD 28 and shield the Rx analog circuitry 48 and other underlying circuitry from incident photons that could otherwise degrade device performance.

[0034] The hybrid bonding 44 between dies 24 and 26 is formed by bonding metal pads 84 and 86 (e.g., copper pads) together at the rear surface of die 24 and the front surface of die 26, respectively. The Rx logic circuit 60 includes a CMOS logic component 88 formed on the silicon substrate 90 of die 26. The CMOS logic component 88 is connected to the Rx analog circuit 48 through the metal layer 92 of die 26 and through pads 86 and 84.

[0035] Figures 3A to 3HThese are schematic cross-sectional views illustrating a series of manufacturing steps in the fabrication of transceiver 20 according to an exemplary embodiment. The steps shown in these figures are typically performed at the wafer level, and at the end of the process, the resulting stack of three wafers is diced to produce multiple transceiver chips. However, for simplicity, only a small portion of the wafers is shown in the figures, and the wafers are labeled in the figures as dies 22, 24, and 26, corresponding to the description above.

[0036] from Figure 3A Initially, an array of SPADs 28 is fabricated in the upper silicon wafer (die 22) by appropriate doping of the p-region and n-region, as is known in the art. Readout components 100, including gates and floating diffusion nodes, are deposited on the SPADs 28 and covered by an oxide layer 102, as... Figure 3B As shown. (Die 22 in) Figures 3A to 3F (The orientation of the middle part is reversed relative to its orientation in the aforementioned figures).

[0037] During the preparation for processing die 24, an etch stop layer 106 and a silicon layer 108 are deposited on the silicon substrate 104 of the intermediate wafer, as follows: Figure 3C As shown. Silicon layer 108 is covered by oxide layer 110. Then the intermediate wafer is flipped and oxidized and bonded to the oxide layer 102 at the top of the upper wafer to form oxide bonds 38, as shown. Figure 3D As shown. After bonding, the back side of the intermediate wafer is thinned, for example by grinding and selective etching to remove the silicon substrate 104 and the etch stop layer 106, as... Figure 3E As shown. Then, high-voltage circuits are fabricated in the intermediate wafer, such as... Figure 3F As shown. These circuits include transistors 78 (typically thick oxide PMOS or NMOS) and other sensor driver components, as well as contacts and wiring, including vias 74 and interconnects 80. For hybrid bonding purposes, copper pads 84 are deposited and etched on the top side of the wafer (in this inverted orientation).

[0038] For example, the circuitry of logic components 88 and the metal layer 92 on the substrate 90 of the bottom wafer (die 26) are fabricated separately using a CMOS process. Similarly, copper pads 86 are formed on the top side of this wafer. Then, the bonded upper and middle wafers (dies 22 and 24) are flipped and overlaid on the bottom wafer (die 26), as shown. Figure 3G As shown, pads 84 and 86 are aligned, and the wafer is annealed to form a hybrid bond 44 between the middle and bottom wafers. Finally, optical components, such as wavelength filters 112 and microlenses 30, are fabricated on SPAD 28. The wafer is then diced to produce multiple individual transceivers 20.

[0039] Figure 4A and Figure 4BThese are schematic top and cross-sectional views of an optical transceiver device 120 according to one embodiment of the present invention; the device 120 includes an integrated optical transceiver 20 as described above, wherein a VCSEL 52 on a III-V semiconductor die 54 is mounted on the upper surface 32 of the transceiver chip. The transceiver 20 is mounted on a carrier substrate 122, such as a ceramic printed circuit board.

[0040] VCSEL 52 emits photons toward the target scene through exit window 124. Photons reflected from the target scene are incident onto the array 33 of SPAD 28 through entrance window 126. In addition to array 33, transceiver 20 includes one or more reference SPADs 46, as described above. These reference SPADs receive stray photons reflected from VCSEL 52 and thus provide a starting signal for measuring the time of flight of photons received by SPAD 28 in array 33. The optical block 128 within device 120 prevents optical crosstalk between VCSEL 52 and SPADs in array 33.

[0041] Figure 5A and Figure 5B These are schematic top and cross-sectional views of an optical transceiver device 130 according to another embodiment of the present invention. In this embodiment, a III-V semiconductor die 54 having a VCSEL 52 is separately mounted on a carrier substrate 122 from a stacked SPAD chip 132. The chip 132 contains substantially the same components as the transceiver 20, but with a Tx drive circuit 50 ( Figure 1 The drive signal is output from the SPAD chip 132 to the III-V semiconductor die 54 via a conductor 134 on the carrier substrate 122, rather than via contacts located on the SPAD chip itself. In other respects, the operation of device 130 is similar to that of device 120. Figure 4A / Figure 4B ) operation.

[0042] Although the above embodiments are specifically designed for dToF depth sensing, the principles of the invention can be similarly applied (with necessary modifications) to the production and operation of other types of integrated optical transceivers for both depth sensing and other applications. Therefore, the specific types of optical transmitters and detectors used in the disclosed embodiments (i.e., VCSEL transmitters and SPAD detector arrays) can be replaced, for example, by other types of avalanche diodes or single-photon detectors, as well as other types of pulsed optical transmitters. Furthermore, although silicon technology is currently best suited for the production of the aforementioned stacked chips, the principles of the invention can be similarly applied to the production of stacked chips based on other types of semiconductors (such as III-V semiconductor dies). By appropriately selecting materials and techniques, this apparatus and method can be adapted to optical radiation in the infrared, visible, or even ultraviolet ranges. All these alternative embodiments and applications are considered to be within the scope of this invention.

[0043] Therefore, it should be understood that the above embodiments are cited by way of example, and the present invention is not limited to the contents specifically shown and described above. Rather, the scope of the present invention includes the various features described above, as well as combinations and sub-combinations of variations and modifications not disclosed in the prior art that would occur to those skilled in the art after reading the above description.

Claims

1. A photoelectric device, the photoelectric device comprising: A first semiconductor die has a first front surface and a first rear surface, and includes at least one avalanche photodetector configured to output an electrical pulse in response to a photon incident on the first front surface. The second semiconductor die has a second front surface and a second rear surface, the second front surface being bonded to the first rear surface, and the second semiconductor die includes a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and a transmitter drive circuit configured to drive a pulsed optical transmitter. and A third semiconductor die having a third front surface and a third rear surface, the third front surface being bonded to the second rear surface, and the third semiconductor die including logic circuitry coupled to control the photodetector receiver analog circuitry and the transmitter drive circuitry, and to receive and process the electrical pulses output by the at least one avalanche photodetector.

2. The apparatus of claim 1, wherein the first semiconductor die, the second semiconductor die, and the third semiconductor die comprise silicon dies.

3. The apparatus of claim 2, further comprising a III-V semiconductor die having a fourth front surface and a fourth rear surface, and including an optical emitter coupled to be driven by the emitter driving circuit and configured to output light pulses through the fourth front surface.

4. The apparatus of claim 3, wherein the optical emitter comprises a vertical-cavity surface-emitting laser.

5. The apparatus of claim 3, wherein the first semiconductor die includes a first electrical contact located on the first front surface, and wherein the III-V semiconductor die is mounted on the first front surface and includes a second electrical contact connected to the first electrical contact.

6. The apparatus of claim 3, further comprising a carrier substrate, wherein both the III-V semiconductor die and the third semiconductor die are mounted on the carrier substrate.

7. The apparatus according to any one of claims 1 to 6, wherein the at least one avalanche photodetector comprises a single-photon avalanche detector.

8. The apparatus according to any one of claims 1 to 6, wherein the at least one avalanche photodetector comprises an array of a plurality of photodetectors.

9. The apparatus according to any one of claims 1 to 6, wherein the first rear surface is bonded to the second front surface by an oxide bond.

10. The apparatus of claim 9, wherein the second rear surface and the third front surface comprise respective metal pads and are bonded together by hybrid bonding between the respective metal pads.

11. The apparatus according to any one of claims 1 to 6, wherein the logic circuit in the third semiconductor die comprises complementary metal-oxide-semiconductor logic components, and the driving circuit in the second semiconductor die comprises an n-type metal-oxide-semiconductor transistor or a p-type metal-oxide-semiconductor transistor.

12. The apparatus of any one of claims 1 to 6, wherein the first semiconductor die includes a metal layer disposed between the at least one avalanche photodetector and the first rear surface and thereby protects the photodetector receiver analog circuitry from photons incident on the first front surface.

13. A method for manufacturing a photoelectric device, the method comprising: At least one avalanche photodetector is formed in a first semiconductor die, the avalanche photodetector being configured to output an electrical pulse in response to a photon incident on a first front surface of the first semiconductor die; The second front surface of the second semiconductor die is bonded to the first rear surface of the first semiconductor die; A photodetector receiver analog circuit and a transmitter drive circuit are formed in the second semiconductor die, the photodetector receiver analog circuit being coupled to the at least one avalanche photodetector, and the transmitter drive circuit being configured to drive a pulsed optical transmitter. Logic circuits are formed in the third semiconductor die; as well as The third front surface of the third semiconductor die is bonded to the second rear surface of the second semiconductor die to couple the logic circuit to control the photodetector receiver analog circuit and the transmitter drive circuit, and to receive and process the electrical pulses output by the at least one avalanche photodetector.

14. The method of claim 13, wherein the first semiconductor die, the second semiconductor die, and the third semiconductor die comprise silicon dies.

15. The method of claim 14, further comprising a coupled III-V semiconductor die having a fourth front surface and a fourth rear surface, and including an optical emitter driven by the emitter driving circuitry to output light pulses through the fourth front surface.

16. The method according to any one of claims 13 to 15, wherein the at least one avalanche photodetector comprises one or more single-photon avalanche detectors.

17. The method of any one of claims 13 to 15, wherein bonding the second front surface of the second semiconductor die to the first rear surface of the first semiconductor die includes forming an oxide bond between the first rear surface and the second front surface.

18. The method of claim 17, wherein bonding the third front surface of the third semiconductor die to the second rear surface of the second semiconductor die includes forming corresponding metal pads on the second semiconductor die and the third semiconductor die, and bonding the third front surface to the second rear surface by hybrid bonding between the corresponding metal pads.

19. The method according to any one of claims 13 to 15, wherein the logic circuit in the third semiconductor die comprises complementary metal-oxide-semiconductor logic components, and the driving circuit in the second semiconductor die comprises an n-type metal-oxide-semiconductor transistor or a p-type metal-oxide-semiconductor transistor.

20. The method of any one of claims 13 to 15, further comprising depositing a metal layer on the first semiconductor die such that the metal layer is disposed between the at least one avalanche photodetector and the first rear surface and protects the photodetector receiver analog circuitry from photons incident on the first front surface.

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