Display panel and display device

Abstract

The present disclosure relates to the field of display technology, and proposes a display panel and a display device, wherein the display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, and the display panel also includes: a substrate, a light shielding layer, a first gate layer, and a second source-drain layer, wherein the light shielding layer is located on one side of the substrate, and the light shielding layer is a grid structure; the first gate layer is located on the side of the light shielding layer away from the substrate, the first gate layer includes a first conductive portion, and the first conductive portion is used to form a gate of the driving transistor; the second source-drain layer is located on the side of the first gate layer away from the substrate, and the second source-drain layer includes a power line; wherein the orthographic projection of the power line on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap, and the orthographic projection of the light shielding layer on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The display panel can improve the problem of unstable gate voltage of the driving transistor.

Description

[0001] This application is a divisional application of the invention application with an application date of March 19, 2021, Chinese application number 202180000505.6, and invention name “Array substrate, display panel and display device thereof”. Technical Field

[0002] Embodiments of the present disclosure relate to the field of display technology, and in particular, to a display panel and a display device. Background Art

[0003] Organic Light-Emitting Diode (OLED) display panels have the advantages of self-luminescence, high efficiency, bright colors, light weight and power saving, rollability and a wide temperature range. They have gradually been used in large-area display, lighting and automotive display fields. Summary of the invention

[0004] Embodiments of the present disclosure provide an array substrate and a related display panel and display device.

[0005] According to a first aspect of the present disclosure, an array substrate is provided, which includes a substrate. The array substrate also includes a plurality of sub-pixels arranged in a plurality of rows and columns on the substrate. At least one of the plurality of sub-pixels includes a pixel circuit. Each pixel circuit includes: a driving circuit, a voltage stabilizing circuit, a driving reset circuit and a light emitting reset circuit. The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current to a light emitting device. The voltage stabilizing circuit is coupled to the control terminal, the first node and the voltage stabilizing control signal input terminal of the driving circuit, and is configured to conduct the control terminal and the first node of the driving circuit under the control of the voltage stabilizing control signal from the voltage stabilizing control signal input terminal. The driving reset circuit is coupled to the driving reset control signal input terminal, the first node and the driving reset voltage terminal, and is configured to provide a driving reset voltage from the driving reset voltage terminal to the voltage stabilizing circuit under the control of the driving reset control signal from the driving reset control signal input terminal, so as to reset the control terminal of the driving circuit. The light emitting reset circuit is coupled to the light emitting reset control signal input terminal, the light emitting device and the light emitting reset voltage terminal, and is configured to provide a light emitting reset voltage from the light emitting reset voltage terminal to the light emitting device under the control of the light emitting reset control signal from the light emitting reset control signal input terminal, so as to reset the light emitting device. The array substrate also includes a driving reset voltage line and a light emitting reset voltage line. The driving reset voltage line is coupled to the driving reset voltage terminal to provide a driving reset voltage. The light emitting reset voltage line is coupled to the light emitting reset voltage terminal to provide a light emitting reset voltage.

[0006] In an embodiment of the present disclosure, the driving circuit includes a driving transistor. The voltage stabilizing circuit includes a voltage stabilizing transistor. The driving reset circuit includes a driving reset transistor. The light emitting reset circuit includes a light emitting reset transistor. The first electrode of the driving transistor is coupled to the first end of the driving circuit, the gate of the driving transistor is coupled to the control end of the driving circuit, and the second electrode of the driving transistor is coupled to the second end of the driving circuit. The first electrode of the voltage stabilizing transistor is coupled to the control end of the driving circuit, the gate of the voltage stabilizing transistor is coupled to the voltage stabilizing control signal input end, and the second electrode of the voltage stabilizing transistor is coupled to the first node. The first electrode of the driving reset transistor is coupled to the driving reset voltage end, the gate of the driving reset transistor is coupled to the driving reset control signal input end, and the second electrode of the driving reset transistor is coupled to the first node. The first electrode of the light emitting reset transistor is coupled to the light emitting reset voltage end, the gate of the light emitting reset transistor is coupled to the light emitting reset control signal input end, and the second electrode of the light emitting reset transistor is coupled to the first end of the light emitting device. The active layer of the voltage stabilizing transistor includes an oxide semiconductor material. The active layers of the driving transistor and the driving reset transistor include silicon semiconductor materials.

[0007] In an embodiment of the present disclosure, the active layer of the light emitting reset transistor includes an oxide semiconductor material.

[0008] In an embodiment of the present disclosure, the array substrate further includes: a first active semiconductor layer located on the substrate, the first active semiconductor layer including a silicon semiconductor material; and a second active semiconductor layer located on a side of the first active semiconductor layer away from the substrate and insulated and isolated from the first active semiconductor layer, the second active semiconductor layer including an oxide semiconductor material.

[0009] In an embodiment of the present disclosure, the first active semiconductor layer includes an active layer of a driving transistor and an active layer of a driving reset transistor. The second active semiconductor layer includes a first portion and a second portion arranged along a column direction. The first portion of the second active semiconductor includes an active layer of a voltage stabilizing transistor. The second portion of the second active semiconductor includes an active layer of a light emitting reset transistor.

[0010] In an embodiment of the present disclosure, the first portion of the second active semiconductor is aligned with the second portion of the second active semiconductor along a column direction.

[0011] In an embodiment of the present disclosure, the pixel circuit further includes a data writing circuit, a compensation circuit, a storage circuit and a light emitting control circuit. The data writing circuit is coupled to a data signal input terminal, a scan signal input terminal and a first terminal of a driving circuit, and is configured to provide a data signal from the data signal input terminal to the first terminal of the driving circuit under the control of a scan signal from the scan signal input terminal. The compensation circuit is coupled to a second terminal of the driving circuit, a first node and a compensation control signal input terminal, and is configured to perform threshold compensation on the driving circuit according to a compensation control signal from the compensation control signal input terminal. The storage circuit is coupled to a first power supply voltage terminal and a control terminal of the driving circuit, and is configured to store a voltage difference between the first power supply voltage terminal and the control terminal of the driving circuit. The light emitting control circuit is coupled to a light emitting control signal input terminal, a first power supply voltage terminal, a first terminal and a second terminal of the driving circuit, a light emitting reset circuit and a light emitting device, and is configured to apply a first power supply voltage from the first power supply voltage terminal to the driving circuit under the control of a light emitting control signal from the light emitting control signal input terminal, and to apply a driving current generated by the driving circuit to the light emitting device.

[0012] In an embodiment of the present disclosure, the data writing circuit includes a data writing transistor. The compensation circuit includes a compensation transistor. The storage circuit includes a storage capacitor. The light emitting control circuit includes a first light emitting control transistor and a second light emitting control transistor. The first electrode of the data writing transistor is coupled to the data signal input terminal, the gate of the data writing transistor is coupled to the scan signal input terminal, and the second electrode of the data writing transistor is coupled to the first terminal of the driving circuit. The first electrode of the compensation transistor is coupled to the second terminal of the driving circuit, the gate of the compensation transistor is coupled to the compensation control signal input terminal, and the second electrode of the compensation transistor is coupled to the first node. The first electrode of the storage capacitor is coupled to the first power supply voltage terminal, the second electrode of the storage capacitor is coupled to the control terminal of the driving circuit, and is configured to store the voltage difference between the first power supply voltage terminal and the control terminal of the driving circuit. The first electrode of the first light emitting control transistor is coupled to the first power supply voltage terminal, the gate of the first light emitting control transistor is coupled to the light emitting control signal input terminal, and the second electrode of the first light emitting control transistor is coupled to the first terminal of the driving circuit. The first electrode of the second light-emitting control transistor is coupled to the second end of the driving circuit, the gate of the second light-emitting control transistor is coupled to the light-emitting control signal input end, and the second electrode of the second light-emitting control transistor is coupled to the first electrode of the light-emitting device.

[0013] In an embodiment of the present disclosure, the first active semiconductor layer includes an active layer of a data writing transistor, a compensation transistor, a first light emission control transistor, and a second light emission control transistor.

[0014] In an embodiment of the present disclosure, the light emitting reset control signal and the light emitting control signal are the same signal.

[0015] In an embodiment of the present disclosure, the scanning signal and the compensation control signal are the same signal.

[0016] In an embodiment of the present disclosure, the array substrate further includes a first conductive layer located between the first active semiconductor layer and the second active semiconductor layer and insulated and isolated from the first active semiconductor layer and the second active semiconductor layer. The first conductive layer includes a drive reset control signal line, a scan signal line, a gate of a drive transistor, a first electrode of a storage capacitor, and a light emitting control signal line arranged in sequence along a column direction. The drive reset control signal line is coupled to a drive reset control signal input terminal and is configured to provide a drive reset control signal thereto. The scan signal line is coupled to a scan signal input terminal and a compensation control signal input terminal, is configured to provide a scan signal to the scan signal input terminal, and is configured to provide a compensation control signal to the compensation control signal input terminal. The first electrode of the storage capacitor is an integral structure with the gate of the drive transistor. And the light emitting control signal line is coupled to the light emitting control signal input terminal and is configured to provide a light emitting control signal thereto.

[0017] In the embodiment of the present disclosure, the portion where the orthogonal projection of the driving reset control signal line on the substrate overlaps with the orthogonal projection of the first active semiconductor layer on the substrate is the gate of the driving reset transistor. The portion where the orthogonal projection of the scanning signal line on the substrate overlaps with the orthogonal projection of the first active semiconductor layer on the substrate is the gate of the compensation transistor and the gate of the data writing transistor. And the portion where the orthogonal projection of the light emission control signal line on the substrate overlaps with the orthogonal projection of the first active semiconductor layer on the substrate is the gate of the first light emission control transistor and the gate of the second light emission control transistor.

[0018] In an embodiment of the present disclosure, the array substrate further includes a second conductive layer located between the first conductive layer and the second active semiconductor layer and insulated and isolated from the first conductive layer and the second active semiconductor layer. The second conductive layer includes a voltage stabilization control signal line arranged along the column direction, a second pole of the storage capacitor, a first power supply voltage line and a light-emitting reset control signal line. The voltage stabilization control signal line is coupled to the voltage stabilization control signal input terminal and is configured to provide a voltage stabilization control signal thereto. The first power supply voltage line is coupled to the first power supply voltage terminal and is configured to provide a first power supply voltage thereto. The second pole of the storage capacitor overlaps at least partially with the positive projection of the first pole of the storage capacitor on the substrate. The second pole of the storage capacitor is formed integrally with the first power supply voltage line. And the light-emitting reset control signal line is coupled to the light-emitting reset control signal input terminal and is configured to provide a light-emitting reset control signal thereto.

[0019] In the embodiment of the present disclosure, the overlapping portion of the orthographic projection of the voltage stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first control electrode of the voltage stabilizing transistor. And the overlapping portion of the orthographic projection of the light emitting control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the first control electrode of the light emitting reset transistor.

[0020] In an embodiment of the present disclosure, the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated from the second active semiconductor layer. The third conductive layer includes a voltage stabilization control signal line, a light emitting reset control signal line, and a light emitting reset voltage line arranged along a column direction.

[0021] In the embodiment of the present disclosure, the overlapping part of the orthographic projection of the voltage stabilizing control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second control electrode of the voltage stabilizing transistor. The overlapping part of the orthographic projection of the light emitting control signal line on the substrate and the orthographic projection of the second active semiconductor layer on the substrate is the second control electrode of the light emitting reset transistor. And the light emitting reset voltage line is coupled to the second active semiconductor layer via a via hole to form the first electrode of the light emitting reset transistor.

[0022] In an embodiment of the present disclosure, the array substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate and insulated from the third conductive layer, the fourth conductive layer including a first connection portion, a second connection portion, a third connection portion, a fourth connection portion, a fifth connection portion, a sixth connection portion, a seventh connection portion, and an eighth connection portion. The first connection portion is used as a driving reset voltage line. The first connection portion is coupled to the drain region of the driving reset transistor via a via hole to form the first pole of the driving reset transistor. The second connection portion is coupled to the light-emitting reset voltage line via a via hole. The third connection portion is coupled to the drain region of the data writing transistor via a via hole to form the first pole of the data writing transistor. The fourth connection portion is coupled to the source region of the driving reset transistor and the source region of the compensation transistor via a via hole to form the second pole of the driving reset transistor and the second pole of the compensation transistor, respectively. The fourth connection portion is coupled to the source region of the voltage stabilizing transistor via a via hole to form the second pole of the voltage stabilizing transistor. The fifth connection portion is coupled to the gate of the driving transistor and the first electrode of the storage capacitor via a via hole, and the fifth connection portion is coupled to the drain region of the voltage stabilizing transistor via a via hole to form the first electrode of the voltage stabilizing transistor. The sixth connection portion is coupled to the drain region of the first light emission control transistor via a via hole to form the first electrode of the first light emission control transistor. The seventh connection portion is coupled to the source region of the second light emission control transistor via a via hole to form the second electrode of the second light emission control transistor, and the seventh connection portion is coupled to the source region of the light emission reset transistor via a via hole to form the second electrode of the light emission reset transistor. And the eighth connection portion is coupled to the source region of the light emission reset transistor via a via hole to form the first electrode of the light emission reset transistor.

[0023] In an embodiment of the present disclosure, the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer facing away from the substrate and insulated from the fourth conductive layer. The fifth conductive layer includes a data signal line, a first power supply voltage line, and a second power supply voltage line arranged in a row direction. The data signal line extends in a column direction and is coupled to a third connection portion of the fourth conductive layer via a via hole. The first power supply voltage line extends in a column direction and is coupled to a third connection portion of the fourth conductive layer via a via hole. And the second power supply voltage line extends in a column direction and is coupled to a seventh connection portion of the fourth conductive layer via a via hole.

[0024] According to a second aspect of the present disclosure, a display panel is provided, comprising an array substrate according to any one of the first aspects.

[0025] According to a third aspect of the present disclosure, a display device is provided, comprising a display panel according to any one of the second aspects.

[0026] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are for illustrative purposes only of selected embodiments, not all possible implementations, and are not intended to limit the scope of the present application, wherein:

[0028] Figure 1 A schematic block diagram of an array substrate according to the present disclosure is shown;

[0029] Figure 2 A schematic block diagram of a sub-pixel according to an embodiment of the present disclosure is shown;

[0030] Figure 3 The embodiment according to the present disclosure is shown Figure 2 A schematic diagram of a pixel circuit in FIG.

[0031] Figure 4 The driving method according to the embodiment of the present disclosure is shown. Figure 3 A timing diagram of signals of a pixel circuit in FIG.

[0032] Figure 5-11 A schematic plan view of each layer in an array substrate according to an embodiment of the present disclosure is shown;

[0033] Fig.12 A schematic plan layout diagram of a pixel circuit including a stacked active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer is shown;

[0034] Fig.13 The embodiment according to the present disclosure is shown Fig.12 A schematic diagram of a cross-sectional structure of an array substrate taken along line A1A2 in FIG.

[0035] Fig.14 The embodiment according to the present disclosure is shown Fig.12 A schematic diagram of a cross-sectional structure of an array substrate taken along line A1A2 in FIG.

[0036] Fig.15 A schematic block diagram of an array substrate according to an embodiment of the present disclosure is shown;

[0037] Fig.16 A schematic block diagram of an array substrate according to an embodiment of the present disclosure is shown;

[0038] Fig.17A schematic block diagram of an array substrate according to an embodiment of the present disclosure is shown;

[0039] Fig.18 A schematic plan layout diagram of a pixel circuit including a stacked shielding layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer is shown;

[0040] Fig.19 A schematic structural diagram of a display panel according to an embodiment of the present disclosure is shown;

[0041] Fig. 20 A schematic structural diagram of a display device according to an embodiment of the present disclosure is shown;

[0042] Fig.21 A schematic diagram of a pixel circuit according to an embodiment of the present disclosure is shown;

[0043] Fig. 22 A schematic diagram showing a shielding layer according to an embodiment of the present disclosure is shown;

[0044] Fig.23 shows a planar layout of a pixel circuit according to an embodiment of the present disclosure;

[0045] Fig.24 shows a planar layout of a pixel circuit according to an embodiment of the present disclosure;

[0046] Fig.25 shows a planar layout of a pixel circuit according to an embodiment of the present disclosure;

[0047] Fig.26 A schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure is shown;

[0048] Fig. 27 This is a schematic diagram of the circuit structure of a pixel driving circuit in an exemplary embodiment of the array substrate disclosed in the present invention;

[0049] Fig.28 for Fig. 27 A timing diagram of each node in a driving method of a pixel driving circuit;

[0050] Fig.29 This is a structural layout of an exemplary embodiment of the array substrate disclosed in the present invention;

[0051] Fig.30 for Fig.29 The structural layout of the middle light-shielding layer;

[0052] Fig.31 for Fig.29 The structural layout of the first active layer in FIG.

[0053] Fig.32 for Fig.29The structural layout of the first gate layer;

[0054] Fig.33 for Fig.29 The structural layout of the second gate layer;

[0055] Fig.34 for Fig.29 The structural layout of the second active layer;

[0056] Fig.35 for Fig.29 The structural layout of the third gate layer;

[0057] Fig.36 for Fig.29 The structural layout of the first source and drain layer;

[0058] Fig.37 for Fig.29 The structural layout of the middle light-shielding layer and the first active layer;

[0059] Fig.38 for Fig.29 The structural layout of the middle light shielding layer, the first active layer, and the first gate layer;

[0060] Fig.39 for Fig.29 Structural layout of the middle light shielding layer, the first active layer, the first gate layer, and the second gate layer;

[0061] Fig.40 for Fig.29 A structural layout of a middle light shielding layer, a first active layer, a first gate layer, a second gate layer, and a second active layer;

[0062] Fig.41 for Fig.29 The structural layout of the middle light shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer;

[0063] Fig.42 This is a structural layout of an exemplary embodiment of the array substrate disclosed in the present invention;

[0064] Fig.43 for Fig.42 The structural layout of the second source and drain layer in FIG.

[0065] Fig.44 This is a structural layout of an exemplary embodiment of the array substrate disclosed in the present invention;

[0066] Fig.45 for Fig.44 The structural layout of the second source and drain layer in FIG.

[0067] Fig.46is a schematic structural diagram of a second initial signal line in another exemplary embodiment of the array substrate disclosed in the present invention;

[0068] Fig.47 is a schematic structural diagram of a second initial signal line in another exemplary embodiment of the array substrate disclosed in the present invention;

[0069] Fig.48 for Fig.42 Partial cross-sectional view along dotted line B.

[0070] Corresponding reference numerals indicate corresponding parts or features throughout the several views of the drawings. DETAILED DESCRIPTION

[0071] First, it should be noted that, unless the context clearly indicates otherwise, the singular form of the words used in this document and the appended claims includes the plural, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" will be interpreted as inclusive rather than exclusive. Similarly, the terms "include" and "or" should be interpreted as inclusive unless otherwise specified herein. Where the term "example" is used in this document, especially when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0072] In addition, it should be noted that when introducing elements of the present application and embodiments thereof, the articles "a", "an", "the" and "said" are intended to indicate the presence of one or more elements; unless otherwise specified, "plurality" means two or more; the terms "comprising", "including", "containing" and "having" are intended to be inclusive and indicate that there may be additional elements besides the listed elements; the terms "first", "second", "third", etc. are used only for descriptive purposes and are not to be understood as indicating or implying relative importance and order of formation.

[0073] In addition, in the drawings, the thickness and area of ​​each layer are exaggerated for clarity. It should be understood that when a layer, region, or component is mentioned as being "on" another part, it means that it is directly located on the other part, or there may be other components in between. On the contrary, when a component is mentioned as being "directly" located on another component, it means that there is no other component in between.

[0074] In a common array substrate, the reset voltage is provided by the same reset voltage line to reset the light emitting device and the pixel circuit. The reset voltage value is set by considering the energy consumption level of the pixel circuit, the display effect after compensation, and keeping the reset light emitting device in an unlit state. In this case, the energy consumption of the pixel circuit, the display effect after compensation, and the charging time of the reset light emitting device cannot be in the optimal state at the same time, thereby affecting the energy consumption, response speed, accuracy, and display effect of the pixel circuit.

[0075] At least some embodiments of the present disclosure provide an array substrate, which includes two reset voltage lines, a driving reset voltage line and a light emitting reset voltage line. The driving reset voltage line is coupled to the driving reset voltage terminal to provide a driving reset voltage. The light emitting reset voltage line is coupled to the light emitting reset voltage terminal to provide a light emitting reset voltage. The driving reset voltage can be set in consideration of the energy consumption level and reset effect of the pixel circuit. When the energy consumption level is relatively low, the pixel circuit is reset more thoroughly, thereby improving the display effect. The light emitting reset voltage line is coupled to the light emitting reset voltage terminal to provide a light emitting reset voltage. The light emitting reset voltage can be set just to keep the light emitting device from being lit, thereby reducing the charging time of the light emitting device before emitting light, thereby increasing the response speed of the pixel circuit to the light emitting signal, shortening the response time, and increasing the accuracy in probability.

[0076] The array substrate provided in the embodiments of the present disclosure is described below in a non-restrictive manner in conjunction with the accompanying drawings. As described below, different features in these specific embodiments can be combined with each other without conflicting with each other to obtain new embodiments, and these new embodiments also fall within the scope of protection of the present disclosure.

[0077] Figure 1 FIG. 1 is a schematic diagram of an array substrate 10 according to the present disclosure. Figure 1 As shown, the array substrate 10 includes a substrate 300 and a plurality of sub-pixels SPX arranged in multiple rows and columns on the substrate 300. The substrate may be a glass substrate, a plastic substrate, etc. The display area of ​​the substrate 300 includes a plurality of pixel units PX, and each pixel unit may include a plurality of sub-pixels SPX, for example, three. The sub-pixels SPX are arranged at intervals along the row direction X and the column direction Y. The row direction X and the column direction Y are perpendicular to each other. At least one of the sub-pixels SPX includes a pixel circuit. The array substrate 10 also includes a drive reset voltage line and a light emitting reset voltage line. The drive reset signal line is coupled to the drive reset voltage terminal and is configured to provide a drive reset voltage thereto. The light emitting reset voltage line is coupled to the light emitting reset voltage terminal and is configured to provide a light emitting reset voltage thereto. The circuit will be described below with reference to FIG. Figure 5-11 The layout of the setting and position of the voltage of the driving reset signal line and the light emission reset control signal line is described in detail.

[0078] In the embodiment of the present disclosure, each pixel circuit includes: a driving circuit, a voltage stabilizing circuit, a driving reset circuit, a light emitting reset circuit, a data writing circuit, a compensation circuit, a storage circuit and a light emitting control circuit. Figure 2 The pixel circuit is described in detail.

[0079] Figure 2 Schematic block diagram of a sub-pixel according to some embodiments of the present disclosure is shown. Figure 2 As shown, the sub-pixel SPX includes a pixel circuit 100 and a light emitting device 200. The pixel circuit 100 includes a driving circuit 110, a voltage stabilizing circuit 120, a driving reset circuit 130 and a light emitting reset circuit 140, a data writing circuit 150, a compensation circuit 160, a storage circuit 170 and a light emitting control circuit 180.

[0080] like Figure 2 As shown, the driving circuit 110 includes a control terminal G, a first terminal F, and a second terminal S. The driving circuit 110 is configured to provide a driving current to the light emitting device 200 under the control of a control signal from the control terminal G.

[0081] The voltage regulator circuit 120 is coupled to the control terminal G of the driving circuit 110, the first node N1 and the voltage regulation control signal input terminal Stv. The voltage regulator circuit 120 is configured to conduct the control terminal G of the driving circuit 110 and the first node N1 under the control of the voltage regulation control signal from the voltage regulation control signal input terminal.

[0082] The driving reset circuit 130 is coupled to the driving reset control signal input terminal Rst1, the first node N1 and the driving reset voltage terminal Vinit1. The driving reset circuit 130 is configured to provide the driving reset voltage from the driving reset voltage terminal Vinit1 to the voltage stabilizing circuit 120 under the control of the driving reset control signal from the driving reset control signal input terminal Rst1, so as to reset the control terminal G of the driving circuit 110.

[0083] The light emitting reset circuit 140 is coupled to the light emitting reset control signal input terminal Rst2, the light emitting device 200, and the light emitting reset voltage terminal Vinit2. Further, the light emitting reset circuit 140 is also coupled to the light emitting control circuit 180. The light emitting reset circuit 140 is configured to provide the light emitting reset voltage from the light emitting reset voltage terminal Vinit2 to the light emitting device 200 under the control of the light emitting reset control signal from the light emitting reset control signal input terminal Rst2, so as to reset the anode of the light emitting device 200.

[0084] The data writing circuit 150 is coupled to the data signal input terminal Data, the scan signal input terminal Gate and the first terminal F of the driving circuit 110. The data writing circuit 150 is configured to provide a data signal from the data signal input terminal Data to the first terminal F of the driving circuit 110 under the control of the scan signal from the scan signal input terminal Gate.

[0085] The compensation circuit 160 is coupled to the second terminal S of the driving circuit 110, the first node N1 and the compensation control signal input terminal Com. The compensation circuit 160 is configured to perform threshold compensation on the driving circuit 110 according to the compensation control signal from the compensation control signal input terminal Com.

[0086] In the embodiment of the present disclosure, the scan signal from the scan signal input terminal Gate and the compensation control signal from the compensation control signal input terminal Com may be the same signal.

[0087] The storage circuit 170 is coupled to the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 . The storage circuit 170 is configured to store a voltage difference between the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110 .

[0088] The light emitting control circuit 180 is coupled to the light emitting control signal input terminal EM, the first power supply voltage terminal VDD, the first terminal F and the second terminal S of the driving circuit 110, the light emitting reset circuit 140, and the light emitting device 200. The light emitting control circuit 180 is configured to apply the first power supply voltage from the first power supply voltage terminal VDD to the driving circuit 110 under the control of the light emitting control signal from the light emitting control signal input terminal EM, and apply the driving current generated by the driving circuit 110 to the light emitting device 200.

[0089] In some embodiments of the present disclosure, the light emitting reset control signal from the light emitting reset control signal input terminal Rst2 and the light emitting control signal from the light emitting control signal input terminal EM may be the same signal.

[0090] Additionally or alternatively, in some embodiments of the present disclosure, the light emitting reset control signal from the light emitting reset control signal input terminal Rst2 and the scan signal from the scan signal input terminal Gate may be the same signal.

[0091] The light emitting device 200 is coupled to the second power supply voltage terminal VSS, the light emitting reset circuit 140, and the light emitting control circuit 180. The light emitting device 200 is configured to emit light under the driving current generated by the driving circuit 110. For example, the light emitting device 200 may be a light emitting diode, etc. The light emitting diode may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED), etc.

[0092] In the embodiments of the present disclosure, the voltage stabilization control signal, the scanning signal, the driving reset control signal, the light emitting reset control signal, the compensation control signal, the light emitting control signal, and the compensation control signal may be square waves, the high level may range from 0 to 15V, and the low level may range from 0 to -15V, for example, the high level is 7V and the low level is -7V. The data signal may range from 0 to 8V, for example, 2 to 5V. The first power supply voltage Vdd may range from 3 to 6V. The second power supply voltage Vss may range from 0 to -6V.

[0093] Figure 3 Shows Figure 2 Schematic diagram of the pixel circuit 100 in FIG. Figure 3 As shown, the driving circuit 110 includes a driving transistor T1, the voltage stabilizing circuit 120 includes a voltage stabilizing transistor T2, the driving reset circuit 130 includes a driving reset transistor T3, the light emitting reset circuit 140 includes a light emitting reset transistor T4, the data writing circuit 150 includes a data writing transistor T5, the compensation circuit 160 includes a compensation transistor T6, the storage circuit 170 includes a storage capacitor C, and the light emitting control circuit 180 includes a first light emitting control transistor T7 and a second light emitting control transistor T8.

[0094] like Figure 3 As shown, the first electrode of the driving transistor T1 is coupled to the first terminal F of the driving circuit 110 , the second electrode of the driving transistor T1 is coupled to the second terminal S of the driving circuit 110 , and the gate of the driving transistor T1 is coupled to the control terminal G of the driving circuit 110 .

[0095] A first electrode of the voltage regulator transistor T2 is coupled to the control terminal G of the driving circuit 110 , a gate of the voltage regulator transistor T2 is coupled to the voltage regulation control signal input terminal Stv, and a second electrode of the voltage regulator transistor T2 is coupled to the first node N1 .

[0096] A first electrode of the driving reset transistor T3 is coupled to the driving reset voltage terminal Vinit1 , a gate of the driving reset transistor T3 is coupled to the driving reset control signal input terminal Rst1 , and a second electrode of the driving reset transistor T3 is coupled to the first node N1 .

[0097] The first electrode of the light emitting reset transistor T4 is coupled to the light emitting reset voltage terminal Vinit2, the gate of the light emitting reset transistor T4 is coupled to the light emitting reset control signal input terminal Rst2, and the second electrode of the light emitting reset transistor T4 is coupled to the anode of the light emitting device 200. Furthermore, the second electrode of the light emitting reset transistor T4 is also coupled to the second electrode of the second light emitting control transistor T8.

[0098] A first electrode of the data writing transistor T5 is coupled to the data signal input terminal Data, a gate of the data writing transistor T5 is coupled to the scan signal input terminal Gate, and a second electrode of the data writing transistor T5 is coupled to the first terminal F of the driving circuit 110 .

[0099] A first electrode of the compensation transistor T6 is coupled to the second end S of the driving circuit 110 , a gate of the compensation transistor T6 is coupled to the compensation control signal input end Com, and a second electrode of the compensation transistor T6 is coupled to the first node N1 .

[0100] A first electrode of the storage capacitor C is coupled to the first power supply voltage terminal VDD, and a second electrode of the storage capacitor C is coupled to the control terminal G of the driving circuit 110. The storage capacitor is configured to store a voltage difference between the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110.

[0101] A first electrode of the first light emitting control transistor T7 is coupled to the first power supply voltage terminal VDD, a gate of the first light emitting control transistor T7 is coupled to the light emitting control signal input terminal EM, and a second electrode of the first light emitting control transistor T7 is coupled to the first terminal F of the driving circuit 110 .

[0102] The first electrode of the second light emitting control transistor T8 is coupled to the second end S of the driving circuit 110 , the gate of the second light emitting control transistor T8 is coupled to the light emitting control signal input end EM, and the second electrode of the second light emitting control transistor T8 is coupled to the anode of the light emitting device 200 .

[0103] In an embodiment of the present disclosure, the active layers of the voltage stabilizing transistor T2 and the light emitting reset transistor T4 may include an oxide semiconductor material, such as a metal oxide semiconductor material. The active layers of the driving transistor T1, the driving reset transistor T3, the data writing transistor T5, the compensation transistor T6, the first light emitting control transistor T7, and the second light emitting control transistor T8 may include a silicon semiconductor material.

[0104] In the embodiment of the present disclosure, when the light-emitting reset control signal and the light-emitting control signal can be the same signal, the light-emitting reset transistor T4 and the first light-emitting control transistor T7 and the second light-emitting control transistor T8 can be transistors of different types. For example, the light-emitting reset transistor T4 can be an N-type transistor, and the first light-emitting control transistor T7 and the second light-emitting control transistor T8 can be P-type transistors. The voltage-stabilizing transistor T2 can be an N-type transistor. The driving transistor T1, the driving reset transistor T3, the data writing transistor T5, and the compensation transistor T6 can be P-type transistors.

[0105] In the embodiment of the present disclosure, when the light emitting reset control signal and the light emitting control signal can be the same signal, the light emitting reset transistor T4 and the data writing transistor T5 are transistors of the same type. For example, the light emitting reset transistor T4 and the data writing transistor T5 can be P-type transistors. The voltage stabilizing transistor T2 can be an N-type transistor. The driving transistor T1, the driving reset transistor T3, the compensation transistor T6, the first light emitting control transistor T7 and the second light emitting control transistor T8 can be P-type transistors.

[0106] In addition, it should be noted that the transistors used in the embodiments of the present disclosure can be P-type transistors or N-type transistors. It is only necessary to connect the electrodes of the selected type of transistors with reference to the electrodes of the corresponding transistors in the embodiments of the present disclosure, and to make the corresponding voltage terminals provide corresponding high voltages or low voltages. For example, for an N-type transistor, its input terminal is a drain and its output terminal is a source, and its control terminal is a gate; for a P-type transistor, its input terminal is a source and its output terminal is a drain, and its control terminal is a gate. For different types of transistors, the level of the control signal at its control terminal is also different. For example, for an N-type transistor, when the control signal is at a high level, the N-type transistor is in a conducting state; and when the control signal is at a low level, the N-type transistor is in a cut-off state. For a P-type transistor, when the control signal is at a low level, the P-type transistor is in a conducting state; and when the control signal is at a high level, the P-type transistor is in a cut-off state. The oxide semiconductor may include, for example, indium gallium zinc oxide (IGZO). The silicon semiconductor material may include low temperature polysilicon (LTPS) or amorphous silicon (eg hydrogenated amorphous silicon). Low temperature polysilicon generally refers to the case where the crystallization temperature of polysilicon obtained by crystallizing amorphous silicon is lower than 600 degrees Celsius.

[0107] In addition, it should be noted that in the embodiment of the present disclosure, the pixel circuit of the sub-pixel can be Figure 4 In addition to the 8T1C structure (i.e., eight transistors and one capacitor) shown, it can also be a structure including other numbers of transistors, such as an 8T2C structure, a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0108] Figure 4 For drive Figure 3 The timing diagram of the signals of the pixel circuit in FIG. Figure 3 As shown, the working process of the pixel circuit 100 includes three stages, namely a first stage P1, a second stage P2 and a third stage P3.

[0109] In the following, the light-emitting reset control signal and the light-emitting control signal are the same signal, the voltage-stabilizing control signal and the scanning signal are the same signal, the voltage-stabilizing transistor T2 and the light-emitting reset transistor T4 are N-type transistors, the driving transistor T1, the driving reset transistor T3, the data writing transistor T5, the compensation transistor T6, the first light-emitting control transistor T7 and the second light-emitting control transistor T8 are P-type transistors. Figure 3 right Figure 4 The working process of the pixel circuit in is explained.

[0110] like Figure 4 As shown, in the first phase P1, a low-level driving reset control signal RST, a high-level scanning signal GA, a high-level light-emitting control signal EMS, a high-level voltage stabilization control signal STV and a low-level data signal DA are input. Figure 4 As shown, the rising edge of the light emitting control signal EMS is earlier than the starting point of the first phase P1, that is, earlier than the rising edge of the voltage stabilizing control signal STV.

[0111] In the first stage P1, the gate of the driving reset transistor T3 receives a low-level driving reset control signal RST, and the driving reset transistor T3 is turned on, thereby applying the driving reset voltage VINT1 to the first node N1. The gate of the voltage regulator transistor T2 receives a high-level voltage regulator control signal STV, and the voltage regulator transistor T2 is turned on, so that the driving reset voltage VINT1 at the first node N1 is applied to the gate of the driving transistor T1 to reset the gate of the driving transistor T1, so that the driving transistor T1 is ready for the writing of the data in the second stage P2. In an embodiment of the present disclosure, the value of the driving reset voltage VINT1 can be set to be lower, for example, the voltage in the reverse direction of the first power supply voltage Vdd is larger, so that the difference between the gate voltage of the driving transistor T1 and the first pole in the second stage is larger, thereby speeding up the process of data writing and compensation in the second stage. It should be noted that the effect of the driving reset voltage VINT1 on the driving transistor T1 tends to saturation as the reverse direction of the driving reset voltage VINT1 increases. The process of data writing and compensation will be described in the second stage P2 below. In addition, in the first stage P1, the voltage of one pole of the storage capacitor C is the first power supply voltage Vdd, and the voltage of the other pole is the driving reset voltage VINT1, and the storage capacitor C is charged. In the embodiment of the present disclosure, considering the influence of the driving reset voltage VINT1 on data writing and compensation and the circuit energy consumption of charging the storage capacitor C and the hardware limitation of the power supply, the value range of the driving reset voltage VINT1 can be -1 to -5V, for example, -3V. This can shorten the time required for data writing and compensation while keeping the energy consumption of the circuit low, thereby improving the compensation effect during a fixed time period, such as the second stage P2, and thus improving the display effect.

[0112] In the first stage P1, the gate of the light emitting reset transistor T4 receives the high-level light emitting control signal EMS, and the light emitting reset transistor T4 is turned on, so that the light emitting reset voltage VINT2 is applied to the anode of the OLED to reset the anode of the OLED, so that the OLED does not emit light before the third stage P3. In the embodiment of the present disclosure, the value of the light emitting reset voltage VINT2 is set to make the OLED just not emit light, that is, the OLED is forward biased to a state close to being turned on. Specifically, when the second power supply voltage Vss ranges from 0 to -6V, the value range of the light emitting reset voltage VINT2 can be -2 to -6V, for example, equal to the second power supply voltage Vss, which is 0 to -6V. This can reduce the PN junction charging time of the OLED before turning on, and reduce the response time of the OLED to the light emitting signal. When the required brightness is consistent, the probability of differences in OLED brightness is reduced. Therefore, the brightness uniformity can be improved, and low-frequency flicker and low-grayscale Mura can be reduced.

[0113] In addition, in the first phase P1, the gate of the data writing transistor T5 receives a high-level scanning signal GA, and the data writing transistor T5 is turned off. The gate of the compensation transistor T6 receives a high-level scanning signal GA, and the compensation transistor T6 is turned off. The gate of the first light-emitting control transistor T7 receives a high-level light-emitting control signal EMS, and the first light-emitting control transistor T7 is turned off. The gate of the second light-emitting control transistor T8 receives a high-level light-emitting control signal EMS, and the second light-emitting control transistor T8 is turned off.

[0114] In the second phase P2, a high-level driving reset control signal RST, a low-level scanning signal GA, a high-level light emitting control signal EMS, a high-level voltage stabilization control signal STV and a high-level data signal DA are input.

[0115] In the second phase P2, the gate of the data writing transistor T5 receives the low-level scanning signal GA, and the data writing transistor T5 is turned on, thereby writing the high-level data signal DA into the first electrode of the driving transistor T1, that is, the first terminal F of the driving circuit 110. The gate of the compensation transistor T6 receives the low-level scanning signal GA, and the compensation transistor T3 is turned on, thereby writing the high-level data signal DA at the first terminal F into the first node N1. The gate of the voltage stabilizing transistor T2 receives the high-level voltage stabilizing control signal STV, and the voltage stabilizing transistor T2 is turned on, thereby writing the high-level data signal DA at the first node N1 into the gate of the driving transistor T1, that is, the control terminal G of the driving circuit 110. Since the data writing transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage stabilizing transistor T2 are all turned on, the data signal DA charges the storage capacitor C again through the data writing transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage stabilizing transistor T2, that is, the gate of the driving transistor T1 is charged, that is, the control terminal G is charged, so the voltage of the gate of the driving transistor T1 gradually increases.

[0116] It can be understood that in the second stage P2, since the data writing transistor T5 is turned on, the voltage of the first terminal F is maintained at Vda. At the same time, according to the characteristics of the driving transistor T1 itself, when the voltage of the control terminal G rises to Vda+Vth, the driving transistor T1 is turned off and the charging process ends. Here, Vda represents the voltage of the data signal DA, and Vth represents the threshold voltage of the driving transistor T1. Since the driving transistor T1 is described as a P-type transistor in this embodiment, the threshold voltage Vth here can be a negative value.

[0117] After the second stage P2, the gate voltage of the driving transistor T1 is Vda+Vth, that is, the voltage information of the data signal DA and the threshold voltage Vth is stored in the storage capacitor C for compensating the threshold voltage of the driving transistor T1 in the subsequent third stage P3.

[0118] In addition, in the second phase P2, the gate of the driving reset transistor T3 receives a high-level driving reset control signal RST, and the driving reset transistor T3 is turned off. The gate of the light emitting reset transistor T4 receives a high-level light emitting reset control signal EMS, and the light emitting reset transistor T4 is turned off. The gate of the first light emitting control transistor T7 receives a high-level light emitting control signal EMS, and the first light emitting control transistor T7 is turned off; the gate of the second light emitting control transistor T8 receives a high-level light emitting control signal EMS, and the second light emitting control transistor T8 is turned off.

[0119] In the third phase P3, a high-level driving reset control signal RST, a high-level scanning signal GA, a low-level light-emitting control signal EMS, a low-level voltage stabilization control signal STV and a low-level data signal DA are input. Figure 4 As shown, in the embodiment of the present disclosure, the low-level light emission control signal EMS may be a low-level effective pulse width modulation signal. Figure 4 As shown, the falling edge of the light emitting control signal EMS is later than the end point of the second phase P1, that is, later than the falling edge of the voltage stabilizing control signal STV.

[0120] In the third phase P3, the gate of the first light emission control transistor T7 receives the light emission control signal EMS. According to an embodiment of the present disclosure, the light emission control signal EMS may be pulse width modulated. When the light emission control signal EMS is at a low level, the first light emission control transistor T7 is turned on, thereby applying the first power supply voltage Vdd to the first terminal F. The gate of the second light emission control transistor T8 receives the light emission control signal EMS. When the light emission control signal EMS is at a low level, the second light emission control transistor T8 is turned on, thereby applying the driving current generated by the driving transistor T1 to the anode of the OLED.

[0121] In addition, in the third phase P3, the gate of the voltage stabilizing transistor T2 receives the low-level voltage stabilizing control signal Stv, and the voltage stabilizing transistor T2 is turned off. As mentioned above, the active layer of the voltage stabilizing transistor T2 includes an oxide semiconductor material, and its leakage current is 10 -16 to 10 -19 A. Compared with a single-gate low-temperature polysilicon transistor and a double-gate low-temperature polysilicon transistor, the leakage current is smaller, so that the electrical leakage of the storage circuit can be further reduced to improve the uniformity of brightness.

[0122] In addition, in the third phase P3, the gate of the light emitting reset transistor T4 receives the light emitting control signal EMS. When the light emitting control signal EMS is at a high level, the light emitting reset transistor T4 is turned on. The light emitting reset voltage is provided to the anode of the OLED to reset the anode of the OLED. In the case where the light emitting control signal EMS is a pulse width modulation signal, this can enable the anode of the OLED to be reset before each light emission of the OLED under the control of the light emitting control signal EMS, thereby further improving the uniformity of the brightness.

[0123] In addition, the gate of the driving reset transistor T3 receives a high-level driving reset control signal RST, and the driving reset transistor T3 is turned off. The gate of the data writing transistor T5 receives a high-level scanning signal GA, and the data writing transistor T5 is turned off. The gate of the compensation transistor T6 receives a high-level scanning signal GA, and the compensation transistor T6 is turned off.

[0124] It is easy to understand that in the third phase P3, since the first light emitting control transistor T7 is turned on, the voltage of the first terminal F is the first power supply voltage Vdd, and the voltage of the control terminal G is Vda+Vth, so the driving transistor T1 is also turned on.

[0125] In the third phase P3 , the anode and cathode of the OLED are connected to the first power supply voltage Vdd (high voltage) and the second power supply voltage Vss (low voltage) respectively, so that the OLED emits light under the driving current generated by the driving transistor T1 .

[0126] Based on the saturation current formula of the driving transistor T1, the driving current ID that drives the OLED to emit light can be obtained according to the following formula:

[0127] ID=K(VGS-Vth) 2

[0128] =K[(Vda+Vth-Vdd)-Vth] 2

[0129] =K(Vda-Vdd) 2

[0130] In the above formula, Vth represents the threshold voltage of the driving transistor T1, VGS represents the voltage between the gate and the source of the driving transistor T1, and K is a constant. It can be seen from the above formula that the driving current ID flowing through the OLED is no longer related to the threshold voltage Vth of the driving transistor T1, but only to the voltage Vda of the data signal DA, thereby compensating the threshold voltage Vth of the driving transistor T1, solving the problem of threshold voltage drift of the driving transistor T1 due to the process and long-term operation, eliminating its influence on the driving current ID, and thus improving the display effect.

[0131] For example, K in the above formula can be expressed as:

[0132] K = 0.5nCox (W / L),

[0133] Wherein, n is the electron mobility of the driving transistor T1 , Cox is the unit capacitance of the gate of the driving transistor T1 , W is the channel width of the driving transistor T1 , and L is the channel length of the driving transistor T1 .

[0134] Alternatively, in some embodiments of the present disclosure, the light emitting reset control signal RST, the compensation control signal COM and the scanning signal GA may be the same signal. The voltage regulator transistor T2 may be an N-type transistor, while the driving transistor T1, the driving reset transistor T3, the light emitting reset transistor T4, the data writing transistor T5, the compensation transistor T6, the first light emitting control transistor T7 and the second light emitting control transistor T8 are P-type transistors. The difference from the working process of the pixel circuit in the above embodiment is that in the first stage P1, the light emitting reset transistor T4 receives a high-level scanning signal GA, and the light emitting reset transistor T4 is turned off. The light emitting reset voltage VINT2 is not provided to the anode of the light emitting device OLED, so the anode of the light emitting device OLED is not reset. In the second stage P2, the light emitting reset transistor T4 receives a low-level scanning signal GA, and the light emitting reset transistor T4 is turned on. The light emitting reset voltage VINT2 is provided to the anode of the light emitting device OLED to reset the anode of the light emitting device OLED. The remaining working processes of the pixel circuit in the first period P1, the second period P2 and the third period P3 are similar to the above embodiment, and will not be repeated here.

[0135] In addition, it should be noted that the relationship between the driving reset control signal RST, the scanning signal GA, the light-emitting control signal EMS, the voltage stabilization control signal STV, and the data signal DA and each stage is only illustrative. The duration of the high level or low level of the driving reset control signal RST, the scanning signal GA, the light-emitting control signal EMS, the voltage stabilization control signal STV, and the data signal DA is only illustrative. For example, each high level duration of the light-emitting control signal EMS can be the same.

[0136] Figure 5-11 FIG. 1 is a plan view of each layer in an array substrate according to an embodiment of the present disclosure. Figure 3 In the pixel circuit, the light emitting reset control signal RST and the light emitting control signal EMS are the same signal, the voltage stabilizing control signal COM and the scanning signal GA are the same signal, and the voltage stabilizing transistor T2 and the light emitting reset transistor T4 are metal oxide transistors.

[0137] The following is combined with Figures 5 to 11 The positional relationship of each circuit in the pixel circuit on the substrate is described. Those skilled in the art will understand that the attached Figures 5 to 11 The proportions in the figure are drawing proportions, so as to more clearly show the positions of the parts, and they cannot be regarded as the real proportions of the parts. Those skilled in the art can select the size of each part based on actual needs, and the present disclosure does not make any specific limitation on this.

[0138] In an embodiment of the present disclosure, the array substrate includes a first active semiconductor layer 310 located on a substrate 300 .

[0139] Figure 5 A schematic plan view of the first active semiconductor layer 310 in the array substrate according to an embodiment of the present disclosure is shown. In an exemplary embodiment of the present disclosure, the driving transistor T1, the driving reset transistor T3, the light emitting reset transistor T4, the data writing transistor T5, the compensation transistor T6, the first light emitting control transistor T7 and the second light emitting control transistor T8 in the pixel circuit are silicon transistors, such as low temperature polysilicon transistors. In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 can be used to form the active area of ​​the above-mentioned driving transistor T1, the driving reset transistor T3, the light emitting reset transistor T4, the data writing transistor T5, the compensation transistor T6, the first light emitting control transistor T7 and the second light emitting control transistor T8. In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 includes a channel region pattern and a doping region pattern of the transistor (that is, a first source / drain region and a second source / drain region of the transistor). In an embodiment of the present disclosure, the channel region pattern and the doping region pattern of each transistor are integrally arranged.

[0140] It should be noted that in Figure 5 In FIG. 1 , dotted-line boxes are used to indicate regions of source / drain regions and channel regions for respective transistors in the first active semiconductor layer 310 .

[0141] like Figure 5 As shown, the first active semiconductor layer 310 includes a channel region T3-c of a driving reset transistor T3, a channel region T5-c of a data writing transistor T5, a channel region T6-c of a compensation transistor T6, a channel region T1-c of a driving transistor T1, a channel region T7-c of a first light emitting control transistor T7, and a channel region T8-c of a second light emitting control transistor T8 in sequence along the Y direction (column direction) and the X direction (row direction).

[0142] In an exemplary embodiment of the present disclosure, the first active semiconductor layer for the above-mentioned transistor may include an integrally formed low-temperature polysilicon layer. The source region and the drain region of each transistor may be conductorized by doping, etc. to achieve electrical connection of each structure. That is, the first active semiconductor layer of the transistor is an integral pattern formed by p-silicon or n-silicon, and each transistor in the same pixel circuit includes a doping region pattern (i.e., source region s and drain region d) and a channel region pattern. The active layers of different transistors are separated by doping structures.

[0143] like Figure 5As shown, the first active semiconductor layer 310 further includes along the Y direction and the X direction: a drain region T3-d of the driving reset transistor T3, a drain region T5-d of the data writing transistor T5, a source region T3-s / T6-s of the driving reset transistor T3 and a source region T3-s / T6-s of the compensation transistor T6, a source region T5-s of the data writing transistor T5, a source region T1-s / T7-s of the driving transistor T1 and a source region T1-s / T7-s of the first light emitting control transistor T7, a drain region T6-d / T1-d / T8-d of the compensation transistor T6 and a drain region T7-d of the driving transistor T1 and a drain region T6-d / T1-d / T8-d of the second light emitting control transistor T8, a drain region T7-d of the first light emitting control transistor T7, and a source region T8-s of the second light emitting control transistor T8.

[0144] In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 may be formed of a silicon semiconductor material such as amorphous silicon or polycrystalline silicon. The source region and the drain region may be regions doped with n-type impurities or p-type impurities. For example, the source region and the drain region of the first light emission control transistor T7, the data writing transistor T5, the driving transistor T1, the compensation transistor T6, and the second light emission control transistor T8 are all regions doped with P-type impurities.

[0145] In the embodiment of the present disclosure, the array substrate further includes a first conductive layer 320 located on a side of the first active semiconductor layer facing away from the substrate.

[0146] Figure 6 FIG. 1 is a plan view of a first conductive layer 320 in an array substrate according to an embodiment of the present disclosure. Figure 6 As shown, the first conductive layer 320 includes a driving reset control signal line RSTL1, a scanning signal line GAL, a first electrode C1 of a capacitor C, and a light emitting control signal line EML which are sequentially arranged along the Y direction. In addition, the first conductive layer 320 also includes a driving reset control signal line RSTL1' for an adjacent pixel circuit along the Y direction. The driving reset control signal line RSTL1' of an adjacent pixel circuit has the same effect on the adjacent pixel circuit as the driving reset control signal line RSTL1 has on the pixel circuit, and a repeated description thereof will not be given below.

[0147] In the embodiment of the present disclosure, the light emitting control signal line EML and the light emitting control signal input terminal EM are configured to provide a light emitting control signal EMS to the light emitting control signal input terminal EM.

[0148] In an embodiment of the present disclosure, the scan signal line GAL is coupled to the scan signal input terminal Gate and the compensation control signal input terminal Com, and is configured to provide a scan signal GA to the scan signal input terminal Gate, and is configured to provide a compensation control signal COM to the compensation control signal input terminal Com.

[0149] In the embodiment of the present disclosure, the first electrode C1 of the capacitor C and the gate T1 - g of the driving transistor T1 are an integrated structure.

[0150] In an embodiment of the present disclosure, the driving reset control signal line RSTL1 is coupled to the driving reset control signal input terminal Rst1 to provide the driving reset control signal RST to the driving reset control signal input terminal Rst1 .

[0151] In the embodiments of the present disclosure, reference Figure 5 and Figure 6 , the portion where the orthogonal projection of the driving reset control signal line RSTL1 on the substrate overlaps with the orthogonal projection of the portion 311 of the first active semiconductor layer 310 on the substrate is the gate T3-g of the driving reset transistor T3 of the pixel circuit. The portions where the orthogonal projection of the scanning signal line GAL on the substrate overlaps with the orthogonal projection of the portion 311 of the first active semiconductor layer 310 on the substrate are respectively the gate T6-g of the compensation transistor T6 and the gate T5-g of the data writing transistor T5 in the pixel circuit. The portion where the orthogonal projection of the first electrode C1 of the capacitor C in the pixel circuit overlaps with the orthogonal projection of the portion 311 of the first active semiconductor layer 310 on the substrate is the gate T1-g of the driving transistor T1 in the pixel circuit. The portions where the orthogonal projection of the emission control signal line EML on the substrate overlaps with the orthogonal projection of the portion 311 of the first active semiconductor layer 310 on the substrate are respectively the gate T7-g of the first emission control transistor T7 and the gate T8-g of the second emission control transistor T8 in the pixel circuit.

[0152] In the embodiments of the present disclosure, Figure 6 As shown, in the Y direction, the gate T3-g of the driving reset transistor T3, the gate T6-g of the compensation transistor T6, and the gate T5-g of the data writing transistor T5 are located on the first side of the gate T1-g of the driving transistor T1. The gate T7-g of the first light emission control transistor T7 and the gate T8-g of the first light emission control transistor T8 are located on the second side of the gate T1-g of the driving transistor T1.

[0153] It should be noted that the first side and the second side of the gate T1 - g of the driving transistor T1 are two opposite sides of the gate T1 - g of the driving transistor T1 in the Y direction. Figure 6As shown, in the XY plane, the first side of the gate T1-g of the driving transistor T1 may be the upper side of the gate T1-g of the driving transistor T1. The second side of the gate T1-g of the driving transistor T1 may be the lower side of the gate T1-g of the driving transistor T1. In the description of the present disclosure, the "lower side" is, for example, a side of the array substrate used to bond the IC. For example, the lower side of the gate T1-g of the driving transistor T1 is the side of the gate T1-g of the driving transistor T1 that is close to the IC (not shown in the figure). The upper side is the opposite side of the lower side, for example, the side of the gate T1-g of the driving transistor T1 that is away from the IC.

[0154] More specifically, the gate T3-g of the drive reset transistor T3 is located above the gate T6-g of the compensation transistor T6 and the gate T5-g of the data writing transistor T5. The gate T3-g of the drive reset transistor T3 is aligned with the gate T1-g of the drive transistor T1 in the Y direction.

[0155] In the embodiment of the present disclosure, in the X direction, as Figure 6 As shown, the gate T5-g of the data writing transistor T5 and the gate T7-g of the first light emission control transistor T7 are located on the third side of the gate T1-g of the driving transistor T1. The gate T6-g of the compensation transistor T6 and the gate T8-g of the second light emission control transistor T8 are located on the fourth side of the gate T1-g of the driving transistor T1.

[0156] It should be noted that the third side and the fourth side of the gate T1 - g of the driving transistor T1 are two opposite sides of the gate T1 - g of the driving transistor T1 in the X direction. Figure 6 As shown, in the XY plane, the third side of the gate T1 - g of the driving transistor T1 may be the left side of the gate T1 - g of the driving transistor T1 . The fourth side of the gate T1 - g of the driving transistor T1 may be the right side of the gate T1 - g of the driving transistor T1 .

[0157] More specifically, the gate T7-g of the first light emission control transistor T7 is on the left side of the gate T5-g of the data writing transistor T5. The gate T8-g of the second light emission control transistor T8 is located on the right side of the gate T6-g of the compensation transistor T6.

[0158] It should be noted that Figure 6 The active regions of the transistors shown correspond to respective regions where the first conductive layer 320 overlaps the first active semiconductor layer 310 .

[0159] In an embodiment of the present disclosure, the array substrate further includes a second conductive layer located on a side of the first conductive layer away from the substrate and insulated from the first conductive layer.

[0160] Figure 7FIG. 2 shows a schematic plan view of the second conductive layer 330 in the array substrate according to an embodiment of the present disclosure. Figure 7 The second conductive layer 330 shown includes a voltage stabilization control signal line STVL, a second electrode C2 of the capacitor, a first power supply voltage line VDL, and a light-emitting reset control signal line RSTL2 arranged along the Y direction. In addition, the second conductive layer 330 also includes a light-emitting reset control signal line RSTL2' of an adjacent pixel circuit along the Y direction. The effect of the light-emitting reset control signal line RSTL2' of an adjacent pixel circuit on the adjacent pixel circuit is the same as the effect of the light-emitting reset control signal line RSTL2 on the pixel circuit, and will not be repeated below.

[0161] In the embodiments of the present disclosure, reference Figure 6 and Figure 7 , projections of the second electrode C2 of the capacitor C and the first electrode C1 of the capacitor C on the substrate at least partially overlap.

[0162] In the embodiments of the present disclosure, Figure 7 As shown, the first power supply voltage line VDL extends along the X direction and is formed integrally with the second electrode C2 of the capacitor C. The first power supply voltage line is coupled to the first power supply voltage terminal VDD and is configured to provide the first power supply voltage Vdd thereto. The voltage stabilization control signal line STVL is coupled to the voltage stabilization control signal input terminal Stv and is configured to provide the voltage stabilization control signal STV thereto. The light emitting reset control signal line RSTL2 is coupled to the light emitting reset control signal input terminal Rst2 and is configured to provide the light emitting reset control signal thereto. In an embodiment of the present disclosure, the light emitting reset control signal and the scan signal EMS are the same signal.

[0163] In the embodiments of the present disclosure, Figure 7 As shown, in the Y direction, the voltage stabilization control signal line STVL is located on the first side of the second electrode C2 of the capacitor. The first power signal line VDL and the light emitting reset control signal line RSTL2 are located on the second side of the second electrode C2 of the capacitor. Similar to the above description of the first side and the second side of the gate T1-g of the driving transistor T1, the first side and the second side of the second electrode C2 of the capacitor are opposite sides of the second electrode C2 of the capacitor in the Y direction. The first side of the second electrode C2 of the capacitor is the upper side of the second electrode C2 of the capacitor in the Y direction, and the second side of the second electrode C2 of the capacitor is the lower side of the second electrode C2 of the capacitor in the Y direction.

[0164] Specifically, in the Y direction, the voltage stabilization control signal line STVL is located on the upper side of the second electrode C2 of the capacitor. The first power signal line VDL and the light emission reset control signal line RSTL2 are located on the lower side of the second electrode C2 of the capacitor.

[0165] In the embodiments of the present disclosure, Figure 7As shown, the first gate T2-g1 of the voltage stabilizing transistor T2 is provided on the voltage stabilizing control signal line STVL. The first gate T4-g1 of the light emitting reset transistor T4 is provided on the light emitting reset control signal line RSTL2. The specific positions of the first gate T2-g1 of the voltage stabilizing transistor T2 and the first gate T4-g1 of the light emitting reset transistor T4 will be referred to below. Figure 8 Provide detailed explanation.

[0166] Specifically, Figure 7 As shown, in the Y direction, the first gate T2-g1 of the voltage stabilizing transistor T2 is on the first side of the first gate T4-g1 of the light emitting reset transistor T4. Similar to the above description of the first side of the gate T1-g of the driving transistor T1, the first side of the first gate T4-g1 of the light emitting reset transistor T4 is the upper side of the first gate T4-g1 of the light emitting reset transistor T4. That is, the first gate T2-g1 of the voltage stabilizing transistor T2 is on the upper side of the first gate T4-g1 of the light emitting reset transistor T4. In the X direction, the first gate T2-g1 of the voltage stabilizing transistor T2 is at the same position as the first gate T4-g1 of the light emitting reset transistor T4.

[0167] In an embodiment of the present disclosure, the array substrate further includes a second active semiconductor layer located on a side of the second conductive layer away from the substrate and insulated from the second conductive layer.

[0168] Figure 8 FIG. 2 shows a schematic plan view of the second active semiconductor layer 340 in the array substrate according to an embodiment of the present disclosure. Figure 8 As shown, the second active semiconductor layer 340 includes a first portion 341 and a second portion 342 in the Y direction, and the first portion 341 of the second active semiconductor layer 340 is aligned with the second portion 342 of the second active semiconductor layer 340. In an exemplary embodiment of the present disclosure, the second active semiconductor layer 340 can be used to form the active layer of the above-mentioned voltage-stabilizing transistor T2 and the light-emitting reset transistor T4. Specifically, the first portion 341 of the second active semiconductor layer 340 can be used to form the active layer of the voltage-stabilizing transistor T2. The second portion 342 of the second semiconductor layer 340 can be used to form the active layer of the voltage-stabilizing transistor T7. In an exemplary embodiment of the present disclosure, similar to the first active semiconductor layer 310, the second active semiconductor layer 340 includes a channel pattern and a doping region pattern of a transistor (i.e., a first source / drain region and a second source / drain region of the transistor).

[0169] exist Figure 8 In FIG. 1 , the dotted-line frame is used to illustrate the regions of the source / drain regions and the channel region for each transistor in the second active semiconductor layer 340 .

[0170] like Figure 8As shown, the first portion 341 of the second active semiconductor layer 340 includes the source region T2-s of the voltage stabilizing transistor T2, the channel region T2-c of the voltage stabilizing transistor T2, and the drain region T2-d of the voltage stabilizing transistor T2 in sequence along the Y direction. The second portion 342 of the second active semiconductor layer 340 includes the source region T4-s of the light emitting reset transistor T4, the channel region T4-c of the light emitting reset transistor T4, and the drain region T4-d of the light emitting reset transistor T4 in sequence along the Y direction.

[0171] In the embodiments of the present disclosure, reference Figure 7 and Figure 8 , the part where the orthographic projection of the voltage stabilizing control signal line STVL on the substrate overlaps with the orthographic projection of the second active semiconductor layer 340 on the substrate is the first gate T2-g1 of the voltage stabilizing transistor T2. The projection of the channel region T8-c of the voltage stabilizing transistor T2 on the substrate completely overlaps with the projection of the first gate T2-g1 of the voltage stabilizing transistor T2. The part where the orthographic projection of the light emitting control signal line RSTL2 on the substrate overlaps with the orthographic projection of the second active semiconductor layer 340 on the substrate is the first gate T4-g1 of the light emitting reset transistor T4. The projection of the channel region T4-c of the light emitting reset transistor T4 on the substrate completely overlaps with the projection of the first gate T4-g1 of the light emitting reset transistor T4.

[0172] In an exemplary embodiment of the present disclosure, the second active semiconductor layer 340 may be formed of an oxide semiconductor material, for example, indium gallium zinc oxide IGZO. The source region and the drain region may be regions doped with n-type impurities or p-type impurities. For example, the source region and the drain region of the voltage regulator transistor T2 and the light emitting reset transistor T4 are both regions doped with N-type impurities.

[0173] In an embodiment of the present disclosure, the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated and isolated from the second active semiconductor layer.

[0174] Fig. 9 FIG. 2 shows a schematic plan view of the third conductive layer 350 in the array substrate according to an embodiment of the present disclosure. Fig. 9 As shown, the third conductive layer 350 includes a voltage stabilization control signal line STVL, a light emitting reset control signal line RSTL2, and a light emitting reset voltage line VINL2. In addition, the third conductive layer 350 also includes a light emitting reset control signal line RSTL2' and a light emitting reset voltage line VINL2' of an adjacent pixel circuit along the Y direction. The light emitting reset control signal line RSTL2' and the light emitting reset voltage line VINL2' of the adjacent pixel circuit have the same effect on the adjacent pixel circuit as the light emitting reset control signal line RSTL2 and the light emitting reset voltage line VINL2 have on the pixel circuit, and will not be described again below.

[0175] Specifically, Fig. 9 As shown, the voltage stabilization control signal line STVL, the light emission reset control signal line RSTL2, and the light emission reset voltage line VINL2 are sequentially arranged in the Y direction.

[0176] In the embodiments of the present disclosure, Fig. 9 As shown, the second gate T2-g2 of the voltage stabilizing transistor T2 is provided on the voltage stabilizing control signal line STVL. The second gate T4-g2 of the light emitting reset transistor T4 is provided on the light emitting reset control signal line RSTL2. Specifically, the overlapping portion of the orthographic projection of the voltage stabilizing control signal line STVL on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the second gate T2-g2 of the voltage stabilizing transistor T2. The overlapping portion of the orthographic projection of the light emitting reset control signal line RSTL2 on the substrate and the orthographic projection of the second active semiconductor layer 340 on the substrate is the second gate T4-g2 of the light emitting reset transistor T4.

[0177] and Figure 7 The first gate T2-g1 of the voltage stabilizing transistor T2 is similar to the first gate T4-g1 of the light emitting reset transistor T4. Fig. 9 As shown, in the Y direction, the second gate T2-g2 of the voltage stabilizing transistor T2 is on the first side of the second gate T4-g2 of the light emitting reset transistor T4. The first side of the second gate T4-g2 of the light emitting reset transistor T4 is the upper side of the second gate T4-g2 of the light emitting reset transistor T4. That is, the second gate T2-g2 of the voltage stabilizing transistor T2 is on the upper side of the second gate T4-g2 of the light emitting reset transistor T4. In the X direction, the second gate T2-g2 of the voltage stabilizing transistor T2 is at the same position as the second gate T4-g2 of the light emitting reset transistor T4.

[0178] In the embodiments of the present disclosure, reference Figure 7 , Figure 8 and Fig. 9 The projections of the second gate T2-g2 of the voltage stabilizing transistor T2, the channel region T2-c of the voltage stabilizing transistor T2, and the first gate T2-g1 of the voltage stabilizing transistor T2 on the substrate completely overlap. The projections of the second gate T4-g2 of the light emitting reset transistor T4, the channel region T4-c of the light emitting reset transistor T4, and the first gate T4-g1 of the light emitting reset transistor T4 on the substrate completely overlap.

[0179] It should be noted that, in the embodiments of the present disclosure, an insulating layer or a dielectric layer is further disposed between adjacent active semiconductor layers and conductive layers or between adjacent conductive layers. Specifically, between the first active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, between the second conductive layer 330 and the second active semiconductor layer 340, between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360 (hereinafter referred to as “the fourth conductive layer”), between the first conductive ..., between the first conductive layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, between the second conductive layer 330 and the Fig.12 Detailed description) and between the fourth conductive layer 360 and the fifth conductive layer 370 (hereinafter referred to as Fig.11 An insulating layer or a dielectric layer (which will be described in detail below with reference to the cross-sectional view) is also provided respectively.

[0180] It should be noted that the via holes described below are via holes that simultaneously penetrate the insulating layer or dielectric layer between adjacent active semiconductor layers and conductive layers or between adjacent conductive layers. Specifically, the via holes are via holes that simultaneously penetrate the insulating layers or dielectric layers between the first active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, between the second conductive layer 330 and the second active semiconductor layer 340, between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360, and between the fourth conductive layer 360 and the fifth conductive layer 370.

[0181] In the drawings of the present disclosure, white circles are used to indicate areas corresponding to vias. Fig. 9 , the light emitting reset voltage line VINL2 is coupled to the second active semiconductor layer 340 via the via hole 3501 to form the first electrode T4-1 of the light emitting reset transistor T4. Figure 8 and Fig. 9 , Fig. 9 The light emitting reset voltage line VINL2 and Figure 8 The projection of the drain region T7 - ​​d of the light emitting reset transistor T4 in the second portion 342 overlaps on the substrate. The light emitting reset voltage line VINL2 is coupled to the drain region T4 - d of the light emitting reset transistor T4 via the via 3501 .

[0182] In an embodiment of the present disclosure, the array substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate and insulated from the third conductive layer.

[0183] Fig.10 FIG. 2 shows a schematic plan view of a fourth conductive layer 360 in an array substrate according to an embodiment of the present disclosure. Fig.10As shown, the fourth conductive layer 360 includes a first connection portion 361, a second connection portion 362, a third connection portion 363, a fourth connection portion 364, a fifth connection portion 365, a sixth connection portion 366, a seventh connection portion 367, and an eighth connection portion 368. In addition, the fourth conductive layer 360 also includes a ninth connection portion 369 for adjacent pixel circuits along the Y direction. The ninth connection portion 369 and the via hole 3691 thereon can serve as the first connection portion 361 of the adjacent pixel circuit and the via hole 3611 thereon. Its specific connection mode and function are similar to the first connection portion 361 and the via hole 3611 thereon in the pixel circuit, and will not be repeated below. For composition needs, the first connection portion 361 of the adjacent pixel circuit and the via hole 3611 thereon are arranged as above.

[0184] In the embodiment of the present disclosure, the second connection part 362, the third connection part 363, the fourth connection part 364, the fifth connection part 365, the sixth connection part 366, the seventh connection part 367, and the eighth connection part 368 are arranged on the second side of the first connection part 361. Similar to the second side of the gate T1-g of the driving transistor T1, in the XY coordinate system, the second side of the first connection part 361 is the lower side of the first connection part 361. That is, the second connection part 362, the third connection part 363, the fourth connection part 364, the fifth connection part 365, the sixth connection part 366, the seventh connection part 367, and the eighth connection part 368 are arranged on the lower side of the first connection part 361. The third connection part 363 and the sixth connection part 366 are arranged in sequence along the Y direction. The second connection part 362, the fourth connection part 364, the fifth connection part 365, the seventh connection part 367, and the eighth connection part 368 are arranged in sequence along the Y direction. The second connection portion 362, the fourth connection portion 364, the fifth connection portion 365, the seventh connection portion 367, and the eighth connection portion 368 are on the third side of the third connection portion 363 and the sixth connection portion 366. Similar to the third side of the gate T1-g of the driving transistor T1, in the XY plane, the third side of the third connection portion 363 and the sixth connection portion 366 is the right side of the third connection portion 363 and the sixth connection portion 366. That is, the second connection portion 362, the fourth connection portion 364, the fifth connection portion 365, the seventh connection portion 367, and the eighth connection portion 368 are on the right side of the third connection portion 363 and the sixth connection portion 366.

[0185] The first connection portion 361 is coupled to the first active semiconductor layer 310 via the via hole 3611. Specifically, the first connection portion 361 is coupled to the drain region T3-d of the driving reset transistor T3 via the via hole 3611 to form the first electrode T3-1 of the driving reset transistor T3. The first connection portion 361 is used as the driving reset voltage line VINL1.

[0186] The second connection portion 362 is coupled to the third conductive layer 350 via the via hole 3621. Specifically, the second connection portion 362 is coupled to the light emitting reset voltage line VINL2 via the via hole 3621.

[0187] The third connection portion 363 is coupled to the first active semiconductor layer 310 via the via hole 3631. Specifically, the third connection portion 363 is coupled to the drain region T5-d of the data writing transistor T5 via the via hole 3631 to form the first electrode T5-1 of the data writing transistor T5.

[0188] The fourth connection portion 364 is coupled to the first active semiconductor layer 310 via the via hole 3641. Specifically, the fourth connection portion 364 is coupled to the source region of the driving reset transistor T3 and the source region T3-s / T6-s of the compensation transistor T6 via the via hole 3641 to form the second electrode of the driving reset transistor T3 and the second electrode T3-2 / T6-2 of the compensation transistor T6. The fourth connection portion 364 is coupled to the second active semiconductor layer 340 via the via hole 3642. Specifically, the fourth connection portion 364 is coupled to the source region T2-s of the voltage stabilizing transistor T2 via the via hole 3642 to form the second electrode T2-2 of the voltage stabilizing transistor T2.

[0189] The fifth connection portion 365 is coupled to the third conductive layer 330 via the via hole 3651. The fifth connection portion 365 is coupled to the second conductive layer 320 via the via hole 3652. Specifically, the fifth connection portion 365 is coupled to the gate T1-g of the driving transistor T1 and the first electrode C1 of the capacitor C via the via hole 3652. The fifth connection portion 365 is coupled to the second active semiconductor layer 340 via the via hole 3653. Specifically, the fifth connection portion 365 is coupled to the drain region T2-d of the voltage stabilizing transistor T2 via the via hole 3653 to form the first electrode T2-1 of the voltage stabilizing transistor T2.

[0190] The sixth connection portion 366 is coupled to the first active semiconductor layer 310 via the via hole 3662. Specifically, the sixth connection portion 366 is coupled to the drain region T7-d of the first light emission control transistor T7 via the via hole 3662 to form the first electrode T7-1 of the first light emission control transistor T7.

[0191] The seventh connection portion 367 is coupled to the first active semiconductor layer 310 via the via hole 3671. Specifically, the seventh connection portion 367 is coupled to the source region T8-s of the second light emission control transistor T8 via the via hole 3671 to form the second electrode T8-2 of the second light emission control transistor T8. The seventh connection portion 367 is coupled to the second active semiconductor layer 340 via the via hole 3672. Specifically, the seventh connection portion 367 is coupled to the source region T4-s of the light emission reset transistor T4 via the via hole 3672 to form the second electrode T4-2 of the light emission reset transistor T4.

[0192] The eighth connection portion 368 is coupled to the second active semiconductor layer 340 via the via hole 3681. Specifically, the eighth connection portion 368 is coupled to the source region T4-d of the light-emitting reset transistor T4 via the via hole 3681 to form the first electrode T4-1 of the light-emitting reset transistor T4. In addition, the eighth connection portion 368 and the via hole 3682 thereon can serve as the second connection portion 362 and the via hole 3621 thereon of the adjacent pixel circuit along the Y direction. Its specific connection mode and function are similar to those of the second connection portion 362 and the via hole 3621 thereon in the pixel circuit, and will not be repeated here. For the purpose of composition, the second connection portion 362 of the adjacent pixel circuit and the via hole 3621 thereon are arranged as above.

[0193] In an embodiment of the present disclosure, the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated from the fourth conductive layer.

[0194] Fig.11 FIG. 4 shows a schematic plan view of a fifth conductive layer 370 in an array substrate according to an embodiment of the present disclosure. Fig.11 As shown, the fifth conductive layer includes a data signal line DAL, a first power supply voltage line VDL, and a second power supply voltage line VSL arranged along the row direction X. The data signal line DAL extends along the column direction Y and is coupled to the third connection portion 363 of the fourth conductive layer 360 via a via 3711. The first power supply voltage line VDL extends along the column direction Y and is coupled to the third connection portion 363 of the fourth conductive layer 360 via a via 3721. The second power supply voltage line VSL extends along the column direction Y and is coupled to the seventh connection portion 367 of the fourth conductive layer 360 via a via 3731. In an embodiment of the present disclosure, the distance that the second power supply voltage line VSL extends along the column direction Y is less than that of the data signal line DAL and the first power supply voltage line VDL. The second power supply voltage line VSL can be used as a cathode of a light-emitting device, such as an OLED.

[0195] In the embodiment of the present disclosure, the first power supply voltage line VDL has a closed rectangular part 371. Figure 8 and 11 , the orthographic projection of the second side of the rectangular component 371 extending in the Y direction arranged along the row direction X on the substrate overlaps with the orthographic projection of the first part 341 of the second active semiconductor layer 340 on the substrate. This arrangement can isolate the second active semiconductor layer 340 from the encapsulation layer which is on the side of the fifth conductive layer 370 away from the substrate and is arranged adjacent to the fifth conductive layer 370, thereby preventing the hydrogen element in the encapsulation layer from making the performance of the oxide material, such as the metal oxide material, in the second active semiconductor layer 340 unstable.

[0196] In the embodiment of the present disclosure, the orthographic projection of the second power supply voltage line VSL on the substrate overlaps with the orthographic projection of the second portion 342 of the second active semiconductor layer 340 on the substrate. The arrangement of the second power supply voltage line VSL has a similar effect to the arrangement of the first power supply voltage line VDL, which can isolate the second active semiconductor layer 340 from the encapsulation layer on the side of the fifth conductive layer 370 away from the substrate and adjacent to the fifth conductive layer 370, thereby preventing the hydrogen element in the encapsulation layer from making the performance of the oxide material in the second active semiconductor layer 340 unstable.

[0197] Fig.12 A schematic plan layout diagram of a pixel circuit (and thus an array substrate) including a stacked first active semiconductor layer, a first conductive layer, a second conductive layer, a second active semiconductor layer, a third conductive layer, and a fourth conductive layer is shown. Fig.12 As shown, the plan layout diagram 380 includes a first active semiconductor layer 310, a first conductive layer 320, a second conductive layer 330, a second active semiconductor layer 340, a third conductive layer 350, a fourth conductive layer 360 and a fifth conductive layer 370. For ease of viewing, Fig.12 The gate T1-g of the driving transistor T1, the gate T2-g of the voltage regulating transistor T2, the gate T3-g of the driving reset transistor T3, the gate T4-g of the light emitting reset transistor T4, the gate T5-g of the data writing transistor T5, the gate T6-g of the compensation transistor T6, the first electrode plate C1 of the storage capacitor C, the gate T7-g of the first light emitting control transistor T7 and the gate T8-g of the second light emitting control transistor T8 are shown. Fig.12 A section line A1A2 of the array substrate passing through the via hole 3651, the gate T6-g of the compensation transistor T6, and the gate T2-g of the voltage regulator transistor T2 is also shown. Fig.13 A cross-sectional view taken along the section line A1A2 will be described.

[0198] Fig.13 The embodiment according to the present disclosure is shown Fig.12 A schematic diagram of the cross-sectional structure of the array substrate taken along line A1A2 in FIG. Fig.13 As shown, and refer to Figures 5 to 12 , the array substrate 10 includes: a substrate 300; a first buffer layer 101 located on the substrate 300; and a first active semiconductor layer 310 located on the first buffer layer 101. The cross-sectional view shows a channel region T6-c of a compensation transistor T6 included in the first active semiconductor layer 310.

[0199] In the embodiments of the present disclosure, Fig.13As shown, the array substrate 10 further includes: a first gate insulating layer 102 covering the first buffer layer 101 and the first active semiconductor layer 310; and a first conductive layer 320 located on the side of the first gate insulating layer 102 away from the substrate 300. The cross section shows the scanning signal line GAL included in the first conductive layer 320. Fig.13 As shown, the overlapping portion of the orthographic projection of the scanning signal line GAL on the substrate 300 and the orthographic projection of the channel region T6 - c of the compensation transistor T6 included in the first active semiconductor layer 310 on the substrate 300 is the gate T6 - g of the compensation transistor T6 .

[0200] In the embodiments of the present disclosure, Fig.13 As shown, the array substrate 10 further includes: a first interlayer insulating layer 103 located on the side of the first conductive layer 320 away from the substrate 300; and a second conductive layer 330 located on the side of the first interlayer insulating layer 103 away from the substrate 300. The cross-sectional view shows a voltage stabilization control signal line STVL and a connecting portion 331 included in the second conductive layer. The voltage stabilization control signal line STVL includes a first gate T2-g1 of a voltage stabilization transistor T2.

[0201] In the embodiments of the present disclosure, Fig.13 As shown, the array substrate 10 further includes: a second interlayer insulating layer 104 located on the side of the second conductive layer 330 away from the substrate 300; a second buffer layer 105 covering the second interlayer insulating layer 104; and a second active semiconductor layer 340 located on the side of the second buffer layer 105 away from the substrate 300. The cross-sectional view shows a channel region T2-c of the voltage regulator transistor T2 whose orthographic projection on the substrate 300 overlaps with the orthographic projection on the substrate 300 of the first gate T2-g1 of the voltage regulator transistor T2 on the voltage regulation control signal line STVL.

[0202] In the embodiments of the present disclosure, Fig.13 As shown, the array substrate 10 further includes: a second gate insulating layer 106 covering the second active semiconductor layer 340 and the second buffer layer 105; and a third conductive layer 350 located on the side of the second gate insulating layer 106 away from the substrate 300. The cross-sectional view shows that the third conductive layer 350 includes a voltage stabilization control signal line STVL. Fig.13 As shown, the overlapping portion of the orthographic projection of the voltage stabilizing control signal line STVL on the substrate 300 and the orthographic projection of the channel region T2 - c of the voltage stabilizing transistor T2 included in the second active semiconductor layer 320 on the substrate 300 is the second gate T2 - g2 of the voltage stabilizing transistor T2 .

[0203] In the embodiments of the present disclosure, Fig.13As shown, the array substrate 10 further includes: a third interlayer insulating layer 107 covering the third conductive layer 350 and the second gate insulating layer 106; and a fourth conductive layer 360 located on a side of the third interlayer insulating layer 107 away from the substrate 300. Fig.10 , the cross-sectional view shows the fifth connection portion 365 . The fifth connection portion 365 is coupled to the connection portion 331 on the second conductive layer 330 through the via 3651 .

[0204] In the embodiments of the present disclosure, Fig.13 As shown, the array substrate 10 further includes: a first planar layer 108 covering the fourth conductive layer 360 and the third interlayer insulating layer 107; and a fifth conductive layer 370 on the side of the first planar layer 108 away from the substrate 300. The cross-sectional view shows a first power supply voltage line VDL.

[0205] In the embodiments of the present disclosure, Fig.13 As shown, the array substrate 10 further includes a second planar layer 109 covering the fifth conductive layer 370 and the first planar layer 108 .

[0206] Fig.14 The embodiment according to the present disclosure is shown Fig.12 A schematic diagram of the cross-sectional structure of the array substrate taken along line A1A2 in FIG. Fig.14 As shown, the array substrate 10 also includes a shielding layer 400 located between the substrate 100 and the first buffer layer 101. On the one hand, when the substrate 300 is a light-transmitting substrate, the shielding layer 400 is configured to at least partially shield the light from the side of the substrate 300 where the pixel circuit is not provided from being incident on the active semiconductor layer of the transistor of the pixel circuit, so as to prevent light degradation of the transistor. On the other hand, the shielding layer 400 is configured to block particles released from the substrate from entering the pixel circuit. If the released particles enter the active semiconductor layer, the performance of the transistor will also be degraded. In addition, in the case where the particles are charged particles, once embedded in the pixel circuit structure (for example, embedded in the dielectric layer of the circuit structure), it will also interfere with various signal voltages input to the pixel circuit, thereby affecting the display performance. For example, when the substrate 300 is a polyimide substrate, since the polyimide material always undesirably contains various impurity ions, these impurity ions will be released from the substrate 300 and enter the pixel circuit during the thermal exposure process of manufacturing the array substrate (for example, the growth of the active semiconductor layer and the sputtering and evaporation of the conductive layer such as metal).

[0207] In an embodiment of the present disclosure, the shielding layer 400 may not be biased (i.e., suspended). In addition, a voltage bias may be applied to the shielding layer 400 to further improve the shielding effect. According to an embodiment of the present disclosure, the voltage applied to the shielding layer may be a constant voltage. The voltage applied to the shielding layer may be selected from one of the following voltages: a first power supply voltage Vdd (anode voltage of the light-emitting device), a second power supply voltage Vss (cathode voltage of the light-emitting device), a drive reset voltage VINT1 or other voltages. According to an embodiment of the present disclosure, the range of the voltage applied to the shielding layer includes one selected from the following ranges: -10V to +10V, -5V to +5V, -3V to +3V, -1V to +1V, or -0.5V to +0.5V. According to an embodiment of the present disclosure, the voltage applied to the shielding layer may be selected from one of the following voltages: -0.3V, -0.2V, 0V, 0.1V, 0.2V, 0.3V or 10.1V. According to an embodiment of the present disclosure, the voltage applied to the shielding layer may be greater than the second power voltage Vss and less than the first power voltage Vdd; or, the voltage applied to the shielding layer may be greater than the driving reset voltage VINT1 and less than the first power voltage Vdd.

[0208] Fig.15 A schematic block diagram of an array substrate according to an embodiment of the present disclosure is shown. Fig.15 A configuration of the shielding layer 400 a is shown. In this configuration, the shielding layer 400 a completely covers the substrate 300 on the area of ​​the array substrate 10 having pixel units (ie, the display area). Fig.14 The cross-sectional structure of corresponds to this configuration. By completely covering the display area of ​​the array substrate, the shielding layer can achieve the best protection effect.

[0209] Fig.16 A schematic block diagram of an array substrate according to an embodiment of the present disclosure is shown. Fig.16Another configuration of a shielding layer 400b is shown, in which the shielding layer 400b does not completely cover the substrate 300 on the area (i.e., display area) of the array substrate 10 having pixel units. In this configuration, the shielding layer 400b includes a first strip 401 extending along the row direction X and spaced apart from each other along the column direction Y and a second strip 402 extending along the column direction Y and spaced apart from each other along the row direction X. The first strip 401 and the second strip 402 have the same width (i.e., the dimension perpendicular to the extending direction of the strip). In addition, the orthographic projection of the intersection of the first strip 401 and the second strip 402 on the substrate 300 and the active area 3101 of the driving transistor T1 (i.e., the portion of the first active semiconductor layer 310 constituting the channel area T1-c, the source area T1-s, and the drain area T1-d of the driving transistor T1) on the substrate 300 at least partially overlap. Through this configuration, not only can the active area of ​​the driving transistor T1, which is a key component of the pixel circuit, be fully protected, but also the undesirable overlap between the shielding layer 400b and the wiring on the array substrate 10 can be reduced while ensuring the continuity of the entire shielding layer 400b, thereby reducing undesirable parasitic effects such as parasitic capacitance.

[0210] Fig.17 A schematic block diagram of an array substrate according to an embodiment of the present disclosure is shown. Fig.17 Another configuration of the shielding layer 400c is shown, wherein Fig.16 Similar to the configuration of the shielding layer 400b, the shielding layer 400c also does not completely cover the substrate 300 on the area of ​​the array substrate 10 having pixel units (i.e., the display area). In this configuration, the shielding layer 400b has a main body 410 located in each sub-pixel, a first connecting portion 420 for connecting the main body 410 along the row direction X, and a second connecting portion 430 for connecting the main body 410 along the column direction Y. The dimension Sc1 of the first connecting portion 420 along the column direction is smaller than the dimension Sb1 of the main body 410 along the column direction, and the dimension Sc2 of the second connecting portion 430 along the row direction is smaller than the dimension Sb2 of the main body 410 along the row direction. It should be understood that in the present disclosure, the term "size" is intended to represent the maximum size of a component. Through this configuration, the undesirable overlap between the shielding layer and the wiring in the array substrate can be further reduced, thereby suppressing potential parasitic effects.

[0211] In the embodiment of the present disclosure, the dimension Sc1 of the first connection portion 420 along the column direction may be the same as the dimension Sc2 of the second connection portion 430 along the row direction. In addition, the dimension Sc1 of the first connection portion 420 along the column direction may be different from the dimension Sc2 of the second connection portion 430 along the row direction. The dimension Sc1 of the first connection portion 420 along the column direction may be smaller than the dimension Sc2 of the second connection portion 430 along the row direction. The inventors have found that the data line DAL (e.g., Fig.11 The sensitivity of the first connection portion 420 to parasitic interference is higher than that of the gate signal line (driving reset control signal line RSTL1, scanning signal line GAL, light emission control signal line EML) in the pixel circuit extending along the row direction X. Therefore, by appropriately reducing the size Sc1 of the first connection portion 420 along the column direction and increasing the size Sc2 of the second connection portion 430 along the row direction, the conductivity of the entire shielding layer can be ensured while reducing the influence of the parasitic effect, so that when a voltage bias is applied to the blocking layer, the bias voltage can be ensured to be uniform across the shielding layer.

[0212] Fig.18 A schematic plan layout diagram of a pixel circuit including a stacked shielding layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer is shown. Fig.18 In the plan layout 381 shown, the shielding layer 401c has Fig.17 Configuration shown. The blocking layer 401c has a main body 411 located in each sub-pixel, a first connection portion 421 for connecting the main body 411 along the row direction, and a second connection portion 431 for connecting the main body 410 along the column direction. The dimension Sc1 of the first connection portion 421 along the column direction is smaller than the dimension Sb1 of the main body 410 along the column direction, and the dimension Sc2 of the second connection portion 430 along the row direction is smaller than the dimension Sb2 of the main body 410 along the column direction. In the configuration, the shape and size of the main body 411 are configured to overlap not only at least partially with the active area 3101 of the driving transistor T1 in the direction perpendicular to the substrate, but also at least partially overlap with the fifth connection portion 365 of the fourth conductive layer 360. In an embodiment of the present disclosure, at least 10% of the area of ​​the fifth connection portion overlaps with the main body 411 in the direction perpendicular to the substrate. For example, Fig.18 Only the case where the main body 411 completely overlaps with the active area 3101 of the driving transistor T1 and the fifth connection portion 365 of the fourth conductive layer 360 is shown, which does not at least limit the scope of the present disclosure. Since the fifth connection portion 365 is connected to the gate of the driving transistor T1, the influence of charged particles on the gate voltage of the driving transistor can be effectively prevented by shielding the fifth connection portion 365, thereby ensuring the normal display of the image.

[0213] In addition, for Fig.17 and Fig.18With the configuration of the shielding layer shown, the size (width) Sc2 of the second connection parts 430 and 431 in the row direction can be varied in the column direction. In an embodiment of the present disclosure, the width of the portion where the second connection part overlaps with the wiring extending in the row direction of the signal with a relatively high frequency can be greater than the width of the portion where the second connection part overlaps with the wiring extending in the row direction of the signal with a relatively low frequency. The wiring extending in the row direction of the signal with a relatively high frequency includes, for example, a light control signal line EML and a scanning signal line GAL. The higher the signal frequency, the more significant the parasitic effect. Therefore, through this configuration, the limiting interference of the shielding layer on the high-frequency signal can be effectively reduced. Similarly, the width of the portion where the first connection part overlaps with the wiring extending in the column direction of the signal with a relatively high frequency can be greater than the width of the portion where the first connection part overlaps with the wiring extending in the column direction of the signal with a relatively low frequency.

[0214] In addition, in an embodiment of the present disclosure, the width of the portion of the second connection portion overlapping with the wiring extending in the row direction with a constant signal may be greater than the width of the portion of the second connection portion overlapping with the wiring extending in the row direction without a constant signal. The wiring extending in the row direction with a constant signal may include, for example, a light emitting reset voltage line VINL and a first power supply voltage line VDL. Similarly, the width of the portion of the first connection portion overlapping with the wiring extending in the column direction with a constant signal may be greater than the width of the portion of the first connection portion overlapping with the wiring extending in the column direction without a constant signal. Fig.19 FIG. 2 shows a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure. Fig.19 As shown, the display panel 700 may include the array substrate 20 according to any embodiment of the present disclosure or an array substrate including the pixel circuit 100 according to any embodiment of the present disclosure.

[0215] For example, the display panel 700 may further include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc. These components may be existing conventional components, which will not be described in detail here.

[0216] For example, the display panel 700 may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel, etc. In addition, the display panel 700 may be not only a flat panel, but also a curved panel or even a spherical panel. For example, the display panel 700 may also have a touch function, that is, the display panel 700 may be a touch display panel.

[0217] An embodiment of the present disclosure further provides a display device, which includes the display panel according to any embodiment of the present disclosure.

[0218] Fig. 20 FIG. 1 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure. Fig. 20 As shown, the display device 800 may include the display panel 700 according to any embodiment of the present disclosure.

[0219] The display device 800 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0220] Fig.21 A pixel circuit is shown, which is a 7T1C structure including 7 transistors and 1 capacitor. In the pixel circuit, the active layers of transistors T1 and T2 include oxide semiconductor materials, and transistors T1 and T2 can be N-type oxide transistors. The active layers of transistors T3-T7 include silicon semiconductor materials, such as low-temperature polysilicon.

[0221] Fig. 22 Shown for Fig.21 The shielding layer of the circuit is shown. Fig.26 The position of the shielding layer 0 is shown. In this embodiment, the shielding layer is located between the active semiconductor layer and the substrate and is at least insulated and isolated from the active semiconductor layer.

[0222] Fig.23 The planar layout of each functional layer (semiconductor layer and conductive layer) of the pixel circuit including the light shielding layer is shown. The oxide semiconductors of T1 and T2 are designed as mirror images; the shielding layer shields the silicon semiconductor material. Fig.23 As shown, the overall planar layout of the pixel circuit including the light shielding layer is also a mirror image design; in the embodiment of the present disclosure, the mirror image design can also be, for example Fig.24 , Fig.29 The planar layout of the pixel circuit including the light shielding layer is shown in FIG. Fig.23 As shown, Da is Fig.21 The data signal terminal Data[m] access point, Vinit_OLED is Fig.21 The initial signal terminal Vinit_OLED access point, N1 is Fig.21 The potential point of the node N1 in the middle, where N1 is located in the first source and drain layer. N4 is Fig.21 The potential point of the middle node N4, ELVDD is Fig.21 The potential point of the middle power supply terminal ELVDD, ELVDD is located at the first source and drain layer. The shielding layer meets at least one of the following conditions:

[0223] 1. The main part of the shielding layer covers the silicon semiconductor material, and the coverage area of ​​the N1 node and the shielding layer is greater than 10% to stabilize the N1 node;

[0224] 2. The shielding layer does not overlap with the oxide channel, or the overlapping area is less than 90%, which alleviates the parasitic capacitance on the oxide layer;

[0225] 3. The overlapping area between the shielding layer and the initialization signal line is minimized to reduce the load on the initialization signal line. In this layout design, the arc-shaped routing line at the T7 position is avoided and only overlaps with the horizontal routing line. For example, Fig.29 As shown, the conductive portion 47 is bent and extended in the orthographic projection of the base substrate to reduce the overlap between the light shielding layer and the second initial signal line Vinit2; and

[0226] 4. The initialization signal line can be narrowed at the position where it overlaps with the shielding layer, and the shielding layer can also be narrowed.

[0227] Fig.24 The plane layout of the pixel circuit of the embodiment of the present disclosure is shown. The connection lines of the shielding layer along the row and column directions try to avoid the scanning lines and the like to avoid parasitic effects. Fig.24 N1 is Fig.21 The potential point of the middle node N1, where N1 is located in the first source and drain layer.

[0228] According to an embodiment of the present disclosure, the biasing of the shielding layer may be achieved in the following manner.

[0229] 1. Extend to the periphery for constant potential connection. It can be connected through a circle of signal wires on the periphery, or not a circle, as long as the signal access can be achieved. One or more layers of gate1, gate2, SD1, SD2, and ITO layers can be used for overlap. Fig.25 As shown;

[0230] 2. Electrical connection is achieved in the AA area, but other signal connection holes need to be avoided;

[0231] Embodiment 3: If VDD or Vint signal is used, a hole can be punched at the overlapping position of the VDD line and the Vint line.

[0232] In specific implementation, SD1 and SD2 layers are source and drain electrode film layers, and the material may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, or a titanium / aluminum / titanium stack.

[0233] In specific implementation, gate1 and gate2 layers are gate electrode film layers, which can be made of the same material and / or the same layer as the gate of the oxide transistor. For example, the material can be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a stack, etc. The potential loaded by the shielding layer may be the same as the potential loaded by the power line VDD (voltage source potential); it may also be the same as the potential loaded by the initialization signal line; it may also be the same as the potential loaded by the cathode (cathode potential VSS); it may also be other fixed potentials, for example, the fixed potential range is -10V to +10V, for example, the fixed potential range is -5V to +5V, for example, the fixed potential range is -3V to +3V, for example, the fixed potential range is -1V to +1V, for example, the fixed potential range is -0.5V to +0.5V, for example, the fixed potential range is 0V, for example, the fixed potential range is 0.1V, for example, the fixed potential range is 10.1V, for example, the fixed potential range is 0.2V, for example, the fixed potential range is -0.2V, for example, the fixed potential range is 0.3V, for example, the fixed potential range is -0.3V.

[0234] Specifically, the potential loaded by the shading layer can be greater than the potential loaded by the cathode (cathode potential VSS) and less than the potential loaded by the power line VDD; or, the potential loaded by the shading layer can be greater than the potential loaded by the initialization signal line and less than the potential loaded by the power line VDD.

[0235] During specific implementation, the shielding layer may be made of amorphous silicon material, or metal material, or oxide semiconductor material such as IGZO, or polycrystalline silicon material, or semiconductor material after being conductive, etc.

[0236] like Fig. 27FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of an array substrate of the present disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor DT, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the node N, the second electrode is connected to the first initial signal terminal Vinit1, the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit can be connected to a light-emitting unit OLED, used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, which have a small leakage current, so that the node N can be prevented from leaking through the first transistor T1 and the second transistor T2 during the light-emitting stage. At the same time, the driving transistor T3, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be low-temperature polysilicon transistors, which have a high carrier mobility, so as to facilitate the realization of a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual conditions.

[0237] like Fig.28 As shown, Fig. 27A timing diagram of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a first reset stage t1, a compensation stage t2, a second reset stage T3, and a light-emitting stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the first gate drive signal terminal G1 outputs a high level signal, the second gate drive signal terminal G2 outputs a low level signal, the fourth transistor T4, the second transistor T2, and the data signal terminal Da output a drive signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the drive signal, and Vth is the threshold voltage of the drive transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. Light-emitting stage t4: the enable signal terminal EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the drive transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the output current formula of the drive transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0238] The array substrate may include a base substrate, a light shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a first source and drain layer which are stacked in sequence. Figure 29-41 As shown, Fig.29 This is a structural diagram of an exemplary embodiment of an array substrate disclosed in the present invention. Fig.30 for Fig.29 The structural layout of the middle shading layer, Fig.31 for Fig.29 The structural layout of the first active layer in Fig.32 for Fig.29 The structural layout of the first gate layer in Fig.33 for Fig.29 The structural layout of the second gate layer in Fig.34 for Fig.29 The structural layout of the second active layer, Fig.35 for Fig.29 The structural layout of the third gate layer, Fig.36 for Fig.29 The structural layout of the first source and drain layer in the figure. Fig.37 for Fig.29 The structural layout of the middle light-shielding layer and the first active layer. Fig.38 for Fig.29 The structural layout of the middle light shielding layer, the first active layer, and the first gate layer. Fig.39 for Fig.29 The structural layout of the middle light shielding layer, the first active layer, the first gate layer, and the second gate layer. Fig.40 for Fig.29 The structural layout of the middle light shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer, Fig.41 for Fig.29 Structural layout of the middle light-shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer.

[0239] like Fig.29 , 30 As shown in , 37, 38, 39, 40, and 41, the light shielding layer may include a plurality of repeating units 0 and a connecting portion 02 connected between the repeating units 0. The repeating unit 0 may include two light shielding portions 01 symmetrically arranged along a dotted line A, wherein the dotted line A extends along the second direction Y. Fig.30As shown, the light shielding portion 01 may include a first light shielding portion 011, a second light shielding portion 012, a third light shielding portion 013, and a fourth light shielding portion 014. The second light shielding portion 012 and the third light shielding portion 013 may extend along the second direction Y in the orthographic projection of the substrate, and the fourth light shielding portion 014 may extend along the first direction X in the orthographic projection of the substrate. The second light shielding portion 012 and the third light shielding portion 013 may be connected to both sides of the first light shielding portion 011 in the second direction Y, respectively, and the orthographic projection of the second light shielding portion 012 and the orthographic projection of the third light shielding portion 013 in the first direction X may be spaced apart by a preset distance. The fourth light shielding portion 014 may be located on one side of the first light shielding portion in the first direction X. In the same repeating unit 0, two adjacent first light shielding portions 011 in the first direction X are connected. In two adjacent repeating units 0 in the first direction X, two adjacent light shielding portions 01 are connected through their respective fourth light shielding portions 014. Two adjacent light shielding portions 01 in the second direction Y may be connected by a connecting portion 02, wherein the connecting portion 02 may respectively connect the second light shielding portion 012 and the third light shielding portion 013 of the two light shielding portions 01, and the connecting portion 02 extends along the first direction X in the orthographic projection of the substrate. The first direction X and the second direction Y may intersect, for example, the first direction X may be a row direction, and the second direction may be a column direction.

[0240] like Fig.29 , 31 , 37, 38, 39, 40, 41, the first active layer may include an active portion 54, an active portion 53, an active portion 55, and an active portion 57. The active portion 54 may be used to form a channel region of the fourth transistor T4, the active portion 53 may be used to form a channel region of the driving transistor T3, the active portion 55 may be used to form a channel region of the fifth transistor T5, and the active portion 57 may be used to form a channel region of the seventh transistor T7. The first active layer may be formed of a polycrystalline silicon semiconductor material.

[0241] like Fig.29 , 32 , 38, 39, 40, 41, the first gate layer may include a second gate drive signal line G2, an enable signal line EM, a second reset signal line Re2, and a conductive portion 11. The orthographic projections of the second gate drive signal line G2, the enable signal line EM, and the second reset signal line Re2 on the substrate may all extend along the first direction X. The second gate drive signal line G2 may be used to provide Fig. 27 The second gate drive signal terminal in the enable signal line EM can be used to provide Fig. 27 The enable signal terminal in the second reset signal line Re2 can be used to provide Fig. 27The second reset signal terminal in. The orthographic projection of the second gate drive signal line G2 on the substrate can cover the orthographic projection of the active part 54 on the substrate, and the partial structure of the second gate drive signal line G2 can be used to form the gate of the fourth transistor T4. The orthographic projection of the enable signal line EM on the substrate can cover the orthographic projection of the active part 55 on the substrate, and the partial structure of the enable signal line EM can be used to form the gate of the fifth transistor T5. The orthographic projection of the second reset signal line Re2 on the substrate covers the orthographic projection of the active part 57 on the substrate, and the partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the conductive part 11 on the substrate can cover the orthographic projection of the active part 53 on the substrate, and the conductive part 11 can be used to form the gate of the driving transistor T3. At the same time, the conductive part 11 can also form an electrode of the capacitor C. Among them, the first active layer can be doped with the first gate layer as a mask, so that the first active layer covered by the first gate layer forms a semiconductor structure, and the part not covered by the first gate layer forms a conductor structure.

[0242] like Fig.29 , 33 As shown in , 39, 40, and 41, the second gate layer may include a first initial signal line Vinit1, a first reset signal line Re1, a first gate drive signal line G1, a conductive portion 21, and a connecting portion 22. The orthographic projections of the first initial signal line Vinit1, the first reset signal line Re1, and the first gate drive signal line G1 on the substrate may all extend along the first direction. Among them, the first initial signal line Vinit1 may be used to provide Fig. 27 The first initial signal terminal in the first reset signal line Re1 can be used to provide Fig. 27 The first reset signal terminal in the first gate drive signal line G1 can be used to provide Fig. 27 The conductive portion 21 is used as another electrode of the capacitor C. The conductive portions 21 adjacent to each other in the first direction X may be connected to each other through the connecting portion 22, and a through hole 211 may be formed on the conductive portion 21.

[0243] like Fig.29 , 34 As shown in FIGS. 40 and 41 , the second active layer may include an active portion 6, and the active portion 6 may include an active portion 61 and an active portion 62, wherein the active portion 61 may form a channel region of the first transistor T1, and the active portion 62 may form a channel region of the second transistor T2. Fig.40 As shown, the active portion 6 located on the side of the active portion 61 away from the active portion 62 can be connected to the first initial signal line Vinit1 through the via 71 to connect the second electrode of the first transistor T1 and the first initial signal line Vinit1. The second active layer can be formed of a metal oxide semiconductor material, such as indium gallium zinc oxide.

[0244] like Fig.29 , 35 As shown in 41, the third gate layer may include gate line 3Re1, gate line 3G1, and gate line 3Re1. Among them, the gate line 3Re1 can extend along the first direction in the orthographic projection of the substrate, and the orthographic projection of the gate line 3Re1 on the substrate can at least partially overlap with the orthographic projection of the first reset signal line Re1 on the substrate. The gate line 3Re1 can be connected to the first reset signal line Re1 through at least one via hole, and the via hole can be located in the non-display area or the display area of ​​the display panel. The gate line 3G1 can extend along the first direction in the orthographic projection of the substrate, and the gate line 3G1 can at least partially overlap with the orthographic projection of the first gate drive signal line G1 on the substrate. The gate line 3G1 can be connected to the first gate drive signal line G1 through at least one via hole, and the via hole can be located in the non-display area or the non-display area of ​​the display panel. The second active layer can be formed by conductorization using the third gate layer as a mask, that is, the second active layer covered by the third gate layer forms a semiconductor structure, and the part not covered by the third gate layer forms a conductor structure.

[0245] like Fig.29 , 36 As shown, the first source-drain layer may include a conductive portion 41, a conductive portion 42, a conductive portion 43, a conductive portion 44, a conductive portion 45, a conductive portion 46, a conductive portion 47, and a second initial signal line Vinit2, the second initial signal line Vinit2 is connected to the conductive portion 47, and is used to provide Fig. 27The second initial signal end in the substrate. The orthographic projection of the second initial signal line Vinit2 on the substrate substrate may at least partially overlap with the orthographic projection of the first reset signal line Re1 on the substrate substrate. The conductive part 41 may be connected to the active part 6 through the via 72, and connected to the first initial signal line Vinit1 through the via 73, so as to connect the second pole of the first transistor T1 and the first initial signal line Vinit1, and the conductive part 41 may further increase the contact efficiency between the active part 6 and the first initial signal line Vinit1. The conductive part 42 may be connected to the active part 6 at a position between the active part 61 and the active part 62 through the via 74, and at the same time connected to the conductive part 11 through the via 75, so as to connect the first pole of the first transistor T1 and the gate of the driving transistor T3. The via 75 may pass through the through hole 211 on the conductive part 21, and the conductor filled in the via 75 is not electrically connected to the conductive part 21. The conductive portion 43 can be connected to the connecting portion 22 through the via 76, and at the same time connected to the first active layer on one side of the active portion 55 through the via 77 to connect the capacitor C and the first electrode of the fifth transistor T5. The conductive portion 44 can be connected to the first active layer located between the active portion 57 and the active portion 56 through the via 78 to connect the second electrode of the sixth transistor T6, wherein the conductive portion 44 can be used to connect the anode of the light emitting unit. The conductive portion 45 can be connected to the active portion 6 located on the side of the active portion 62 away from the active portion 61 through the via 710, and connected to the first active layer on one side of the active portion 53 through the via 711 to connect the second electrode of the second transistor T2 and the second electrode of the driving transistor T3. The conductive portion 46 can be connected to the connecting portion 22 through the via 712, and the conductive portion 46 can also be connected to provide Fig. 27 The conductive portion 47 may be connected to the first active layer on one side of the active portion 57 through the via 79 to connect the second initial signal line Vinit2 and the second electrode of the seventh transistor T7.

[0246] In this exemplary embodiment, Fig.29 , 39 As shown, the orthographic projection of the fourth light shielding portion 014 on the substrate at least partially overlaps with the orthographic projection of the connecting portion 22 on the substrate. This arrangement can minimize the shielding effect of the fourth light shielding portion 014 on light and increase the light transmittance of the array substrate.

[0247] In this exemplary embodiment, Fig.29 , 39As shown, the orthographic projection of the connection portion 02 on the substrate substrate and the orthographic projection of the first reset signal line Re1 on the substrate substrate at least partially overlap. Similarly, this setting can minimize the shielding effect of the connection portion 02 on light and increase the light transmittance of the array substrate. In addition, since the first reset signal line Re1 is located in the second gate layer, the first reset signal line Re1 is at a large distance from the light shielding layer, and the capacitive coupling effect of the connection portion 02 on the first reset signal line Re1 is small. Compared with setting the connection portion 02 directly below the gate line in the first gate layer, this setting can reduce the capacitive coupling effect of the connection portion 02 on the gate line.

[0248] like Fig.29 , 33 As shown in Figures 39, the second gate layer may further include a protrusion 23, the protrusion 23 is connected to the first initial signal line Vinit1, the protrusion 23 includes a side 231, the first initial signal line Vinit1 includes a side 232 connected to the side 231, and the angle between the side 231 and the side 232 on the substrate is less than 180°. The substrate projection of the protrusion 23 and the substrate projection of the second light shielding portion 012 at least partially overlap. The protrusion 23 can reduce the resistance of the first initial signal line Vinit1. In addition, the substrate projection of the protrusion 23 and the substrate projection of the second light shielding portion 012 at least partially overlap, so that the light shielding effect of the protrusion 23 on the array substrate can be minimized. It should be understood that in other exemplary embodiments, a protrusion with a similar structure can also be provided on the gate extending in other row directions, and the protrusion can reduce the resistance of the gate line without affecting the transmittance of the array substrate.

[0249] In this exemplary embodiment, the light shielding layer may be a conductor structure, for example, the light shielding layer may be located on a metal light shielding layer, and the light shielding layer may be connected to a stable voltage source, which may be Fig. 27 Any one of the first power signal terminal VDD, the second power signal terminal VSS, the first initial signal terminal Vinit1, and the second initial signal terminal Vinit2. The light shielding layer can be connected to the above-mentioned stable power supply in the non-display area or the display area of ​​the array substrate. In addition, the above-mentioned stable voltage source can also be provided by other power supplies. Fig.29 As shown, the orthographic projection of the conductive portion 42 on the substrate and the orthographic projection of the third light shielding portion 013 on the substrate at least partially overlap, and since the third light shielding portion 013 is connected to a stable power supply, the third light shielding portion 013 has a voltage stabilizing effect on the conductive portion 42. At the same time, since the conductive portion 42 is connected to the gate (conductive portion 11) of the driving transistor T3, that is, the third light shielding portion 013 has a voltage stabilizing effect on the gate of the driving transistor T3, this setting can reduce the voltage fluctuation of the gate of the driving transistor T3 during the light emitting stage.

[0250] like Fig.29As shown, the first light shielding portion 011 can cover the projection of the active portion 53 on the substrate when projected on the substrate, and the first light shielding portion 011 can shield the active portion 53, thereby reducing the change in the output characteristics of the driving transistor T3 caused by the active portion 53 due to light. In addition, the first light shielding portion 011 can also cover the projection of the gate (conductive portion 11) of the driving transistor T3 on the substrate when projected on the substrate, so that the first light shielding portion 011 can stabilize the gate of the driving transistor T3, thereby reducing the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting stage. Fig.29 As shown, the orthographic projection of the first light shielding portion 011 on the substrate can also at least partially overlap with the orthographic projection of the conductive portion 42 on the substrate, so that the first light shielding portion 011 can further stabilize the gate of the driving transistor T3. The area of ​​the gate of the driving transistor (conductive portion 11) and the conductive portion 42 covered by the light shielding layer can be greater than 50% of the total area of ​​the conductive portion 11 and the conductive portion 42, for example, 60% to 70%; 80% to 90%, or a numerical range therebetween, or full coverage, etc.

[0251] In addition, the array substrate may further include a second source-drain layer and an anode layer. The second source-drain layer may be located on a side of the first source-drain layer away from the substrate, and the anode layer may be located on a side of the second source-drain layer away from the substrate. Fig. 27 The data signal line of the data signal terminal and the power line for providing the first power signal terminal can extend along the second direction Y in the positive projection of the data signal line and the power line on the base substrate. The anode layer can form the anode of the light emitting unit.

[0252] In this exemplary embodiment, the array may also include a second source and drain layer, such as Fig.42 , 43 As shown, Fig.42 This is a structural diagram of an exemplary embodiment of an array substrate disclosed in the present invention. Fig.43 for Fig.42 The second source-drain layer may include a data line Da and a power line VDD, and the orthographic projections of the data line Da and the power line VDD on the substrate may extend along the second direction Y. The data line Da may be used to provide Fig. 27 The data signal terminal, the power line VDD can be used to provide Fig. 27 The first power signal terminal in. Fig.42As shown, the power line VDD can be connected to the connecting portion 22 through a via 713 to connect the first power signal terminal and the capacitor C. The data line can be connected to the first active layer on one side of the active portion 54 through a via 714 to connect the first electrode and the data signal terminal of the fourth transistor T4. Wherein, the power line VDD may include an extension portion 91 and an extension portion 92 distributed along its extension direction, wherein the size of the extension portion 91 in the positive projection of the substrate in the first direction X may be greater than the size of the extension portion 92 in the positive projection of the substrate in the first direction X. The extension portion 91 in the positive projection of the substrate may cover the channel region of the first transistor and the second transistor. On the one hand, this arrangement can shield and light-block the transistor through the power line VDD; on the other hand, this arrangement can reduce the resistance of the power line VDD.

[0253] like Fig.44 , 45 As shown, Fig.44 This is a structural diagram of an exemplary embodiment of an array substrate disclosed in the present invention. Fig.45 for Fig.44 The structural layout of the second source and drain layer in FIG. Fig.45 The second source and drain layer shown Fig.43 The difference between the second source and drain layer shown is that the extension portion 91 not only covers the channel regions of the first transistor and the second transistor, but also covers the channel regions of the sixth transistor T6 and the driving transistor T3.

[0254] like Fig.46 , 47 , which are schematic diagrams of the structure of the second initial signal line in another exemplary embodiment of the array substrate disclosed in the present invention. In other exemplary embodiments, the second initial signal line Vinit2 can be a parallel grid line or a fold line, and can be designed according to the voltage drop of the initialization signal line.

[0255] like Fig.48 As shown, Fig.42Partial cross-sectional view along dotted line B in FIG. The array substrate may also include a first insulating layer 82, a second insulating layer 83, a third insulating layer 84, a fourth insulating layer 85, a sixth insulating layer 86, a dielectric layer 87, a passivation layer 88, and a first flat layer 89. Among them, the base substrate 81, the light shielding layer, the first insulating layer 82, the first active layer, the second insulating layer 83, the first gate layer, the third insulating layer 84, the second gate layer, the fourth insulating layer 85, the second active layer, the fifth insulating layer 86, the third gate layer, the dielectric layer 87, the first source and drain layer, the passivation layer 88, the first flat layer 89, and the second source and drain layer are stacked in sequence. Among them, the first insulating layer 82 includes at least one of a silicon oxide layer and a silicon nitride layer, and the thickness of the first insulating layer 82 may be 2500-3500 angstroms. The second insulating layer 83 may be a silicon oxide layer, and the thickness of the second insulating layer 83 may be 1000-2000 angstroms. The third insulating layer 84 may be an interlayer insulating layer or an interlayer dielectric layer, and the third insulating layer 84 may be a silicon nitride layer, and the thickness may be 1000 to 2000 angstroms. The fourth insulating layer 85 may include a silicon oxide layer and a silicon nitride layer, wherein the thickness of the silicon oxide layer may be 3000 to 4000 angstroms, and the thickness of the silicon nitride may be 500 to 1000 angstroms. The fifth insulating layer 86 may be a silicon oxide layer, and the thickness may be 1000 to 1700 angstroms. The dielectric layer 87 may include a silicon oxide layer and a silicon nitride layer, and the thickness of the silicon oxide layer may be 1500 to 2500, and the thickness of the silicon nitride layer may be 2500 to 3500. A second flat layer may be further provided on the side of the second source and drain layer away from the substrate, and the anode layer is located on the side of the second flat layer away from the substrate, and a light-emitting unit layer may be further provided on the side of the anode layer away from the substrate, and the light-emitting unit layer may include an electron injection layer, an organic light-emitting layer, a hole injection layer, etc.

[0256] The display panel and the display device provided in the embodiments of the present disclosure have the same or similar beneficial effects as the array substrate provided in the aforementioned embodiments of the present disclosure. Since the array substrate has been described in detail in the aforementioned embodiments, it will not be repeated here.

[0257] The foregoing description of the embodiment is provided above for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present application. Each element or feature of a particular embodiment is generally not limited to a particular embodiment, but, in appropriate circumstances, these elements and features are interchangeable and can be used in selected embodiments, even if not specifically shown or described. Also can be changed in many ways. This change cannot be considered to be out of the present application, and all these modifications are included in the scope of the present application.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, and the display panel further includes: substrate substrate; A light shielding layer, located on one side of the base substrate, and the light shielding layer is a grid structure; A first gate layer is located on a side of the light shielding layer away from the base substrate, the first gate layer comprises a first conductive portion (11), and the first conductive portion is used to form a gate of the driving transistor; A second source-drain layer, located on a side of the first gate layer away from the substrate, the second source-drain layer comprising a power line; The orthographic projection of the power line on the base substrate and the orthographic projection of the first conductive portion on the base substrate at least partially overlap, and the orthographic projection of the light shielding layer on the base substrate and the orthographic projection of the first conductive portion on the base substrate at least partially overlap; The pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to a gate electrode of the driving transistor, a second electrode of the first transistor is connected to a first initial signal line, a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: A second active layer, located between the first gate layer and the second source-drain layer, the second active layer comprising a first active portion (61) and a second active portion (62), the first active portion being used to form a channel region of the first transistor, and the second active portion being used to form a channel region of the second transistor; The orthographic projection of the light shielding layer on the base substrate does not overlap with the orthographic projection of the first active portion on the base substrate, and the orthographic projection of the light shielding layer on the base substrate does not overlap with the orthographic projection of the second active portion on the base substrate.

2. The display panel according to claim 1, wherein: The pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; The display panel further includes: A first source-drain layer is located between the first gate layer and the second source-drain layer, the first source-drain layer comprises a second conductive portion (42), the second conductive portion is connected to the first electrode of the second transistor, and the second conductive portion is connected to the first conductive portion through a via hole; The orthographic projection of the light shielding layer on the base substrate and the orthographic projection of the second conductive portion on the base substrate at least partially overlap.

3. The display panel according to claim 1, wherein: The display panel further includes a light emitting unit, and the pixel driving circuit further includes a seventh transistor, wherein a first electrode of the seventh transistor is connected to a first electrode of the light emitting unit, and a second electrode of the seventh transistor is connected to a second initial signal line; The display panel further includes: a first source-drain layer, located between the first gate layer and the second source-drain layer, the first source-drain layer comprising the second initial signal line and a seventh conductive portion (47), the seventh conductive portion being connected to the second initial signal line; The orthographic projection of the second initial signal line on the base substrate extends along a first direction, the orthographic projection of the seventh conductive portion on the base substrate bends and extends along a second direction, and the first direction and the second direction intersect; The seventh conductive portion includes a first sub-conductive portion and a second sub-conductive portion distributed along the extension direction thereof, the first sub-conductive portion is connected between the second initial signal line and the second sub-conductive portion, the light shielding layer includes a third light shielding portion, and the orthographic projection of the third light shielding portion on the base substrate extends along the second direction; The orthographic projection of the first sub-conductive portion on the base substrate overlaps with the orthographic projection of the third shading portion on the base substrate, and the orthographic projection of the second sub-conductive portion on the base substrate is located on one side of the orthographic projection of the third shading portion on the base substrate in the first direction.

4. The display panel according to claim 2, wherein: The orthographic projection of the second conductive part on the base substrate and the orthographic projection of the via connected between the second conductive part and the first conductive part on the base substrate overlap in the first projection area, and the orthographic projection of the power line on the base substrate covers the first projection area.

5. The display panel according to claim 1, wherein: The light shielding layer comprises a plurality of first light shielding portions, a second light shielding portion, a third light shielding portion, and a first connecting portion (02), wherein the first light shielding portions adjacent to each other in the second direction are connected via the second light shielding portions, the third light shielding portions, and the first connecting portion; The orthographic projection of the second light shielding portion on the base substrate and the orthographic projection of the third light shielding portion on the base substrate extend along the second direction, the orthographic projection of the first connecting portion on the base substrate extends along the first direction, the first connecting portion is connected between the second light shielding portion and the third light shielding portion, and the first direction intersects with the second direction; The pixel driving circuit further comprises a first transistor, a first electrode of the first transistor is connected to a gate of the driving transistor, a second electrode of the first transistor is connected to a first initial signal line, and a gate of the first transistor is connected to a first reset signal line; The display panel further includes: A second gate layer, located between the first gate layer and the second source-drain layer, the second gate layer comprising the first reset signal line, an orthographic projection of the first reset signal line on the base substrate extending along the first direction; An orthographic projection of the first connection portion on the base substrate and an orthographic projection of the first reset signal line on the base substrate at least partially overlap.

6. The display panel according to claim 5, wherein: The gate of the first transistor is also connected to a gate line (3Re1); The size of the orthographic projection of the first connecting portion on the base substrate in the first direction is greater than the size of the orthographic projection of the first reset signal line on the base substrate in the second direction; And / or the size of the orthographic projection of the first connecting portion on the base substrate in the first direction is greater than the size of the orthographic projection of the gate line (3Re1) on the base substrate in the second direction.

7. The display panel according to claim 1, wherein: The light shielding layer is connected to a stable voltage source.

8. The display panel according to claim 2, wherein: The areas of the first conductive portion and the second conductive portion covered by the light shielding layer are greater than 50% of the total area of ​​the first conductive portion and the second conductive portion.

9. The display panel according to claim 1, wherein: The power line comprises a first extension portion (91) and a second extension portion (92), wherein the size of the orthographic projection of the first extension portion on the base substrate in the first direction is larger than the size of the orthographic projection of the second extension portion on the base substrate in the first direction.

10. The display panel according to claim 9, wherein: The pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to a gate electrode of the driving transistor, a second electrode of the first transistor is connected to a first initial signal line, a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The orthographic projection of the first extension portion on the base substrate covers the orthographic projections of the first transistor channel region and the second transistor channel region on the base substrate.

11. The display panel according to claim 1, wherein: The pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, a second electrode of the capacitor is connected to the power line, and the first conductive part is multiplexed as the first electrode of the capacitor; The display panel further includes: a second gate layer, the second gate layer is located between the first gate layer and the second source-drain layer, and the second gate layer includes: a plurality of third conductive parts (21), wherein the orthographic projections of the third conductive parts on the base substrate at least partially overlap with the orthographic projections of the first conductive parts on the base substrate, and the third conductive parts are used to form second electrodes of the capacitor; A second connecting portion (22) connected between the third conductive portions adjacent to each other in the first direction; The orthographic projection of the power line on the base substrate and the orthographic projection of the second connecting portion (22) on the base substrate at least partially overlap.

12. The display panel according to claim 11, wherein: The third conductive portion includes a first side, the first side is connected to the second connecting portion, and the orthographic projection of the power line on the base substrate covers at least a partial structure of the orthographic projection of the first side on the base substrate.

13. The display panel according to claim 11, wherein: The first conductive portion includes a second side, the orthographic projection of the second side on the base substrate extends along a second direction, and the orthographic projection of the power line on the base substrate covers at least a partial structure of the orthographic projection of the second side on the base substrate.

14. The display panel according to claim 11, wherein: The pixel driving circuit further comprises a fifth transistor, a first electrode of the fifth transistor is connected to the power line, a second electrode is connected to the first electrode of the driving transistor, and a gate is connected to the enable signal line; The first gate layer further includes: The enable signal line, the orthographic projection of the enable signal line on the base substrate extends along a first direction; The display panel further includes: A first source-drain layer is located between the second gate layer and the second source-drain layer, the first source-drain layer includes a sixth conductive portion (46), the sixth conductive portion is connected to the second connecting portion and the power line through vias, and the orthographic projection of the sixth conductive portion on the base substrate and the orthographic projection of the enable signal line on the base substrate at least partially overlap.

15. The display panel according to claim 1, wherein: The display panel further includes a light emitting unit, and the pixel driving circuit further includes: a first transistor, wherein a first electrode of the first transistor is connected to a gate of the driving transistor, and a second electrode of the first transistor is connected to a first initial signal line; a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the power line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light emitting unit; a seventh transistor, wherein a first electrode of the seventh transistor is connected to the first electrode of the light emitting unit, and a second electrode of the seventh transistor is connected to the second initial signal line; Among them, the first transistor and the second transistor are N-type transistors, and the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

16. A display device, wherein: A display panel comprising any one of claims 1-15.

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