Methods, apparatus, systems and electronic devices for accessing DDR memory

Abstract

A method, apparatus, system, and electronic device for accessing DDR memory are provided. The method includes: monitoring the used memory space of a first wafer and a second wafer; determining whether the sum of the used memory space of the first wafer and the second wafer is less than the first threshold; if the sum of the used memory space of the first wafer and the second wafer is less than the first threshold, then moving data stored on the second wafer to the first wafer and controlling the second wafer to enter a low-power mode. When the DDR memory can free up the memory space of one wafer through data migration, this embodiment controls the wafer to enter a low-power mode, which helps to reduce the power consumption of the DDR memory.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and specifically to a method, apparatus, system, and electronic device for accessing DDR memory. Background Technology

[0002] Double data rate synchronous dynamic random access memory (DDR SDRAM) is commonly referred to as DDR memory. Due to its high data transfer rate and low cost, DDR memory is widely used in electronic devices such as mobile phones, watches, and computers.

[0003] As electronic devices demand increasingly larger memory capacities, DDR memory has evolved from containing a single die to containing two dies. However, this capacity expansion has also led to increased power consumption. Summary of the Invention

[0004] This application provides a method, apparatus, system, and electronic device for accessing DDR memory. The various aspects involved in the embodiments of this application will be described below.

[0005] In a first aspect, embodiments of this application provide a method for accessing a DDR memory, the DDR memory including a first wafer and a second wafer, the method including: monitoring the used storage space of the first wafer and the used storage space of the second wafer; determining whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold; if the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than the first threshold, then moving the data stored in the second wafer to the first wafer, and controlling the second wafer to enter a low-power mode.

[0006] Secondly, embodiments of this application provide an apparatus for accessing a DDR memory, the DDR memory including a first wafer and a second wafer. The apparatus includes: a memory for storing instructions; and a processor for executing the instructions stored in the memory to perform the following operations: monitoring the used storage space of the first wafer and the used storage space of the second wafer; determining whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold; if the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than the first threshold, then moving the data stored on the second wafer to the first wafer, and controlling the second wafer to enter a low-power mode.

[0007] Thirdly, embodiments of this application provide a system for accessing a DDR memory, including: a DDR memory; and the apparatus as described in the second aspect for accessing the DDR memory.

[0008] Fourthly, embodiments of this application provide an electronic device, including: the system described in the third aspect.

[0009] When the DDR memory can free up a wafer's storage space through data migration, the embodiments of this application control the wafer to enter a low-power mode, which helps to reduce the power consumption of the DDR memory. Attached Figure Description

[0010] Figure 1 The diagram shows the architecture of a SOC-DDR system.

[0011] Figure 2 The diagram shown is a simplified flowchart of the DDR memory's operating state.

[0012] Figure 3 The diagram shows the structure of a single-die DDR memory.

[0013] Figure 4 The diagram shows the structure of a dual-die DDR memory.

[0014] Figure 5 As shown Figure 4 A schematic diagram of the internal storage space of a DDR memory.

[0015] Figure 6 The diagram shows a power consumption optimization scheme for DDR devices in related technologies.

[0016] Figure 7 The diagram shown is a flowchart illustrating a method for accessing DDR memory according to an embodiment of this application.

[0017] Figure 8 The diagram shown is a flowchart illustrating another method for accessing DDR memory provided in an embodiment of this application.

[0018] Figure 9 The diagram shown is a structural schematic of a device for accessing DDR memory provided in an embodiment of this application.

[0019] Figure 10 The diagram shown is a structural schematic of another device for accessing DDR memory provided in an embodiment of this application.

[0020] Figure 11 The diagram shown is a schematic representation of the system for accessing DDR memory provided in an embodiment of this application.

[0021] Figure 12 The diagram shown is a structural schematic of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0023] DDR memory is an improvement upon SDRAM memory. SDRAM transmits data on the rising edge of the clock, once per clock cycle. DDR memory, on the other hand, transmits data twice per clock cycle, once on the rising edge and once on the falling edge. DDR memory can achieve a higher data transfer rate at the same bus frequency as SDRAM. Therefore, DDR memory, as a high-speed data storage medium, is widely used in electronic devices such as mobile phones, watches, and computers.

[0024] External devices can access DDR memory. In this application, these external devices are collectively referred to as devices for accessing DDR memory. These devices for accessing DDR memory can be, for example, a system-on-chip (SOC) or a microcontroller unit (MCU), or electronic devices such as mobile phones, watches, and computers.

[0025] The following is combined Figure 1 Taking a System-on-a-Chip (SoC) as an example, this section explains the access methods for DDR memory. See [link / reference] Figure 1 A System-on-Chip (SOC) and DDR memory constitute an SOC-DDR system. SOC access to DDR memory is achieved through signal lines such as the clock line (CK), command / address line (CA), data line (DQ), and chip select line (CS). Among these signal lines, the chip select line (CS) is used to select the DDR memory to access, while the clock line (CK) sends the SOC's clock signal to the accessed DDR memory, achieving clock synchronization. Furthermore, read and write requests are transmitted via the CA signal line. The data contained in the read and write requests is transmitted via the DQ signal line.

[0026] Different access methods correspond to different operating modes of DDR memory. The main operating modes of DDR memory include data read, data write, self-refresh, and deep sleep mode (DSM). Idle and active states are intermediate states during state transitions. Figure 2A simplified flowchart of the DDR memory's operating state.

[0027] The capacity of DDR memory indicates the amount of data it can store, and different capacities are available. The capacity of DDR memory is determined by the size of the memory chips packaged within the DDR memory chip. Generally, a chip package contains one memory chip (i.e., one die), and in this case, the capacity of the DDR memory is the capacity of one die. This type of DDR memory can be a single-die DDR architecture; a schematic diagram of a single-die DDR memory can be seen... Figure 3 .

[0028] As devices accessing DDR memory increasingly demand higher memory capacity, DDR memory manufacturers have adopted a dual-core packaging approach to achieve capacity expansion. This means that a single DDR memory chip contains two memory chips (two dies), and the capacity of the DDR memory is the capacity of those two dies. For example, combining two 8GB dies in a dual-die architecture to form a DDR memory results in a 16GB memory capacity.

[0029] Dual die DDR is a type of DDR memory packaged with two cores. A schematic diagram of the dual die DDR memory structure can be found here. Figure 4 . Figure 4 A schematic diagram of the internal storage space of a DDR memory is shown below. Figure 5 As shown, this memory contains two dies, die0 and die1, and each die contains four channels. The four channels mean that the device has four data channels that can transmit data simultaneously.

[0030] As the capacity of DDR memory continues to increase, its power consumption also increases. Taking mobile phones as an example, in actual tests, dual-die DDR memory consumes 10% to 20% more power than single-die DDR memory. Moreover, during mobile phone use, DDR memory power consumption accounts for about 10% of the phone's total power consumption, significantly impacting the user's battery life experience.

[0031] To reduce the power consumption of DDR memory, several power optimization schemes have been proposed. The following section combines... Figure 6 Taking electronic devices as an example, this paper introduces a power consumption optimization scheme for DDR memory.

[0032] In scenarios where electronic devices are on, there is a lot of data interaction between the device and the DDR (DDR memory). As the amount of data accessed by the DDR increases, the power consumption of the DDR memory also increases. At this time, the power consumption of the DDR memory mainly consists of the power consumption for data reading and writing. When the electronic device is in the off state, there is less access to the data inside the DDR, so the power consumption of the DDR memory at this time mainly consists of the power consumption for self-refresh.

[0033] Therefore, related technologies can shut down some data channels of DDR memory when the electronic device is in a screen-off state, thereby reducing the power consumption of DDR memory. At the same time, some data channels are retained for data transmission. For example, see... Figure 3 It can disable three channels in a 4-channel DDR memory, reserving one data channel for data transmission.

[0034] The above method is applicable to screen-off scenarios and cannot optimize DDR power consumption in screen-on scenarios. Furthermore, the power consumption optimization achieved by this method is very small. In actual testing, the power consumption optimization was less than 4mW.

[0035] To address the aforementioned issues, this application proposes a method for accessing DDR memory. When data migration frees up storage space on a wafer in the DDR memory, embodiments of this application control the wafer to enter a low-power mode, which helps reduce the power consumption of the DDR memory.

[0036] Figure 7 This is a flowchart illustrating a method 700 for accessing DDR memory according to an embodiment of this application. The DDR memory may be, for example, DDR, DDR2, DDR3, GDDR5, etc. The DDR memory may include a first wafer and a second wafer. The first wafer and the second wafer can be understood as two independent memory chips in the DDR memory. Taking a dual-die DDR memory as an example, the first wafer can refer to either die0 or die1.

[0037] Figure 7 Method 700 includes steps S710, S720 and S730. Figure 7 The steps in this method can be performed by a device that accesses DDR memory. This device can be, for example, a System-on-a-Chip (SoC) or Microcontroller Unit (MCU), or an electronic device such as a mobile phone, watch, or computer. These steps are described in more detail below.

[0038] In step S710, the used storage space of the first wafer and the used storage space of the second wafer are monitored.

[0039] Monitoring the storage space of the first wafer and the storage space of the second wafer can provide a basis for low-power management of storage space. One implementation approach is to include a storage space monitoring module in the device accessing DDR memory, and then use this module to monitor the storage space of the first wafer and the second wafer. For example, the monitoring content can include the used storage space of the first wafer and / or the second wafer, or it can include the unused storage space of the first wafer and / or the second wafer. Alternatively, the monitoring content can include the proportion of used storage space of the first wafer and / or the second wafer to the total storage space, or it can include the proportion of unused storage space of the first wafer and / or the second wafer to the total storage space.

[0040] In step S720, it is determined whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold.

[0041] The used memory space of the first wafer and the used memory space of the second wafer can be obtained by monitoring the memory space, and thus the sum of the used memory space of the first wafer and the used memory space of the second wafer can be calculated.

[0042] There are several ways to set the first threshold. The first threshold can be the maximum storage space of the first wafer, or it can be less than the maximum storage space of the first wafer. In some embodiments, the first threshold can be set to a value greater than 60% of the maximum storage space of the first wafer. For example, the first threshold can be set to 70% or 80% of the maximum storage space of the first wafer. That is, the first threshold can be set to a threshold close to the maximum storage space of the first wafer.

[0043] When memory operates near full capacity, data read speeds decrease and stuttering is more likely. Therefore, by setting a threshold, it's possible to prevent memory from operating near full capacity, thus avoiding unnecessary slowdowns in memory read speeds and improving the user experience when accessing DDR memory devices or systems.

[0044] In step S730, if the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold, the data stored in the second wafer is moved to the first wafer, and the second wafer is controlled to enter a low-power mode.

[0045] If the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold, that is, if the storage space in the first wafer meets the storage requirements of the data in the DDR memory (i.e. all the data in the first and second wafers) without affecting memory performance, then the valid data in the second wafer can be moved to the first wafer.

[0046] Since the addresses of the first and second wafers are identical, when data is moved from the second wafer to the first wafer, the data address may change, meaning the data is stored in different locations on the first and second wafers; alternatively, the data address may remain unchanged, meaning the data is stored in the same location on both wafers. Therefore, it is crucial to maintain the mapping between the data and the new address while moving the valid data to ensure that the corresponding data can be accurately located on subsequent accesses.

[0047] Moving data stored on the second wafer to the first wafer frees up storage space on the second wafer without data loss. In other words, after the data is moved, the storage space on the second wafer is freed up and unused. In some embodiments, "the storage space on the second wafer is unused" may include one or more of the following: the storage space on the second wafer does not store data; the storage space on the second wafer does not store valid data (it may store junk data).

[0048] After the data migration is complete, the storage space on the second wafer is unused. The second wafer can be controlled to enter a low-power mode to reduce the power consumption of the DDR memory. A low-power mode refers to a mode that consumes less power than when the second wafer is operating normally. For example, a low-power mode could refer to a deep sleep mode.

[0049] If the sum of the used storage space of the first wafer and the used storage space of the second wafer is greater than or equal to the first threshold, that is, if the free storage space in the first wafer is insufficient to store the valid data in the second wafer, then no data migration will be performed to avoid data loss due to exceeding the storage space.

[0050] When the DDR memory can free up a wafer's storage space through data migration, the embodiments of this application control the wafer to enter a low-power mode, which helps to reduce the power consumption of the DDR memory.

[0051] To further optimize the power consumption of DDR memory, a space cleanup operation can be performed on the DDR memory before determining whether the sum of the used memory space of the first wafer and the used memory space of the second wafer is less than a first threshold.

[0052] During the use of DDR memory, invalid data, or garbage data, often accumulates in the memory for various reasons. Therefore, in order to effectively utilize the storage space of DDR memory, the garbage data in the DDR memory can be cleaned up.

[0053] Typically, cleaning up storage space consumes certain control resources. By setting the timing of storage space cleanup, it's possible to balance efficient storage space utilization with resource conservation. As an example, the cleanup timing can be based on a threshold of used storage space. For instance, when the used storage space of the first wafer exceeds a second threshold, the storage space of the first wafer is cleaned. Similarly, when the used storage space of the second wafer exceeds a third threshold, the storage space of the second wafer is cleaned. As another example, the cleanup timing can be based on a fixed time period. For example, DDR memory might undergo storage space cleanup every 500 hours of operation.

[0054] There are multiple ways to set the second and third thresholds. For example, the second threshold can be determined based on factors such as the usage frequency and data storage volume of the first wafer, and the third threshold can be determined based on factors such as the usage frequency and data storage volume of the second wafer. The second threshold can be the same as or different from the third threshold.

[0055] Devices accessing DDR memory generate data read and write requests when under load. When data needs to be stored in DDR memory, the write request for DDR memory includes the data to be written.

[0056] DDR memory can receive data write requests. For example, after monitoring the used memory space of a first wafer and a second wafer, DDR memory can receive data write requests.

[0057] Before writing the data in the write request to the DDR memory, the used memory space of the first wafer can be determined. If the used memory space of the first wafer is less than a first threshold, the data to be written can be written to the first wafer according to the write request. If the used memory space of the first wafer is greater than or equal to the first threshold, the data to be written can be written to the second wafer according to the write request.

[0058] After the data to be written is written to the first wafer, it is also possible to determine whether the storage space of the second wafer is being used. If the storage space of the second wafer is not being used, the second wafer is controlled to enter a low-power mode.

[0059] After determining whether the storage space of the second wafer is used, it is also possible to determine whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold. If the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than the first threshold, the data stored on the second wafer is moved to the first wafer, and the second wafer is controlled to enter a low-power mode.

[0060] In heavy-load scenarios with high memory requirements, the first wafer alone cannot meet the memory demands. Therefore, after controlling the second wafer to enter low-power mode, it can be determined whether the used storage space of the first wafer is less than a first threshold. If the used storage space of the first wafer is greater than or equal to the first threshold, the second wafer is woken up from low-power mode, and the data to be written is written to the second wafer. If the used storage space of the first wafer is less than the first threshold, the data to be written is written to the first wafer. It should be noted that the above method steps are only one implementation provided by the embodiments of this application. The execution order of the above steps can be adjusted based on the embodiments provided by this application according to usage requirements. For example, the execution order of some steps can be changed. Or, some steps can be executed simultaneously.

[0061] Figure 8 Flowchart 800 illustrates another method for accessing DDR memory provided in this application embodiment. The following is in conjunction with… Figure 8 Taking SOC access to dual die DDR memory as an example, the working process of this implementation method is introduced.

[0062] In step S810, the SOC issues a data write request.

[0063] See again Figure 1 The SOC sends write requests to the DDR memory via signal lines such as clock line CK, command / address line CA, data line DQ, and chip select line CS. The write request includes the data to be written.

[0064] In step S820, the storage space information of die0 and die1 is monitored.

[0065] The storage space monitoring module can monitor the storage space information of die0 and die1 in the memory. The storage space information can include the amount of used memory space or the amount of unused memory space.

[0066] Additionally, the storage space information of die0 and die1 is updated in real time whenever the data in die0 and die1 changes. For example, the storage space information is updated when data writing is completed. Similarly, the storage space information is updated when data migration is completed.

[0067] In step S830, it is determined whether the used storage space of die0 exceeds the first threshold.

[0068] If the used storage space of die0 exceeds the first threshold, proceed to step S8310. If the used storage space of die0 does not exceed the first threshold, proceed to step S8320.

[0069] In step S8310, the data to be written is written to die1, and steps S8312 and S8324 are executed.

[0070] In step S8320, the data to be written is written to die0.

[0071] In step S8322, it is determined whether the storage space of die1 is being used.

[0072] If the storage space of die1 is not used, proceed to step S860. If data is stored in die1, continue to proceed to steps S8312 and S8324.

[0073] In step S8312, it is determined whether the used storage space of die1 exceeds the third threshold.

[0074] If the used storage space of die1 exceeds the third threshold, proceed to step S8314. If the used storage space of die1 does not exceed the third threshold, proceed to step S840.

[0075] In step S8314, the storage space of die1 is cleared, and step S840 is executed.

[0076] In step S8324, it is determined whether the used storage space of die0 exceeds the second threshold. If the used storage space of die0 exceeds the second threshold, then proceed to step S8326. If the used storage space of die0 does not exceed the second threshold, proceed to step S840.

[0077] In step S8326, clean up the storage space of die0 and continue to step S840.

[0078] In step S840, it is determined whether the sum of the used storage space of die0 and the used storage space of die1 is less than the first threshold.

[0079] If the sum of the used storage space of die0 and the used storage space of die1 is less than the first threshold, then proceed to step S850. If the sum of the used storage space of die0 and the used storage space of die1 is equal to or greater than the first threshold, then return to step S830 and wait for the next data write request.

[0080] In step S850, the data in die1 is moved to die0.

[0081] In step S860, control die1 to enter low power mode.

[0082] Return to step S830 and wait for the next data write request.

[0083] Through actual testing, the method for accessing DDR memory provided in this application embodiment is applicable to light and medium load scenarios. Since most applications of devices accessing DDR memory are in light and medium load scenarios, this method can effectively reduce the power consumption of DDR memory.

[0084] See again Figure 3 and Figure 4 DDR memory is primarily powered by three power rails: VDD1, VDD2, and VDDQ. VDD1, VDD2, and VDDQ supply power to the DDR memory core, interface, and I / O ports, respectively. Therefore, when calculating the power consumption of DDR memory, the power consumption (mW = mA × V) of the three power rails is added together as the total power consumption of the DDR memory.

[0085] Taking a light-load scenario of playing Douyin videos as an example and a medium-load scenario of playing Honor of Kings games as an example, the power consumption of the mobile phone before and after using the DDR memory access method provided in this application embodiment was tested, and the test results are shown in Table 1.

[0086]

[0087] Table 1 Comparison of power consumption before and after optimization

[0088] As can be seen from the test results in Table 1, the method for accessing DDR memory provided in this application embodiment can reduce the power consumption of dual die DDR memory by tens of milliwatts in medium and light load scenarios, with significant power consumption optimization effect.

[0089] The method for accessing DDR memory provided in this application can allocate write locations for data to be written based on the memory information of the first and second wafers. This allows the first wafer to be used and the second wafer to be controlled in a low-power mode during medium-to-light load scenarios, effectively reducing the overall power consumption of the DDR memory. Simultaneously, during heavy load scenarios with high memory demand, the second wafer is controlled to operate, thereby ensuring memory requirements are met. This method effectively reduces power consumption while ensuring a smooth user experience.

[0090] It should be noted that reading data from DDR memory involves retrieving data from pre-allocated addresses, which is a purely passive process. If writing data can reduce the power consumption of DDR memory, then reading data can also reduce its power consumption. Therefore, this application mainly describes the data writing process in the method of accessing DDR memory.

[0091] The above text combined Figures 1 to 8 The method embodiments of this application have been described in detail below, in conjunction with... Figures 9 to 12The apparatus embodiments of this application are described in detail below. It should be understood that the descriptions of the apparatus embodiments correspond to the descriptions of the method embodiments; therefore, any parts not described in detail can be referred to the foregoing method embodiments.

[0092] Figure 9 This is a schematic diagram of a structure for accessing a DDR memory device according to an embodiment of this application. The DDR memory device 900 may include a memory 910 and a processor 920.

[0093] The memory 910 can be used to store executable code. The processor 920 can be used to execute the instructions stored in the memory 910 to perform the following operations:

[0094] Monitor the used storage space of the first wafer and the used storage space of the second wafer; determine whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold; if the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than the first threshold, then move the data stored on the second wafer to the first wafer and control the second wafer to enter a low-power mode.

[0095] Optionally, before determining whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold, the processor is further configured to perform the following operations: if the used storage space of the first wafer is greater than a second threshold, clean up invalid data in the storage space of the first wafer; and / or, if the used storage space of the second wafer is greater than a third threshold, clean up invalid data in the storage space of the second wafer.

[0096] Optionally, after monitoring the used memory space of the first wafer and the used memory space of the second wafer, the processor is further configured to perform the following operations: receive a write request for the DDR memory, the write request including data to be written; if the used memory space of the first wafer is less than a first threshold, write the data to be written to the first wafer according to the write request; if the used memory space of the first wafer is greater than or equal to the first threshold, write the data to be written to the second wafer according to the write request.

[0097] Optionally, after writing the data to be written to the first wafer according to the write request, the processor is further configured to: determine whether the storage space of the second wafer is used; if the storage space of the second wafer is not used, control the second wafer to enter a low-power mode; determine whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold; if the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than the first threshold, then move the data stored on the second wafer to the first wafer, and control the second wafer to enter a low-power mode.

[0098] Optionally, after controlling the second wafer to enter the low-power mode, the processor is further configured to: determine whether the used storage space of the first wafer is less than a first threshold; if the used storage space of the first wafer is greater than the first threshold, wake up the second wafer from the low-power mode and write the data to be written to the second wafer; if the used storage space of the first wafer is less than the first threshold, write the data to be written to the first wafer.

[0099] Figure 10 This is a schematic diagram illustrating another structure for accessing a DDR memory device according to an embodiment of this application. Taking accessing a dual-die DDR memory via a System-on-a-Chip (SoC) as an example, the working process of accessing a DDR memory device will be described.

[0100] The storage space monitoring module 1030 monitors the used memory space of the first and second wafers in the dual-die DDR memory in real time. Additionally, the storage space monitoring module 1030 feeds back the memory space information to the storage space allocation module 1010, the data migration module 1040, and the storage space cleanup module 1050. Simultaneously, the storage space monitoring module 1030 updates the memory space information in real time based on the processing results of the data migration module 1040 and the storage space cleanup module 1050.

[0101] The storage space allocation module 1010 dynamically adjusts the write position (first wafer or second wafer) of the data to be written based on the data write request, the memory space information of the first wafer and the second wafer fed back by the storage space monitoring module, and the preset first threshold.

[0102] The control module 1020 writes the data to be written to the DDR memory according to the data write location allocated by the storage space allocation module 1010. For example, if the write location of the storage space allocation module 1010 is the first wafer, then the control module 1020 controls the data to be written to the first wafer. Simultaneously, the control module 1020 controls the first wafer and die1 to enter independent working states respectively according to the memory information of the first wafer or the second wafer in the dual-die DDR memory. For example, it controls the first wafer to be in a working state to meet the data write requirements of the SOC. Or, when the storage space of the second wafer is not used, it controls the second wafer to enter a low-power mode to reduce the power consumption of the DDR memory.

[0103] The data migration module 1040 determines whether to perform data migration based on the memory space information of the first and second wafers fed back by the storage space monitoring module 1030 and the first threshold. Simultaneously, it feeds back the processing result to the storage space monitoring module 1030.

[0104] The storage space cleanup module 1050 determines whether to perform space cleanup based on the memory space information of the first and second wafers fed back by the storage space monitoring module 1030, as well as the second and third thresholds. Simultaneously, it feeds back the processing result to the storage space monitoring module 1030.

[0105] Figure 11 This is a schematic diagram of a system for accessing DDR memory provided in an embodiment of this application. Figure 11 The system 1100 shown may include any implementation of the DDR memory 1110 and the DDR memory access device 900 described above.

[0106] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 12 The electronic device 1200 shown may include any implementation of the system 1100 for accessing DDR memory as described above.

[0107] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any other combination. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0108] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0110] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0111] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0112] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of accessing a DDR memory, the method comprising: The DDR memory includes a first wafer and a second wafer, wherein the first wafer and the second wafer are two dies in a dual-die DDR device. The method includes: Monitor the used memory space of the first wafer and the used memory space of the second wafer; Determine whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold. If the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than the first threshold, then the data stored in the second wafer is moved to the first wafer, and the second wafer is controlled to enter a low-power mode.

2. The method according to claim 1, characterized in that, Before determining whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold, the method further includes: If the used storage space of the first wafer exceeds the second threshold, clean up invalid data in the storage space of the first wafer; and / or, If the used storage space of the second wafer is greater than the third threshold, clean up the invalid data in the storage space of the second wafer.

3. The method according to claim 1 or 2, characterized in that, After monitoring the used memory space of the first wafer and the used memory space of the second wafer, the method further includes: Receive a write request for the DDR memory, the write request including data to be written; If the used storage space of the first wafer is less than the first threshold, then the data to be written is written to the first wafer according to the write request; If the used storage space of the first wafer is greater than or equal to the first threshold, the data to be written is written to the second wafer according to the write request.

4. The method according to claim 3, characterized in that, After writing the data to be written to the first wafer according to the write request, the method further includes: Determine whether the storage space of the second wafer is being used; If the storage space of the second wafer is not used, control the second wafer to enter the low-power mode.

5. The method according to claim 4, characterized in that, After controlling the second wafer to enter the low-power mode, the method further includes: Determine whether the used storage space of the first wafer is less than the first threshold. If the used storage space of the first wafer is greater than or equal to the first threshold, the second wafer is woken up from the low-power mode and the data to be written is written to the second wafer; If the used storage space of the first wafer is less than the first threshold, the data to be written is written to the first wafer.

6. An apparatus for accessing DDR memory, characterized in that, The DDR memory includes a first wafer and a second wafer, wherein the first wafer and the second wafer are two dies in a dual-die DDR device. The device includes: Memory, used to store instructions; A processor, configured to execute instructions stored in the memory to perform the following operations: Monitor the used memory space of the first wafer and the used memory space of the second wafer; Determine whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold. If the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than the first threshold, then the data stored in the second wafer is moved to the first wafer, and the second wafer is controlled to enter a low-power mode.

7. The apparatus according to claim 6, characterized in that, Before determining whether the sum of the used storage space of the first wafer and the used storage space of the second wafer is less than a first threshold, the processor is further configured to perform the following operations: If the used storage space of the first wafer exceeds the second threshold, clean up invalid data in the storage space of the first wafer; and / or, If the used storage space of the second wafer is greater than the third threshold, clean up the invalid data in the storage space of the second wafer.

8. The apparatus according to claim 6 or 7, characterized in that, After monitoring the used memory space of the first wafer and the second wafer, the processor is further configured to perform the following operations: Receive a write request for the DDR memory, the write request including data to be written; If the used storage space of the first wafer is less than the first threshold, then the data to be written is written to the first wafer according to the write request; If the used storage space of the first wafer is greater than or equal to the first threshold, the data to be written is written to the second wafer according to the write request.

9. A system for accessing DDR memory, characterized in that, include: DDR memory; as well as The apparatus as described in any one of claims 6-8 is used to access the DDR memory.

10. An electronic device, characterized in that, Includes the system as described in claim 9.

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