Current mirror circuit, amplifier and electronic device

Abstract

The application relates to a current mirror circuit, an amplifier and an electronic device, the current mirror circuit comprising a common-source unit, a common-gate unit, a first load, a second load and a feedback circuit, the feedback circuit being used for providing bias for the common-gate unit. The common-source unit comprises a first transistor and a second transistor, the common-gate unit comprises a third transistor and a fourth transistor; the gate of the first transistor, the gate of the second transistor and the drain of the third transistor are connected to an input current; the drain of the first transistor is connected to the source of the third transistor, and the source of the first transistor is connected to the first load; the gate of the third transistor and the gate of the fourth transistor are connected to the feedback circuit; the source of the second transistor is connected to the second load, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the fourth transistor provides an output current. Therefore, the current mirror circuit still has high current mirror precision when the input current range changes greatly.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to current mirror circuits, amplifiers, and electronic devices. Background Technology

[0002] In integrated circuit design, the current mirror circuit is a very important basic unit. Due to its advantages such as constant output current and insensitivity to input voltage, it is often used as an active load or current bias in amplifier circuits.

[0003] Traditional current mirrors use a resistor and diode to connect and bias a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor). The MOS transistors in the current mirror are all biased in the saturation region. However, the gate-source voltage and drain-source voltage of the MOS transistors in the current mirror vary greatly with the input current. When the input current range varies greatly, the MOS transistors can easily enter the non-saturation region, thereby affecting the performance of the current mirror and reducing its accuracy. Summary of the Invention

[0004] Therefore, it is necessary to provide a current mirror circuit, amplifier, and electronic device to address the issue of reduced accuracy when the input current range of the current mirror varies significantly.

[0005] A current mirror circuit includes: a common source cell, a common gate cell, a first load, a second load, and a feedback circuit, wherein the feedback circuit is used to provide a bias voltage for the common gate cell;

[0006] The common-source unit includes a first transistor and a second transistor, and the common-gate unit includes a third transistor and a fourth transistor; the gate of the first transistor, the gate of the second transistor, and the drain of the third transistor are respectively connected to the input current; the drain of the first transistor is connected to the source of the third transistor, and the source of the first transistor is connected to the first load; the gate of the third transistor and the gate of the fourth transistor are respectively connected to the feedback circuit; the source of the second transistor is connected to the second load, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the fourth transistor provides the output current.

[0007] In one embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors; the source of the first transistor is grounded through the first load, and the source of the second transistor is grounded through the second load.

[0008] In one embodiment, the feedback circuit includes a current source and a fifth transistor; the positive terminal of the current source is connected to a power supply, and the negative terminal of the current source is connected to the source of the fifth transistor, the gate of the third transistor, and the gate of the fourth transistor, respectively; the gate of the fifth transistor is connected to the source of the first transistor, and the drain of the fifth transistor is grounded.

[0009] In one embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are all PMOS transistors; the source of the first transistor is connected to a power supply through the first load, and the source of the second transistor is connected to a power supply through the second load.

[0010] In one embodiment, the feedback circuit includes a current source and a fifth transistor; the drain of the fifth transistor is connected to a power supply, the source of the fifth transistor is connected to the positive terminal of the current source, the gate of the third transistor, and the gate of the fourth transistor, respectively, and the negative terminal of the current source is grounded; the gate of the fifth transistor is also connected to the source of the first transistor.

[0011] In one embodiment, the ratio between the width-to-length ratio of the first transistor and the width-to-length ratio of the second transistor is a first ratio; the ratio between the width-to-length ratio of the third transistor and the width-to-length ratio of the fourth transistor is a second ratio; and the first ratio is equal to the second ratio.

[0012] In one embodiment, the first load is a first source degradation resistor, and the second load is a second source degradation resistor.

[0013] In one embodiment, the ratio of the resistance of the second source degradation resistor to the resistance of the first source degradation resistor is equal to the first ratio.

[0014] An amplifier comprising a current mirror circuit as described above.

[0015] An electronic device comprising an amplifier as described above.

[0016] The aforementioned current mirror circuit, amplifier, and electronic device include a common-source transistor, a common-gate transistor, a first load, a second load, and a feedback circuit. The feedback circuit provides bias to the common-gate transistor. When the input current changes significantly, the feedback circuit can quickly adjust the gate voltage of the transistor in the common-gate transistor, thereby adjusting the source-drain voltage of the transistor in the common-source transistor. This ensures that each transistor remains in the saturation region even with large input current variations, resulting in high current mirror accuracy despite wide input current ranges. This improves the response speed of the current mirror and guarantees its accuracy under large input current variations. By adding the first and second loads, the output resistance of the current mirror is increased, reducing the impact of output voltage deviation on the output current and improving the current mirror accuracy. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the current mirror circuit in one embodiment;

[0018] Figure 2 This is a schematic diagram of a traditional current mirror.

[0019] Figure 3 This is a schematic diagram of the current mirror circuit in another embodiment;

[0020] Figure 4 This is a schematic diagram of a traditional common-source cascode current mirror. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] In one embodiment, such as Figure 1 As shown, a current mirror circuit is provided, including: a common-source unit 10, a common-gate unit 20, a first load 30, a second load 40, and a feedback circuit 50. The feedback circuit 50 is used to provide a bias voltage for the common-gate unit 20. Specifically, the common-source unit 10 includes a first transistor M1 and a second transistor M3, and the common-gate unit 20 includes a third transistor M2 and a fourth transistor M4. The gate of the first transistor M1, the gate of the second transistor M3, and the drain of the third transistor M2 are respectively connected to the input current Iin; the drain of the first transistor M1 is connected to the source of the third transistor M2, and the source of the first transistor M1 is connected to the first load 30; the gate of the third transistor M2 and the gate of the fourth transistor M4 are respectively connected to the feedback circuit 50; the source of the second transistor M3 is connected to the second load 40, and the drain of the second transistor M3 is connected to the source of the fourth transistor M4. The drain of the fourth transistor M4 provides the output current Iout.

[0023] In traditional current mirror structures, when the input current range varies significantly, the MOSFETs easily enter the non-saturation region, thus reducing the accuracy of the current mirror. In this embodiment, transistors M1 and M3 in the common-source cell 10 and transistors M2 and M4 in the common-gate cell 20 are all biased in the saturation region. The effect of the drain voltage change of the common-gate cell 20 on the output current Iout is as follows:

[0024]

[0025] Wherein, △Iout represents the change in output current, △Vout represents the change in output voltage, R1 represents the resistance of the first load, gm3 represents the transconductance of the second transistor M3, gm4 represents the transconductance of the fourth transistor M4, ro3 represents the channel impedance of the second transistor M3, and ro4 represents the channel impedance of the fourth transistor M4.

[0026] It can be seen that by setting the source load, the output resistance of the current mirror is increased, thus reducing the impact of the output voltage deviation on the output current.

[0027] However, when the transistors are in the linear region, the intrinsic gains gm3ro3 and gm4ro4 of transistors M3 and M4 decrease significantly, and the output resistance decreases. This increases the impact of the mismatch between the output voltage Vout and the input voltage Vin on the current mirror mismatch, thus reducing the accuracy of the current mirror. In this embodiment, the feedback circuit 50 quickly adjusts the gate voltage of the common-gate cell 20, thereby adjusting the source-drain voltage of the common-source cell 10. This ensures that the common-source cell 10 and the common-gate cell 20 remain in the saturation region even when the input current changes significantly. The mismatch between the output voltage Vout and the input voltage Vin has a smaller impact on the mismatch current, allowing the current mirror circuit to maintain high accuracy even with a wide range of input current changes.

[0028] In the aforementioned current mirror circuit, when the transistors are in the linear region, the feedback loop responds quickly, adjusting the gate voltage of the transistors in the common-gate unit 20, thereby adjusting the source-drain voltage of the transistors in the common-source unit 10. This ensures that each transistor remains in the saturation region even when the input current varies significantly, thus maintaining high current mirror accuracy even with large variations in the input current range. Furthermore, by setting the first load 30 and the second load 40, the output resistance of the current mirror is increased, reducing the impact of output voltage deviation on the output current and improving the current mirror accuracy.

[0029] It should also be noted that in the traditional cascode current mirror structure, the current mismatch caused by the threshold voltage mismatch mainly depends on the threshold voltage mismatch of the common-source cell 10. In this embodiment, the magnitude of the current change ΔI caused by the slight change ΔVth in the threshold voltage of transistor M3 in the common-source cell 10 is:

[0030]

[0031]

[0032] Where ΔI represents the change in current, ΔVth represents the change in the threshold voltage of the second transistor M3, and G m3 Indicates the transconductance and V of the second transistor M3. gs3 Vth represents the gate-source voltage of the second transistor M3, R2 represents the threshold voltage of the second transistor M3, and I represents the resistance of the second load. D This represents the drain current of the second transistor M3.

[0033] In such Figure 2 The current mismatch caused by the threshold voltage mismatch ΔVth shown in the traditional current mirror is as follows:

[0034]

[0035] Where ΔI represents the change in current, I D Represents the drain current of the NMOS transistor, V th Indicates the threshold voltage of the NMOS transistor, V gs This represents the gate-source voltage of the NMOS transistor.

[0036] Comparing formulas (2) and (3), it can be seen that the current mismatch caused by the mismatch threshold voltage ΔVth in this embodiment is reduced by (1+g) m3 R2) times.

[0037] The relationship between transistor threshold voltage mismatch and transistor area is as follows:

[0038]

[0039] Where W represents the width of the transistor, L represents the length of the transistor, and V represents the width of the transistor. th Avth represents the transistor threshold voltage, and Avth represents the proportionality coefficient (obtained by measurement).

[0040] As can be determined by the formula, the deviation of the threshold voltage is negatively correlated with the area. Increasing the area of ​​the transistor can improve the accuracy of the current mirror. Therefore, under the same current mirror accuracy, the current mirror provided in this embodiment has a smaller area.

[0041] In the aforementioned current mirror circuit, when the transistors are in the linear region, the feedback circuit 50 adjusts the gate voltage of the transistors in the common-gate unit 20, thereby adjusting the source-drain voltage of the transistors in the common-source unit 10. This ensures that each transistor remains in the saturation region even when the input current changes significantly, resulting in high current mirror accuracy even with large variations in the input current range. This improves the response speed of the current mirror and increases its input current range. Furthermore, by setting the first load 30 and the second load 40, the output resistance of the current mirror is increased, reducing the impact of output voltage deviation on the output current and improving the current mirror accuracy. Additionally, the current mirror area is smaller.

[0042] In one embodiment, the ratio between the width-to-length ratio of the first transistor M1 and the width-to-length ratio of the second transistor M3 is a first ratio; the ratio between the width-to-length ratio of the third transistor M2 and the width-to-length ratio of the fourth transistor M4 is a second ratio; the first ratio equals the second ratio. This makes the output circuit Iout a proportional mirror current of the input current Iin.

[0043] Assume the aspect ratio of the first transistor M1 is W1 / L1, the aspect ratio of the second transistor M3 is W3 / L3, the aspect ratio of the third transistor M2 is W2 / L2, and the aspect ratio of the fourth transistor M4 is W4 / L4. The first ratio and the second ratio are both 1:N, where N is an integer. The first ratio and the second ratio can be specifically expressed as follows:

[0044] W1 / L1:W3 / L3=1:N

[0045] W2 / L2:W4 / L4=1:N

[0046] In one embodiment, the first load 30 is a first source degradation resistor R1, and the second load 40 is a second source degradation resistor R2. This embodiment utilizes the characteristic that resistance is relatively insensitive to environmental changes to provide a stable output impedance, and the circuit structure is simple and low in cost.

[0047] Furthermore, the ratio of the resistance values ​​of the second source degradation resistor R2 to the first source degradation resistor R1 is equal to the first ratio.

[0048] If the first ratio is 1:N, then set R1:R2 = N:1. This makes the output circuit Iout a proportional mirror current of the input current Iin, Iin:Iout = 1:N, resulting in a more accurate output current.

[0049] Understandably, the types and parameters of the first transistor M1, the second transistor M3, the third transistor M2, and the fourth transistor M4 can be set according to actual needs. In one embodiment, such as Figure 1As shown, the first transistor M1, the second transistor M3, the third transistor M2 and the fourth transistor M4 are all NMOS transistors; the source of the first transistor M1 is grounded through the first load 30, and the source of the second transistor M3 is grounded through the second load 40.

[0050] Furthermore, the feedback circuit 50 includes a current source I0 and a fifth transistor M0; the positive terminal of the current source I0 is connected to the power supply, the negative terminal of the current source I0 is connected to the source of the fifth transistor M0, the negative terminal of the current source I0 serves as the feedback terminal of the feedback circuit 50, and is also connected to the gate of the third transistor M2 and the gate of the fourth transistor M4; the gate of the fifth transistor M0 is connected to the source of the first transistor M1, and the drain of the fifth transistor M0 is grounded. This feedback circuit 50 can keep the MOSFET in the saturation region when the input current increases over a wide range, thus ensuring high current mirror accuracy even when the input current varies significantly.

[0051] In one embodiment, such as Figure 3 As shown, the first transistor M1, the second transistor M3, the third transistor M2 and the fourth transistor M4 are all PMOS transistors; the source of the first transistor M1 is connected to the power supply through the first load 30, and the source of the second transistor M3 is connected to the power supply through the second load 40.

[0052] Furthermore, the feedback circuit 50 includes a current source I0 and a fifth transistor M0; the drain of the fifth transistor M0 is connected to the power supply, and the source of the fifth transistor M0 is connected to the positive terminal of the current source I0, the gate of the third transistor M2, and the gate of the fourth transistor M4, respectively; the negative terminal of the current source I0 is grounded; the gate of the fifth transistor M0 is also connected to the source of the first transistor M1. This feedback circuit 50 can keep the MOSFET in the saturation region when the input current increases over a wide range, thus ensuring high current mirror accuracy even when the input current varies significantly.

[0053] For ease of understanding, the following will be used as... Figure 1 The illustrated embodiments will be explained. Figure 3 The principle of the embodiments shown is the same, and will not be described again.

[0054] Understandably, MOS transistors need to meet the following requirements in the saturation region:

[0055] Vgs-Vth <Vds

[0056] Vgs+ΔVgs-Vth <Vds+ΔVds

[0057] ΔVgs-ΔVds <Vds-(Vgs-Vth)

[0058] Where Vgs represents the gate-source voltage of the transistor, Vth represents the threshold voltage of the transistor, and Vds represents the drain-source voltage of the transistor. It is evident that the smaller ΔVgs-ΔVds is, the less likely the transistor is to enter the non-saturation region.

[0059] When the input current varies over a wide range ΔIin, neglecting second-order effects, we can obtain:

[0060] ΔVs1=ΔVd2=ΔIinR1

[0061] ΔVg2=ΔIin*R1

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[0068] Wherein, Vs1 represents the source voltage of transistor M1, Vd2 represents the drain voltage of transistor M2, Iin represents the input current, R1 represents the resistance value of the first source degradation resistor R1, Vg2 represents the gate voltage of transistor M2, Vg1 represents the gate voltage of transistor M1, μ represents the carrier mobility, Cox represents the gate oxide capacitance per unit area, W1 represents the width of transistor M1, L1 represents the length of transistor M1, Vgs2 represents the gate-source voltage of transistor M2, W2 represents the width of transistor M2, L2 represents the length of transistor M2, Vds1 represents the drain-source voltage of transistor M1, Vgs1 represents the gate-source voltage of transistor M1, and Vds2 represents the drain-source voltage of transistor M2.

[0069] As can be seen from the above formula, ΔVgs1 and ΔVds1 change little with the current, which can keep the MOSFET in the saturation region when the current input changes over a wide range, thus enabling the current mirror to still have high accuracy when the input current changes over a wide range.

[0070] Reference Figure 4 , Figure 4 For a traditional common-source cascode current mirror structure, when the input current varies over a large range by ΔIin:

[0071] ΔVgs22-ΔVds22=ΔIR0

[0072] Where Vgs22 represents the gate-source voltage of MOSFET 22, Vds22 represents the drain-source voltage of MOSFET 22, I represents the input current, and R0 represents the resistance value of resistor R0.

[0073] Combining the above formula, we can obtain:

[0074] ΔVgs22-ΔVds22>ΔVgs1-ΔVds1>ΔVgs2-ΔVds2

[0075] It is evident that when there is the same current change ΔIin, ΔVgs22-ΔVds22 is the largest. Compared to the current mirror structure in this embodiment, the transistor is more likely to enter the non-saturation region in the traditional cascode current mirror structure. Therefore, for MOS transistors with the same Vds-(Vgs-Vth), the current mirror in this embodiment allows for a larger ΔI and a wider input current range.

[0076] Furthermore, the feedback circuit 50 in this embodiment also features a fast response speed. Specifically,

[0077] The poles of the feedback circuit 50 are as follows:

[0078] The equivalent resistance at point A is approximately:

[0079] The capacitance at point A is approximately: C = Cs1 + Cg0

[0080] The pole of point A is:

[0081] The equivalent resistance at point B is approximately:

[0082] The capacitance at point B is approximately: C = Cg1 + Cd2

[0083] The pole of point B is:

[0084] The equivalent resistance at point C is approximately:

[0085] The capacitance at point C is approximately: C = Cg² + Cs₀

[0086] The pole of point C is:

[0087] Among them, g m1 Cs1 represents the transconductance of transistor M1, Cs1 represents the source capacitance of transistor M1, Cg0 represents the gate capacitance of transistor M0, R1 represents the resistance of the first source degradation resistor R1, Cg1 represents the gate capacitance of transistor M1, Cd2 represents the drain capacitance of transistor M2, g m0Cg2 represents the transconductance of transistor M0, Cg2 represents the gate capacitance of transistor M2, and Cs2 represents the source capacitance of transistor M2.

[0088] R1 can be set as a small resistor, with a base value of approximately several hundred ohms, making the pole at point B high. As can be seen from the above node formula, the capacitance and resistance of the node are very small, and the pole frequency is 1 / RC, which is very high. Therefore, the feedback circuit 50 has a fast response speed and can quickly respond to changes in the input current to adjust the gate voltage of the common gate unit 20.

[0089] In summary, the current mirror circuit described above improves current matching accuracy, increases current range, and enhances response speed by adding two source degradation resistors and feedback circuit 50. It also has advantages such as simple circuit and small area.

[0090] In one embodiment, an amplifier is provided, the amplifier including a current mirror circuit, the current mirror circuit including: a common-source cell, a common-gate cell, a first load, a second load, and a feedback circuit, the feedback circuit being used to provide a bias voltage for the common-gate cell; the common-source cell includes a first transistor and a second transistor, the common-gate cell includes a third transistor and a fourth transistor; the gate of the first transistor, the gate of the second transistor, and the drain of the third transistor are respectively connected to an input current; the drain of the first transistor is connected to the source of the third transistor, and the source of the first transistor is connected to the first load; the gate of the third transistor and the gate of the fourth transistor are respectively connected to the feedback circuit; the source of the second transistor is connected to the second load, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the fourth transistor provides an output current.

[0091] When the input current changes significantly, the feedback circuit can quickly adjust the gate voltage of the transistors in the common-gate cell, thereby adjusting the source-drain voltage of the transistors in the common-source cell. This ensures that each transistor remains in the saturation region even with large input current variations, maintaining high current mirror accuracy despite wide ranges of input current variation. This improves the current mirror's response speed and guarantees accuracy even with large input current changes. By adding a first and second load, the output resistance of the current mirror is increased, reducing the impact of output voltage deviation on the output current and improving current mirror accuracy. This, in turn, enhances the amplifier's input current range and accuracy.

[0092] In one embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors; the source of the first transistor is grounded through a first load, and the source of the second transistor is grounded through a second load.

[0093] In one embodiment, the feedback circuit includes a current source and a fifth transistor; the positive terminal of the current source is connected to a power supply, and the negative terminal of the current source is connected to the source of the fifth transistor, the gate of the third transistor, and the gate of the fourth transistor, respectively; the gate of the fifth transistor is connected to the source of the first transistor, and the drain of the fifth transistor is grounded.

[0094] In one embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are all PMOS transistors; the source of the first transistor is connected to the power supply through a first load, and the source of the second transistor is connected to the power supply through a second load.

[0095] In one embodiment, the feedback circuit includes a current source and a fifth transistor; the drain of the fifth transistor is connected to a power supply, the source of the fifth transistor is connected to the positive terminal of the current source, the gate of the third transistor, and the gate of the fourth transistor, respectively, and the negative terminal of the current source is grounded; the gate of the fifth transistor is also connected to the source of the first transistor.

[0096] In one embodiment, the ratio between the width-to-length ratio of the first transistor and the width-to-length ratio of the second transistor is a first ratio; the ratio between the width-to-length ratio of the third transistor and the width-to-length ratio of the fourth transistor is a second ratio; the first ratio is equal to the second ratio.

[0097] In one embodiment, the first load is a first source degradation resistor, and the second load is a second source degradation resistor.

[0098] In one embodiment, the ratio of the resistance of the second source degradation resistor to the resistance of the first source degradation resistor is equal to the first ratio.

[0099] In one embodiment, an electronic device is provided, which includes an amplifier whose structure can be configured as described in the above embodiments. Specifically, in one embodiment, the amplifier includes a current mirror circuit, which includes: a common-source unit, a common-gate unit, a first load, a second load, and a feedback circuit. The feedback circuit is used to provide a bias voltage for the common-gate unit. The common-source unit includes a first transistor and a second transistor, and the common-gate unit includes a third transistor and a fourth transistor. The gate of the first transistor, the gate of the second transistor, and the drain of the third transistor are respectively connected to an input current. The drain of the first transistor is connected to the source of the third transistor, and the source of the first transistor is connected to the first load. The gates of the third transistor and the fourth transistor are respectively connected to the feedback circuit. The source of the second transistor is connected to the second load, and the drain of the second transistor is connected to the source of the fourth transistor. The drain of the fourth transistor provides an output current.

[0100] In one embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors; the source of the first transistor is grounded through a first load, and the source of the second transistor is grounded through a second load.

[0101] In one embodiment, the feedback circuit includes a current source and a fifth transistor; the positive terminal of the current source is connected to a power supply, and the negative terminal of the current source is connected to the source of the fifth transistor, the gate of the third transistor, and the gate of the fourth transistor, respectively; the gate of the fifth transistor is connected to the source of the first transistor, and the drain of the fifth transistor is grounded.

[0102] In one embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are all PMOS transistors; the source of the first transistor is connected to the power supply through a first load, and the source of the second transistor is connected to the power supply through a second load.

[0103] In one embodiment, the feedback circuit includes a current source and a fifth transistor; the drain of the fifth transistor is connected to a power supply, the source of the fifth transistor is connected to the positive terminal of the current source, the gate of the third transistor, and the gate of the fourth transistor, respectively, and the negative terminal of the current source is grounded; the gate of the fifth transistor is also connected to the source of the first transistor.

[0104] In one embodiment, the ratio between the width-to-length ratio of the first transistor and the width-to-length ratio of the second transistor is a first ratio; the ratio between the width-to-length ratio of the third transistor and the width-to-length ratio of the fourth transistor is a second ratio; the first ratio is equal to the second ratio.

[0105] In one embodiment, the first load is a first source degradation resistor, and the second load is a second source degradation resistor.

[0106] In one embodiment, the ratio of the resistance of the second source degradation resistor to the resistance of the first source degradation resistor is equal to the first ratio.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A current mirror circuit, characterized in that, include: The system includes a common source cell, a common gate cell, a first load, a second load, and a feedback circuit. The feedback circuit is used to quickly adjust the gate voltage of the common gate cell, thereby adjusting the source-drain voltage of the common source cell, so that the common source cell and the common gate cell remain in the saturation region when the input current changes. The common-source unit includes a first transistor and a second transistor, and the common-gate unit includes a third transistor and a fourth transistor; the gate of the first transistor, the gate of the second transistor, and the drain of the third transistor are respectively connected to the input current; the drain of the first transistor is connected to the source of the third transistor, and the source of the first transistor is connected to the first load; the gate of the third transistor and the gate of the fourth transistor are respectively connected to the feedback circuit; the source of the second transistor is connected to the second load, the drain of the second transistor is connected to the source of the fourth transistor, and the drain of the fourth transistor provides the output current; Wherein, the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors; The source of the first transistor is grounded through the first load, and the source of the second transistor is grounded through the second load; the feedback circuit includes a current source and a fifth transistor; the positive terminal of the current source is connected to a power supply, and the negative terminal of the current source is connected to the source of the fifth transistor, the gate of the third transistor, and the gate of the fourth transistor, respectively; the gate of the fifth transistor is connected to the source of the first transistor, and the drain of the fifth transistor is grounded.

2. The current mirror circuit according to claim 1, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are all PMOS transistors; the source of the first transistor is connected to the power supply through the first load, and the source of the second transistor is connected to the power supply through the second load.

3. The current mirror circuit according to claim 2, characterized in that, The feedback circuit includes a current source and a fifth transistor; the drain of the fifth transistor is connected to a power supply, and the source of the fifth transistor is connected to the positive terminal of the current source, the gate of the third transistor, and the gate of the fourth transistor, respectively; the negative terminal of the current source is grounded; the gate of the fifth transistor is also connected to the source of the first transistor.

4. The current mirror circuit according to claim 1, characterized in that, The ratio between the width-to-length ratio of the first transistor and the width-to-length ratio of the second transistor is a first ratio; the ratio between the width-to-length ratio of the third transistor and the width-to-length ratio of the fourth transistor is a second ratio; the first ratio is equal to the second ratio.

5. The current mirror circuit according to claim 4, characterized in that, The first load is a first source degradation resistor, and the second load is a second source degradation resistor.

6. The current mirror circuit according to claim 5, characterized in that, The ratio of the resistance of the second source degradation resistor to the resistance of the first source degradation resistor is equal to the first ratio.

7. An amplifier, characterized in that, Includes the current mirror circuit as described in claims 1-6.

8. An electronic device, characterized in that, Includes the amplifier as described in claim 7.

Images