Display panel

Abstract

The embodiment of the present application discloses a display panel, comprising a pull-down circuit with a pull-down control unit and a pull-down unit, the pull-down control unit is connected with a forward scanning signal, a reverse scanning signal and a constant voltage low-level signal, and is used for outputting the constant voltage low-level signal to the pull-down unit according to the forward scanning signal or the reverse scanning signal, the pull-down unit is located in a display area and comprises a plurality of pull-down sub-units in cascade, each pull-down sub-unit is connected with a next-stage scanning driving signal and a previous-stage scanning driving signal, and is used for pulling down the potential of a scanning driving signal input end of a current-stage pixel circuit according to the previous-stage scanning driving signal or the next-stage scanning driving signal, and the present application effectively improves the resistance-capacitance delay problem of the scanning driving signal input end of the current-stage pixel circuit by setting the pull-down circuit, reduces the display abnormality of the display panel, and improves the display quality of the display panel.

Description

Technical Field

[0001] This invention relates to the field of displays, and more specifically to a display panel. Background Technology

[0002] Currently, with the rapid development of display technology, people's needs for display products are becoming more diversified. Higher resolution, larger screens, and higher driving frequencies are the directions for improvement in display panels. However, this also presents challenges such as increased load on the display panel's signal lines and resistor / capacitor delays at the scan drive signal input terminals connected to the scan signal lines, leading to display abnormalities. For example... Figure 1 As shown, when the display panel screen is wide, the scanning drive signal input terminals in different display sub-areas (AA1, AA2, AA3) within the display area all have varying degrees of resistance and capacitance delay problems. Moreover, the further away the display sub-area is from the gate on array (GOA) circuit, the more obvious the resistance and capacitance delay problem at the scanning drive signal input terminal becomes.

[0003] Therefore, there is an urgent need for a display panel to solve the above-mentioned technical problems. Summary of the Invention

[0004] This invention provides a display panel that can alleviate the technical problem of abnormal image display caused by the resistance and capacitance delay at the scan drive signal input terminal connected to the scan signal line.

[0005] The present invention provides a display panel having a display area and a non-display area surrounding the display area, and comprising:

[0006] The pull-down circuit includes a pull-down control unit and a pull-down unit;

[0007] The pull-down control unit is connected to a forward scan signal, a reverse scan signal, and a constant voltage low-level signal, and is used to output the constant voltage low-level signal to the pull-down unit according to the forward scan signal or the reverse scan signal.

[0008] The pull-down unit is located within the display area and includes multiple cascaded pull-down sub-units. Each pull-down sub-unit is connected to the next-level scan drive signal, the previous-level scan drive signal, and the constant voltage low-level signal, and is used to pull down the potential of the scan drive signal input terminal of the pixel circuit of this level according to the previous-level scan drive signal or the next-level scan drive signal.

[0009] Preferably, the pull-down control unit includes a positive pull-down control subunit and a negative pull-down control subunit, and the pull-down unit includes a positive pull-down unit and a negative pull-down unit;

[0010] Each of the positive pull-down control subunits outputs the constant voltage low-level signal to a corresponding positive pull-down unit according to the positive scanning signal.

[0011] Each of the aforementioned reverse pull-down control subunits outputs the constant voltage low-level signal to a corresponding reverse pull-down unit according to the reverse scan signal.

[0012] Preferably, the pull-down control unit includes a positive pull-down control subunit and a negative pull-down control subunit, and the pull-down unit includes a positive pull-down unit and a negative pull-down unit;

[0013] Each of the positive pull-down control subunits outputs the constant voltage low-level signal to multiple corresponding positive pull-down units according to the positive scanning signal;

[0014] Each of the aforementioned reverse pull-down control subunits outputs the constant voltage low-level signal to multiple corresponding reverse pull-down units according to the reverse scan signal.

[0015] Preferably, the positive pull-down control subunit includes a first transistor, the first terminal of the first transistor is connected to the positive scanning signal, the second terminal of the first transistor is connected to the constant voltage low-level signal, and the third terminal of the first transistor is connected to the constant voltage low-level signal input terminal of the pull-down unit.

[0016] The reverse pull-down control subunit includes a second transistor, the first terminal of which is connected to the reverse scan signal, the second terminal of which is connected to the constant voltage low-level signal, and the third terminal of which is connected to the constant voltage low-level signal input terminal of the pull-down unit.

[0017] Preferably, the positive pull-down unit includes multiple cascaded positive pull-down sub-units, each positive pull-down sub-unit including a positive pull-down transistor. The first terminal of the positive pull-down transistor is connected to the next-level scan drive signal, the second terminal of the positive pull-down transistor is connected to the constant voltage low-level signal output terminal corresponding to the positive pull-down control sub-unit, and the third terminal of the positive pull-down transistor is connected to the scan drive signal input terminal of the pixel circuit at this level.

[0018] The reverse pull-down unit includes multiple cascaded reverse pull-down sub-units. Each reverse pull-down sub-unit includes a reverse pull-down transistor. The first terminal of the reverse pull-down transistor is connected to the previous stage scan drive signal. The second terminal of the reverse pull-down transistor is connected to the constant voltage low-level signal output terminal corresponding to the reverse pull-down control sub-unit. The third terminal of the reverse pull-down transistor is connected to the scan drive signal input terminal of the pixel circuit at this stage.

[0019] Preferably, the display panel includes multiple positive pull-down control lines and multiple negative pull-down control lines, with the third terminal of the first transistor connected to the positive pull-down control line and the third terminal of the second transistor connected to the negative pull-down control line.

[0020] The second terminal of the positive pull-down transistor in each of the positive pull-down units is connected to the same positive pull-down control line, and the second terminal of the reverse pull-down transistor in each of the reverse pull-down units is connected to the same reverse pull-down control line.

[0021] Preferably, the positive pull-down control trace includes a first positive pull-down control trace segment located in the display area and a second positive pull-down control trace segment located in the non-display area, and the negative pull-down control trace includes a first negative pull-down control trace segment located in the display area and a second negative pull-down control trace segment located in the non-display area.

[0022] The first end of the second positive pull-down control trace is connected to the third end of the first transistor in a one-to-one correspondence, and the second end of the second positive pull-down control trace is connected to the first positive pull-down control trace.

[0023] The first end of the second reverse pull-down control trace is connected to the third end of the second transistor in a one-to-one correspondence, and the second end of the second reverse pull-down control trace is connected to the first reverse pull-down control trace.

[0024] Preferably, the second end of the second positive pull-down control trace is connected to the first end of the first positive pull-down control trace in a one-to-one correspondence, and the second end of the second reverse pull-down control trace is connected to the first end of the first reverse pull-down control trace in a one-to-one correspondence.

[0025] Preferably, the second end of the second positive pull-down control routing segment is connected to the first end of the plurality of first positive pull-down control routing segments, and the second end of the second reverse pull-down control routing segment is connected to the first end of the plurality of first reverse pull-down control routing segments.

[0026] Preferably, the display panel further includes:

[0027] The scan signal lines are arranged continuously along the row direction;

[0028] The data signal lines are arranged continuously along the column direction and are interleaved with the scan signal lines;

[0029] Wherein, the extension direction of the positive pull-down control trace is parallel to the extension direction of the data signal line, and the extension direction of the reverse pull-down control trace is parallel to the extension direction of the data signal line.

[0030] This invention effectively improves the resistor-capacitor delay problem at the scanning drive signal input terminal of the pixel circuit by setting a pull-down circuit, thereby reducing display abnormalities and improving the display quality of the display panel. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram illustrating the resistor-capacitor delay problem in existing display panels;

[0033] Figure 2 This is a schematic diagram of the first structure of the pull-down circuit provided in the embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the second structure of the pull-down circuit provided in the embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the forward scanning signal and the reverse scanning signal of the display panel during the forward scanning stage provided in the embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the forward scanning signal and the reverse scanning signal of the display panel during the forward scanning stage provided in the embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the first structure of the display panel provided in an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of a second structure of the display panel provided in an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram illustrating the improvement of the resistance-capacitance delay problem of the display panel provided in an embodiment of the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0041] Currently, due to the increased load on the scan signal lines of the display panel, a resistor-capacitor delay problem occurs at the input terminal of the scan drive signal connected to the scan signal lines, resulting in abnormal image display on the display panel.

[0042] Please see Figures 2 to 8 This invention provides a display panel 10, which has a display area AA and a non-display area NA surrounding the display area AA, and includes:

[0043] The pull-down circuit 100 includes a pull-down control unit 101 and a pull-down unit 102;

[0044] The pull-down control unit 101 is connected to a forward scan signal U2D, a reverse scan signal D2U, and a constant voltage low-level signal VGL, and is used to output the constant voltage low-level signal VGL to the pull-down unit 102 according to the forward scan signal U2D or the reverse scan signal D2U.

[0045] The pull-down unit 102 is located within the display area AA and includes multiple cascaded pull-down sub-units. Each pull-down sub-unit is connected to the next-level scan drive signal, the previous-level scan drive signal, and the constant voltage low-level signal VGL, and is used to pull down the potential of the scan drive signal input terminal of the pixel circuit of this level according to the previous-level scan drive signal or the next-level scan drive signal.

[0046] This invention, by setting the pull-down circuit 100 within the display area AA, allows the pull-down control unit 101 to output a constant low-level signal VGL to the pull-down unit 102 based on the forward scan signal U2D or the reverse scan signal D2U. The pull-down unit 102 then pulls down the potential of the scan drive signal input terminal of the current pixel circuit based on the previous or next level scan drive signal. This effectively improves the resistance-capacitance delay of the scan drive signal input terminal of the current pixel circuit, reduces display abnormalities of the display panel 10, and improves the display quality of the display panel 10.

[0047] The technical solution of the present invention will now be described in conjunction with specific embodiments.

[0048] Please see Figure 2 as well as Figure 3 In this embodiment, the pull-down control unit 101 includes a positive pull-down control subunit 103 and a negative pull-down control subunit 104;

[0049] Each of the positive pull-down control subunits 103 outputs the constant voltage low-level signal VGL to a corresponding pull-down unit 102 according to the positive scanning signal U2D.

[0050] Each of the reverse pull-down control subunits 104 outputs the constant voltage low-level signal VGL to a corresponding pull-down unit 102 according to the reverse scan signal D2U.

[0051] In some embodiments, the pull-down control unit 101 may be located in the non-display area NA.

[0052] In some embodiments, the pull-down unit 102 may include a positive pull-down unit 105 and a negative pull-down unit 106. Each positive pull-down control subunit 103 outputs the constant voltage low-level signal VGL to a corresponding positive pull-down unit 105 according to the positive scan signal U2D; each negative pull-down control subunit 104 outputs the constant voltage low-level signal VGL to a corresponding negative pull-down unit 106 according to the negative scan signal D2U. The one-to-one correspondence between the positive pull-down control subunits 103 and 105, and between the negative pull-down control subunits 104 and 106, helps reduce the load on each positive pull-down control subunit 103 and each negative pull-down control subunit 104, and simplifies the circuit design of the display panel 10, thereby reducing the manufacturing cost of the display panel 10.

[0053] Alternatively, each of the positive pull-down control subunits 103 outputs the constant voltage low-level signal VGL to multiple corresponding positive pull-down units 105 according to the positive scan signal U2D; each of the negative pull-down control subunits 104 outputs the constant voltage low-level signal VGL to multiple corresponding negative pull-down units 106 according to the negative scan signal D2U. This one-to-many arrangement of the positive pull-down control subunits 103 and 105, and the one-to-many arrangement of the negative pull-down control subunits 104 and 106, helps to reduce the number of positive pull-down control subunits 103 and 104, saving space in the display panel 10 and improving the space utilization of the display panel 10.

[0054] Please see Figure 6 as well as Figure 7 In some embodiments, the positive pull-down control subunit 103 includes a first transistor T1, the first terminal of the first transistor T1 is connected to the positive scan signal U2D, the second terminal of the first transistor T1 is connected to the constant voltage low level signal VGL, and the third terminal of the first transistor T1 is connected to the constant voltage low level signal input terminal of the pull-down unit 102.

[0055] The reverse pull-down control subunit 104 includes a second transistor T2. The first terminal of the second transistor T2 is connected to the reverse scan signal D2U, the second terminal of the second transistor T2 is connected to the constant voltage low-level signal VGL, and the third terminal of the second transistor T2 is connected to the constant voltage low-level signal input terminal of the pull-down unit 102.

[0056] The first terminal of the first transistor T1 can be the gate of the first transistor T1, the second terminal of the first transistor T1 can be the source or drain of the first transistor T1, and the third terminal of the first transistor T1 can be either the source or drain of the first transistor T1 that is different from the second terminal of the first transistor T1; the first terminal of the second transistor T2 can be the gate of the second transistor T2, the second terminal of the second transistor T2 can be either the source or drain of the second transistor T2, and the third terminal of the second transistor T2 can be either the source or drain of the second transistor T2 that is different from the second terminal of the second transistor T2.

[0057] Please see Figure 4 , Figure 6 as well as Figure 7When the display panel 10 is in the forward scanning phase, the forward scanning signal U2D is a high-level signal, the first terminal of the first transistor T1 is connected to a high-level signal, the first transistor T1 is turned on, and the constant voltage low-level signal VGL is connected from the second terminal of the first transistor T1 and output from the third terminal of the first transistor T1 to the constant voltage low-level signal input terminal of the pull-down unit 102. Simultaneously, the reverse scanning signal D2U is a low-level signal, the first terminal of the second transistor T2 is connected to a low-level signal, and the second transistor T2 is turned off. When the forward scanning signal U2D is a high-level signal, the value of this high-level signal can be 9V; when the reverse scanning signal D2U is a low-level signal, the value of this low-level signal can be -7V.

[0058] Please see Figures 5 to 7 When the display panel 10 is in the reverse scanning phase, the reverse scanning signal D2U is a high-level signal, the first terminal of the second transistor T2 is connected to a high-level signal, the second transistor T2 is turned on, and the constant voltage low-level signal VGL is connected from the second terminal of the second transistor T2 and output from the third terminal of the second transistor T2 to the constant voltage low-level signal input terminal of the pull-down unit 102. Simultaneously, the forward scanning signal U2D is a low-level signal, the first terminal of the first transistor T1 is connected to a low-level signal, and the first transistor T1 is turned off. When the reverse scanning signal D2U is a high-level signal, the value of this high-level signal can be 9V; when the forward scanning signal U2D is a low-level signal, the value of this low-level signal can be -7V.

[0059] Please see Figures 6 to 7 In some embodiments, the positive pull-down unit 105 includes multiple cascaded positive pull-down sub-units, each including a positive pull-down transistor T. 正 The positive pull-down transistor T 正 The first terminal is connected to the next-stage scan drive signal, and the positive pull-down transistor T 正 The second terminal is connected to the constant voltage low-level signal output terminal corresponding to the positive pull-down control subunit 103, and the positive pull-down transistor T 正 The third terminal is connected to the scan drive signal input terminal of the pixel circuit of this stage.

[0060] The reverse pull-down unit 106 includes multiple cascaded reverse pull-down sub-units, each of which includes a reverse pull-down transistor T. 反 The reverse pull-down transistor T 反 The first terminal is connected to the previous stage scan drive signal, and the reverse pull-down transistor T 反The second terminal is connected to the constant voltage low-level signal output terminal corresponding to the reverse pull-down control subunit 104, and the reverse pull-down transistor T 反 The third terminal is connected to the scan drive signal input terminal of the pixel circuit of this stage.

[0061] The positive pull-down transistor T 正 The first terminal is the positive pull-down transistor T. 正 The gate of the positive pull-down transistor T 正 The second terminal can be the positive pull-down transistor T 正 The source or drain of the positive pull-down transistor T 正 The third terminal can be the positive pull-down transistor T. 正 The source or drain of the positive pull-down transistor T 正 The second end is different from one of the reverse pull-down transistors T. 反 The first terminal can be the reverse pull-down transistor T 反 The gate of the reverse pull-down transistor T 反 The second terminal can be the reverse pull-down transistor T 反 The source or drain of the reverse pull-down transistor T 反 The third terminal can be the reverse pull-down transistor T. 反 The source or drain of the reverse pull-down transistor T 反 The second end is different from the other.

[0062] The display panel 10 includes a gate-on-array (GOA) circuit located within the non-display area NA. The gate-on-array circuit can be located on one side of the display area AA or on opposite sides of the display area AA. The gate-on-array circuit provides a progressive scan drive signal to the display area AA of the display panel 10 via a scan signal line (Scan). When the display panel 10 is in the forward scan phase, the progressive scan drive signal provided by the gate-on-array circuit is transmitted forward along the row direction; when the display panel 10 is in the reverse scan phase, the progressive scan drive signal provided by the gate-on-array circuit is transmitted backward along the row direction.

[0063] Please see Figure 8In some embodiments, the gate driving circuit may include a first sub-gate driving circuit 109 and a second sub-gate driving circuit 110 located on opposite sides of the display area AA. The display area AA includes a first display sub-area AA1 near the first sub-gate driving circuit 109, a third display sub-area AA3 near the second sub-gate driving circuit 110, and a second display sub-area AA2 located between the first display sub-area AA1 and the third display sub-area AA3.

[0064] Please see Figures 6 to 8 In some embodiments, the scan signal lines Scan are arranged continuously along the row direction and sequentially in the forward direction. The display panel 10 also includes data signal lines Data arranged continuously along the column direction, with the data signal lines Data and Scan being interleaved. The data signal lines Data and Scan are interleaved to form sub-pixel areas. The display panel 10 also includes pixel circuits corresponding to each sub-pixel area, and each pixel circuit includes a switching transistor T. pixel The switching transistor T pixel The first terminal is the scan drive signal input terminal, and the switching transistors T of the Nth row pixel drive circuit are... pixel The first terminal is connected to the Nth level scan signal line, and each of the switching transistors T in the Nth row pixel driving circuit is... pixel The second end is respectively connected to different data signal lines Data, and each of the switching transistors T of the Nth row pixel driving circuit pixel The third terminal is connected to the pixel electrode in the corresponding pixel sub-region of each pixel circuit, where N is a positive integer. The switching transistor T pixel The first terminal can be the switching transistor T pixel The gate of the switching transistor T pixel The second terminal can be the switching transistor T pixel The source or drain of the switching transistor T pixel The third terminal can be the switching transistor T. pixel The source or drain of the switching transistor T pixel The second end is different from the other.

[0065] Please see Figures 6 to 8 When the display panel 10 is in the forward scanning phase, the positive pull-down transistor T 正 The second terminal is connected to the constant low-level signal VGL output from the constant low-level signal output terminal corresponding to the positive pull-down control subunit 103. When the Nth stage positive pull-down transistor T 正When the (N+1)th level scan drive signal GateN+1 connected to the first terminal is a high-level signal, the Nth level scan drive signal Gate N is a low-level signal. Based on this, the Nth level positive pull-down transistor T... 正 Turn on, the constant voltage low-level signal VGL is pulled down from the Nth stage transistor T 正 The second terminal input is drawn from the Nth stage positive pull-down transistor T. 正 The third terminal outputs to the scan drive signal input terminal of the Nth-level pixel circuit, thereby pulling down the potential of the scan drive signal input terminal of the Nth-level pixel circuit, that is, pulling down the switching transistor T of the Nth-level pixel circuit. pixel The potential at the first end of the device easily and effectively improves the resistance and capacitance delay problem at the input terminal of the scanning drive signal of the pixel circuit in each display sub-area within the display area AA. While reducing the abnormal display of the screen of the display panel 10, it is beneficial to compress the output time interval of the timing signal, thereby improving the charging time of the pixel circuit, further improving the display quality of the display panel 10, and realizing a higher frequency of screen display.

[0066] Please see Figures 6 to 8 Similarly, when the display panel 10 is in the reverse scanning phase, the reverse pull-down transistor T 反 The second terminal is connected to the constant low-level signal VGL output from the constant low-level signal VGL output terminal corresponding to the reverse pull-down control subunit 104. When the Nth stage reverse pull-down transistor T 反 When the (N-1)th level scan drive signal Gate N-1 connected to the first terminal is a high-level signal, the Nth level scan drive signal Gate N is a low-level signal. Based on this, the Nth level reverse pull-down transistor T... 反 Turn on, the constant voltage low-level signal VGL is pulled down from the Nth stage reverse transistor T 反 The second terminal is input and pulled down from the Nth stage inversely by the transistor T. 反 The third terminal outputs to the scan drive signal input terminal of the Nth-level pixel circuit, thereby further pulling down the potential of the scan drive signal input terminal of the Nth-level pixel circuit, that is, pulling down the switching transistor T of the Nth-level pixel circuit. pixel The potential at the first end of the device easily and effectively improves the resistance and capacitance delay problem at the input terminal of the scanning drive signal of the pixel circuit in each display sub-area within the display area AA. While reducing the abnormal display of the screen of the display panel 10, it is beneficial to compress the output time interval of the timing signal, thereby improving the charging time of the pixel circuit, further improving the display quality of the display panel 10, and realizing a higher frequency of screen display.

[0067] In some embodiments, in each display panel 10, the positive pull-down unit 105 and the negative pull-down unit 106 can be one or more. When there are multiple positive pull-down units 105 and multiple negative pull-down units 106, the scan drive signal input terminal of each pixel circuit is connected to multiple positive pull-down sub-units and multiple negative pull-down sub-units. This is beneficial to improving the pull-down efficiency and effect of the potential at the scan drive signal input terminal of the pixel circuit of the positive pull-down unit 105 during the forward scanning phase of the display panel 10, and the pull-down efficiency and effect of the potential at the scan drive signal input terminal of the pixel circuit of the negative pull-down unit 106 during the reverse scanning phase of the display panel 10, further reducing display abnormalities of the display panel 10 and improving the display quality of the display panel 10.

[0068] In some embodiments, the display panel 10 further includes at least one first-type virtual trace parallel to the scan signal line Scan. The first-type virtual trace is connected to the GOA circuit. When the display panel 10 is in the forward scanning phase, the GOA circuit provides the last stage of the cascaded scan drive signal to the first-type virtual trace, and the last stage of the positive pull-down sub-unit's positive pull-down transistor T... 正 The first end is connected to the first type of virtual trace, thereby completing the switching transistor T of the last stage positive pull-down sub-unit to the last stage pixel circuit. pixel The first end is pulled down; the GOA circuit provides the last stage of the cascaded scan drive signal to the first type of virtual trace, and the last stage of the reverse pull-down sub-unit's reverse pull-down transistor T 反 The first end is connected to the first type of virtual trace, thereby completing the switching transistor T of the last stage pixel circuit through the last stage reverse pull-down sub-unit. pixel The first dropdown.

[0069] In some embodiments, the Nth stage positive pull-down transistor T 正 The first terminal is connected to the (N+1)th level scan signal line to receive the (N+1)th level scan drive signal, and the Nth level positive pull-down transistor T 正 The third terminal is connected to the Nth level scan signal line, and thus connected to the Nth level pixel circuit through the Nth level scan signal line; the Nth level positive pull-down transistor T 正 The first terminal is connected to the (N-1)th level scan signal line to receive the (N-1)th level scan drive signal, and the Nth level positive pull-down transistor T 正 The third terminal is connected to the Nth level scan signal line, and thus connected to the Nth level pixel circuit through the Nth level scan signal line.

[0070] When the display panel 10 includes multiple positive pull-down units 105 and multiple negative pull-down units 106, the display panel 10 includes multiple positive pull-down control lines 107 and multiple negative pull-down control lines 108, and the positive pull-down transistor T in each of the positive pull-down units 105... 正 The second end is connected to the same positive pull-down control trace 107, and the reverse pull-down transistor T in each of the reverse pull-down units 106 反 The second end is connected to the same reverse pull-down control line 108.

[0071] The third terminal of the first transistor T1 is connected to the positive pull-down control line 107, and the third terminal of the second transistor T2 is connected to the negative pull-down control line 108.

[0072] In some embodiments, the positive pull-down control trace 107 includes a first positive pull-down control trace segment located in the display area AA and a second positive pull-down control trace segment located in the non-display area NA, and the negative pull-down control trace 108 includes a first negative pull-down control trace segment located in the display area AA and a second negative pull-down control trace segment located in the non-display area NA.

[0073] The first end of the second positive pull-down control trace is connected to the third end of the first transistor T1 in a one-to-one correspondence, and the second end of the second positive pull-down control trace is connected to the first positive pull-down control trace.

[0074] The first end of the second reverse pull-down control trace is connected to the third end of the second transistor T2 in a one-to-one correspondence, and the second end of the second reverse pull-down control trace is connected to the first reverse pull-down control trace.

[0075] In some embodiments, the second end of the second positive pull-down control trace segment is connected to the first end of the first positive pull-down control trace segment in a one-to-one correspondence, and the second end of the second negative pull-down control trace segment is connected to the first end of the first negative pull-down control trace segment in a one-to-one correspondence.

[0076] In some embodiments, the second end of the second positive pull-down control trace is connected to the first end of a plurality of first positive pull-down control traces, and the second end of the second negative pull-down control trace is connected to the first end of a plurality of first negative pull-down control traces.

[0077] Each of the first positive pull-down control trace segments includes multiple second terminals, and each second terminal of the first positive pull-down control trace segment is correspondingly connected to the positive pull-down transistor T of a positive pull-down sub-unit. 正 The second end.

[0078] Each of the first reverse pull-down control trace segments includes multiple second terminals, and each second terminal of the first reverse pull-down control trace segment is correspondingly connected to the reverse pull-down transistor T of one of the reverse pull-down sub-units. 反 The second end.

[0079] In some embodiments, the extension direction of the first positive pull-down control trace is parallel to the extension direction of the data signal line Data, and the extension direction of the first reverse pull-down control trace is parallel to the extension direction of the data signal line Data. The positive pull-down sub-units in each positive pull-down unit 105 are arranged sequentially along the extension direction of the data signal line Data, and the reverse pull-down sub-units in each reverse pull-down unit 106 are arranged sequentially along the extension direction of the data signal line Data. This avoids the loss of aperture ratio of the display panel 10 caused by lateral cross-line, which is beneficial to improving the light emission efficiency of the display panel 10 and improving the display quality of the display panel 10.

[0080] When the second end of the second positive pull-down control trace is connected to the first end of the first positive pull-down control trace, and the second end of the second negative pull-down control trace is connected to the first end of the first negative pull-down control trace, the extension direction of the positive pull-down control trace 107 is parallel to the extension direction of the data signal line Data, and the extension direction of the negative pull-down control trace 108 is parallel to the extension direction of the data signal line Data. This helps to simplify the circuit design of the display panel 10 and reduce the manufacturing cost of the display panel 10.

[0081] In some embodiments, the positive pull-down control trace 107 and the negative pull-down control trace 108 are arranged alternately along the arrangement direction of the data signal line Data.

[0082] In some embodiments, the number of the first positive pull-down control traces is the same as the number of the first negative pull-down control traces, and the number of the positive pull-down units 105 is the same as the number of the negative pull-down units 106. This is beneficial to the consistency of the display effect of the display panel 10 in the forward scanning stage and the reverse scanning stage, and improves the display quality of the display panel 10.

[0083] In some embodiments, the display panel 10 includes a second type of virtual trace, the extension direction of which is parallel to the extension direction of the data signal line Data. The positive pull-down control trace 107 is collinear with a portion of the second type of virtual trace, and the negative pull-down control trace 108 is collinear with a portion of the second type of virtual trace. That is, the original portion of the second type of virtual trace of the display panel 10 is used as the positive pull-down control trace 107 and the negative pull-down control trace 108, eliminating the need for additional traces in the display area AA as the positive pull-down control trace 107 or the negative pull-down control trace 108. This helps reduce the wiring in the display area AA of the display panel 10 and improves the light emission efficiency of the display panel 10.

[0084] In some embodiments, the positive pull-down control trace 107 can be disposed on the same layer or on a different layer, and the positive pull-down control trace 107 can be connected to the switching transistor T of the pixel circuit. pixel The source or drain of the transistor is disposed on the same layer; or, the display panel 10 further includes a touch layer, the touch layer including at least one touch metal layer, and the positive pull-down control trace 107 is disposed on the same layer as the touch metal layer. Similarly, the negative pull-down control trace 108 can be connected to the switching transistor T of the pixel circuit. pixel The source or drain is disposed on the same layer; or, the reverse pull-down control trace 108 is disposed on the same layer as the touch metal layer.

[0085] In this embodiment of the invention, the pull-down unit 102 of the pull-down circuit 100 is set within the display area AA. The pull-down control unit 101 outputs a constant voltage low-level signal VGL to the pull-down unit 102 according to the forward scan signal U2D or the reverse scan signal D2U. The pull-down unit 102 pulls down the potential of the scan drive signal input terminal of the current pixel circuit according to the previous level scan drive signal or the next level scan drive signal. This effectively improves the resistance and capacitance delay problem of the scan drive signal input terminal of the current pixel circuit, reduces display abnormalities of the display panel 10, and improves the display quality of the display panel 10.

[0086] This invention discloses a display panel including a pull-down circuit with a pull-down control unit and a pull-down unit. The pull-down control unit is connected to a forward scan signal, a reverse scan signal, and a constant voltage low-level signal, and is used to output the constant voltage low-level signal to the pull-down unit according to the forward scan signal or the reverse scan signal. The pull-down unit is located in the display area and includes multiple cascaded pull-down sub-units. Each pull-down sub-unit is connected to the next-level scan drive signal, the previous-level scan drive signal, and the constant voltage low-level signal, and is used to pull down the potential of the scan drive signal input terminal of the pixel circuit of this level according to the previous-level scan drive signal or the next-level scan drive signal. By setting up the pull-down circuit, this invention effectively improves the resistance-capacitance delay problem of the scan drive signal input terminal of the pixel circuit of this level, reduces display abnormalities of the display panel, and improves the display quality of the display panel.

[0087] The above provides a detailed description of a display panel provided by an embodiment of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, The display panel has a display area and a non-display area surrounding the display area, and includes: The pull-down circuit includes a pull-down control unit and a pull-down unit; The pull-down control unit is located in the non-display area and is connected to a forward scan signal, a reverse scan signal, and a constant voltage low-level signal. It is used to output the constant voltage low-level signal to the pull-down unit according to the forward scan signal or the reverse scan signal. The pull-down unit is located within the display area and includes multiple cascaded pull-down sub-units. Each pull-down sub-unit is connected to the next-level scan drive signal, the previous-level scan drive signal, and the constant voltage low-level signal, and is used to pull down the potential of the scan drive signal input terminal of the pixel circuit of this level according to the previous-level scan drive signal or the next-level scan drive signal. The pull-down control unit includes a positive pull-down control sub-unit and a negative pull-down control sub-unit, and the pull-down unit includes a positive pull-down unit and a negative pull-down unit. Each of the positive pull-down control subunits outputs the constant voltage low-level signal to a corresponding positive pull-down unit according to the positive scanning signal. Each of the aforementioned reverse pull-down control subunits outputs the constant voltage low-level signal to a corresponding reverse pull-down unit according to the reverse scan signal; The positive pull-down control subunit includes a first transistor, the first terminal of the first transistor is connected to the positive scanning signal, the second terminal of the first transistor is connected to the constant voltage low level signal, and the third terminal of the first transistor is connected to the constant voltage low level signal input terminal of the pull-down unit. The reverse pull-down control subunit includes a second transistor, the first terminal of which is connected to the reverse scan signal, the second terminal of which is connected to the constant voltage low-level signal, and the third terminal of which is connected to the constant voltage low-level signal input terminal of the pull-down unit. The positive pull-down unit includes multiple cascaded positive pull-down sub-units. Each positive pull-down sub-unit includes a positive pull-down transistor. The first terminal of the positive pull-down transistor is connected to the next-level scan drive signal. The second terminal of the positive pull-down transistor is connected to the constant voltage low-level signal output terminal corresponding to the positive pull-down control sub-unit. The third terminal of the positive pull-down transistor is connected to the scan drive signal input terminal of the pixel circuit at this level. The reverse pull-down unit includes multiple cascaded reverse pull-down sub-units. Each reverse pull-down sub-unit includes a reverse pull-down transistor. The first terminal of the reverse pull-down transistor is connected to the previous stage scan drive signal. The second terminal of the reverse pull-down transistor is connected to the constant voltage low-level signal output terminal corresponding to the reverse pull-down control sub-unit. The third terminal of the reverse pull-down transistor is connected to the scan drive signal input terminal of the pixel circuit at this stage.

2. The display panel according to claim 1, characterized in that, The pull-down control unit includes a positive pull-down control subunit and a negative pull-down control subunit, and the pull-down unit includes a positive pull-down unit and a negative pull-down unit; Each of the positive pull-down control subunits outputs the constant voltage low-level signal to multiple corresponding positive pull-down units according to the positive scanning signal; Each of the aforementioned reverse pull-down control subunits outputs the constant voltage low-level signal to multiple corresponding reverse pull-down units according to the reverse scan signal.

3. The display panel according to claim 1, characterized in that, The display panel includes multiple positive pull-down control lines and multiple negative pull-down control lines. The third terminal of the first transistor is connected to the positive pull-down control line, and the third terminal of the second transistor is connected to the negative pull-down control line. The second terminal of the positive pull-down transistor in each of the positive pull-down units is connected to the same positive pull-down control line, and the second terminal of the reverse pull-down transistor in each of the reverse pull-down units is connected to the same reverse pull-down control line.

4. The display panel according to claim 3, characterized in that, The positive pull-down control trace includes a first positive pull-down control trace segment located in the display area and a second positive pull-down control trace segment located in the non-display area; the negative pull-down control trace includes a first negative pull-down control trace segment located in the display area and a second negative pull-down control trace segment located in the non-display area. The first end of the second positive pull-down control trace is connected to the third end of the first transistor in a one-to-one correspondence, and the second end of the second positive pull-down control trace is connected to the first positive pull-down control trace. The first end of the second reverse pull-down control trace is connected to the third end of the second transistor in a one-to-one correspondence, and the second end of the second reverse pull-down control trace is connected to the first reverse pull-down control trace.

5. The display panel according to claim 4, characterized in that, The second end of the second positive pull-down control trace is connected to the first end of the first positive pull-down control trace in a one-to-one correspondence, and the second end of the second negative pull-down control trace is connected to the first end of the first negative pull-down control trace in a one-to-one correspondence.

6. The display panel according to claim 4, characterized in that, The second end of the second positive pull-down control routing segment is connected to the first end of multiple first positive pull-down control routing segments, and the second end of the second reverse pull-down control routing segment is connected to the first end of multiple first reverse pull-down control routing segments.

7. The display panel according to claim 3, characterized in that, The display panel also includes: The scan signal lines are arranged continuously along the row direction; The data signal lines are arranged continuously along the column direction and are interleaved with the scan signal lines; Wherein, the extension direction of the positive pull-down control trace is parallel to the extension direction of the data signal line, and the extension direction of the reverse pull-down control trace is parallel to the extension direction of the data signal line.

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