A phase-locked loop output frequency calibration circuit

Abstract

This application discloses a phase-locked loop (PLL) output frequency calibration circuit. A reference clock is input into a fractional-division PLL and used as its reference clock. Simultaneously, this clock is also input to a voltage-controlled pulse (VCP) generator. Under the influence of a control voltage, the VCP generator produces digital pulses with the number of logic high levels proportional to the control voltage, which are then fed into a ΣΔ modulator. The ΣΔ modulator processes the configuration value from the fractional register and, together with the configuration value from the integer register, sends it to the frequency divider controller to generate the required division ratio for the PLL, thus outputting a clock. This clock is adjusted according to changes in the external control voltage. Using this technical solution, the frequency of the reference clock does not need to be changed. The relationship between the number of logic high levels in the digital pulses generated by the VCP generator and the number of logic high levels in the digital pulses of the ΣΔ modulator determines whether to change the output of the ΣΔ modulator, thereby achieving calibration of the PLL output frequency.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a phase-locked loop output frequency calibration circuit. Background Technology

[0002] In traditional fractional-order frequency-locked loops (PLLs), the division ratio determines the final output frequency of the PLL under a fixed reference clock. If the reference clock experiences a frequency shift, the output clock will also change. However, many practical applications require the PLL's output clock to remain stable within a certain frequency range, not exceeding the required operating frequency range as operating temperature and time increase. To achieve this, current technologies typically use high-stability quartz crystals instead of inexpensive crystal oscillators, along with a crystal oscillator to generate the reference clock; alternatively, voltage-controlled crystal oscillators are used, where an external voltage is applied to change the internal variable capacitor, thereby altering the resonant frequency and achieving frequency pulling.

[0003] However, in practice, the output frequency of a crystal oscillator is related not only to the resonant frequency of the quartz crystal, but also to the parasitic capacitance inside the oscillator. The parasitic capacitance changes with temperature, so using a high-stability quartz crystal oscillator in conjunction with an internal crystal oscillator circuit cannot guarantee that the obtained reference clock will not change with temperature and operating time. Moreover, high-stability quartz crystals are expensive.

[0004] Therefore, how to calibrate the output frequency of the phase-locked loop without changing the reference clock frequency is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a phase-locked loop (PLL) output frequency calibration circuit to calibrate the PLL output frequency without changing the reference clock frequency.

[0006] To solve the above-mentioned technical problems, this application provides a phase-locked loop output frequency calibration circuit, including: a ΣΔ modulator, a fractional register, a frequency divider controller, and an integer register, characterized in that it further includes: a voltage-controlled pulse generator;

[0007] The voltage-controlled pulse generator is connected to a reference clock and a control voltage, and generates digital pulses based on the reference clock and the control voltage;

[0008] The voltage-controlled pulse generator is connected to the ΣΔ modulator of the phase-locked loop to maintain the output of the ΣΔ modulator unchanged when the number of logic high levels in the digital pulse is equal to the number of logic high levels in the preset pulse of the ΣΔ modulator; when the number of logic high levels in the digital pulse is greater than the number of logic high levels in the preset pulse of the ΣΔ modulator, the digital pulse is added to the preset pulse of the ΣΔ modulator as the output of the ΣΔ modulator; when the number of logic high levels in the digital pulse is less than the number of logic high levels in the preset pulse of the ΣΔ modulator, the digital pulse is subtracted from the preset pulse of the ΣΔ modulator as the output of the ΣΔ modulator.

[0009] Preferably, the voltage-controlled pulse generator includes:

[0010] Amplification module, buffer module, push-pull module, comparison module, clock generation module;

[0011] The amplification module is used to receive the control voltage, and after amplifying the control voltage, it is processed by the buffer module and the push-pull module and then transmitted to the comparison module for comparison. The output of the comparison module is connected to the clock generation module to generate a corresponding clock according to the comparison result of the comparison module.

[0012] Preferably, the amplification module includes:

[0013] First switching transistor, second switching transistor, first current source, first operational amplifier, first resistor, second resistor, and third resistor;

[0014] The control terminal of the first switching transistor is connected to the control voltage, the first terminal of the first switching transistor is connected to the power supply, the first terminal of the second resistor is connected to the second terminal of the first switching transistor, the second terminal of the second resistor and the first terminal of the third resistor are connected to the non-inverting input terminal of the first operational amplifier, the second terminal of the third resistor is grounded, the inverting input terminal of the first operational amplifier is connected to the first terminal of the first resistor and the first terminal of the second switching transistor, the second terminal of the first resistor is grounded, the output terminal of the first operational amplifier is connected to the control terminal of the second switching transistor, the second terminal of the second switching transistor is connected to the output terminal of the first current source, the buffer module, and the push-pull module, and the input terminal of the first current source is connected to the power supply.

[0015] Preferably, the buffer module and the push-pull module include:

[0016] Second current source, first switch, second switch, third switch, fourth switch, second operational amplifier, third operational amplifier, first capacitor;

[0017] The second terminal of the second switch is connected to the first terminal of the first switch, the inverting input terminal of the third operational amplifier, and the first terminal of the first capacitor. The second terminal of the first switch and the first terminal of the second switch are connected to the output terminal of the first current source. The input terminal of the first current source is connected to a power supply. The non-inverting input terminals of the second operational amplifier and the third operational amplifier are connected to a first comparison voltage. The inverting input terminal and the output terminal of the second operational amplifier are connected to the second terminal of the second switch and the first terminal of the third switch. The second terminal of the third switch and the first terminal of the fourth switch are connected to the input terminal of the second current source. The input terminal of the second current source is grounded. The second terminal of the first capacitor, the output terminal of the third operational amplifier, and the second terminal of the fourth switch are connected to the comparison module.

[0018] Preferably, the comparison module includes:

[0019] Fourth operational amplifier, latch comparator;

[0020] The inverting input terminal of the fourth operational amplifier and the non-inverting input terminal of the fourth operational amplifier are connected to the second comparison voltage. The non-inverting output terminal of the fourth operational amplifier is connected to the inverting input terminal of the latch comparator. The inverting output terminal of the fourth operational amplifier is connected to the non-inverting input terminal of the latch comparator. The non-inverting and inverting output terminals of the latch comparator are connected to the clock generation module.

[0021] Preferably, the clock generation module includes: a first AND gate, a second AND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a divide-by-two chip, and a delay unit;

[0022] The positive output of the latch comparator is connected to the input of the first inverter, the output of the first inverter is connected to the control terminal of the second inverter, the inverting output of the latch comparator is connected to the input of the third inverter, the output of the third inverter is connected to the input of the fourth inverter and the control terminal of the fifth inverter, the output of the fourth inverter is connected to the input of the sixth inverter, the output of the sixth inverter is connected to the ΣΔ modulator, the input of the seventh inverter, the first input of the first AND gate, and the clock terminal of the divide-by-two chip are all connected to the reference clock, and the second input of the first AND gate is connected to the reference clock. The output of the second inverter is connected to serve as the control terminal of the first switch and the fourth switch. The output of the first AND gate is connected to the input of the fifth inverter. The output of the fifth inverter and the first input of the second AND gate are connected to serve as the control terminal of the second switch and the third switch. The output of the seventh inverter is connected to the second input of the second AND gate. The output of the second AND gate is connected to the input of the second inverter. The output of the divide-by-two chip is connected to the input of the delay unit. The output of the delay unit is connected to the control terminal of the latch comparator. The D input of the divide-by-two chip is connected to the QN terminal.

[0023] Preferably, the second current source includes a third switch and a fourth switch;

[0024] The control terminals of the third and fourth switches are connected to a power supply. The first terminal of the third switch serves as the input terminal of the second current source and is connected to the second terminal of the third switch and the first terminal of the fourth switch. The second terminal of the third switch is connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is grounded.

[0025] Preferably, it also includes: a bias circuit;

[0026] The input terminal of the bias circuit is connected to the power supply. The first output terminal of the bias circuit is connected to the non-inverting input terminal of the first operational amplifier. The second output terminal is connected to the non-inverting input terminal of the fourth operational amplifier. The third output terminal is connected to the control terminal of the third switching transistor. The fourth output terminal is connected to the control terminal of the fourth switching transistor.

[0027] Preferably, it also includes: an LDO circuit;

[0028] The input terminal of the LDO circuit is connected to the fifth output terminal of the bias circuit, and the output terminal of the LDO circuit is connected to the input terminal of the first current source.

[0029] Preferably, it also includes: a signal processing module, a digital-to-analog converter module, and a low-pass filter;

[0030] The input terminal of the signal processing module is connected to the output of the phase-locked loop, the output terminal of the signal processing module is connected to the input terminal of the digital-to-analog converter module, the output terminal of the digital-to-analog converter module is connected to the input terminal of the low-pass filter, and the output terminal of the low-pass filter is connected to the control terminal of the first switching transistor as the control voltage.

[0031] The phase-locked loop (PLL) output frequency calibration circuit provided in this application uses a reference clock fed into a fractional-division PLL as its reference clock. This clock is also input to a voltage-controlled pulse (VCP) generator. Under the influence of a control voltage, the VCP generator produces digital pulses with a number of logic high levels proportional to the control voltage, which are then fed into a ΣΔ modulator. The ΣΔ modulator processes the configuration value from the fractional register and, together with the configuration value from the integer register, sends it to the frequency divider controller to generate the required division ratio for the PLL, resulting in the PLL output clock. This clock is adjusted according to changes in the external control voltage. Using this technical solution, the frequency of the reference clock does not need to be changed. The relationship between the number of logic high levels in the digital pulses generated by the VCP generator and the number of logic high levels in the digital pulses of the ΣΔ modulator determines whether to change the output of the ΣΔ modulator, thereby achieving calibration of the PLL output frequency. Attached Figure Description

[0032] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A structural diagram of a phase-locked loop output frequency calibration circuit provided in an embodiment of this application;

[0034] Figure 2 A circuit diagram of a voltage-controlled pulse generator provided in an embodiment of this application;

[0035] Figure 3 This is a timing diagram provided for an embodiment of this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0037] A phase-locked loop (PLL), as the name suggests, is a loop that locks the phase of the input signal. A PLL is a control system that generates an output signal whose phase is the same as the input signal. It uses an externally input reference signal to control the frequency and phase of the internal oscillation signal, achieving automatic tracking of the input signal frequency with the output signal frequency. It is generally used in closed-loop tracking circuits. There are several different types of PLLs, typically composed of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector identifies the phase difference between the input signal Ui and the output signal Uo, and outputs an error voltage Ud. Noise and interference components in Ud are filtered out by a low-pass loop filter, forming the control voltage Uc of the VCO. Uc acts on the VCO, pulling its output oscillation frequency fo towards the loop input signal frequency fi. When the two are equal, the loop is locked, a process called lock-in. The DC control voltage maintaining the lock is provided by the phase detector; therefore, a certain phase difference exists between the two input signals of the phase detector. An oscillator generates a periodic signal, and a phase detector compares the phase of this signal with the phase of the input periodic signal, adjusting the oscillator to maintain phase matching. Keeping the input and output phases locked also means keeping the input and output frequencies the same. Therefore, in addition to a synchronization signal, a phase-locked loop can track the input frequency or generate frequencies that are multiples of the input frequency. These properties are used for computer clock synchronization, demodulation, and frequency synthesis.

[0038] A phase-locked loop (PLL) is a circuit or module used in communication receivers to process received signals and extract the phase information of a specific clock signal. In other words, it simulates a clock signal for the received signal, making the two signals synchronized (or coherent) from a certain perspective. Because the simulated clock signal has a certain phase difference relative to the clock signal in the received signal when locked (i.e., after acquisition), it is aptly named a phase-locked loop.

[0039] Phase-locked loops (PLLs) are widely used in radio, telecommunications, computer, and other electronic applications. They can be used to demodulate signals, recover signals from noisy communication channels, generate stable frequencies at multiples of the input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Because a single integrated circuit can provide the complete PLL building block, this technology is widely used in modern electronic devices with output frequencies ranging from fractions of a hertz to several megahertz.

[0040] Almost all electronic products require a clock to function properly, and a phase-locked loop (PLL) is the core component for generating that clock. Any PLL requires a reference clock to operate, and the generation of this reference clock can take many forms. One low-cost and relatively high-frequency-accuracy method utilizes the resonant frequency of a quartz crystal as the source, then uses an internal oscillation circuit to amplify the extremely small amplitude resonant signal generated by the quartz crystal to an amplitude that can be recognized by subsequent circuits. However, the resonant frequency of a quartz crystal changes with usage time and temperature variations, which is insufficient for applications requiring a stable clock over a long period.

[0041] In traditional fractional-order frequency-locked loops (PLLs), the division ratio determines the final output frequency of the PLL under a fixed reference clock. If the reference clock experiences a frequency shift, the output clock will also change. However, many practical applications require the PLL's output clock to remain stable within a certain frequency range, not exceeding the required operating frequency range as operating temperature and time increase. To achieve this, current technologies typically use high-stability quartz crystals instead of inexpensive crystal oscillators, along with a crystal oscillator to generate the reference clock; alternatively, voltage-controlled crystal oscillators are used, where an external voltage is applied to change the internal variable capacitor, thereby altering the resonant frequency and achieving frequency pulling.

[0042] However, in practice, the output frequency of a crystal oscillator is related not only to the resonant frequency of the quartz crystal, but also to the parasitic capacitance inside the oscillator. The parasitic capacitance changes with temperature, so using a high-stability quartz crystal oscillator in conjunction with an internal crystal oscillator circuit cannot guarantee that the obtained reference clock will not change with temperature and operating time. Moreover, high-stability quartz crystals are expensive.

[0043] Therefore, how to calibrate the output frequency of the phase-locked loop without changing the reference clock frequency is a problem that urgently needs to be solved by those skilled in the art.

[0044] The core of this application is to provide a phase-locked loop (PLL) output frequency calibration circuit to calibrate the PLL output frequency without changing the reference clock frequency.

[0045] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Figure 1 A structural diagram of a phase-locked loop output frequency calibration circuit provided in an embodiment of this application is shown below. Figure 1 As shown, the circuit includes: a ΣΔ modulator, a fractional register, a frequency divider controller, and an integer register. Its distinguishing feature is that it further includes: a voltage-controlled pulse generator.

[0047] The voltage-controlled pulse generator is connected to a reference clock and a control voltage, and generates digital pulses based on the reference clock and the control voltage;

[0048] The voltage-controlled pulse generator is connected to the ΣΔ modulator of the phase-locked loop. When the number of logic high levels in the digital pulse is equal to the number of logic high levels in the preset pulse in the ΣΔ modulator, the output of the ΣΔ modulator remains unchanged. When the number of logic high levels in the digital pulse is greater than the number of logic high levels in the preset pulse in the ΣΔ modulator, the digital pulse is added to the preset pulse in the ΣΔ modulator as the output of the ΣΔ modulator. When the number of logic high levels in the digital pulse is less than the number of logic high levels in the preset pulse in the ΣΔ modulator, the digital pulse is subtracted from the preset pulse in the ΣΔ modulator as the output of the ΣΔ modulator.

[0049] In this embodiment, the ΣΔ modulator is a nonlinear system, which in practice typically consists of a filter, a one-bit quantizer with a feedback loop, and a subtractor.

[0050] The application of ΣΔ modulation in digital signal processing and communication systems is attracting increasing attention because it primarily employs digital technology and does not require high precision from the analog input. ΣΔ modulation typically modulates an analog signal to generate a single-bit digital signal. However, in many cases, the input signal itself is digital, making it essential to study ΣΔ modulation implementations for digital signals.

[0051] A voltage-controlled pulse generator (VCP) is used to generate trigger pulses, which can be current or voltage trigger pulses. For example, some power electronic devices (thyristors) require trigger pulses to conduct. In this embodiment, the bit width of each bit in the digital pulse generated by the VCP generator is equal to twice the reference clock period, thereby determining the number of logic high or low levels within a certain period. Furthermore, the number of logic high levels in the digital pulse generated by the VCP generator is proportional to the applied control voltage.

[0052] The phase-locked loop (PLL) output frequency calibration circuit provided in this application uses a reference clock fed into a fractional-division PLL as its reference clock. This clock is also input to a voltage-controlled pulse (VCP) generator. Under the influence of a control voltage, the VCP generator produces digital pulses with a number of logic high levels proportional to the control voltage, which are then fed into a ΣΔ modulator. The ΣΔ modulator processes the configuration value from the fractional register and, together with the configuration value from the integer register, sends it to the frequency divider controller to generate the required division ratio for the PLL, resulting in the PLL output clock. This clock is adjusted according to changes in the external control voltage. Using this technical solution, the frequency of the reference clock does not need to be changed. The relationship between the number of logic high levels in the digital pulses generated by the VCP generator and the number of logic high levels in the digital pulses of the ΣΔ modulator determines whether to change the output of the ΣΔ modulator, thereby achieving calibration of the PLL output frequency.

[0053] Based on the above embodiments, this embodiment also provides a specific voltage-controlled pulse generator. Figure 2 A circuit diagram of a voltage-controlled pulse generator provided in this application embodiment is shown below. Figure 2 As shown, the circuit includes:

[0054] First switch NM1, second switch NM2, first current source, second current source, first switch S11, second switch S21, third switch S22, fourth switch S12, first operational amplifier AMP1, second operational amplifier AMP2, third operational amplifier AMP3, fourth operational amplifier AMP4, first AND gate AND1, second AND gate AND2, first inverter N1, second inverter N2, third inverter N3, fourth inverter N4, fifth inverter N5, sixth inverter N6, seventh inverter N7, frequency divider chip, first resistor R1, first capacitor C1, latch comparator CMP;

[0055] The control terminal of the first switching transistor NM1 is connected to a control voltage. The first terminal of the first switching transistor NM1 is connected to a power supply. The second terminal of the first switching transistor NM1 is connected to the non-inverting input of the first operational amplifier AMP1. The inverting input of the first operational amplifier AMP1 is connected to the first terminal of the first resistor R1 and the first terminal of the second switching transistor NM2. The second terminal of the first resistor R1 is grounded. The output terminal of the first operational amplifier AMP1 is connected to the control terminal of the second switching transistor NM2. The second terminal of the second switching transistor NM2 is connected to the first terminal of the first switch S11, the inverting input of the third operational amplifier AMP3, and the first terminal of the first capacitor C1. The second terminal of the first switch S11 and the first terminal of the second switch S21 are both connected to the output of the first current source. The input terminal of the first current source is connected to the power supply. The non-inverting input terminals of the second operational amplifier AMP2 and the third operational amplifier AMP3 are connected to the first comparison voltage. The inverting input terminal and output terminal of the second operational amplifier AMP2 are connected to the second terminal of the second switch S21 and the first terminal of the third switch S22. The second terminal of the third switch S22 and the first terminal of the fourth switch S12 are connected to the input terminal of the second current source, which is grounded. The second terminal of the first capacitor C1, the output terminal of the third operational amplifier AMP3, and the second terminal of the fourth switch S12 are connected to the inverting input terminal of the fourth operational amplifier AMP4. The non-inverting input terminal of the fourth operational amplifier AMP4 is connected to the second comparison voltage. The positive output of the first inverter is connected to the inverting input of the latch comparator CMP. The inverting output of the fourth operational amplifier AMP4 is connected to the non-inverting input of the latch comparator CMP. The positive output of the latch comparator CMP is connected to the input of the first inverter N1. The output of the first inverter N1 is connected to the control terminal of the second inverter N2. The inverting output of the latch comparator CMP is connected to the input of the third inverter N3. The output of the third inverter N3 is connected to the input of the fourth inverter N4 and the control terminal of the fifth inverter N5. The output of the fourth inverter N4 is connected to the input of the sixth inverter N6. The output of the sixth inverter N6 is connected to the ΣΔ modulator. The input of the seventh inverter N7 is connected to the first input of the first AND gate AND1. The clock input of the divider chip and the clock input of the divider chip are connected to the reference clock. The second input of the first AND gate AND1 is connected to the output of the second inverter N2 and together they serve as the control terminals of the first switch S11 and the fourth switch S12. The output of the first AND gate AND1 is connected to the input of the fifth inverter N5. The output of the fifth inverter N5 is connected to the first input of the second AND gate AND2 and together they serve as the control terminals of the second switch S21 and the third switch S22. The output of the seventh inverter N7 is connected to the second input of the second AND gate AND2. The output of the second AND gate AND2 is connected to the input of the second inverter N2. The output of the divider chip is connected to the control terminal of the latch comparator CMP. The D input of the divider chip is connected to the QN terminal.

[0056] The switching transistor can be either a bipolar junction transistor (BJT) or a MOSFET. A BJT is a current-controlled device, controlling the output current by controlling the base current; therefore, there is always a certain current at the base, resulting in a relatively low input resistance. A MOSFET, on the other hand, is a voltage-controlled device; its output current depends on the voltage between the gate and source, and the gate draws virtually no current. Therefore, a MOSFET has a very high input resistance.

[0057] In a transistor, both majority and minority carriers participate in conduction, while in a MOSFET, only majority carriers participate in conduction. Since the concentration of minority carriers is greatly affected by factors such as temperature and radiation, MOSFETs have better temperature stability, stronger radiation resistance, and lower noise figure than transistors.

[0058] MOSFETs have advantages such as high input resistance, low noise, low power consumption, no secondary breakdown, wide safe operating area, and minimal susceptibility to temperature and radiation. Therefore, the switching transistors in this embodiment are all MOSFETs.

[0059] It should be noted that in specific implementations, to prevent excessive power supply voltage from damaging the components in the circuit, voltage divider resistors can be added to protect the circuit. Therefore, this embodiment may also include a second resistor R2 and a third resistor R3. Figure 2The first current source I1 must be greater than I3, and I1 is slightly greater than I2. The external control voltage CV is input to the first switching transistor NM1, controlling the gate-source voltage of the first switching transistor NM1 to generate current. This current is divided by the second resistor R2 and the third resistor R3 and input to the non-inverting input of the first operational amplifier AMP1. VREF1 is the first comparison voltage of the non-inverting input of the second operational amplifier AMP2 and the third operational amplifier AMP3, and VREF2 is the second comparison voltage of the non-inverting input of the fourth operational amplifier AMP4. The first operational amplifier AMP1 is a high-gain, low-noise amplifier. Its feedback loop, formed with the second switch NM2 and the first resistor R1, determines the magnitude of the current I3 flowing into the second switch NM2. The second operational amplifier AMP2 constitutes a unity-gain buffer, used to absorb the portion of the current greater than I2 flowing out of I1 when the second switch S21 and the third switch S22 are closed (i.e., I1-I2). The third operational amplifier AMP3 is a high-gain, push-pull output amplifier; the voltage rise or fall at nodes A and B is achieved by the third operational amplifier AMP3 and the four switches working together. The fourth operational amplifier AMP4 operates in open-loop mode, used to amplify the voltage difference between point B and VREF2, making the fourth operational amplifier AMP4... The output can reach the threshold voltage of the latch comparator CMP, thereby causing the comparator's output state to flip. The latch comparator CMP is a dynamic latch comparator, latching when CLK_LATCH is high and comparing when it is low. The positive output of the latch comparator CMP generates DATAN through the first inverter N1, and the negative output generates DATAP through the third inverter N3. These two output signals control the switching control signals S1* and S2* generated by the non-overlapping clock generation circuit composed of the first AND gate AND1 and the second AND2, as well as the fifth inverter N5, the second inverter N2, and the seventh inverter N7. The clock control terminal CLK_LATCH of the latch comparator CMP is obtained by dividing the reference clock by two and then delaying it. The second current source is used to absorb part of the current of I1. In other embodiments, it may include a third switch NM3 and a fourth switch NM4. The control terminals of the third switch NM3 and the fourth switch NM4 are connected to the power supply. The first terminal of the third switch NM3 serves as the input terminal of the second current source and is connected to the second terminal of the third switch S22 and the first terminal of the fourth switch S12. The second terminal of the third switch NM3 is connected to the first terminal of the fourth switch NM4, and the second terminal of the fourth switch NM4 is grounded.

[0060] The tail current sink I2, composed of the third switch NM3 and the fourth switch NM4, is used to absorb part of the current in I1, thereby reducing the design complexity of the second operational amplifier AMP2 and the third operational amplifier AMP3. The final output pulse DATA is obtained by delaying DATAP through two stages of inverters. The existence of CLK_LATCH determines that the high or low level pulse width of DATA can only appear as an integer multiple of the CLK_LATCH period, which facilitates processing by subsequent digital circuits.

[0061] In a specific implementation, it may also include: an eighth inverter; the input terminal of the eighth inverter is connected to the output terminal of the first inverter. The output terminal of the eighth inverter is unconnected to balance the impedance in the circuit.

[0062] To suppress output pulse jumps caused by power supply disturbances, Figure 2 In addition to the markings, it also includes: bias circuit;

[0063] The input terminal of the bias circuit is connected to the power supply. The first output terminal of the bias circuit is connected to the non-inverting input terminal of the first operational amplifier AMP1. The second output terminal is connected to the non-inverting input terminal of the fourth operational amplifier AMP4. The third output terminal is connected to the control terminal of the third switching transistor NM3. The fourth output terminal is connected to the control terminal of the fourth switching transistor NM4.

[0064] Also includes: LDO circuits;

[0065] The input terminal of the LDO circuit is connected to the fifth output terminal of the bias circuit, and the output terminal of the LDO circuit is connected to the input terminal of the first current source.

[0066] Based on the above embodiments, this embodiment further includes: a signal processing module, a digital-to-analog conversion module, and a low-pass filter;

[0067] The input terminal of the signal processing module is connected to the output of the phase-locked loop, the output terminal of the signal processing module is connected to the input terminal of the digital-to-analog converter module, the output terminal of the digital-to-analog converter module is connected to the input terminal of the low-pass filter, and the output terminal of the low-pass filter is connected to the control terminal of the first switching transistor NM1 as the control voltage.

[0068] In this embodiment, the output clock or frequency division clock of the phase-locked loop is fed into the signal processor to detect the frequency deviation. This difference is sent to the digital-to-analog converter to be converted into an analog voltage signal, and then fed back to the voltage-controlled pulse generator through a low-pass filter to form the negative feedback of the phase-locked loop system.

[0069] Nodes A and B are the upper and lower plates of capacitor C1, respectively. When S11 and S12 are closed and S21 and S22 are open, the direction of Ix flow is as shown in the figure. Point A is charged with current Ix, and Ix = I1 - I3. When S11 and S12 are open and S21 and S22 are closed, Ix flows into NM1 in the opposite direction to that shown in the figure. At this time, the value of Ix is equal to I3.

[0070] Figure 3 A timing diagram provided for an embodiment of this application, such as Figure 3 As shown, DATAP and DATAN are a pair of inverted clocks, and S1* and S2* are a pair of inverted non-overlapping clocks. When DATAP is high, the output S2* is equal to the reference clock. When DATAP is low, S2* is forced to output low. S1* represents S11 and S12, and S2* represents S21 and S22. S11 equals S12, and S21 equals S22. CLK_LATCH is obtained by dividing the reference clock by two and then delaying it.

[0071] Assume that at a certain moment DATAP is high, and that the voltage at point B is higher than VREF2. When S1* is low, S1* is closed and S2* is open. At this time, point A is charged, and the voltage at point A rises. Because point A is connected to the inverting input of AMP3, the voltage at the output point B of AMP3 decreases. If the voltage at point B is still higher than VREF2 before S1* goes high, then the output of comparator CMP remains unchanged, and the output DATAP of inverter N2 remains high. When S1* goes high, S1* is open and S2* is closed. Point A discharges in the opposite direction to Ix, and the discharge current is equal to I3, which comes from the output of AMP3. The voltage at point A decreases, and the voltage at point B increases. At this time, the voltage at point B is still greater than VREF2. When S1* goes low again... When S1* is closed and S2* is open, point A is charged again with current I1-I3 along the direction of Ix shown in the diagram. The voltage at point A rises, and the voltage at point B falls. If the voltage at point B is still higher than VREF2, the process of point A discharging when S1* is low and charging when S1* is high is repeated until the voltage at point B drops below VREF2. At this time, the output of comparator CMP flips on the falling edge of CLK_LATCH, and DATAP outputs a low level. DATAP controls S1* to output high and S2* to output low, and point A discharges with current I3. The voltage at point A continues to decrease, and the voltage at point B continues to rise until the voltage at point B is higher than VREF2. The output of comparator CMP flips on the falling edge of CLK_LATCH, and DATAP becomes high. Then the process when DATAP is high is repeated.

[0072] When the external control voltage CV is small, the I3 generated by it is also small. When point A is charged, its charging current Ix = I1 - I3 is large, while the current Ix = I3 during discharge is small. During the high level phase of DATAP, point A rises quickly during charging, and point B drops quickly accordingly. Point B can output a voltage drop below VREF2 in a shorter reference clock cycle, which means that the voltage of point B is greater than VREF2 for a short time. That is, the high level output time of DATAP is short and the low level output time is long. The corresponding number of "1"s in DATA is small and the number of "0"s is large.

[0073] As the control voltage CV increases, the I3 generated by it also increases. The charging current Ix = I1 - I3 at point A decreases, while the discharging current Ix = I3 increases. During the high-level phase of DATAP, the rise of point A during charging slows down, and the corresponding rate of voltage drop at point B also slows down. The number of reference clock cycles required for point B to drop below VREF2 increases, which means that the time for the voltage at point B to be above VREF2 is increasing. The high-level time of DATAP output becomes longer and the low-level time becomes shorter, correspondingly increasing the number of "1"s and decreasing the number of "0"s in DATA.

[0074] As can be seen from the above description, the control voltage CV is directly proportional to and linear with the number of "1"s in DATA.

[0075] When the external control voltage CV makes the charging and discharging currents equal, the voltage that rises at point A during the charging cycle is exactly equal to the voltage that falls at point A during the discharging cycle. This means that the voltage at point B of AMP3 decreases and rises at the same rate during the charging and discharging cycles. Since the system as a whole is a negative feedback loop, the output of comparator CMP must be a square wave signal with a 50% duty cycle and a period that is an integer multiple of CLK_LATCH. This means that the data in DATA is in the state of "10101010......".

[0076] DATA enters the ΣΔ modulator and is superimposed on the fractional part of the division ratio. To enable bidirectional adjustment of the PLL output frequency, a preset threshold "10101010......" is used in the ΣΔ modulator. When DATA equals the preset threshold, the fractional part remains unchanged; when DATA is greater than the preset value, the fractional part is added to the portion exceeding the threshold; when DATA is less than the preset threshold, the fractional part is subtracted from the portion below the threshold, thus achieving calibration of the PLL output frequency.

[0077] The phase-locked loop output frequency calibration circuit provided in this application has been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0078] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A phase-locked loop output frequency calibration circuit, comprising: The ΣΔ modulator, fractional register, frequency divider controller, and integer register are characterized by further comprising: a voltage-controlled pulse generator; The voltage-controlled pulse generator is connected to a reference clock and a control voltage, and generates digital pulses based on the reference clock and the control voltage; The voltage-controlled pulse generator is connected to the ΣΔ modulator of the phase-locked loop to maintain the output of the ΣΔ modulator unchanged when the number of logic high levels in the digital pulse is equal to the number of logic high levels in the preset pulse of the ΣΔ modulator; when the number of logic high levels in the digital pulse is greater than the number of logic high levels in the preset pulse of the ΣΔ modulator, the digital pulse is added to the preset pulse of the ΣΔ modulator as the output of the ΣΔ modulator; when the number of logic high levels in the digital pulse is less than the number of logic high levels in the preset pulse of the ΣΔ modulator, the digital pulse is subtracted from the preset pulse of the ΣΔ modulator as the output of the ΣΔ modulator. The voltage-controlled pulse generator includes: Amplification module, buffer module, push-pull module, comparison module, clock generation module; The amplification module is used to receive the control voltage, and after amplifying the control voltage, it is processed by the buffer module and the push-pull module and then transmitted to the comparison module for comparison. The output of the comparison module is connected to the clock generation module to generate a corresponding clock according to the comparison result of the comparison module.

2. The phase-locked loop output frequency calibration circuit according to claim 1, characterized in that, The amplification module includes: First switching transistor, second switching transistor, first current source, first operational amplifier, first resistor, second resistor, and third resistor; The control terminal of the first switching transistor is connected to the control voltage, the first terminal of the first switching transistor is connected to the power supply, the first terminal of the second resistor is connected to the second terminal of the first switching transistor, the second terminal of the second resistor and the first terminal of the third resistor are connected to the non-inverting input terminal of the first operational amplifier, the second terminal of the third resistor is grounded, the inverting input terminal of the first operational amplifier is connected to the first terminal of the first resistor and the first terminal of the second switching transistor, the second terminal of the first resistor is grounded, the output terminal of the first operational amplifier is connected to the control terminal of the second switching transistor, the second terminal of the second switching transistor is connected to the output terminal of the first current source, the buffer module, and the push-pull module, and the input terminal of the first current source is connected to the power supply.

3. The phase-locked loop output frequency calibration circuit according to claim 2, characterized in that, The buffer module and the push-pull module include: Second current source, first switch, second switch, third switch, fourth switch, second operational amplifier, third operational amplifier, first capacitor; The second terminal of the second switch is connected to the first terminal of the first switch, the inverting input terminal of the third operational amplifier, and the first terminal of the first capacitor. The second terminal of the first switch and the first terminal of the second switch are connected to the output terminal of the first current source. The input terminal of the first current source is connected to a power supply. The non-inverting input terminals of the second operational amplifier and the third operational amplifier are connected to a first comparison voltage. The inverting input terminal and the output terminal of the second operational amplifier are connected to the second terminal of the second switch and the first terminal of the third switch. The second terminal of the third switch and the first terminal of the fourth switch are connected to the input terminal of the second current source. The input terminal of the second current source is grounded. The second terminal of the first capacitor, the output terminal of the third operational amplifier, and the second terminal of the fourth switch are connected to the comparison module.

4. The phase-locked loop output frequency calibration circuit according to claim 3, characterized in that, The comparison module includes: Fourth operational amplifier, latch comparator; The inverting input terminal of the fourth operational amplifier and the non-inverting input terminal of the fourth operational amplifier are connected to the second comparison voltage. The non-inverting output terminal of the fourth operational amplifier is connected to the inverting input terminal of the latch comparator. The inverting output terminal of the fourth operational amplifier is connected to the non-inverting input terminal of the latch comparator. The non-inverting and inverting output terminals of the latch comparator are connected to the clock generation module.

5. The phase-locked loop output frequency calibration circuit according to claim 4, characterized in that, The clock generation module includes: a first AND gate, a second AND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, a frequency divider chip, and a delay unit; The positive output of the latch comparator is connected to the input of the first inverter, the output of the first inverter is connected to the control terminal of the second inverter, the inverting output of the latch comparator is connected to the input of the third inverter, the output of the third inverter is connected to the input of the fourth inverter and the control terminal of the fifth inverter, the output of the fourth inverter is connected to the input of the sixth inverter, the output of the sixth inverter is connected to the ΣΔ modulator, the input of the seventh inverter, the first input of the first AND gate, and the clock terminal of the divide-by-two chip are all connected to the reference clock, and the second input of the first AND gate is connected to the reference clock. The output of the second inverter is connected to serve as the control terminal of the first switch and the fourth switch. The output of the first AND gate is connected to the input of the fifth inverter. The output of the fifth inverter and the first input of the second AND gate are connected to serve as the control terminal of the second switch and the third switch. The output of the seventh inverter is connected to the second input of the second AND gate. The output of the second AND gate is connected to the input of the second inverter. The output of the divide-by-two chip is connected to the input of the delay unit. The output of the delay unit is connected to the control terminal of the latch comparator. The D input of the divide-by-two chip is connected to the QN terminal.

6. The phase-locked loop output frequency calibration circuit according to claim 3, characterized in that, The second current source includes: a third switch and a fourth switch; The control terminals of the third and fourth switches are connected to a power supply. The first terminal of the third switch serves as the input terminal of the second current source and is connected to the second terminal of the third switch and the first terminal of the fourth switch. The second terminal of the third switch is connected to the first terminal of the fourth switch, and the second terminal of the fourth switch is grounded.

7. The phase-locked loop output frequency calibration circuit according to claim 4, characterized in that, Also includes: Bias circuit; The input terminal of the bias circuit is connected to the power supply. The first output terminal of the bias circuit is connected to the non-inverting input terminal of the first operational amplifier. The second output terminal is connected to the non-inverting input terminal of the fourth operational amplifier. The third output terminal is connected to the control terminal of the third switching transistor. The fourth output terminal is connected to the control terminal of the fourth switching transistor.

8. The phase-locked loop output frequency calibration circuit according to claim 7, characterized in that, Also includes: LDO circuit; The input terminal of the LDO circuit is connected to the fifth output terminal of the bias circuit, and the output terminal of the LDO circuit is connected to the input terminal of the first current source.

9. The phase-locked loop output frequency calibration circuit according to any one of claims 1 to 8, characterized in that, Also includes: Signal processing module, digital-to-analog converter module, low-pass filter; The input terminal of the signal processing module is connected to the output of the phase-locked loop, the output terminal of the signal processing module is connected to the input terminal of the digital-to-analog converter module, the output terminal of the digital-to-analog converter module is connected to the input terminal of the low-pass filter, and the output terminal of the low-pass filter is connected to the control terminal of the first switching transistor as the control voltage.

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