Semiconductor device with redistribution structure configured for switchable routing

Abstract

Semiconductor devices having redistribution structures and related systems and methods are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be located between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be changed based on a location of the interconnect structure.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more specifically, to semiconductor devices having a redistributed structure configured to accommodate different packaging designs. Background Technology

[0002] A packaged semiconductor die containing memory chips, microprocessor chips, and imager chips typically comprises a semiconductor die mounted on a substrate and encased in a protective cover. The semiconductor die may include functional features such as memory cells, processor circuitry, and imager devices, as well as bonding pads electrically connected to said functional features. The bonding pads may be electrically connected to terminals outside the protective cover to allow the semiconductor die to be connected to higher-level circuitry.

[0003] Market pressures are constantly driving semiconductor manufacturers to reduce the size of die packages to fit the space constraints of electronic devices, while simultaneously increasing the functional capacity of each package to meet operating parameters. One method for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the package's "coverage area") is to vertically stack multiple semiconductor dies on top of each other within a single package. Dies in such vertically stacked packages can be electrically coupled to each other and / or electrically coupled to the substrate via wires, interconnects, or other conductive structures. However, conventional structures and techniques for interconnecting vertically stacked semiconductor dies may not accommodate diverse semiconductor package designs. Attached Figure Description

[0004] Many aspects of the invention can be better understood by referring to the accompanying drawings. The components in the drawings are not necessarily to scale. The focus is on clearly illustrating the principles of the invention.

[0005] Figure 1 This is a side cross-sectional view of a semiconductor package configured according to an embodiment of the present invention.

[0006] Figure 2A and 2B These are perspective views of a first redistribution structure and a second redistribution structure configured for use with different packaging designs according to embodiments of the present invention.

[0007] Figure 3A and 3B The first semiconductor die and the second semiconductor die are described respectively according to embodiments of the present invention.

[0008] Figure 4A and 4B The description explains how, in the first package design configured according to embodiments of the present invention, [the following is a description of the process]. Figure 3A and 3BSignal routing for the first and second semiconductor dies.

[0009] Figure 5A and 5B The description explains how, in the second packaging design configured according to embodiments of the present invention, [the following is a description of the process]. Figure 3A and 3B Signal routing for the first and second semiconductor dies.

[0010] Figures 6A to 6D This describes the signal routing via the packaging substrate configured according to an embodiment of the present invention.

[0011] Figure 7 This is a schematic diagram of a system comprising a semiconductor device or package configured according to an embodiment of the technology according to the present invention. Detailed Implementation

[0012] The following describes several embodiments of semiconductor devices and specific details of associated systems and methods. Those skilled in the art will recognize that suitable stages of the methods described herein can be performed at the wafer level or the die level. Therefore, depending on the context, the term "substrate" can refer to a wafer-level substrate or a die-level substrate. Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques can be used to deposit materials. Similarly, for example, plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques can be used to remove materials.

[0013] In several embodiments described below, a semiconductor package configured according to the present invention includes a first semiconductor die comprising a first redistribution structure; and a second semiconductor die comprising a second redistribution structure. The first and second semiconductor dies may be mounted on a substrate in a face-to-face (F2F) configuration such that at least some components of the first redistribution structure are aligned with corresponding components of the second redistribution structure. The semiconductor package may further include at least one interconnect structure (e.g., solder bump) between the first and second redistribution structures to electrically connect the first and second semiconductor dies to each other.

[0014] In some embodiments, the first and second redistribution structures are each configured to be compatible with multiple package designs (e.g., x4, x8, and / or x16 package designs). The location of the interconnect structures can be used to switch or otherwise change the signal routing through the first and second redistribution structures to accommodate these different package designs. Therefore, different redistribution structures are not required for different packages; the present invention allows the same redistribution structure design to be used simply across different packages by changing the layout of the interconnect structures. Therefore, the present invention may be desirable for reducing costs and supply chain complexity, and improving the efficiency and flexibility of design and manufacturing processes.

[0015] Numerous specific details are disclosed herein to provide a detailed and useful description of embodiments of the present invention. However, those skilled in the art will understand that the present invention may have additional embodiments, and may be described without further reference. Figures 1 to 7 The described embodiments are practiced in several details. For example, some details of semiconductor devices and / or packages well known in the art have been omitted to avoid obscuring the technical aspects of the invention. Generally, it should be understood that various other devices and systems besides the specific embodiments disclosed herein are within the scope of the invention.

[0016] As used herein, the terms “vertical,” “horizontal,” “upper,” “lower,” “above,” and “below” may refer to the relative orientation or position of a feature in a semiconductor device, given the orientation shown in the figures. For example, “upper” or “topmost” may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be broadly understood to include semiconductor devices with other orientations, such as inverted or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0017] Figure 1This is a side cross-sectional view of a semiconductor package 100 (“package 100”) configured according to an embodiment of the present invention. Package 100 may include a first semiconductor die 102a and a second semiconductor die 102b disposed above a package substrate 103. The first and second semiconductor dies 102a-b may each include a corresponding semiconductor substrate 104a-b (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) having a corresponding upper side or surface 106a-b and a corresponding lower side or surface 108a-b. In some embodiments, the first and second semiconductor dies 102a-b are arranged vertically, wherein the second semiconductor die 102b is mounted on the first semiconductor die 102a such that the lower surface 108b of the second semiconductor die 102b faces the upper surface 106a of the first semiconductor die 102a. The first semiconductor die 102a may be mounted on the package substrate 103 such that the lower surface 108a of the first semiconductor die 102a faces the package substrate 103 and is coupled to the package substrate 103.

[0018] In some embodiments, at least one of the surfaces of each of the first and second semiconductor dies 102a-b is an active surface, which includes various types of semiconductor components, such as memory circuitry (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, or other types of memory circuitry), controller circuitry (e.g., DRAM controller circuitry), logic circuitry, processing circuitry, circuit elements (e.g., wires, traces, interconnects, transistors, etc.), imaging components, and / or other semiconductor features. The first and second semiconductor dies 102a-b can be mounted such that the active surfaces of the semiconductor dies 102a-b face each other (e.g., F2F configuration). For example, in the illustrated embodiment, the upper surface 106a of the first semiconductor die 102a and the lower surface 108b of the second semiconductor die 102b are active surfaces.

[0019] The first and second semiconductor dies 102a-b can be connected via at least one interconnect structure 109 (e.g., bumps, microbumps, pillars, columns, columns, etc. - for clarity, Figure 1(Only a single interconnect structure is shown in the diagram) are coupled to each other (e.g., mechanically, thermally, and / or electrically). Each interconnect structure 109 may be formed of any suitable conductive material (e.g., copper, nickel, gold, silicon, tungsten, solder (e.g., SnAg-based solder), conductive epoxy resin, combinations thereof, etc.) and may be formed by electroplating, electroless plating, or another suitable process. In some embodiments, the interconnect structure 109 may also include a barrier material (e.g., nickel, nickel-based intermetallic compounds, and / or gold) formed over the end portions of the interconnect structure 109. The barrier material may promote adhesion and / or prevent or at least inhibit electromigration of the copper or other metals used to form the interconnect structure 109. Optionally, the interconnect structure 109 may be surrounded by an underfill material (not shown).

[0020] The package substrate 103 may be or include an interposer, such as a printed circuit board, dielectric spacers, another semiconductor die (e.g., a logic die), or another suitable substrate. In some embodiments, the package substrate 103 includes additional semiconductor components (e.g., a doped silicon wafer or a gallium arsenide wafer), non-conductive components (e.g., various ceramic substrates, such as alumina (Al2O3)), aluminum nitride, and / or conductive portions (e.g., interconnect circuitry, through-silicon vias (TSVs), etc.). The package substrate 103 may further include electrical connectors 124 (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements) electrically coupled to the package substrate 103 and configured to electrically couple the package 100 to an external device or circuitry (not shown).

[0021] Package 100 may further include molding material 126 formed over and / or at least partially surrounding the first and second semiconductor dies 102a-b on the package substrate 103. Molding material 126 may be a resin, epoxy resin, silicone-based material, polyimide, or any other material suitable for encapsulating at least a portion of the first and second semiconductor dies 102a-b and / or the package substrate 103 to protect these components from contamination and / or physical damage. In some embodiments, semiconductor package 100 includes other components such as an external heat sink, a sleeve (e.g., a thermally conductive sleeve), an electromagnetic interference (EMI) shielding assembly, etc.

[0022] In some embodiments, the first and second semiconductor dies 102a-b each include a corresponding redistribution layer or structure. For example, such as Figure 1As shown, the first semiconductor die 102a includes a first redistribution structure 110a formed on the upper surface 106a, and the second semiconductor die 102b includes a second redistribution structure 110b formed on the lower surface 108b. The first and second redistribution structures 110a-b may each include one or more conductive components, such as contacts, traces, pads, pins, wiring, circuitry, etc. The components of the redistribution structures 110a-b may be made of any suitable conductive material, such as one or more metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the redistribution structures 110a-b are or include an embedded redistribution layer (iRDL). The iRDL may be formed at a front-end stage of the manufacturing process (e.g., before wafer probe testing).

[0023] The first and second redistribution structures 110a-b can be configured to electrically couple different portions of the respective semiconductor dies to route signals therebetween. For example, the first redistribution structure 110a may include a first signal trace 112a extending between and electrically coupling the first die contact or pin 114a and the package contact or pin 116. The first die contact 114a and the package contact 116 may be located at different locations on the first semiconductor die 102a. For example, the first die contact 114a may be located at or near the center and / or inner portion of the first semiconductor die 102a, while the package contact 116 may be located at or near the peripheral portion of the first semiconductor die 102a. The package contact 116 may be electrically coupled to a corresponding bonding pad 118 on the package substrate 103 via a conductive element such as a wire 120 (e.g., a bonding wire). Therefore, a signal originating from the first semiconductor die 102a can be transmitted to the package substrate 103 via the first redistribution structure 110a (e.g., from the first die contact 114a through the first signal trace 112a, package contact 116, wire 120 and bonding pad 118 to the package substrate 103).

[0024] In the illustrated embodiment, the second semiconductor die 102b does not have any package contacts for direct coupling to the substrate 103. Alternatively, signals from the second semiconductor die 102b may be routed to the package substrate 103 indirectly via the first semiconductor die 102a, as described in more detail below. However, in other embodiments, the second semiconductor die 102b may include one or more package contacts configured to connect directly to the package substrate 103 (e.g., via wire bonding) to allow direct signal transmission between the second semiconductor die 102b and the package substrate 103. Optionally, some signals from the second semiconductor die 102b may be transmitted indirectly to the package substrate 103 via the first semiconductor die 102a, while other signals may be transmitted directly to the package substrate 103.

[0025] exist Figure 1 In some embodiments, the first and second redistribution structures 110a-b and the interconnect structure 109 route signals from the second semiconductor die 102b to the first semiconductor die 102a and the package substrate 103. A first signal trace 112a of the first redistribution structure 110a may be connected to a first interconnect pad 122a (e.g., a bump pad). The first interconnect pad 122a may be located at or near the center and / or inner portion of the first semiconductor die 102a, for example, near the first die contact 114a. In some embodiments, the first interconnect pad 122a is located along the first signal trace 112a between the first die contact 114a and the package contact 116. The second redistribution structure 110b may include a second signal trace 112b extending between the second die contact or pin 114b and the second interconnect pad 122b (e.g., a bump pad) and electrically coupling the second die contact or pin 114b and the second interconnect pad 122b. The second die contact 114b and the second interconnect pad 122b may be located near each other, for example, at or near the center and / or inner portion of the second semiconductor die 102b.

[0026] like Figure 1 As shown, when the first and second semiconductor dies 102a-b are arranged vertically in an F2F configuration, the first and second redistribution structures 110a-b can face each other, aligning the first and second interconnect pads 122a-b. The first and second interconnect pads 122a-b can be electrically coupled to each other via interconnect structure 109. Therefore, signals originating from the second semiconductor die 102b can be transmitted to the package substrate 103 via the first and second redistribution structures 110a-b (e.g., from the second die contact 114b through the second signal trace 112b, the second interconnect pad 122b, the interconnect structure 109, the first interconnect pad 122a, the first signal trace 112a, the package contact 116, the wire 120, and the bonding pad 118 to the package substrate 103).

[0027] In some embodiments, the first and second redistribution structures 110a-b are configured to accommodate different types of semiconductor package designs. For example, the first and second redistribution structures 110a-b can be used with at least two different package designs (e.g., x4 / x8 and x16 designs). In some embodiments, the x4 / x8 package provides eight different data channels, while the x16 design provides sixteen different data channels. The different package designs may involve different signal routing between the die contacts of the first semiconductor die 102a, the die contacts of the second semiconductor die 102b, and the package contacts of the first semiconductor die 102a. In such embodiments, the signal routing between these components is switched to a different configuration by changing the location of the interconnect structure 109 between the first and second redistribution structures 110a-b, rather than by changing the design of the first and second redistribution structures 110a-b.

[0028] Figure 2A and 2B This is a perspective view of a first redistribution structure 200a and a second redistribution structure 200b configured for use with different packaging designs according to embodiments of the present invention. The first and second redistribution structures 200a-b may be incorporated into any of the embodiments described herein (e.g., as relative to...). Figure 1 (A portion of the first and second redistribution structures 110a-b described). For example, the first redistribution structure 200a may be formed on the upper surface of a first semiconductor die (e.g., the lower semiconductor die in an F2F semiconductor package - not shown), and the second redistribution structure 200b may be formed on the lower surface of a second semiconductor die (e.g., the upper semiconductor die in an F2F semiconductor package - not shown). In other embodiments, this configuration may be reversed, such that the second redistribution structure 200b is formed on the upper surface of the first semiconductor die, and the first redistribution structure 200a is formed on the lower surface of the second semiconductor die.

[0029] Let's refer to each other. Figure 2A and 2BThe first redistribution structure 200a includes a first signal trace 202 and a second signal trace 204. The first signal trace 202 is electrically coupled to a first die contact 206, a first interconnect pad 208, and a first package contact 210. The second signal trace 204 is electrically coupled to a second interconnect pad 212 to a second package contact 214. In some embodiments, the first die contact 206 includes or is coupled to an output pin (e.g., a data pin, address pin, control pin, etc.) of the first semiconductor die. The first interconnect pad 208 may be located along the first signal trace 202 between the first die contact 206 and the first package contact 210. The first package contact 210 and the second package contact 214 may be configured to be electrically coupled to corresponding first and second bonding pads of the package substrate via wire bonding or other techniques known to those skilled in the art. The first die contact 206, the first interconnect pad 208, and the second interconnect pad 212 may be located at a first portion (e.g., the center and / or inner portion) of the first semiconductor die, and the first package contact 210 and the second package contact 214 may be located at a second different portion (e.g., the peripheral portion) of the first semiconductor die. In some embodiments, the first signal trace 202 and the second signal trace 204 are spaced apart and / or electrically isolated from each other, such that signals carried by the first signal trace 202 are not transmitted to the second signal trace 204, and vice versa.

[0030] The second redistribution structure 200b includes a third signal trace 216. The third signal trace 216 is electrically coupled to a second die contact 218, a third interconnect pad 220, and a fourth interconnect pad 222. In some embodiments, the second die contact 218 includes or is coupled to an output pin (e.g., a data pin, address pin, control pin, etc.) of the second semiconductor die. The third interconnect pad 220 may be located along the third signal trace 216 between the second die contact 218 and the fourth interconnect pad 222. The second die contact 218, the third interconnect pad 220, and the fourth interconnect pad 222 may be located at the center and / or an inner portion of the second semiconductor die. In some embodiments, the third signal trace 216 does not include any package contacts or other components directly connected to the package substrate.

[0031] When the first and second semiconductor dies are assembled in an F2F configuration, the first and second redistribution structures 200a-b can be positioned close to each other such that one or a portion of the first and second redistribution structures 200a-b are aligned and bridged via interconnect structure 224. For example, in the illustrated embodiment, the first interconnect pad 208 of the first redistribution structure 200a is aligned with the third interconnect pad 220 of the second redistribution structure 200b such that the first interconnect pad 208 and the third interconnect pad 220 can be electrically and mechanically coupled to each other by interconnect structure 224. As can be seen in... Figure 2A and 2BAs seen in the diagram, the first interconnect pad 208 extends at least partially above the third interconnect pad 220, such that when viewed from directly above or below, the area occupied by the first interconnect pad 208 at least partially covers the area occupied by the third interconnect pad 220. Optionally, the central vertical axis of the first interconnect pad 208 may be collinear with or at least partially overlap with the central vertical axis of the third interconnect pad 220. The second interconnect pad 212 of the first redistribution structure 200a may be aligned with the fourth interconnect pad 222 of the second redistribution structure 200b in a similar manner. In some embodiments, the interconnect structure 224 is used to electrically couple the first and second redistribution structures 200a-b to each other. The positioning of the interconnect structure 224 may be selected to form a desired signal routing path between the first die contact 206, the second die contact 218, the first package contact 210, and the second package contact 214.

[0032] refer to Figure 2A For example, in a first package design (e.g., an x4 and / or x8 package design), interconnect structure 224 can electrically and mechanically couple a first signal trace 202 of a first redistribution structure 200a to a third signal trace 216 of a second redistribution structure 200b. In the illustrated embodiment, interconnect structure 224 is located between a first interconnect pad 208 of the first redistribution structure 200a and a third interconnect pad 220 of the second redistribution structure 200b, thereby electrically coupling the first signal trace 202 to the third signal trace 216. Therefore, signals from a first die contact 206 of a first semiconductor die and / or a second die contact 218 of a second semiconductor die are transmitted to a first package contact 210.

[0033] exist Figure 2A In the illustrated embodiment, there is no interconnect structure between the second interconnect pad 212 of the first redistribution structure 200a and the fourth interconnect pad 222 of the second redistribution structure 200b, such that the second signal trace 204 of the first redistribution structure 200a remains electrically isolated from the third signal trace 216 of the second redistribution structure 200b. Therefore, signals from the second die contact 218 of the second semiconductor die are not transmitted to the second package contact 214. In some embodiments, the second package contact 214 also does not receive any signals from the first semiconductor die because the second signal trace 204 is not connected to any die contact on the first semiconductor die. Therefore, the first package contact 210 can transmit signals from the first and / or second semiconductor dies, while the second package contact 214 remains unused.

[0034] refer to Figure 2BIn a second package design (e.g., an x16 package design), interconnect structure 224 electrically and mechanically couples the second signal trace 204 of the first redistribution structure 200a to the third signal trace 216 of the second redistribution structure 200b. In the illustrated embodiment, interconnect structure 224 is located between the second interconnect pad 212 of the first redistribution structure 200a and the fourth interconnect pad 222 of the second redistribution structure 200b, thereby electrically coupling the second signal trace 204 to the third signal trace 216. Therefore, a signal from the second die contact 218 of the second semiconductor die can be transmitted to the second package contact 214. In some embodiments, the second package contact 214 does not receive any signal from the first semiconductor die because the second signal trace 204 is not connected to any die contact on the first semiconductor die.

[0035] exist Figure 2B In the illustrated embodiment, there is no interconnect structure between the first interconnect pad 208 of the first redistribution structure 200a and the third interconnect pad 220 of the second redistribution structure 200b, such that the first signal trace 202 of the first redistribution structure 200a remains electrically isolated from the third signal trace 216 of the second redistribution structure 200b. Therefore, the first package contact 210 can receive signals from the first die contact 206, rather than the second die contact 218. In such embodiments, the first package contact 210 can transmit signals from the first semiconductor die, while the second package contact 214 can transmit signals from the second semiconductor die.

[0036] The first and second redistribution structures 200a-b can be configured in many different ways to implement the encapsulation-related signal routing described herein. For example, although in Figure 2A and 2BIn this embodiment, the first interconnect pad 208 is located between the first die contact 206 and the first package contact 210. However, in other embodiments, the first die contact 206 may be located between the first interconnect pad 208 and the first package contact 210. As another example, the positions of the first signal trace 202 and the second signal trace 204 may be interchanged, such that the first interconnect pad 208 of the first redistribution structure 200a is aligned with the fourth interconnect pad 222 of the second redistribution structure 200b, and the second interconnect pad 212 of the first redistribution structure 200a is aligned with the third interconnect pad 220 of the second redistribution structure 200b. Optionally, the first die contact 206 may be omitted and / or the second signal trace 204 may be electrically coupled to the die contact. In some embodiments, the first redistribution structure 200a includes additional signal traces (e.g., one, two, three, four, five or more additional signal traces), each signal trace having a corresponding interconnect pad, and the second redistribution structure 200b may include a corresponding number of interconnect pads to allow the third signal trace 216 to be selectively connected to the additional signal traces based on the positioning of the interconnect structure 224.

[0037] Figure 3A and 3B The first semiconductor die 102a and the second semiconductor die 102b, respectively, are described according to embodiments of the present invention. More specifically, Figure 3A It is a top view of the upper surface 106a of the first semiconductor die 102a and Figure 3B This is a top view of the lower surface 108b of the second semiconductor die 102b. As previously described, the first and second semiconductor dies 102a-b can be arranged in an F2F configuration, wherein the lower surface 108b of the second semiconductor die 102b is aligned with and located above the upper surface 106a of the first semiconductor die 102a. The first semiconductor die 102a includes a first redistribution structure 300a formed on the upper surface 106a, and the second semiconductor die 102b includes a second redistribution structure 300b formed on the lower surface 108b. The first and second redistribution structures 300a-b can be substantially similar to those previously described relative to... Figures 1 to 2B The corresponding structure described.

[0038] refer to Figure 3A For example, the first redistribution structure 300a may include signal traces 302a, die contacts 304a, interconnect pads 306a, and package contacts 308. (As can be...) Figure 3AAs can be seen, some signal traces 302a are connected to corresponding die contacts 304a, interconnect pads 306a, and package contacts 308 (e.g., signal trace 312), while other signal traces 302a are connected to corresponding interconnect pads 306a and package contacts 308, but not to any of the die contacts 304a (e.g., signal trace 314). The signal traces 302a may be spaced apart and / or electrically isolated from each other, so that signal transmission can occur independently along each signal trace 302a.

[0039] In the illustrated embodiment, die contacts 304a are arranged in a single row along or near the central axis of the first semiconductor die 102a, and interconnect pads 306a are arranged in multiple rows around both sides of the row of die contacts 304a. Package contacts 308 may be arranged in two rows extending along two of the side edges of the first semiconductor die 102a, respectively. Therefore, signal traces 302a may extend outward from the central portion of the semiconductor die in two directions to route signals from the die contacts 304a and / or the interconnect pads 306a to the package contacts 308. In other embodiments, the first redistribution structure 300a may be configured differently (e.g., die contacts 304a may be arranged in two or more rows, package contacts 308 may be arranged in a single row along a single side edge of the first semiconductor die 102a, interconnect pads 306a may be arranged in fewer or more rows, interconnect pads 306a may be located on one side of the row of die contacts 304a, etc.).

[0040] refer to Figure 3B The second redistribution structure 300b may include signal traces 302b, die contacts 304b, and interconnect pads 306b. For example, it can be... Figure 3B As seen, each signal trace 302b can be connected to a corresponding die contact 304b and at least two interconnect pads 306b. The signal traces 302b can be spaced apart and / or electrically isolated from each other, allowing signals to be transmitted independently along each signal trace 302b. In the illustrated embodiment, the second redistribution structure 300b does not include any package contacts for direct connection to the package substrate. However, in other embodiments, the second redistribution structure 300b may include one or more package contacts for direct connection to the package substrate.

[0041] In the illustrated embodiment, die contacts 304b are arranged in a single row along or near the central axis of the second semiconductor die 102b, and interconnect pads 306b are arranged in multiple rows around both sides of the row of die contacts 304b. In other embodiments, the second redistribution structure 300b may be configured in different ways (e.g., die contacts 304b may be arranged in two or more rows, interconnect pads 306b may be arranged in fewer or fewer rows, interconnect pads 306b may be located on one side of the row of die contacts 304b, etc.).

[0042] It can be based on the interconnect structure (e.g., solder balls) in, as previously mentioned relative to Figure 2A and 2B The positioning of the first and second semiconductor dies 102a-b described herein switches or otherwise alters the signal routing between the first and second semiconductor dies 102a-b via the first and second redistribution structures 300a-b. In some embodiments, the arrangement of the interconnect pads 306a of the first semiconductor die 102a may be the same as or substantially similar to the arrangement of the interconnect pads 306b of the second semiconductor die 102b. Therefore, the first and second redistribution structures 300a-b may be bridged by interconnect structures located between the interconnect pads 306a-b, as previously described.

[0043] Optionally, the interconnect pads 306a of the first redistribution structure 300a may be arranged in pairs (or larger groups) to allow switchable signal routing between corresponding pairs of signal traces 302a, and the interconnect pads 306b of the second redistribution structure 300b may be arranged in pairs (or larger groups) to align with the first redistribution structure 300a pair. For example, a pair of interconnect pads 310a (“pair 310a”) of the first redistribution structure 300a may be aligned with a corresponding pair of interconnect pads 310b (“pair 310b”) of the second redistribution structure 300b to allow switchable signal routing through a pair of signal traces 312, 314 of the first semiconductor die 102a.

[0044] Figure 4A and 4B The description describes how, in the first package design (e.g., x4 and / or x8 package design) configured according to embodiments of the present invention, [the following is a description of the process]. Figure 3A and 3BSignal routing for the first and second semiconductor dies 102a-b. In the illustrated embodiment, some interconnect pads 306a-b are connected (“connected”) via interconnect structures (not shown), while other interconnect pads 306a-b are not connected by any interconnect structure (“not connected”). Depending on the arrangement of the interconnect structures, each signal trace 302a and package contact 308 may: (1) receive a signal from the first semiconductor die 102a, but not the second semiconductor die 102b (“die 1”), (2) receive a signal from the second semiconductor die 102b, but not the first semiconductor die 102a (“die 2”), (3) receive a signal from the first and / or second semiconductor dies 102a-b (“die 1 and / or die 2”), or (4) not receive a signal from the first or second semiconductor dies 102a-b (“no”).

[0045] For example, in the illustrated embodiment, the first interconnect pad 316a of 310a is connected to the second interconnect pad 316b of 310b by an interconnect structure (not shown), while the remaining interconnect pads of 310a-b are not connected to each other. Therefore, signals from the die contacts 318a of the first semiconductor die 102a and / or the die contacts 318b of the second semiconductor die 102 can be transmitted to the package contacts 320 via signal trace 312, while signal trace 314 and package contacts 322 remain unused and do not receive signals from the first or second semiconductor dies 102a-b.

[0046] Figure 5A and 5B The description describes how, in the second package design (e.g., x16 package design) configured according to embodiments of the present invention, [the following is a description of the process]. Figure 3A and 3B The signal routing of the first and second semiconductor dies 102a-b. In the second package design, the location of some or all interconnect structures (not shown) may differ from that in the first package design. Therefore, the signal routing for some or all of the signal traces 302a and package contacts 308 may differ from that in the first package design. For example, signal traces 302a and package contacts 308 that previously received signals from the first and second semiconductor dies 102a-b may now receive signals only from the first semiconductor die 102a or only from the second semiconductor die 102b; previously unused signal traces 302a and package contacts 308 may now receive signals from the first and / or second semiconductor dies 102a-b; and so on.

[0047] For example, in the illustrated embodiment, the second interconnect pad 317a of 310a is connected to the second interconnect pad 317b of 310b by an interconnect structure (not shown), while the remaining interconnect pads of 310a-b are not connected to each other. Therefore, signal trace 312 and package contact 320 receive signals from die contact 318a of the first semiconductor die 102a, while signal trace 314 and package contact 322 receive signals from die contact 318b of the second semiconductor die 102b.

[0048] The present invention provides switchable routing for many different types of signals in semiconductor packages, such as data signals, control signals, address signals, calibration signals, or any other signal types known to those skilled in the art. According to the techniques described herein, signal connections and configurations can be changed in a package-related manner as needed.

[0049] Figures 6A to 6D This describes the signal routing configured through the packaging substrate 103 according to an embodiment of the present invention. More specifically, Figure 6A This is a top view of the first wiring layer 600a of the packaging substrate 103. Figure 6B This is a top view of the second wiring layer 600b of the packaging substrate 103. Figure 6C This is a top view of the third wiring layer 600c of the packaging substrate 103, and Figure 6D This is a top view of a packaging substrate 103 having overlapping wiring layers 600a-c. The packaging substrate 103 may be incorporated into a semiconductor package described herein (e.g., Figure 1 In any embodiment of the package 100).

[0050] The first wiring layer 600a of the packaging substrate 103 can be electrically coupled to the lower surface of the first semiconductor die 102a (only when...). Figures 6A to 6D The outline of the first semiconductor die 102a is shown to illustrate its positioning relative to the packaging substrate 103. The second wiring layer 600b is electrically coupled to an array of electrical connectors 124 (e.g., a ball grid array). Figure 6B and 6D Only the outline of the electrical connector 124 is included to illustrate its positioning relative to the package substrate 103. (As previously stated relative to...) Figure 1As described, the electrical connector 124 can be used to electrically couple the package substrate 103 to an external device or other higher-level component to allow signal transmission thereto. In some embodiments, the package substrate 103 is electrically coupled to a first semiconductor die 102a via wires (not shown). The wires can connect package contacts (not shown) on the first semiconductor die 102a to corresponding bonding pads 118 contained in or electrically coupled to a first wiring layer 600a of the package substrate 103. Each bonding pad 118 may be electrically coupled to the corresponding electrical connector 124 via wiring, traces, metal layers or structures, vias, or other conductive features extending along and / or through the wiring layers 600a-c of the package substrate 103.

[0051] In some embodiments, the number and / or positioning of the bonding pads 118 relative to the electrical connectors 124 may make it difficult or impossible to route all electrical interconnections between the bonding pads 118 and the electrical connectors 124 within a single layer of the package substrate 103. For example, the location of the bonding pads 118 may be constrained by the geometry of the first semiconductor die 102a. Since the width of the first semiconductor die 102a is close to the width of the array of electrical connectors 124, signal routing through the package substrate 103 can become more congested and challenging. To mitigate these issues, the package substrate 103 may route electrical interconnections between the bonding pads 118 and the electrical connectors 124 across multiple layers (e.g., at least two, three, four, or more layers). For example, a first subset of signals from the bonding pads 118 may be routed through a first wiring layer 600a (“first subset”), a second subset of signals through a second wiring layer 600b (“second subset”), a third subset of signals through a third wiring layer 600c (“third subset”), and so on.

[0052] In the illustrated embodiments, for example, bonding pad 118 includes a first subset of bonding pads 610, a second subset of bonding pads 620, and optionally a third subset of bonding pads 630 (reference numerals for a single instance of each subset are shown only for clarity). In some embodiments, the first bonding pad 610 corresponds to a first set of data signals (e.g., upper bytes) for a semiconductor package, the second bonding pad 620 corresponds to a second set of data signals (e.g., lower bytes), and the third bonding pad 630 corresponds to other signals (e.g., control signals, address signals, calibration signals, power signals, etc.). Each subset of bonding pads 118 may be electrically coupled to a corresponding subset of the array of electrical connectors 124 via a respective wiring structure. For example, the first bonding pad 610 may be connected to a first subset of electrical connectors 612 via a first wiring structure 614, the second bonding pad 620 may be connected to a second subset of electrical connectors 622 via a second wiring structure 624, and optionally, the third subset of bonding pads 630 may be connected to a third subset of electrical connectors 632 via a wiring structure 634.

[0053] Signals from the first bonding pad 610 can be routed in the first wiring layer 600a. Therefore, as... Figure 6A As shown, a first wiring structure 614 may be located in a first wiring layer 600a and may extend from a first bonding pad 610 to a corresponding first via 616. In some embodiments, the first bonding pad 610 is located at or near a peripheral portion of the package substrate 103, while the first via 616 is located away from the first bonding pad 610 at or near an internal portion of the package substrate 103. The first via 616 may be located near a first electrical connector 612 to provide electrical connection thereto. Figure 6A and 6B As shown, for example, each of the first through-holes 616 may extend through the first wiring layer 600a to a position in the second wiring layer 600b adjacent to or close to the corresponding first electrical connector 612.

[0054] Signals from the second bonding pad 620 can be routed in the second wiring layer 600b, rather than in the first wiring layer 600a. Therefore, as... Figure 6A As shown, in the first wiring layer 600a, the second bonding pad 620 may be connected to a corresponding second via 626 located near the second bonding pad 620 (e.g., near the peripheral portion of the package substrate 103). Figure 6A and 6B As shown, the second through-hole 626 may extend through the first wiring layer 600a to a position in the second wiring layer 600b away from the corresponding second electrical connector 622. The second wiring structure 624 may be located in the second wiring layer 600b and may extend from the second through-hole 626 to the second electrical connector 622.

[0055] Let's refer to each other. Figure 6C The packaging substrate 103 may optionally include a third wiring layer 600c between the first and second wiring layers 600a-b. In such embodiments, the first via 616 and the second via 626 may extend through the wiring layer 600c. The third wiring layer 600c may also be used to route signals from the third bonding pad 630. Thus, as Figure 6A As shown, in the first wiring layer 600a, the third bonding pad 630 can be connected to a third via 626a located near the third bonding pad 630 (e.g., near the peripheral portion of the package substrate 103). Figure 6A and 6C As shown, the third via 636 may extend through the first wiring layer 600a and into the third wiring layer 600c. A third wiring structure 634 may be located in the third wiring layer 600c and may extend from the third via 636 to a fourth via 638. The fourth via 638 may be spaced apart from the third via 636. Figure 6B and 6CAs shown, the fourth through-hole 638 can extend through the third wiring layer 600c to reach a position in the second wiring layer 600b adjacent to or close to the corresponding third electrical connector 632.

[0056] Figure 6D A package substrate 103 is shown having overlapping wiring layers 600a-c. As can be seen from the illustrated embodiments, the use of multiple wiring layers, as described herein, enables multiple complex interconnections between the bonding pads 118 and the electrical connectors 124. In other embodiments, the package substrate 103 may contain fewer or more wiring layers (e.g., one, two, four, five, or more wiring layers), each wiring layer containing a corresponding wiring structure for routing signals between a subset of the bonding pads 118 and the electrical connectors 124. The package substrate 103 may also include Figures 6A to 6D Additional layers not shown. For example, the package substrate 103 may include one or more insulating material layers between wiring layers to reduce or prevent electrical interference. The package substrate 103 may also include one or more material layers configured to provide structural support and / or mechanical strength.

[0057] References above Figures 1 to 6D Any of the semiconductor devices and / or packages with the described features can be incorporated into any of a large number of larger and / or more complex systems, a representative example of which is... Figure 7 The system 700 is schematically shown in the diagram. System 700 may include a processor 702, a memory 704 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 706, and / or other subsystems or components 708. (See above reference) Figures 1 to 6D The described semiconductor die and / or package may be included Figure 7 The system 700 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of the system 700 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, networked appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics devices, network computers, and microcomputers. Additional representative examples of the system 700 include lamps, cameras, vehicles, etc. Regarding these and other examples, the system 700 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. Accordingly, the components of the system 700 can include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0058] In summary, it should be understood that specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Therefore, the invention is not limited except by the appended claims. Furthermore, certain aspects of the new technology described in the context of specific embodiments may be combined or removed in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are required to exhibit such advantages to fall within the scope of the invention. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A semiconductor package comprising: Packaging substrate; A first semiconductor die, mounted to the packaging substrate, the first semiconductor die including a first redistribution structure, the first redistribution structure including - A first signal trace, electrically coupled to a first die contact, a first interconnect pad, and a first package contact, and A second signal trace is electrically coupled to a second interconnect pad and a second package contact, wherein the second signal trace is electrically isolated from the first signal trace; and A second semiconductor die, mounted to the first semiconductor die, includes a second redistribution structure having a third signal trace electrically coupled to second die contacts, a third interconnect pad, and a fourth interconnect pad. Wherein (1) the first interconnect pad of the first redistribution structure is aligned with the third interconnect pad of the second redistribution structure, such that the first interconnect pad and the third interconnect pad can be bridged by the interconnect structure, and (2) the second interconnect pad of the first redistribution structure is aligned with the fourth interconnect pad of the second redistribution structure, such that the second interconnect pad and the fourth interconnect pad can be bridged by the interconnect structure.

2. The semiconductor package of claim 1, further comprising an interconnect structure electrically coupling the first semiconductor die and the second semiconductor die.

3. The semiconductor package of claim 2, wherein the interconnect structure includes solder bumps.

4. The semiconductor package of claim 2, wherein the interconnect structure connects the first interconnect pad to the third interconnect pad such that both the first die contact and the second die contact are electrically coupled to the first package contact.

5. The semiconductor package of claim 2, wherein the interconnect structure connects the second interconnect pad to the fourth interconnect pad such that the first die contact is electrically coupled to the first package contact and the second die contact is electrically coupled to the second package contact.

6. The semiconductor package according to claim 1, wherein: The first redistribution structure is located on the upper surface of the first semiconductor die; The second redistribution structure is located on the lower surface of the second semiconductor die; and The first semiconductor die and the second semiconductor die are mounted on the packaging substrate, wherein the upper surface of the first semiconductor die faces the lower surface of the second semiconductor die.

7. The semiconductor package according to claim 1, wherein: The first die contact, the first interconnect pad, and the second interconnect pad are located within the inner portion of the first semiconductor die. The first package contact and the second package contact are located at the peripheral portion of the first semiconductor die; and The second die contact, the third interconnect pad, and the fourth interconnect pad are located within the inner portion of the second semiconductor die.

8. The semiconductor package of claim 1, wherein the first package contact and the second package contact are electrically coupled to corresponding first and second bonding pads on the package substrate via wire bonding.

9. The semiconductor package of claim 8, wherein the package substrate is coupled to a first electrical connector and a second electrical connector, the first electrical connector being electrically coupled to the first bonding pad, and the second electrical connector being electrically coupled to the second bonding pad.

10. The semiconductor package of claim 9, wherein the first electrical connector and the second electrical connector are solder balls of a ball grid array.

11. The semiconductor package of claim 9, wherein the first bonding pad and the second bonding pad are electrically coupled to the first electrical connector and the second electrical connector via first and second wiring structures, respectively, and wherein the first and second wiring structures are wired on different layers of the package substrate.

12. A method for manufacturing a semiconductor package, the method comprising: A first redistribution structure is formed on a first semiconductor die, the first redistribution structure comprising - A first signal trace, electrically coupled to a first die contact, a first interconnect pad, and a first package contact, and The second signal trace is electrically coupled to the second interconnect pad and the second package contact; A second redistribution structure is formed on a second semiconductor die, the second redistribution structure including a third signal trace electrically coupled to a second die contact, a third interconnect pad, and a fourth interconnect pad; and Based on the design of the semiconductor package, a first location or a second location is selected for the interconnect structure between the first semiconductor die and the second semiconductor die, wherein - When in the first position, the interconnect structure is located between the first interconnect pad and the third interconnect pad to electrically couple the second die contact to the first package contact. When in the second position, the interconnect structure is between the second interconnect pad and the fourth interconnect pad to electrically couple the second die contact to the second package contact; and The first semiconductor die and the second semiconductor die are electrically coupled to the interconnect structure at the selected first or second location.

13. The method of claim 12, wherein the first signal trace is electrically isolated from the second signal trace.

14. The method of claim 12, wherein the design is an x4 and / or x8 package design, and the method further comprises positioning the interconnect structure in the first location such that the first die contact and the second die contact are electrically coupled to the first package contact.

15. The method of claim 14, further comprising transmitting a signal from one or more of the first die contact or the second die contact to the first package contact.

16. The method of claim 12, wherein the design is an x16 package design, and the method further comprises positioning the interconnect structure in the second location such that the first die contact is electrically coupled to the first package contact and the second die contact is electrically coupled to the second package contact.

17. The method of claim 16, further comprising: The first signal is transmitted from the first die contact to the first package contact; and A second signal is transmitted from the second die contact to the second package contact, wherein the second signal is different from the first signal.

18. The method of claim 12, further comprising: The first semiconductor die is mounted on the packaging substrate; and The second semiconductor die is mounted on the first semiconductor die.

19. The method of claim 18, wherein the first semiconductor die and the second semiconductor die are mounted in a face-to-face configuration.

20. The method of claim 18, further comprising bonding the first semiconductor die lead to the package substrate.

21. The method of claim 20, further comprising transmitting a signal from the second semiconductor die to the package substrate via the first redistribution structure, the second redistribution structure, and the interconnect structure.

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