A power amplifier with improved bias linearity

Abstract

This invention provides a power amplifier with improved bias following performance. An ADC converts the measured analog voltage into digital data, which is then fed into a DSP. The DSP acquires the signal and performs model matching with a pre-established power amplifier stage bias model to detect overload trends and whether the power amplifier is about to exceed the bias linearity range. This determines whether to adjust the power amplifier bias. If a strong overload trend (short circuit) is detected, the final stage of the power amplifier is shut down promptly. For stages exceeding the bias lead region (Class A region), a certain degree of overfit compensation is applied, ensuring the power amplifier stage remains in the high linearity region while reducing fixed bias current and power consumption, thus protecting the equipment. This invention solves the problem of large dispersion and poor bias following performance in traditional power amplifiers using analog bias. It employs a high-speed sampling and signal processing loop to improve bias following performance while effectively protecting the circuit from damage.

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