An amplifier based on a DSP chip to improve bias following performance

Abstract

This invention provides an amplifier with improved bias tracking performance based on a DSP chip. It includes a file acquisition module that directly acquires the audio file to be played via an interface. The audio file is pre-input into the DSP for standard waveform analysis, which speeds up processing and reduces latency during actual playback. During actual playback, the actual played energy is compared with the pre-calculated energy to determine if it matches the pre-designed output. If it matches, the pre-designed output is used directly; otherwise, it is further input into a model for processing, ensuring operational stability and safety.

Description

Technical Field

[0001] This invention relates to the field of audio amplifiers, and more specifically to an amplifier based on a DSP chip to improve bias following performance. Background Technology

[0002] A power amplifier is an amplifier that can produce maximum power output to drive a load (such as a loudspeaker) under a given distortion rate. The power amplifier plays a pivotal role in the entire audio system, acting as a "coordinator" and, to a certain extent, determining whether the entire system can provide good sound quality.

[0003] For example, application number CN201210114078.7 discloses a headphone detection circuit for detecting whether a headphone is connected to the headphone jack of an electronic device. The electronic device includes a processing unit and an audio amplifier. The headphone detection circuit includes a level output module and a trigger signal generation module. When a headphone is connected to the headphone jack, the level output module generates a first level to trigger the audio amplifier to output amplified left and right channel analog signals to the speaker. When a headphone is not connected to the headphone jack, the level output module generates a second level to trigger the audio amplifier to output amplified left and right channel analog signals to the headphone jack.

[0004] Application number CN202020860202.4 discloses a Bluetooth headset amplifier, including a Bluetooth module, a process control module, a signal modulation module, and a shielding layer. The Bluetooth headset amplifier is detachably connected to the outer shell of the Bluetooth headset. The Bluetooth headset amplifier controls the working state of the Bluetooth module by reading the characteristic information of the audio source file, thereby controlling the influence of near-end Bluetooth radio frequency interference sources on the Bluetooth headset. The Bluetooth headset amplifier also includes a shielding layer structure to directionally block and reflect near-end radio frequency radiation interference to the Bluetooth headset.

[0005] This invention includes a file acquisition module that directly acquires the audio file to be played through an interface. The audio file is pre-input into the DSP for standard waveform analysis, which can speed up processing and reduce latency during actual playback. Summary of the Invention

[0006] To address the aforementioned issues, this invention provides an amplifier with improved bias tracking performance based on a DSP chip, comprising: an input interface, a bias power amplifier module, and an output interface; further comprising a file acquisition module, a storage module, a current copying module, an analog-to-digital converter, a digital signal processor / DSP, a digital-to-analog converter, a low-pass filter, a current-to-voltage converter, and a current-to-voltage control module;

[0007] The bias power amplifier module is connected to the input interface and the output interface respectively. The input interface is used to input signals, which are amplified by the bias amplifier and then output through the output interface.

[0008] The file acquisition module connects to the input interface, acquires the file to be played from the input interface, and stores the file to be played in the storage module; the storage module sends the file to be played to the DSP, and performs waveform analysis in the DSP to obtain standard waveform and standard voltage control data;

[0009] The current sampling module is connected to the bias power amplifier module and is used to replicate the proportional current of the output stage of the bias power amplifier module. The replicated current is then converted into a digital signal by the analog-to-digital converter module and input to the DSP.

[0010] The signal output from the analog-to-digital converter module is input into the DSP and compared with the standard waveform inside the DSP. The DSP outputs voltage control data based on the comparison result.

[0011] After the voltage control data is input to the digital-to-analog converter, it passes through a low-pass filter and enters the current-to-voltage converter to obtain the control current. The control current is input to the current-to-voltage control module to obtain the regulated voltage, which is then applied to the bias amplifier module along with the input signal.

[0012] The signal acquired by the DSP is model matched with the pre-established power amplifier bias model in 5 ms increments.

[0013] The sampling rate of the analog-to-digital converter and the digital-to-analog converter is 100kSPS.

[0014] Waveform analysis within a DSP includes the following steps:

[0015] The DSP storage module sends the audio file to the DSP in segments, with each segment being 20-40 seconds long. The DSP performs waveform analysis on the audio segments to obtain the waveform amplitude variation curve over time. It further calculates the waveform energy variation curve over time to obtain the standard energy curve, i.e., the standard waveform curve.

[0016] The DSP inputs the standard energy curve into the overload identification model and the compensation model to obtain standard voltage control data;

[0017] The overload identification model is used to detect whether there is an overload trend and to implement corresponding control, while the compensation model is used to detect whether the power amplifier is about to exceed the bias linear range and to apply corresponding control.

[0018] If there is an overload trend, the corresponding output voltage control data will shut down the final stage of the power amplifier. If it exceeds the bias linear region, the voltage control data will be used to compensate for overfitting of the bias power amplifier module, so that the power amplification stage of the bias power amplifier is always in the high linear region.

[0019] The signal output from the analog-to-digital converter module is input into the DSP and compared with the standard waveform curve in the DSP. Before the comparison, the energy curve of the signal output from the analog-to-digital converter module is calculated in the DSP.

[0020] If the deviation of the comparison result is less than the threshold, the DSP directly outputs the standard voltage control data; if the deviation of the comparison result is greater than the threshold, the voltage control data obtained by directly inputting the overload identification model and compensation model from the analog-to-digital conversion module is output in real time.

[0021] The working process of the overload recognition model is as follows:

[0022] The digital signal input to the DSP undergoes time-domain to frequency-domain transformation at fixed time intervals, using either Fourier transform or wavelet transform. The frequency-domain signal is used to calculate waveform energy in real time, and the waveform energy is compared with an energy threshold. If the waveform energy exceeds the energy threshold, the DSP controls the power amplifier's final stage to shut down.

[0023] The energy threshold is a curve that varies with frequency, that is, the energy threshold G is a function G(f), where f represents the frequency of the signal; the waveform energy calculated in real time is also a curve that varies with frequency. The energy of signals at different frequencies is different, and the waveform energy H is a function H(f).

[0024] Calculate Y(f) = H(f) - G(f). When any value of Y(f) > 0 occurs, the DSP controls the shutdown of the final stage of the power amplifier.

[0025] The working process of the compensation model is as follows:

[0026] The digital signal input to the DSP undergoes time-domain to frequency-domain transformation at fixed time intervals, using either Fourier transform or wavelet transform. The DSP then extracts features from the frequency-domain signal, including the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of energy values ​​M of the characteristic frequency band. The characteristic frequency band is a pre-set frequency range.

[0027] The DSP inputs the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the total energy value M of the characteristic frequency band as parameters into the neural network model to obtain voltage control data.

[0028] The training method for neural network models is as follows:

[0029] Install a power amplifier with the same structure as the one used in actual applications in the laboratory and control it to work, the difference being that the voltage control data output by the DSP is set to random numbers;

[0030] The digital signal input to the DSP is transformed from the time domain to the frequency domain at fixed time intervals. The transformation method is Fourier transform or wavelet transform. The DSP extracts features from the frequency domain signal. The extracted features include the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of energy values ​​M of the characteristic frequency band.

[0031] The system monitors the time period during which the power amplifier exceeds the bias linear range and then returns to the linear range, and extracts the data within this time period. The extracted data includes the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, the total energy value M of the characteristic frequency band, and the corresponding voltage control data.

[0032] The neural network model is constructed by taking the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of the energy values ​​of the characteristic frequency bands M as inputs, and the corresponding voltage control data as outputs; the type of neural network model is a convolutional neural network model.

[0033] The current replication module includes a circuit that performs current-to-voltage conversion and low-pass filtering simultaneously. It converts the current signal into a voltage signal and performs low-pass filtering at the same time. The purpose of low-pass filtering is to remove out-of-band interference.

[0034] Q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6, and R8 constitute the proportional current replicator of the power output stage;

[0035] Q1, Q2, Q3, and Q5 are PNP transistors, Q7 and Q8 are NPN transistors, and R1, R2, R5, R6, and R8 are resistors. One end of R1, R2, and R5 is connected to Vcc, the other end of R1 is connected to the emitter of Q1, the other end of R2 is connected to the emitter of Q2, and the other end of R5 is connected to the emitter of Q3 and the base of Q5. The emitter of Q5 is connected to Vcc, and the collector of Q5 is connected to the base of Q3 and then grounded through R6.

[0036] The collector and base of Q1 are connected to the collector of Q7. The emitter of Q7 is connected to the emitter of Q6. The base of Q7 is connected to the base and collector of Q8, as well as the collector of Q3. The collector of Q2 is connected to one end of R9 and the negative terminal of OP-1. The other end of R9 is connected to the positive terminal of OP-1. R7, OP-1 and C1 are connected in parallel. The output of OP-1 is sent to the analog-to-digital converter.

[0037] The DSP chip uses a multi-core high-performance DSP chip to improve the data processing capability of the DSP chip. R7, OP-1 and C1 are connected in parallel to form a circuit that converts current to voltage and performs low-pass filtering at the same time. The purpose of low-pass filtering is to remove out-of-band interference.

[0038] The beneficial effects of this invention are as follows:

[0039] This invention includes a file acquisition module that directly acquires the audio file to be played through an interface. The audio file is pre-input into the DSP for standard waveform analysis, which can speed up processing and reduce latency during actual playback. During actual playback, the actual playback energy is compared with the pre-calculated energy to determine whether it meets the pre-designed output. If it does, the pre-designed output is used directly; otherwise, it is further input into the model for processing, ensuring the stability and safety of the operation.

[0040] The ADC of this invention converts the measured analog voltage into digital data and sends it to the DSP. To ensure the tracking performance of the control and the real-time performance of the protection, the ADC sampling rate is 100KSPS. The signal acquired by the DSP is compared with the standard waveform in 5ms increments to detect whether it meets the expectations. If it does not meet the expectations, it further detects whether there is an overload trend and whether the power amplifier is about to exceed the bias linear range, thereby determining whether to adjust the power amplifier bias, reduce delay, reduce fixed bias current, reduce power consumption, and protect the equipment. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Appendix Figure 1 This is a schematic diagram of the overall architecture of the present invention;

[0043] Appendix Figure 2 This is a circuit structure diagram of the present invention.

[0044] Where Q represents a transistor and R represents a resistor; Q4, Q6 and R3, R4 form the output stage of the power amplifier; Q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6 and R8 constitute the proportional current replicator of the power output stage; R7, OP-1 complete the current-to-voltage conversion, and C1 and R7 form a low-pass filter to remove out-of-band interference. Detailed Implementation

[0045] Example 1:

[0046] See Figure 1 The present invention provides an amplifier based on a DSP chip to improve bias following performance, comprising: an input interface, a bias power amplifier module, and an output interface; and further comprising a file acquisition module, a storage module, a current copying module, an analog-to-digital converter, a digital signal processor / DSP, a digital-to-analog converter, a low-pass filter, a current-to-voltage converter, and a current-to-voltage control module;

[0047] The bias power amplifier module is connected to the input interface and the output interface respectively. The input interface is used to input signals, which are amplified by the bias amplifier and then output through the output interface.

[0048] The file acquisition module connects to the input interface, acquires the file to be played from the input interface, and stores the file to be played in the storage module; the storage module sends the file to be played to the DSP, and performs waveform analysis in the DSP to obtain standard waveform and standard voltage control data;

[0049] The current sampling module is connected to the bias power amplifier module and is used to replicate the proportional current of the output stage of the bias power amplifier module. The replicated current is then converted into a digital signal by the analog-to-digital converter module and input to the DSP.

[0050] The signal output from the analog-to-digital converter module is input into the DSP and compared with the standard waveform inside the DSP. The DSP outputs voltage control data based on the comparison result.

[0051] After the voltage control data is input to the digital-to-analog converter, it passes through a low-pass filter and enters the current-to-voltage converter to obtain the control current. The control current is input to the current-to-voltage control module to obtain the regulated voltage, which is then applied to the bias amplifier module along with the input signal.

[0052] The signal acquired by the DSP is model matched with the pre-established power amplifier bias model in 5 ms increments.

[0053] The sampling rate of the analog-to-digital converter and the digital-to-analog converter is 100kSPS.

[0054] Waveform analysis within a DSP includes the following steps:

[0055] The DSP storage module sends the audio file to the DSP in segments, with each segment being 20-40 seconds long. The DSP performs waveform analysis on the audio segments to obtain the waveform amplitude variation curve over time. It further calculates the waveform energy variation curve over time to obtain the standard energy curve, i.e., the standard waveform curve.

[0056] The DSP inputs the standard energy curve into the overload identification model and the compensation model to obtain standard voltage control data;

[0057] The overload identification model is used to detect whether there is an overload trend and to implement corresponding control, while the compensation model is used to detect whether the power amplifier is about to exceed the bias linear range and to apply corresponding control.

[0058] If there is an overload trend, the corresponding output voltage control data will shut down the final stage of the power amplifier. If it exceeds the bias linear region, the voltage control data will be used to compensate for overfitting of the bias power amplifier module, so that the power amplification stage of the bias power amplifier is always in the high linear region.

[0059] The signal output from the analog-to-digital converter module is input into the DSP and compared with the standard waveform curve in the DSP. Before the comparison, the energy curve of the signal output from the analog-to-digital converter module is calculated in the DSP.

[0060] If the deviation of the comparison result is less than the threshold, the DSP directly outputs the standard voltage control data; if the deviation of the comparison result is greater than the threshold, the voltage control data obtained by directly inputting the overload identification model and compensation model from the analog-to-digital conversion module is output in real time.

[0061] The working process of the overload recognition model is as follows:

[0062] The digital signal input to the DSP undergoes time-domain to frequency-domain transformation at fixed time intervals, using either Fourier transform or wavelet transform. The frequency-domain signal is used to calculate waveform energy in real time, and the waveform energy is compared with an energy threshold. If the waveform energy exceeds the energy threshold, the DSP controls the power amplifier's final stage to shut down.

[0063] The energy threshold is a curve that varies with frequency, that is, the energy threshold G is a function G(f), where f represents the frequency of the signal; the waveform energy calculated in real time is also a curve that varies with frequency. The energy of signals at different frequencies is different, and the waveform energy H is a function H(f).

[0064] Calculate Y(f) = H(f) - G(f). When any value of Y(f) > 0 occurs, the DSP controls the shutdown of the final stage of the power amplifier.

[0065] The working process of the compensation model is as follows:

[0066] The digital signal input to the DSP undergoes time-domain to frequency-domain transformation at fixed time intervals, using either Fourier transform or wavelet transform. The DSP then extracts features from the frequency-domain signal, including the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of energy values ​​M of the characteristic frequency band. The characteristic frequency band is a pre-set frequency range.

[0067] The DSP inputs the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the total energy value M of the characteristic frequency band as parameters into the neural network model to obtain voltage control data.

[0068] The training method for neural network models is as follows:

[0069] Install a power amplifier with the same structure as the one used in actual applications in the laboratory and control it to work, the difference being that the voltage control data output by the DSP is set to random numbers;

[0070] The digital signal input to the DSP is transformed from the time domain to the frequency domain at fixed time intervals. The transformation method is Fourier transform or wavelet transform. The DSP extracts features from the frequency domain signal. The extracted features include the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of energy values ​​M of the characteristic frequency band.

[0071] The system monitors the time period during which the power amplifier exceeds the bias linear range and then returns to the linear range, and extracts the data within this time period. The extracted data includes the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, the total energy value M of the characteristic frequency band, and the corresponding voltage control data.

[0072] The neural network model is constructed by taking the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of the energy values ​​of the characteristic frequency bands M as inputs, and the corresponding voltage control data as outputs; the type of neural network model is a convolutional neural network model.

[0073] Furthermore, in this invention, the comparison between the input DSP signal and the standard waveform is performed using time stamps. That is, time stamps are set on the standard waveform, and the comparison between the input DSP signal and the standard waveform only considers positions with the same time stamps, ensuring the accuracy of the comparison. The time stamp represents the playback time of the audio file from its start to the playback time.

[0074] Cutting the file before inputting it into the DSP can reduce the DSP's workload and improve processing efficiency; at the same time, the file acquisition module recognizes the file format. If it is an audio file, it is acquired directly; if it is a video or other format file, only the audio track data is acquired.

[0075] The input interface is a Type-C interface, which can transmit both analog data and digital file data.

[0076] Example 2:

[0077] See Figure 2 The circuit structure diagram of the present invention is as follows:

[0078] The bias power amplifier module includes two resistors R3 and R4 connected in series, an NPN transistor Q6 and a PNP transistor Q4; the bases of both the NPN transistor Q6 and the PNP transistor Q4 are connected to drive the output; the emitters of the NPN transistor Q6 and the PNP transistor Q4 are connected between two resistors in series, and the output is located between the two resistors in series.

[0079] The collector of NPN transistor Q6 is connected to vcc, and the base of PNP transistor Q4 is connected to vee.

[0080] Q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6, and R8 constitute the proportional current replicator of the power output stage.

[0081] R7, OP-1, and C1 connected in parallel form a circuit that performs current-to-voltage conversion and low-pass filtering simultaneously. This circuit converts the current signal into a voltage signal and performs low-pass filtering at the same time. The purpose of low-pass filtering is to remove out-of-band interference.

[0082] Q1, Q2, Q3, and Q5 are PNP transistors, and Q7 and Q8 are NPN transistors. One end of R1, R2, and R5 is connected to Vcc. The other end of R1 is connected to the emitter of Q1, the other end of R2 is connected to the emitter of Q2, and the other end of R5 is connected to the emitter of Q3 and the base of Q5. The emitter of Q5 is connected to Vcc, and the collector of Q5 is connected to the base of Q3 and then grounded through R6.

[0083] The collector and base of Q1 are connected to the collector of Q7. The emitter of Q7 is connected to the emitter of Q6. The base of Q7 is connected to the base and collector of Q8, as well as the collector of Q3. The collector of Q2 is connected to one end of R9 and the negative terminal of OP-1. The other end of R9 is connected to the positive terminal of OP-1. R7, OP-1, and C1 are connected in parallel. The output of OP-1 is sent to a high-speed ADC, i.e., an analog-to-digital converter.

[0084] Thus far, the description of the above embodiments has been provided for illustrative and descriptive purposes. This is not intended to be exhaustive or limiting of the present disclosure. Individual elements or features of particular embodiments are generally not limited to those particular embodiments, but may be interchanged and used in selected embodiments where applicable, even if not specifically shown or described. In many respects, the same elements or features may also be varied. Such variations are not considered a departure from this disclosure, and all such modifications are intended to be included within the scope of this disclosure.

[0085] Example embodiments are provided so that this disclosure will become thorough and will fully convey the scope to those skilled in the art. Numerous details, such as examples of specific parts, apparatus, and methods, are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that the specific details are not required, and the example embodiments may be implemented in many different forms, neither of which should be construed as limiting the scope of this disclosure. In some example embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.

[0086] Technical terms are used herein for the purpose of describing specific exemplary embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a” and “the” as used herein may also refer to the plural forms. The terms “comprising” and “having” are inclusive and therefore specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or additional having of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Unless expressly indicated in order of execution, the method steps, processes, and operations described herein are not to be construed as necessarily requiring performance in the specific order discussed and shown. It should also be understood that additional or optional steps may be employed.

Claims

1. An amplifier based on a DSP chip to improve bias follower performance, comprising: The system includes an input interface, a bias power amplifier module, and an output interface; its features include: a file acquisition module, a storage module, a current copying module, an analog-to-digital converter, a DSP, a digital-to-analog converter, a low-pass filter, a current-to-voltage converter, and a current-to-voltage control module. The bias power amplifier module is connected to the input interface and the output interface respectively. The input interface is used to input signals, which are amplified by the bias amplifier and then output through the output interface. The file acquisition module connects to the input interface, acquires the file to be played from the input interface, and stores the file to be played in the storage module; the storage module sends the file to be played to the DSP, and performs waveform analysis in the DSP to obtain standard waveform and standard voltage control data; The current replication module is connected to the bias power amplifier module and is used to replicate the proportional current of the output stage of the bias power amplifier module. The replicated current is then converted into a digital signal by the analog-to-digital converter module and input to the DSP. The signal output from the analog-to-digital converter module is input into the DSP and compared with the standard waveform inside the DSP. The DSP outputs voltage control data based on the comparison result. After the voltage control data is input to the digital-to-analog converter, it passes through a low-pass filter and enters the current-to-voltage converter to obtain the control current. The control current is input to the current-to-voltage control module to obtain the regulated voltage, which is then applied to the bias amplifier module along with the input signal.

2. The amplifier with improved bias following performance based on a DSP chip according to claim 1, characterized in that: The signal acquired by the DSP is model matched with the pre-established power amplifier bias model in 5 ms increments.

3. The amplifier with improved bias tracking based on a DSP chip according to claim 1, characterized in that: The sampling rate of the analog-to-digital converter and the digital-to-analog converter is 100kSPS.

4. The amplifier with improved bias following performance based on a DSP chip according to claim 1, characterized in that: Waveform analysis within a DSP includes the following steps: The DSP storage module sends the audio file to the DSP in segments, with each segment being 20-40 seconds long. The DSP performs waveform analysis on the audio segments to obtain the waveform amplitude variation curve over time. It further calculates the waveform energy variation curve over time to obtain the standard energy curve, i.e., the standard waveform curve. The DSP inputs the standard energy curve into the overload identification model and the compensation model to obtain standard voltage control data; The overload identification model is used to detect whether there is an overload trend and to implement corresponding control, while the compensation model is used to detect whether the power amplifier is about to exceed the bias linear range and to apply corresponding control. If there is an overload trend, the corresponding output voltage control data will shut down the final stage of the power amplifier. If it exceeds the bias linear region, the voltage control data will be used to compensate for overfitting of the bias power amplifier module, so that the power amplification stage of the bias power amplifier is always in the high linear region.

5. The amplifier with improved bias tracking based on a DSP chip according to claim 4, characterized in that: The signal output from the analog-to-digital converter module is input into the DSP and compared with the standard waveform curve in the DSP. Before the comparison, the energy curve of the signal output from the analog-to-digital converter module is calculated in the DSP. If the deviation of the comparison result is less than the threshold, the DSP directly outputs the standard voltage control data; If the deviation of the comparison result is greater than the threshold, the voltage control data obtained from the direct input overload identification model and compensation model of the analog-to-digital conversion module that exceeds the threshold will be output in real time.

6. The amplifier with improved bias tracking based on a DSP chip according to claim 5, characterized in that: The working process of the overload recognition model is as follows: The digital signal input to the DSP undergoes time-domain to frequency-domain transformation at fixed time intervals, using either Fourier transform or wavelet transform. The frequency-domain signal is used to calculate waveform energy in real time, and the waveform energy is compared with an energy threshold. If the waveform energy exceeds the energy threshold, the DSP controls the power amplifier's final stage to shut down. The energy threshold is a curve that varies with frequency, that is, the energy threshold G is a function G(f), where f represents the frequency of the signal; the waveform energy calculated in real time is also a curve that varies with frequency. The energy of signals at different frequencies is different, and the waveform energy H is a function H(f). Calculate Y(f) = H(f) - G(f). When any value of Y(f) > 0 occurs, the DSP controls the shutdown of the final stage of the power amplifier. The working process of the compensation model is as follows: The digital signal input to the DSP is transformed from the time domain to the frequency domain at fixed time intervals. The transformation method is Fourier transform or wavelet transform. The DSP extracts features from the frequency domain signal. The extracted features include the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of energy values ​​M of the characteristic frequency band. The characteristic frequency band is a pre-set frequency range; The DSP inputs the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of the energy values ​​of the characteristic frequency bands M into the neural network model to obtain voltage control data.

7. The amplifier with improved bias tracking based on a DSP chip according to claim 6, characterized in that: The training method for neural network models is as follows: Install a power amplifier with the same structure as the one used in actual applications in the laboratory and control it to work, the difference being that the voltage control data output by the DSP is set to random numbers; The digital signal input to the DSP is transformed from the time domain to the frequency domain at fixed time intervals. The transformation method is Fourier transform or wavelet transform. The DSP extracts features from the frequency domain signal. The extracted features include the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of energy values ​​M of the characteristic frequency band. The system monitors the time period during which the power amplifier exceeds the bias linear range and then returns to the linear range, and extracts the data within this time period. The extracted data includes the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, the total energy value M of the characteristic frequency band, and the corresponding voltage control data. The neural network model is constructed by taking the graph of the frequency domain signal, the strongest frequency Fmax, the peak height Pmax corresponding to Fmax, the full width at half maximum (Wmax) corresponding to Fmax, and the sum of the energy values ​​of the characteristic frequency bands M as inputs, and the corresponding voltage control data as outputs; the type of neural network model is a convolutional neural network model.

8. The amplifier with improved bias follower performance based on a DSP chip according to claim 1, characterized in that: The current replication module includes a circuit that performs current-to-voltage conversion and low-pass filtering simultaneously. It converts the current signal into a voltage signal and performs low-pass filtering at the same time. The purpose of low-pass filtering is to remove out-of-band interference.

9. The amplifier with improved bias tracking based on a DSP chip according to claim 8, characterized in that: Q1, Q2, Q3, Q5, Q7, Q8, R1, R2, R5, R6, and R8 constitute the proportional current replicator of the power output stage; Q1, Q2, Q3, and Q5 are PNP transistors, Q7 and Q8 are NPN transistors, and R1, R2, R5, R6, and R8 are resistors. One end of R1, R2, and R5 is connected to Vcc, the other end of R1 is connected to the emitter of Q1, the other end of R2 is connected to the emitter of Q2, and the other end of R5 is connected to the emitter of Q3 and the base of Q5. The emitter of Q5 is connected to Vcc, and the collector of Q5 is connected to the base of Q3 and then grounded through R6. The collector and base of Q1 are connected to the collector of Q7. The emitter of Q7 is connected to the emitter of Q6. The base of Q7 is connected to the base and collector of Q8, as well as the collector of Q3. The collector of Q2 is connected to one end of R9 and the negative terminal of OP-1. The other end of R9 is connected to the positive terminal of OP-1. R7, OP-1 and C1 are connected in parallel. The output of OP-1 is sent to the analog-to-digital converter.

10. The amplifier based on a DSP chip to improve bias following performance according to claim 8, characterized in that: The DSP chip uses a multi-core high-performance DSP chip to improve the data processing capability of the DSP chip. R7, OP-1 and C1 are connected in parallel to form a circuit that converts current to voltage and performs low-pass filtering at the same time. The purpose of low-pass filtering is to remove out-of-band interference.

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