A convolutional code generation device, method, communication device and computing device

Abstract

The embodiment of the present invention provides a convolutional code generation device, method, communication device and computing device, and the technical solution thereof includes: configuring a generator polynomial for each convolution branch, and each convolution branch performs convolution according to the configured generator polynomial. The embodiment of the present invention can be used to generate a convolutional code (n, k, m) of any algorithm, and is suitable for the generation of convolutional codes for channels with various characteristics and / or code streams with various characteristics.

Description

Technical Field

[0001] The present invention relates to the field of wireless communications, and in particular to a convolutional code generation device, method, communication equipment and computing equipment. Background Art

[0002] The TBCC convolutional code protocol defined by 3GPP 36.212 uses the protocol-defined generator polynomial and interleaving matrix for convolutional coding. The maximum code rate of the convolutional code defined by the protocol is 1 / 3. The bit stream to be coded needs to be coded in three branches. Three branches require three different generator polynomials. After the coding is completed, sub-block interleaving is performed. The interleaving scheme of each sub-block is uniformly defined by the protocol.

[0003] In the prior art, when implementing the TBCC convolutional code protocol defined in 3GPP 36.212, the generator polynomial of the encoder of the convolutional code of each branch is fixed, and the number of columns interleaved in the block interleaver is also fixed. This fixed implementation method cannot realize the generation of convolutional codes in any form. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a convolutional code generation device, method, communication device and computing device, configure the generator polynomial of each convolution branch, and each convolution branch performs convolution according to the configured generator polynomial. The embodiments of the present invention can be used to generate any convolutional code (n, k, m), which is suitable for convolutional code generation of various channels and various code streams to be encoded.

[0005] In a first aspect, an embodiment of the present invention provides a convolutional code generation device for generating a convolutional code (n, k, m), where n and k represent that n convolutional code bits are output for every k bits to be encoded, and m+1 represents the constraint width of the convolutional code. The device includes: a configuration module, a convolution module, an interleaving module and a merging module, wherein each convolution module and its one-to-one corresponding interleaving module constitute a convolution branch; the configuration module is used to configure the generating polynomial of each convolution branch according to the characteristics of the wireless channel and / or the characteristics of the code stream to be encoded; the convolution module is used to convolve the bit stream to be encoded according to the generating polynomial of each convolution branch, respectively, to generate a first convolution bit stream of each convolution branch; the interleaving module is used to interleave the first convolution bit stream of the convolution branch according to the agreed number of interleaving columns, to generate a second convolution bit stream of the convolution branch; the merging module is used to merge the second convolution bit streams of each convolution branch through parallel-to-serial conversion to obtain the bit stream of the convolution code.

[0006] From the above, by configuring the generating polynomial of each convolution branch, each convolution branch performs convolution according to the configured generating polynomial. The technical solution of the present invention can be used to generate any convolution code (n, k, m), using various channels and various code streams to be encoded.

[0007] In a possible implementation of the first aspect, the configuration module is further used to configure the number of interleaving columns of the interleaving module of each convolution branch.

[0008] From the above, the number of interleaving columns of each interleaving module is configured to suit different fast fading scenarios.

[0009] In a possible implementation of the first aspect, each convolution module includes a sliding window, an out-of-window node and an XOR module; the sliding window is used to input the bit stream to be encoded in time sequence, and the width of the sliding window is (m+1)*k; each out-of-window node corresponds to the bit to be encoded in the sliding window one by one, and the node value of each out-of-window node is set to 0 or 1 according to the generating polynomial of the convolution branch in which it is located; the XOR module is used to put the node value of each out-of-window node and the product of the corresponding bit to be encoded in the current sliding window together to calculate the XOR, and obtain the first convolution bit of the convolution branch, wherein, after each first convolution bit is obtained, the bit stream to be encoded is rolled forward k bits and input into the sliding window, and the first convolution bit at each time constitutes the first bit stream.

[0010] From the above, in the convolution module, by storing the sliding window of the bits to be encoded and associating the sliding window with the nodes outside the window that store the bits to be encoded, the convolution algorithm corresponding to any generating polynomial can be implemented.

[0011] In a possible implementation of the first aspect, when used to generate the TBCC code of 4G, the generating polynomial of each convolution branch is obtained from the 3GPP 36.212 protocol.

[0012] From the above, the device of the present invention can be used to generate 4G TBCC codes.

[0013] In a second aspect, an embodiment of the present invention provides a convolutional code generation method for generating a convolutional code (n, k, m), wherein n and k represent the output of n convolutional code bits for every k bits to be encoded, and m+1 represents the constraint width of the convolutional code. The method comprises: configuring a generating polynomial for each convolution branch according to characteristics of a wireless channel and / or characteristics of a code stream to be encoded; convolving the bit stream to be encoded according to the generating polynomial of each convolution branch to generate a first convolution bit stream for each convolution branch; interleaving the first convolution bit stream of each convolution branch according to an agreed number of interleaving columns to generate a second convolution bit stream for each convolution branch; and merging the second convolution bit streams of each convolution branch through parallel-to-serial conversion to obtain a bit stream of the convolution code.

[0014] From the above, by configuring the generating polynomial of each convolution branch, each convolution branch performs convolution according to the configured generating polynomial. The technical solution of the present invention can be used to generate any convolution code (n, k, m), using various channels and various code streams to be encoded.

[0015] In a possible implementation of the second aspect, it also includes: configuring the number of interleaved columns corresponding to the first convolution bit stream of each convolution branch according to characteristics of the wireless channel.

[0016] From the above, the number of interleaving columns of each interleaving module is configured to suit different fast fading scenarios.

[0017] In a possible implementation of the second aspect, the bit stream to be encoded is convolved according to the generating polynomial of each convolution branch to generate the first convolution bit stream of each convolution branch, including: setting a sliding window with a width of (m+1)*k, for inputting the bit stream composed of the input code to be encoded in chronological order; setting each out-of-window node of each convolution branch corresponding to the bit to be encoded in the sliding window, and the node value of each out-of-window node of a convolution branch is set to 0 or 1 according to the generating polynomial of the convolution branch; putting the node value of each out-of-window node of each convolution branch and the product of the corresponding bit to be encoded in the current sliding window together for XOR, and obtaining the current first convolution bit in the first convolution bit stream of each convolution branch, wherein after each first convolution bit is obtained, the bit stream to be encoded is rolled forward by k bits and input into the sliding window, and the first convolution bits at each time constitute the first bit stream.

[0018] From the above, by storing the sliding window of the to-be-coded bits and associating the sliding window with the nodes outside the window that store the to-be-coded bits, a convolution algorithm corresponding to any generating polynomial can be implemented.

[0019] In a possible implementation of the second aspect, when used to generate the TBCC code of 4G, the generating polynomial of each convolution branch is obtained from the 3GPP 36.212 protocol.

[0020] From the above, the method of the present invention can be used to generate 4G TBCC codes.

[0021] In a third aspect, an embodiment of the present invention also provides a communication device, including: the device described in any implementation manner of the first aspect.

[0022] In a fourth aspect, an embodiment of the present invention further provides a computing device, comprising:

[0023] bus;

[0024] A communication interface connected to the bus;

[0025] at least one processor connected to the bus; and

[0026] At least one memory is connected to the bus and stores program instructions, and when the program instructions are executed by the at least one processor, the at least one processor executes any implementation of the second aspect of the present invention.

[0027] In a fifth aspect, an embodiment of the present invention further provides a computer-readable storage medium having program instructions stored thereon, wherein when the program instructions are executed by a computer, the computer executes any implementation method described in the second aspect of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of a convolutional code generating device in the prior art;

[0029] Figure 2 It is a structural schematic diagram of a convolutional code generation device according to a first embodiment of the present invention;

[0030] Figure 3 It is a structural schematic diagram of a second embodiment of a convolutional code generating device of the present invention;

[0031] Figure 4 It is a structural schematic diagram of a convolution module of a second embodiment of a convolutional code generation device;

[0032] Figure 5 A schematic diagram of a flow chart of a first embodiment of a convolutional code generation method of the present invention;

[0033] Figure 6 Schematic diagram of a flow chart of a second embodiment of a convolutional code generation method of the present invention;

[0034] Figure 7 A detailed flow chart of a convolution method for each convolution branch in Embodiment 2 of a convolutional code generation method of the present invention;

[0035] Figure 8 A schematic diagram of the structure of a computing device according to various embodiments of the present invention. DETAILED DESCRIPTION

[0036] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] In the following description, the terms "first\second\third, etc." or module A, module B, module C, etc. are only used to distinguish similar objects, or to distinguish different embodiments, and do not represent a specific ordering of the objects. It can be understood that the specific order or sequence can be interchanged where permitted, so that the embodiments of the present invention described here can be implemented in an order other than that illustrated or described here.

[0038] In the following description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps must be executed in this manner. If permitted, the order of the previous and next steps can be interchanged, or they can be executed simultaneously.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0040] The characteristics of a convolutional code are generally described by (n, k, m), where n and k represent that n convolutional code bits are output for every k bits to be encoded, and m+1 represents the constraint width of the convolutional code.

[0041] Figure 1 An existing convolutional code generation device is shown, including several convolution modules, several interleaving modules and a merging module. Each convolution module performs convolution according to a generating polynomial. The generating polynomial is fixed in each convolution module and cannot be configured, and the usage scenario is limited.

[0042] The embodiment of the present invention provides a convolutional code generation device, method, communication device and computing device, configures a generator polynomial for each convolution branch, and each convolution branch performs convolution according to the configured generator polynomial. The embodiment of the present invention can be used to generate any convolutional code (n, k, m), which is suitable for convolutional code generation of various channels and various code streams to be encoded.

[0043] The following describes various device embodiments of the present invention in conjunction with the accompanying drawings.

[0044] First, according to Figure 2 A first embodiment of a convolutional code generating device is introduced.

[0045] A convolutional code generation device embodiment 1 includes a configuration module, a convolution module, an interleaving module and a merging module, wherein the configuration module is used to configure the generator polynomial of each convolution branch; the convolution module is used to convolve the bit stream to be encoded according to the configured generator polynomial of each convolution branch to generate the first convolution bit stream of each convolution branch; the interleaving module is used to interleave the first convolution bit stream of each convolution branch to generate the second convolution bit stream of each convolution branch; the merging module is used to merge the second convolution bit stream of each convolution branch to generate the final convolution code bit stream. This device embodiment can be used to generate any convolution code (n, k, m), which is suitable for the generation of convolution codes for various channels and various code streams to be encoded.

[0046] Figure 2The structure of a first embodiment of a convolutional code generating device is shown, which is used to generate a convolutional code (n, k, m), including: a configuration module 110, n convolution modules 120, n interleaving modules 130 and a merging module 140, each convolution module 120 and its one-to-one corresponding interleaving module 130 form a convolution branch, and the number of convolution branches is n.

[0047] The configuration module 110 is used to configure the generator polynomial of each convolution branch according to the characteristics of the wireless channel and / or the characteristics of the code stream to be encoded.

[0048] Among them, convolutional codes are used to increase the anti-interference capability of the communication system. Different generating polynomials are used for different wireless channel characteristics, and different generating polynomials are also used for different code stream characteristics to be encoded.

[0049] Any convolution module 120 is used to convolve the bit stream to be encoded according to the generating polynomial of the convolution branch to generate the first convolution bit stream of the convolution branch.

[0050] Among them, each first convolution bit is obtained by convolution of k*(m+1) bits to be encoded. After obtaining the first convolution bit of the current time, the bit stream to be encoded is rolled forward by k bits to obtain the first convolution bit of the next time. The first convolution bits of each convolution branch at each time constitute the first convolution bit stream of the convolution branch. Then, combined with n convolution branches, that is, n convolution code bits are output for every k bits to be encoded.

[0051] Among them, the generating polynomial of each convolution branch determines the convolution method of each branch to meet the needs of different systems.

[0052] Any interleaving module 130 is used to interleave the first convolution bit stream of the convolution branch according to the agreed number of interleaving columns to generate the second convolution bit stream of the convolution branch.

[0053] In some embodiments, the agreed number of interleaving columns is a relatively fixed number of columns; in other embodiments, the configuration module 110 is further used to configure the agreed number of interleaving columns.

[0054] Among them, interleaving is used to improve the ability of the final generated convolutional code to resist fast fading. The more the agreed number of interleaving columns is, the stronger the ability to resist fast fading is, but the amount of calculation is also greater.

[0055] The merging module 140 is used to merge the second convolution bit streams of each convolution branch through parallel-to-serial conversion to obtain the bit stream of the convolution code.

[0056] Among them, the second convolution bit of each convolution branch is only one bit among the n convolution code bits. After merging, a convolution code with n code elements is obtained, and the convolution codes at different times constitute a convolution code stream.

[0057] When the device embodiment is used to generate the TBCC code of 4G, n=3, k=1, m=7, the generating polynomial of the 3 convolution branches is obtained from the 3GPP 36.212 protocol, and each data block of 4G is processed according to the tail biting method specified in the protocol before convolution.

[0058] In summary, a convolutional code generation device embodiment 1 configures a generator polynomial for each convolution branch, and each convolution branch performs convolution according to the configured generator polynomial. This device embodiment can be used for generating any convolutional code (n, k, m), using various channels and various code streams to be encoded.

[0059] According to the following Figure 3 A second embodiment of a convolutional code generating device is introduced.

[0060] A second embodiment of a convolutional code generating device inherits the structure of the first embodiment of a convolutional code generating device, and implements the convolution module in the convolution module by storing a sliding window for storing bits to be encoded and associating the sliding window with nodes outside the window for storing bits to be encoded, wherein the association method is generated according to the generating polynomial of the convolution branch, thereby realizing the convolution algorithm corresponding to any generating polynomial, and also configuring the number of interleaving columns of each interleaving module in the configuration module to suit different fast fading scenarios.

[0061] Figure 3 The structure of a second embodiment of a convolutional code generating device is shown, which is used to generate a convolutional code (n, k, m), including: a configuration module 210, n convolution modules 220, n interleaving modules 230 and a merging module 240, each convolution module 220 and its one-to-one corresponding interleaving module 230 form a convolution branch, and the number of convolution branches is n.

[0062] The configuration module 210 is used to configure the generator polynomial and the number of interleaving columns of each module convolution branch.

[0063] Among them, the configuration module 210 is based on the configuration module 110 of the first embodiment of a convolutional code generation device, and increases the number of interleaving columns of each convolution branch according to the characteristics of the wireless channel, so as to control the amount of interleaving operations on the basis of meeting the ability to resist fast fading.

[0064] Each convolution module 220 is used to adopt a universal structure to convolve the bit stream to be encoded according to the generating polynomial of the convolution branch to generate the first convolution bit stream of the convolution branch.

[0065] The universal structure refers to the structure of the convolution module 120 in the second embodiment of a convolutional code generating device described later, which is suitable for using a convolution algorithm corresponding to any generating polynomial.

[0066] Each interleaving module 230 is used to interleave the first convolution bit stream of the convolution branch according to the configured number of interleaving columns to generate the second convolution bit stream of the convolution branch.

[0067] Among them, the interleaving module 230 is based on the interleaving module 130 of the first embodiment of a convolutional code generation device, and adds interleaving according to the configured number of interleaving columns, so as to control the amount of interleaving operations on the basis of meeting the ability to resist fast fading.

[0068] The merging module 240 is used to merge the second convolution bit streams of each convolution branch through parallel-to-serial conversion to obtain the bit stream of the convolution code.

[0069] The principle and advantages of the merging module 240 may refer to the merging module 140 in the first embodiment of a convolutional code generating device.

[0070] Figure 4 The structure of a convolution module 220 of a second embodiment of a convolutional code generating device is shown, including a sliding window 2210, a configuration node 2220 and an XOR module 2230.

[0071] The sliding window 2210 is used to input the bit stream to be encoded in time sequence. For generating convolutional code (n, k, m), the width of the sliding window is (m+1)*k. After each convolution, the bit stream to be encoded is rolled forward k bits and input into the sliding window 2210.

[0072] The configuration node 2220 includes several out-of-window nodes, each of which corresponds one-to-one to a bit to be encoded in the sliding window, and the node value of each out-of-window node is set to 0 or 1 according to the generating polynomial of the convolution branch in which it is located.

[0073] Among them, the width of the sliding window is (m+1)*k, and the number of nodes outside the window is also (m+1)*k.

[0074] The XOR module 2230 is used to XOR the product of the node value of each node outside the window and the corresponding bit to be encoded in the current sliding window to obtain the current first convolution bit in the first convolution bit stream of the convolution branch, and the first convolution bits at each time constitute the first bit stream.

[0075] As described above, the convolution module of the second embodiment of a convolutional code generation device adopts a structure including a sliding window, a configuration node and an XOR module, and is suitable for using a convolution algorithm corresponding to any generating polynomial.

[0076] In summary, a second embodiment of a convolutional code generating device inherits the structure of a first embodiment of a convolutional code generating device, and implements a convolution algorithm corresponding to an arbitrary generating polynomial in a convolution module by storing a sliding window for storing bits to be encoded and associating the sliding window with nodes outside the window for storing bits to be encoded, and also configures the number of interleaving columns of each interleaving module in a configuration module to suit different fast fading scenarios.

[0077] A convolutional code generation method embodiment 1 uses a convolutional code generation device embodiment 1 to perform convolution to generate a convolutional code (n, k, m).

[0078] Figure 5 A process of a convolutional code generation method is shown, including steps S410 to S440.

[0079] S410: configuring each generator polynomial of the convolutional code according to the characteristics of the wireless channel, configuring n generator polynomials in total, corresponding to n convolution branches.

[0080] Among them, convolutional codes are used to increase the anti-interference capability of the communication system. Different generating polynomials are used for different wireless channel characteristics, and different generating polynomials are also used for different code stream characteristics to be encoded.

[0081] S420: Convolve the bit stream to be encoded in time sequence according to the generating polynomial of each convolution branch to generate a first convolution bit stream of each convolution branch.

[0082] Among them, each first convolution bit is obtained by convolution of k*(m+1) bits to be encoded. After obtaining the first convolution bit of the current time, the bit stream to be encoded is rolled forward by k bits to obtain the first convolution bit of the next time. The first convolution bits of each convolution branch at each time constitute the first convolution bit stream of the convolution branch. Then, combined with n convolution branches, that is, n convolution code bits are output for every k bits to be encoded.

[0083] S430: Interleave the first convolution bit stream of each convolution branch according to the agreed number of interleaving columns to generate the second convolution bit stream of each convolution branch.

[0084] In some embodiments, the agreed number of interleaving columns is a relatively fixed number of columns; in other embodiments, S410 further configures the agreed number of interleaving columns according to the characteristics of the wireless channel.

[0085] Among them, interleaving is used to improve the ability of the final generated convolutional code to resist fast fading. The more the agreed number of interleaving columns is, the stronger the ability to resist fast fading is, but the amount of calculation is also greater.

[0086] S440: The second convolution bit streams of each convolution branch are combined by parallel-to-serial conversion to obtain a bit stream of the convolution code.

[0087] Among them, the second convolution bit of each convolution branch is only one bit among the n convolution code bits. After merging, a convolution code with n code elements is obtained, and the convolution codes at different times constitute a convolution code stream.

[0088] When the device embodiment is used to generate the TBCC code of 4G, n=3, k=1, m=7, the generating polynomial of the 3 convolution branches is obtained from the 3GPP 36.212 protocol, and each data block of 4G is processed according to the tail biting method specified in the protocol before convolution.

[0089] In summary, a convolutional code generation method embodiment 1 configures a generator polynomial for each convolution branch, and each convolution branch performs convolution according to the configured generator polynomial. This method embodiment can be used for generating any convolutional code (n, k, m), using various channels and various code streams to be encoded.

[0090] A convolutional code generation method embodiment 2 uses a convolutional code generation device embodiment 2 to perform convolution to generate a convolutional code (n, k, m).

[0091] Figure 6 A process of a convolutional code generation method is shown, including steps S510 to S540.

[0092] S510: Configure the generating polynomial and the number of interleaving columns of each convolution branch according to the characteristics of the wireless channel, and configure n generating polynomials in total, corresponding to n convolution branches.

[0093] Among them, this step increases the number of interleaving columns of each convolution branch configured according to the characteristics of the wireless channel in step S410 of the first embodiment of a convolutional code generation method, thereby controlling the amount of interleaving operations on the basis of meeting the ability to resist fast fading.

[0094] S520: Convolve the bit stream to be encoded in time sequence according to the generating polynomial of each convolution branch to generate a first convolution bit stream of each convolution branch.

[0095] Among them. Each first convolution bit is obtained by convolving k*(m+1) bits to be encoded. After obtaining the first convolution bit of the current time, the bit stream to be encoded is rolled forward by k bits to obtain the first convolution bit of the next time. The first convolution bits of each convolution branch at each time constitute the first convolution bit stream of the convolution branch.

[0096] Figure 7 The detailed implementation process of convolution of each convolution branch, that is, the detailed process of step S520, is shown, including steps S5210 to S5230.

[0097] S5210: The bit stream to be encoded is input in time sequence. For generating a convolutional code (n, k, m), the width of the sliding window is (m+1)*k.

[0098] S5220: The node value of each out-of-window node is set to 0 or 1 according to the generating polynomial of the convolution branch in which it is located.

[0099] S5230: XOR the product of the node value of each node outside the window and the corresponding bit to be encoded in the current sliding window together to obtain the current first convolution bit in the first convolution bit stream of the convolution branch. The first convolution bits at each time constitute the first bit stream.

[0100] S530: Interleave the first convolution bit stream of each convolution branch according to the configured number of interleaving columns to generate the second convolution bit stream of each convolution branch.

[0101] Among them, this step increases the number of interleaving columns configured for each convolution branch in step S430 of the first embodiment of a convolutional code generation method for interleaving, thereby controlling the amount of interleaving operations on the basis of meeting the ability to resist fast fading.

[0102] S540: The second convolution bit streams of each convolution branch are combined by parallel-to-serial conversion to obtain a bit stream of the convolution code.

[0103] For the method and advantages of this step, please refer to step S440 of the first embodiment of a convolutional code generation method.

[0104] In summary, embodiment 2 of a convolutional code generation method implements a convolution algorithm corresponding to an arbitrary generating polynomial by storing a sliding window of bits to be encoded and associating the sliding window with nodes outside the window that store bits to be encoded, and the number of interleaving columns of each convolution branch during interleaving can be configured to suit different fast fading scenarios.

[0105] The embodiment of the present invention also provides a communication device, including: a device described in Embodiment 1 of a convolutional code generating device or a device described in Embodiment 2 of a convolutional code generating device.

[0106] The communication device may be a terminal device in any form, or a site device in any form.

[0107] The embodiment of the present invention further provides a computing device, Figure 8 Detailed introduction.

[0108] The computing device 800 includes a processor 810 , a memory 820 , a communication interface 830 , and a bus 840 .

[0109] It should be understood that the communication interface 830 in the computing device 800 shown in this figure can be used to communicate with other devices.

[0110] The processor 810 may be connected to a memory 820. The memory 820 may be used to store the program code and data. Therefore, the memory 820 may be a storage unit inside the processor 810, or an external storage unit independent of the processor 810, or a component including a storage unit inside the processor 810 and an external storage unit independent of the processor 810.

[0111] Optionally, the computing device 800 may further include a bus 840. The memory 820 and the communication interface 830 may be connected to the processor 810 via the bus 840. The bus 840 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus 840 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the figure is represented by only one line, but it does not mean that there is only one bus or one type of bus.

[0112] It should be understood that in the embodiment of the present invention, the processor 810 may adopt a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. Alternatively, the processor 810 may adopt one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiment of the present invention.

[0113] The memory 820 may include a read-only memory and a random access memory, and provides instructions and data to the processor 810. A portion of the processor 810 may also include a nonvolatile random access memory. For example, the processor 810 may also store information on the device type.

[0114] When the computing device 800 is running, the processor 810 executes the computer-executable instructions in the memory 820 to perform the operation steps of each method embodiment.

[0115] It should be understood that the computing device 800 according to an embodiment of the present invention can correspond to the corresponding subjects in the methods according to the various embodiments of the present invention, and the above-mentioned and other operations and / or functions of each module in the computing device 800 are respectively for implementing the corresponding processes of each method of the present embodiment. For the sake of brevity, they will not be repeated here.

[0116] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0117] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0118] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0122] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, it is used to execute the operating steps of each method embodiment.

[0123] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include, an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0124] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0125] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0126] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0127] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, all of which belong to the scope of protection of the present invention.

Claims

1. A convolutional code generating device, characterized in that: Used to generate a convolutional code (n, k, m), where n and k represent that n convolutional code bits are output for every k bits to be encoded, and m+1 represents the constraint width of the convolutional code, the device comprising: a configuration module, a convolution module, an interleaving module and a merging module, each convolution module and its one-to-one corresponding interleaving module forming a convolution branch; The configuration module is used to configure the generating polynomial of each convolution branch according to the characteristics of the wireless channel and / or the characteristics of the code stream to be encoded; The convolution module is used to convolve the bit stream to be encoded according to the generating polynomial of each convolution branch, so as to generate the first convolution bit stream of each convolution branch; The interleaving module is used to interleave the first convolution bit stream of the convolution branch according to the agreed number of interleaving columns to generate the second convolution bit stream of the convolution branch; The merging module is used to merge the second convolution bit streams of each convolution branch through parallel-to-serial conversion to obtain the bit stream of the convolution code; Among them, each convolution module includes a sliding window, an outer-window node and an XOR module; The sliding window is used for the bit stream to be encoded to be input in time order, and the width of the sliding window is (m+1)*k; Each out-of-window node corresponds to the bit to be encoded in the sliding window one by one, and the node value of each out-of-window node is set to 0 or 1 according to the generating polynomial of the convolution branch where it is located; The XOR module is used to XOR the product of the node value of each node outside the window and the corresponding bit to be encoded in the current sliding window to obtain the first convolution bit of the convolution branch. After each first convolution bit is obtained, the bit stream to be encoded is rolled forward k bits and input into the sliding window, and the first convolution bit at each time constitutes the first bit stream.

2. The device according to claim 1, characterized in that: The configuration module is also used to configure the number of interleaving columns of the interleaving module of each convolution branch.

3. The device according to any one of claims 1 to 2, characterized in that: When used to generate the 4G TBCC code, the generating polynomial of each convolution branch is obtained from the 3GPP 36.212 protocol.

4. A convolutional code generation method, characterized in that: For generating a convolutional code (n, k, m), wherein n and k represent that n convolutional code bits are output for every k bits to be encoded, and m+1 represents the constraint width of the convolutional code, the method comprising: Configure the generating polynomial of each convolution branch according to the characteristics of the wireless channel and / or the characteristics of the code stream to be encoded; Convolving the bit stream to be encoded according to the generator polynomial of each convolution branch to generate a first convolution bit stream of each convolution branch; Interleaving the first convolution bit stream of each convolution branch according to the agreed number of interleaving columns to generate the second convolution bit stream of each convolution branch; The second convolution bit streams of each convolution branch are combined by parallel-to-serial conversion to obtain a bit stream of the convolution code; The step of convolving the bit stream to be encoded according to the generator polynomial of each convolution branch to generate the first convolution bit stream of each convolution branch includes: Setting a sliding window with a width of (m+1)*k for a bit stream composed of input codes to be encoded to be input in time sequence; and Setting each out-of-window node of each convolution branch corresponding to the bits to be encoded in the sliding window, and setting the node value of each out-of-window node of a convolution branch to 0 or 1 according to the generator polynomial of the convolution branch; and The node value of each out-of-window node of each convolution branch and the product of the corresponding bit to be encoded in the current sliding window are put together for XOR, and the current first convolution bit in the first convolution bit stream of each convolution branch is obtained, wherein after each first convolution bit is obtained, the bit stream to be encoded is scrolled forward k bits to input the sliding window, and the first convolution bits at each time constitute the first bit stream.

5. The method according to claim 4, characterized in that: Also includes: The number of interleaved columns corresponding to the first convolution bit stream of each convolution branch is configured according to the characteristics of the wireless channel.

6. The method according to any one of claims 4 to 5, characterized in that: When used to generate the 4G TBCC code, the generating polynomial of each convolution branch is obtained from the 3GPP 36.212 protocol.

7. A communication device, characterized in that: include: The device according to any one of claims 1 to 3.

8. A computing device, characterized in that include: bus; A communication interface connected to the bus; at least one processor connected to the bus; as well as At least one memory is connected to the bus and stores program instructions, and when the program instructions are executed by the at least one processor, the at least one processor executes the method according to any one of claims 4 to 6.

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