Quantum device preparation method, superconducting circuit and quantum chip

Abstract

The present invention discloses a method for fabricating a quantum device, a superconducting circuit, and a quantum chip. The method comprises: sequentially forming multiple superconducting material layers on different regions of a substrate, wherein each of the multiple superconducting material layers comprises a superconducting material deposited on the substrate and a hard mask covering the corresponding superconducting material, and the superconducting material in the multiple superconducting material layers comprises a superconducting material having kinetic inductance; etching away the hard mask on the multiple superconducting material layers to obtain multiple target circuit elements integrated on the substrate; and fabricating a target quantum device based on the multiple target circuit elements. The present invention solves the technical problem of the difficulty in fabricating superconducting quantum devices.

Description

Technical Field

[0001] The present invention relates to the field of superconducting quantum devices, and in particular to a method for preparing a quantum device, a superconducting circuit and a quantum chip. Background Art

[0002] In related technologies, the use of high-inductance materials to prepare superconducting quantum bits requires high preparation technology, making it difficult to prepare superconducting quantum devices.

[0003] Therefore, in the related art, there is a technical problem that it is difficult to realize the preparation of superconducting quantum devices.

[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0005] The embodiments of the present invention provide a method for preparing a quantum device, a superconducting circuit, and a quantum chip, so as to at least solve the technical problem of difficulty in preparing superconducting quantum devices.

[0006] According to one aspect of an embodiment of the present invention, a method for preparing a quantum device is provided, wherein a plurality of superconducting material layers are sequentially obtained on different regions of a substrate, wherein the plurality of superconducting material layers respectively include a superconducting material deposited on the substrate and a hard mask covering the corresponding superconducting material, and the superconducting material in the plurality of superconducting material layers includes a superconducting material having kinetic inductance; the hard masks on the plurality of superconducting material layers are etched away to obtain a plurality of target circuit elements integrated on the substrate; and a target quantum device is prepared based on the plurality of target circuit elements.

[0007] Optionally, in the case where the multiple superconducting material layers are two superconducting material layers, and the two superconducting material layers are a first superconducting material layer and a second superconducting material layer, the multiple superconducting material layers are obtained in sequence on different areas of the substrate, including: depositing a first superconducting material layer of a first superconducting material in the first target area range on the substrate covered by a first hard mask in the first target area range, wherein the first superconducting material is a superconducting material with kinetic inductance; depositing a second superconducting material on the substrate on which the first superconducting material layer is deposited; covering the second superconducting material with a second hard mask; and etching the second hard mask and the second superconducting material to obtain a second superconducting material layer of a second superconducting material in the second target area range covered by a second hard mask in the second target area range.

[0008] Optionally, depositing a first superconducting material layer of the first superconducting material in a first target area range covered by a first hard mask in a first target area range on the substrate includes: depositing the first superconducting material on the substrate; covering the first superconducting material with the first hard mask; determining a first target area range on the substrate where the first superconducting material is to remain; and etching the first hard mask and the first superconducting material to obtain a first superconducting material layer of the first superconducting material in the first target area range covered by the first hard mask in the first target area range.

[0009] Optionally, the etching of the first hard mask and the first superconducting material to obtain a first superconducting material layer of the first superconducting material in the first target area range covered by the first hard mask in the first target area range includes: gradually etching away the first hard mask in the first other area range in the first hard mask, and etching away the superconducting material in the first other area in the first superconducting material to obtain the first superconducting material layer of the first superconducting material in the first target area range covered by the first hard mask in the first target area range, wherein the first other area range is an area range on the substrate other than the first target area range.

[0010] Optionally, the etching of the second hard mask and the second superconducting material to obtain a second superconducting material layer of the second superconducting material in the second target area range covered by the second hard mask in the second target area range includes: gradually etching away the second hard mask in the second other area in the second hard mask, and etching away the superconducting material in the second other area in the second superconducting material to obtain a second superconducting material layer of the second superconducting material in the second target area range covered by the second hard mask in the second target area range, wherein the second other area range is an area range on the substrate other than the second target area range.

[0011] Optionally, preparing a target superconducting device based on the multiple target circuit elements includes: determining a junction region and an ohmic contact region on the substrate; and using a shadow evaporation method to evaporate and deposit a Josephson junction in the junction region and an ohmic contact in the ohmic contact region to obtain a superconducting quantum bit as the target superconducting device.

[0012] Optionally, the superconducting quantum bit is a Fluxonium quantum bit.

[0013] Optionally, after depositing a first superconducting material layer of the first superconducting material in the first target area covered by a first hard mask in the first target area on the substrate, the method further includes: performing a high-temperature annealing treatment on the first superconducting material layer to obtain a target first superconducting material layer, wherein the value of the kinetic inductance of the first superconducting material in the target first superconducting material layer reaches a target kinetic inductance value.

[0014] Optionally, performing high-temperature annealing on the first superconducting material layer to obtain a target first superconducting material layer includes: selecting a target high-temperature annealing control parameter from a plurality of candidate high-temperature annealing control parameters; and performing high-temperature annealing on the first superconducting material layer based on the target high-temperature annealing control parameter to obtain the target first superconducting material layer.

[0015] Optionally, etching away the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer to obtain a target circuit element integrated on the substrate includes: using a hydrofluoric acid solution to etch away the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer to obtain a target circuit element integrated on the substrate.

[0016] Optionally, the hard mask is silicon nitride.

[0017] According to another aspect of the present invention, a method for preparing a Fluxonium quantum bit is provided, comprising: depositing a first superconducting material layer of a first superconducting material in a first target region covered by a first hard mask in a first target region on a substrate, wherein the first superconducting material is a superconducting material having kinetic inductance; depositing a second superconducting material on the substrate on which the first superconducting material layer is deposited; covering the second superconducting material with a second hard mask; etching the second hard mask and the second superconducting material to obtain a second superconducting material layer of the second superconducting material in a second target region covered by a second hard mask in a second target region, wherein the second ... in a second target region The second target area range includes three separate first sub-area ranges, a second sub-area range, and a third sub-area range; the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer are etched away to obtain the first superconducting material integrated on the substrate and located within the first target area range, the first sub-area range, the second sub-area range, and the third sub-area range; an ohmic contact is deposited between the first superconducting material and the second superconducting material within the first sub-area range, and a Josephson junction is deposited between the second superconducting material in the second sub-area range and the second superconducting material in the third sub-area range to obtain a Fluxonium quantum bit.

[0018] According to another aspect of an embodiment of the present invention, a superconducting circuit is further provided, comprising a Fluxonium qubit prepared by the above-mentioned method for preparing a Fluxonium qubit.

[0019] According to another aspect of an embodiment of the present invention, a quantum chip is provided, comprising a Fluxonium quantum bit prepared by the above-mentioned method for preparing a Fluxonium quantum bit.

[0020] According to yet another aspect of the embodiments of the present invention, a quantum computer is provided, comprising: a quantum memory and the above-mentioned quantum chip.

[0021] In an embodiment of the present invention, a superconducting material with kinetic inductance is used as the material for preparing the target quantum device. By integrating multiple superconducting materials with kinetic inductance on the same substrate, the quantum device preparation scheme using a large number of Josephson junctions in the related art is replaced, thereby achieving the purpose of reducing the requirements for quantum device preparation conditions, thereby achieving the technical effect of facilitating large-scale integration of quantum bits, and further solving the technical problem of difficulty in preparing superconducting quantum devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0023] Figure 1 is a flow chart of a method for preparing a quantum device according to an embodiment of the present invention;

[0024] Figure 2 is a flow chart of a method for preparing a Fluxonium quantum bit according to an embodiment of the present invention;

[0025] Figure 3 is a synthetic schematic diagram provided according to an optional embodiment of the present invention;

[0026] Figure 4 Schematic diagram of photolithography provided according to an optional embodiment of the present invention Figure 1 ;

[0027] Figure 5 is a schematic diagram of wet etching provided according to an optional embodiment of the present invention;

[0028] Figure 6 is a schematic diagram of separating two layers of superconducting materials according to an optional embodiment of the present invention;

[0029] Figure 7 is a schematic diagram of photolithography provided according to an optional embodiment of the present invention Figure 2 ;

[0030] Figure 8 is a schematic diagram of an etching process provided according to an optional embodiment of the present invention;

[0031] Figure 9 2. A schematic diagram of wafer cleaning according to an optional embodiment of the present invention;

[0032] Figure 10 is a schematic diagram of forming an ohmic contact and a nonlinear Josephson junction according to an optional embodiment of the present invention;

[0033] Figure 11 is a schematic diagram of a preparation device provided according to an optional embodiment of the present invention;

[0034] Figure 12 Schematic diagram of a quantum computer provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following interpretations:

[0038] Thermal budget refers to the amount of heat that silicon is exposed to during processing. One of the goals of semiconductor processing is to minimize the amount of heat required to heat the silicon. A key factor in determining the processing conditions for most silicon-based semiconductors is minimizing the thermal budget by reducing the temperature or time required to process the silicon.

[0039] Etching is a crucial step in semiconductor manufacturing, microelectronic IC manufacturing, and micro-nanofabrication. It is a key patterning process associated with photolithography. Etching, in a narrower sense, is essentially photolithographic etching. First, the photoresist is exposed through photolithography, and then the desired portions are etched away using other methods. Etching is the process of selectively removing unwanted material from the surface of a silicon wafer using chemical or physical methods. Its fundamental goal is to accurately replicate the mask pattern on the coated silicon wafer. With the advancement of microfabrication, etching has broadly come to encompass the removal of material using solutions, reactive ions, or other mechanical methods, becoming a universal term for microfabrication. The simplest and most commonly used classifications of etching are dry etching and wet etching. The obvious difference between these two methods is that wet etching uses a solvent or solution for etching. Wet etching is a purely chemical process, utilizing a chemical reaction between a solution and the pre-etching material to remove portions not covered by the masking film. The advantages of wet etching are good selectivity, good repeatability, high production efficiency, simple equipment, and low cost. There are many types of dry etching, including photoevaporation, vapor phase etching, and plasma etching. According to the type of material being etched, dry etching is mainly divided into three types: metal etching, dielectric etching, and silicon etching. Dielectric etching is used for etching dielectric materials such as silicon dioxide. The advantages of dry etching are: good anisotropy, high selectivity, good controllability, flexibility, and repeatability, safe fine line operation, easy automation, no chemical waste, no pollution introduced during the treatment process, and high cleanliness.

[0040] Wafers are silicon wafers used to make silicon semiconductor circuits. The starting material is silicon. High-purity polycrystalline silicon is dissolved, doped with silicon seed crystals, and then slowly pulled out to form cylindrical single crystals. Silicon ingots are then ground, polished, and sliced to form silicon wafers, also known as wafers.

[0041] Example 1

[0042] According to an embodiment of the present invention, a method for preparing a quantum device is provided. Figure 1 is a flow chart of a method for preparing a quantum device according to an embodiment of the present invention, such as Figure 1 As shown, the method includes the following steps:

[0043] Step S102, sequentially forming a plurality of superconducting material layers on different regions of the substrate, wherein the plurality of superconducting material layers respectively include a superconducting material deposited on the substrate and a hard mask covering the corresponding superconducting material, and the superconducting material in the plurality of superconducting material layers includes a superconducting material having kinetic inductance;

[0044] Step S104, etching away the hard masks on the multiple superconducting material layers to obtain multiple target circuit elements integrated on the substrate;

[0045] Step S106: preparing a target quantum device based on the multiple target circuit elements.

[0046] Through the above steps, the method of forming multiple superconducting material layers on different areas of the substrate is applied to the preparation of superconducting quantum devices. That is, by combining the superconducting material with kinetic inductance as the material for preparing the target quantum device with the above preparation method, multiple superconducting materials with kinetic inductance can be integrated on the same substrate, replacing the quantum device preparation scheme using a large number of Josephson junctions in the related art, achieving the purpose of reducing the requirements for quantum device preparation conditions, thereby achieving the technical effect of facilitating large-scale integration of quantum bits, and further solving the technical problem of difficulty in preparing superconducting quantum devices.

[0047] As an optional embodiment, different superconducting materials are used to prepare different quantum devices. These superconducting materials differ not only in the superconducting material itself, but also in the amount of superconducting material used. Therefore, to meet the needs of preparing a variety of superconducting quantum devices, the superconducting material can be determined based on the required quantum device.

[0048] As an optional embodiment, when multiple superconducting material layers are sequentially obtained on different regions of the substrate, different quantum devices may require different numbers of superconducting material layers. In this embodiment, two superconducting material layers are used as an example for illustration, and the two superconducting material layers include a first superconducting material layer and a second superconducting material layer. It should be noted that two superconducting material layers are merely an example; depending on the needs of the quantum superconducting device, three superconducting material layers, four superconducting material layers, etc., may be used. However, the preparation method used for three or four superconducting material layers is similar to the preparation method for two superconducting material layers, differing only in the number of repeated operations.

[0049] For example, when the multiple superconducting material layers are two superconducting material layers, and the two superconducting material layers are a first superconducting material layer and a second superconducting material layer, the multiple superconducting material layers are sequentially obtained on different regions of the substrate, including:

[0050] Step S1022, depositing a first superconducting material layer of a first superconducting material in a first target area covered by a first hard mask in a first target area on the substrate, wherein the first superconducting material is a superconducting material with kinetic inductance;

[0051] Step S1024, depositing a second superconducting material on the substrate having the first superconducting material layer deposited thereon;

[0052] Step S1026, covering the second superconducting material with a second hard mask;

[0053] Step S1028 , etching the second hard mask and the second superconducting material to obtain a second superconducting material layer in which the second superconducting material in the second target area is covered by the second hard mask in the second target area.

[0054] Through the above steps, a second superconducting material is deposited on a substrate on which a first superconducting material layer is deposited, a second hard mask is covered on the second superconducting material, and the second hard mask and the second superconducting material are etched to obtain a second superconducting material layer in which the second superconducting material in a second target area is covered by the second hard mask in a second target area (wherein the first target area and the second target area are different areas on the substrate). Thus, a first superconducting material layer and a second superconducting material layer, i.e., two superconducting material layers, are obtained on the substrate. In the above preparation process, since the second superconducting material is deposited on the first superconducting material layer, and since the first superconducting material in the first superconducting material layer is covered by the first hard mask, when preparing the second superconducting material layer, the influence on the first superconducting material layer can be effectively avoided, so that the prepared superconducting quantum device is more precise.

[0055] It should be noted that the above-mentioned substrate can be a wafer, for example, a silicon wafer or sapphire, etc. In addition, the kinetic inductance referred to above, also called dynamic inductance, is relative to the geometric inductance of the classical device. The geometric inductance is mainly determined based on the geometric shape and size of the device. Dynamic inductance is a special property manifested by the quantum characteristics of superconducting materials. Therefore, when preparing quantum devices, considering dynamic inductance is a relatively important and necessary physical quantity. Considering dynamic inductance and preparing corresponding superconducting quantum devices based on superconducting materials with dynamic inductance can make the prepared quantum devices more precise.

[0056] As an optional embodiment, depositing a first superconducting material layer on a substrate, wherein the first superconducting material is covered by a first hard mask within a first target region, includes: depositing the first superconducting material on the substrate; covering the first superconducting material with a first hard mask; determining a first target region on the substrate where the first superconducting material is to be retained; and etching the first hard mask and the first superconducting material to obtain a first superconducting material layer, wherein the first superconducting material is covered by the first hard mask within the first target region. Etching the first hard mask and the first superconducting material yields a first superconducting material layer, wherein the first superconducting material is covered by the first hard mask within the first target region. Because the first superconducting material in the first superconducting material layer is covered by the first hard mask, subsequent formation of other superconducting material layers on the substrate can avoid affecting the first superconducting material, effectively protecting the first superconducting material during the preparation of the other superconducting material layers.

[0057] As described above, the first target region and the second target region are different regions on the substrate. When determining the first target region where the first superconducting material is to be left on the substrate, and in the process of etching the second hard mask and the second superconducting material to obtain a second superconducting material layer of the second superconducting material covered by the second hard mask in the second target region, when determining the second target region where the second superconducting material is to be left on the substrate, there are various ways to determine the target region. For example, it can be determined directly manually, such as manually determining the position on the substrate where the superconducting material is to be prepared. The size of the target region can be determined based on the size of each circuit element in the previous preparation of the target quantum bit. For another example, it can be determined based on a circuit design drawing. When determining based on the circuit design drawing, it can be determined in combination with the above manual method, or the size of the region can be determined proportionally based on the circuit design drawing by a computer.

[0058] As an optional embodiment, etching the first hard mask and the first superconducting material to obtain a first superconducting material layer in which the first superconducting material in the first target region is covered by the first hard mask in the first target region may include: gradually etching away the first hard mask in a first other region within the first hard mask, and etching away the superconducting material in a first other region within the first superconducting material, to obtain the first superconducting material layer in which the first hard mask in the first target region is covered by the first superconducting material in the first target region, wherein the first other region is an area on the substrate other than the first target region. The aforementioned "gradual etching" may refer to first etching away the first hard mask in the first other region within the first hard mask, and then etching away the superconducting material in the first other region within the first superconducting material.

[0059] After covering the first superconducting material deposited on the substrate with the first hard mask, the first hard mask in first other areas of the substrate except the first target area is gradually etched away, and the superconducting material in first other areas of the substrate except the first target area is etched away in the first superconducting material, so that the first superconducting material layer finally obtained is a combination of the first superconducting material in the first target area covered by the first hard mask in the first target area on the substrate.

[0060] It should be noted that when etching away the first hard mask in the first other region of the first hard mask, various methods can be used. For example, a combination of photolithography and dry etching can be used to etch away the first hard mask in the first other region of the first hard mask. When etching away the superconducting material in the first other region of the first superconducting material, various methods can also be used. For example, wet etching can be used to etch away the superconducting material in the first other region of the first superconducting material.

[0061] Therefore, a method combining photolithography, dry etching, and wet etching is employed to sequentially deposit the superconducting materials on the substrate according to the type of superconducting material to be integrated. After each superconducting material deposition is completed, a hard mask is applied thereto. After determining a first target region and a first other region, the hard mask can be used to achieve regional integration of the superconducting material on the substrate. If the superconducting material within the first target region needs to be retained, the first hard mask within the first other region is etched away using a combination of photolithography and dry etching, i.e., only the first hard mask within the first target region is retained. Then, wet etching is performed using an etchant that dissolves only the superconducting material but not the hard mask, to etch away the first superconducting material exposed within the first other region, i.e., only the first superconducting material within the first target region is retained, thereby achieving integration of the first superconducting material layer.

[0062] As an optional embodiment, the second hard mask and the second superconducting material are etched to obtain a second superconducting material layer of the second superconducting material in the second target area range covered by the second hard mask in the second target area range, including: gradually etching away the second hard mask in the second other area in the second hard mask, and etching away the superconducting material in the second other area in the second superconducting material to obtain a second superconducting material layer of the second superconducting material in the second target area range covered by the second hard mask in the second target area range, wherein the second other area range is the area range on the substrate except the second target area range.

[0063] Similarly, when etching away the second hard mask in the second other region of the second hard mask, a combination of photolithography and dry etching may be used to etch away the second hard mask in the second other region of the second hard mask. When etching away the superconducting material in the second other region of the second superconducting material, wet etching may also be used to etch away the superconducting material in the second other region of the second superconducting material.

[0064] Among them, when the hard mask is removed by combining photolithography and dry etching, the hard mask can be first patterned by photolithography, that is, the graphic area of the hard mask to be removed is determined, and then dry etching is used to etch away the hard mask to be removed based on the determined graphic area.

[0065] It should be noted that the above-described deposition of the first superconducting material layer and the second superconducting material layer on the substrate is merely an example. Depending on specific deposition requirements or if the substrate is subsequently used to fabricate different superconducting devices, more types of superconducting material layers may be deposited on the substrate, and these examples are not given here.

[0066] In addition, when preparing quantum devices, it may be necessary to integrate different superconducting materials on the same substrate. For different superconducting materials, the same deposition and etching method can be used. After completing the regional integration of all required superconducting materials, an etchant that can only dissolve the hard mask but not the superconducting material can be uniformly used to etch the hard mask, so as to remove the hard mask and only retain the multiple superconducting materials that have been integrated on the substrate.

[0067] As an optional embodiment, a target superconducting device is prepared based on multiple target circuit elements, including: determining a junction region and an ohmic contact region on a substrate; using a shadow evaporation method to evaporate and deposit a Josephson junction in the junction region and an ohmic contact in the ohmic contact region, thereby obtaining a superconducting quantum bit as the target superconducting device. The Josephson junction can be produced using shadow evaporation technology, and the ohmic contact can be formed together when producing the Josephson junction. During the shadow evaporation process, a first evaporation layer is used to form the first layer of the Josephson junction and the ohmic contact. After the first layer of evaporation is completed, oxygen is introduced into the process chamber to oxidize the metal surface, thereby achieving the preparation of the insulating layer required for the Josephson junction. After the oxidation is completed, a second evaporation layer is formed at a different evaporation angle to form a Josephson junction at the intersection of the first and second metal layers.

[0068] As an optional embodiment, the superconducting qubit may be a variety of types of qubits, for example, a Fluxonium qubit.

[0069] As an optional embodiment, after depositing a first superconducting material layer of a first superconducting material in a first target area covered by a first hard mask in a first target area on a substrate, the method further includes: performing a high-temperature annealing treatment on the first superconducting material layer to obtain a target first superconducting material layer, wherein the value of the kinetic inductance of the first superconducting material in the target first superconducting material layer reaches a target kinetic inductance value.

[0070] After wet etching, whether to perform a high-temperature annealing treatment on the material stack can be selected based on whether the properties of the current material stack need to be changed. Through the high-temperature annealing treatment, the properties of the first superconducting material layer or the surface properties of the substrate can be modified and adjusted. For example, the kinetic inductance value of the first superconducting material layer can be adjusted. In the embodiment of the present invention, the performance adjustment is performed after wet etching, which can also avoid the problem of increased difficulty in wet etching due to prioritizing performance adjustment. It should be noted that, after depositing a first superconducting material layer of the first superconducting material in the first target region covered by a first hard mask on the substrate, the first superconducting material layer is subjected to a high-temperature annealing treatment. Compared with adjusting the first superconducting material to the desired performance before depositing the first superconducting material, since the preparation operation of processing the first superconducting material may cause a certain degree of damage to the material itself, resulting in performance changes and thus affecting the precision of the manufactured device, adjusting the entire first superconducting material layer to the desired target performance after the first superconducting material is deposited, that is, after the preparation operation is completed, can ensure that the desired first superconducting material meets the expected performance requirements.

[0071] As an optional embodiment, performing a high-temperature annealing treatment on the first superconducting material layer to obtain a target first superconducting material layer includes: selecting a target high-temperature annealing control parameter from a plurality of candidate high-temperature annealing control parameters; and performing a high-temperature annealing treatment on the first superconducting material layer based on the target high-temperature annealing control parameter to obtain the target first superconducting material layer. The high-temperature annealing treatment on the first superconducting material layer can adjust the performance of the first superconducting material layer, and the specific extent to which the performance of the first superconducting material layer is adjusted (for example, adjusting the kinetic inductance of the first superconducting material layer to a target kinetic inductance value) can be achieved by adjusting the high-temperature annealing control parameters during the high-temperature annealing, for example, the temperature during the high-temperature annealing, the heating duration, etc. It should be noted that when the target high-temperature annealing control parameter is selected from the plurality of candidate high-temperature annealing control parameters, the kinetic inductance of the first superconducting material of the first superconducting material layer can be as large as possible after the high-temperature annealing treatment on the first superconducting material layer according to the selected high-temperature annealing control parameter, thereby meeting the performance requirements of the quantum device.

[0072] As an optional embodiment, etching away the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer to obtain a target circuit element integrated on the substrate includes: etching away the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer using a hydrofluoric acid (DHF) solution to obtain the target circuit element integrated on the substrate. The hydrofluoric acid (DHF) solution can only dissolve the hard mask but not the superconducting material. Therefore, after the various superconducting materials on the substrate have been deposited and etched, the hydrofluoric acid (DHF) solution can be used as an etchant to wet-etch the first and second hard masks on the superconducting material layers again, thereby finally removing the hard masks on the superconducting material layers to obtain the target circuit element integrated on the substrate. Since a wet etching method is adopted, that is, a solution etchant (i.e., a hydrofluoric acid DHF solution) is used to etch away the hard masks on the first superconducting material layer and the second superconducting material layer, compared with the photoresist etching method, the solution etchant can penetrate into the edges where the hard mask contacts the superconducting material. Therefore, the hard mask at the edge gaps of the superconducting material can be more thoroughly removed, making the first superconducting material and the second superconducting material integrated on the substrate purer, providing a foundation for the subsequent preparation of precise superconducting devices.

[0073] As an optional embodiment, the first hard mask and the second hard mask may be various types of nitrides, for example, silicon nitride.

[0074] According to an embodiment of the present invention, a preparation method embodiment of a Fluxonium quantum bit is also provided. Figure 2 FIG. 1 is a flow chart of a method for preparing a Fluxonium quantum bit according to an embodiment of the present invention. Figure 2 As shown, the method includes the following steps:

[0075] Step S202 , depositing a first superconducting material layer of a first superconducting material in a first target area covered by a first hard mask in a first target area on the substrate, wherein the first superconducting material is a superconducting material having kinetic inductance;

[0076] Step S204, depositing a second superconducting material on the substrate on which the first superconducting material layer is deposited;

[0077] Step S206, covering the second superconducting material with a second hard mask;

[0078] Step S208, etching the second hard mask and the second superconducting material to obtain a second superconducting material layer in which the second hard mask in the second target region covers the second superconducting material in the second target region, wherein the second target region includes three separate first sub-regions, a second sub-region, and a third sub-region.

[0079] Step S210, etching away the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer to obtain the first superconducting material integrated on the substrate within the first target region, the first sub-region, the second sub-region, and the third sub-region;

[0080] In step S212, an ohmic contact is deposited between the first superconducting material and the second superconducting material in the first sub-region, and a Josephson junction is deposited between the second superconducting material in the second sub-region and the second superconducting material in the third sub-region, to obtain a Fluxonium quantum bit.

[0081] Through the above method, multiple superconducting material layers for preparing Fluxonium qubits are obtained in sequence on different regions of the substrate: a first superconducting material layer and a second superconducting material layer, wherein the second superconducting material layer is located within three different sub-regions. After obtaining the corresponding superconducting materials within the corresponding regional ranges, the target circuit elements for preparing Fluxonium qubits are generated between the superconducting material layers: ohmic contacts and Josephson junctions, thereby obtaining the target quantum device: Fluxonium qubit. Compared with the traditional method of preparing Fluxonium qubits (which requires the integration of a large number of Josephson junctions), the above method can integrate inductive materials with the largest possible kinetic inductance. Therefore, it can effectively reduce the difficulty of preparation and effectively improve the preparation efficiency and accuracy.

[0082] Based on the above embodiments and optional embodiments, the present invention proposes an optional implementation manner, which is described below.

[0083] Fluxonium qubits are a promising implementation scheme for superconducting quantum computing bits, characterized by long coherence times and large anharmonicity between computational and non-computational energy levels. In order to use Fluxonium qubits to achieve universal quantum computing, it is necessary to construct a quantum circuit with a large number of physical Fluxonium qubits (more than thousands of qubits), high process yield, and precise bit parameter control, which is also a major challenge in the field of quantum computing. Based on this, an optional embodiment of the present invention has developed a scalable method for manufacturing low-microwave loss Fluxonium qubits using kinetic inductance materials. The method includes: the preparation of high-kinetic inductance circuit elements, the integration of low-inductance materials, and the integration of nonlinear circuit elements. The method has the advantages of good material uniformity, high process compatibility, and a large thermal budget.

[0084] The process flow of an optional embodiment of the present invention is as follows. Figure 3 This is a schematic diagram of a synthesis process according to an optional embodiment of the present invention. First, a material with kinetic inductance is synthesized on a bare wafer (layer 1 in the figure). Next, a hard mask is applied over layer 1 for subsequent photolithography patterning and dry etching (dielectric mask in the figure). Figure 4 Schematic diagram of photolithography provided according to an optional embodiment of the present invention Figure 1 , dry etching technology is used to etch the hard mask; wherein, layer 1 material can be used as an etch stop layer during the etching process to protect the substrate surface. Figure 5 : This is a schematic diagram of wet etching provided in accordance with an optional embodiment of the present invention. After the hard mask is patterned, the first layer of superconducting material (layer 1) is wet etched (the wet etchant has a very large etching selectivity for the first layer of material and the hard mask material). After the wet etching, there is an optional step that can be selected based on whether the properties of the material stack need to be modified. For example, the current material stack can be subjected to high temperature annealing to adjust the properties of the first layer of material or modify the surface properties of the substrate for subsequent process steps. The hard mask layer is generally suitable for high temperature processing and can be retained during the processing and used in subsequent process steps.

[0085] Next, the wafer is sent to deposit the second layer of superconducting material (layer 2 in the figure). The important point here is that the hard mask is not removed after the first layer is patterned during the whole process, but is used to separate the two layers of superconducting material ( Figure 6 is a schematic diagram of separating two layers of superconducting material according to an optional embodiment of the present invention. After depositing the second layer of superconducting material, another hard mask is deposited and the second layer of superconducting material is patterned using steps similar to the patterning of the first layer of material ( Figure 7is a schematic diagram of photolithography provided according to an optional embodiment of the present invention Figure 2 First, the hard mask is patterned by photolithography and dry etching to expose the portion of the second layer of superconducting material that needs to be etched. Then, wet etching is used to etch the second layer of material. Due to the protection of the first dielectric layer, the first layer of material is intact and unaffected during the etching process ( Figure 8 is a schematic diagram of the etching process according to an optional embodiment of the present invention. The necessity of using wet etching technology in this step is that isotropic etching is conducive to completely removing the second layer material that may remain around the edge of the first layer material. After the etching step is completed, the wafer is cleaned in an acidic solution (diluted hydrofluoric acid solution, DHF) to remove the hard mask layer, while the superconducting material is not affected in this step ( Figure 9 is a schematic diagram of wafer cleaning provided according to an optional embodiment of the present invention).

[0086] After forming the first and second layers of material on the wafer, that is, after the linear circuit elements of the Fluxonium qubit are formed, the last step is to form the necessary Ohmic contacts and nonlinear Josephson junctions ( Figure 10 is a schematic diagram of the formation of an ohmic contact and a nonlinear Josephson junction provided according to an optional embodiment of the present invention). The Josephson junction can be produced by using shadow evaporation technology, and the ohmic contact can also be formed together when producing the nonlinear Josephson junction. Simply put, a double layer of photoresist is used to achieve regional metal deposition in the exposed areas of the junction area and the ohmic contact area of the wafer. During the shadow evaporation process, the first evaporated layer forms the first layer of the Josephson junction and the ohmic contact. After the first layer of evaporation deposition is completed, oxygen is introduced into the process chamber to complete the oxidation of the metal surface to achieve the preparation of the insulating layer required for the Josephson junction. After the oxidation is completed, the second evaporated layer is completed at a different evaporation angle, so that a Josephson junction is formed at the intersection of the first layer of metal and the second layer of metal.

[0087] Figure 11 This figure is a schematic diagram of a superconducting qubit fabricated using a method according to an optional embodiment of the present invention. The various types of circuit components within the superconducting qubit are labeled as shown. A typical Fluxonium structure includes three different materials, labeled as key circuit components. Specifically, the superinductor (composed of the first layer of superconducting material), the qubit capacitor and circuit ground (composed of the second layer of superconducting material), and the Josephson junction and ohmic contact (typically made of aluminum) are constructed.

[0088] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0089] Example 2

[0090] According to an embodiment of the present invention, a quantum device is further provided, comprising a Fluxonium quantum bit prepared by the above-mentioned method for preparing a Fluxonium quantum bit.

[0091] According to an embodiment of the present invention, a superconducting circuit is further provided, comprising a Fluxonium quantum bit prepared by the above-mentioned method for preparing a Fluxonium quantum bit.

[0092] According to an embodiment of the present invention, a quantum chip is further provided, comprising a Fluxonium quantum bit prepared by the above-mentioned method for preparing a Fluxonium quantum bit.

[0093] According to an embodiment of the present invention, a quantum computer is further provided. Figure 12 is a schematic diagram of a quantum computer provided according to an embodiment of the present invention. The quantum computer may be any quantum computer device in a quantum computer group, such as Figure 12 As shown, the quantum computer includes: a quantum memory 1201 and the above-mentioned quantum chip 1202.

[0094] It can be understood by those skilled in the art that Figure 12 The structure shown is for illustration only. Figure 12 It does not limit the structure of the above electronic device. For example, a quantum computer may also include Figure 12 More or fewer components than shown, or with Figure 12 Different configurations shown.

[0095] A person skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant preparation hardware through a program, and the program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0096] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0097] In the above embodiments of the present invention, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the embodiments described above are merely illustrative, and the entire implementation process of the above embodiments still needs to be completed in conjunction with the control program unit of the computer, and the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0099] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0100] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0101] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, etc. Various media that can store program codes.

[0102] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A method for preparing a quantum device, characterized in that: include: Sequentially obtaining a plurality of superconducting material layers on different regions of the substrate, wherein the plurality of superconducting material layers respectively include a superconducting material deposited on the substrate and a hard mask covering the corresponding superconducting material, and the superconducting material in the plurality of superconducting material layers includes a superconducting material having kinetic inductance; Etching away the hard masks on the multiple superconducting material layers to obtain multiple target circuit elements integrated on the substrate; preparing a target quantum device based on the plurality of target circuit elements; The method of preparing a target superconducting device based on the multiple target circuit elements includes: determining a junction region and an ohmic contact region on the substrate; and using a shadow evaporation method to evaporate and deposit a Josephson junction in the junction region and an ohmic contact in the ohmic contact region to obtain a superconducting quantum bit as the target superconducting device.

2. The method according to claim 1, characterized in that In a case where the multiple superconducting material layers are two superconducting material layers, and the two superconducting material layers are a first superconducting material layer and a second superconducting material layer, sequentially obtaining the multiple superconducting material layers on different regions of the substrate includes: Depositing a first superconducting material layer of a first superconducting material in a first target area covered by a first hard mask in a first target area on the substrate, wherein the first superconducting material is a superconducting material with kinetic inductance; depositing a second superconducting material on the substrate having the first superconducting material layer deposited thereon; covering the second superconducting material with a second hard mask; The second hard mask and the second superconducting material are etched to obtain a second superconducting material layer in which the second superconducting material in the second target area is covered by the second hard mask in the second target area.

3. The method according to claim 2, characterized in that The step of depositing a first superconducting material layer of a first superconducting material in a first target area on the substrate and covering the first target area with a first hard mask comprises: depositing the first superconducting material on the substrate; covering the first hard mask on the first superconducting material; determining a first target region on the substrate where the first superconducting material is to be left; The first hard mask and the first superconducting material are etched to obtain a first superconducting material layer in which the first superconducting material in the first target area is covered by the first hard mask in the first target area.

4. The method according to claim 3, characterized in that The etching process is performed on the first hard mask and the first superconducting material to obtain a first superconducting material layer in which the first hard mask in the first target area covers the first superconducting material in the first target area, including: The first hard mask in the first other area range in the first hard mask and the superconducting material in the first other area in the first superconducting material are etched away step by step respectively to obtain a first superconducting material layer in which the first superconducting material in the first target area range is covered by the first hard mask in the first target area range, wherein the first other area range is an area range on the substrate excluding the first target area range.

5. The method according to claim 2, characterized in that The etching process is performed on the second hard mask and the second superconducting material to obtain a second superconducting material layer in which the second hard mask in the second target area covers the second superconducting material in the second target area, comprising: The second hard mask in the second other area in the second hard mask and the superconducting material in the second other area in the second superconducting material are etched away step by step respectively to obtain a second superconducting material layer in which the second superconducting material in the second target area is covered by the second hard mask in the second target area, wherein the second other area is an area on the substrate excluding the second target area.

6. The method according to claim 1, characterized in that The superconducting quantum bit is a Fluxonium quantum bit.

7. The method according to claim 2, characterized in that After depositing a first superconducting material layer of a first superconducting material in a first target area on the substrate and covering the first target area with a first hard mask, the method further includes: The first superconducting material layer is subjected to a high-temperature annealing treatment to obtain a target first superconducting material layer, wherein the kinetic inductance value of the first superconducting material in the target first superconducting material layer reaches a target kinetic inductance value.

8. The method according to claim 7, characterized in that The step of performing high-temperature annealing on the first superconducting material layer to obtain a target first superconducting material layer includes: selecting a target high temperature annealing control parameter from a plurality of candidate high temperature annealing control parameters; Based on the target high-temperature annealing control parameters, a high-temperature annealing process is performed on the first superconducting material layer to obtain the target first superconducting material layer.

9. The method according to claim 2, characterized in that The etching of the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer to obtain a target circuit element integrated on the substrate includes: The first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer are etched away using a hydrofluoric acid solution to obtain a target circuit element integrated on the substrate.

10. The method according to any one of claims 1 to 9, characterized in that The hard mask is silicon nitride.

11. A method for preparing a Fluxonium quantum bit, characterized in that: include: Depositing a first superconducting material layer of a first superconducting material in a first target area covered by a first hard mask in a first target area on the substrate, wherein the first superconducting material is a superconducting material with kinetic inductance; depositing a second superconducting material on the substrate having the first superconducting material layer deposited thereon; covering the second superconducting material with a second hard mask; Etching the second hard mask and the second superconducting material to obtain a second superconducting material layer in which the second hard mask in the second target area covers the second superconducting material in the second target area, wherein the second target area includes three separate first sub-area areas, a second sub-area area, and a third sub-area area; Etching away the first hard mask on the first superconducting material layer and the second hard mask on the second superconducting material layer to obtain the first superconducting material integrated on the substrate and located within the first target region, the first sub-region, the second sub-region, and the third sub-region; An ohmic contact is deposited between the first superconducting material and the second superconducting material within the first sub-region, and a Josephson junction is deposited between the second superconducting material within the second sub-region and the second superconducting material within the third sub-region, to obtain a Fluxonium quantum bit, wherein a junction region and an ohmic contact region are determined on the substrate; and a shadow evaporation method is used to evaporate and deposit the Josephson junction in the junction region and the ohmic contact in the ohmic contact region to obtain the Fluxonium quantum bit.

12. A superconducting circuit, characterized in that: Including a Fluxonium quantum bit prepared by the preparation method according to claim 11.

13. A quantum chip, characterized in that: Including a Fluxonium quantum bit prepared by the preparation method according to claim 11.

14. A quantum computer, characterized in that include: A quantum memory and a quantum chip as claimed in claim 13.

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