A security detection apparatus for bios and ec firmware

Abstract

This invention discloses a security detection device for BIOS and EC firmware, comprising a security module, a CPU, an EC chip, EC flash memory, a BIOS chip, and a switching circuit. The switching circuit is connected to the security module, CPU, EC chip, EC flash memory, and BIOS chip respectively, and is a composite circuit composed of multiple switching switches. When the computer is powered on, the switching circuit, according to the first control command of the security module, sequentially controls the connection of the lines between the security module and the BIOS chip, and between the security module and the EC flash memory, in a preset order, so that the security module sends SPI signals to sequentially verify the BIOS chip and EC flash memory. The technical solution provided by this invention enables security detection of both the BIOS chip and the EC chip before the computer is powered on.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a security detection device for BIOS and EC firmware. Background Technology

[0002] Computers are essential devices in our daily lives and work, storing vast amounts of data that require careful protection. However, the proliferation of attack methods poses a significant threat to personal computer security. While operating systems and networks are relatively secure due to protections such as firewalls and antivirus software, computer firmware offers weaker protections. If hackers embed malicious code into the firmware, they can remotely control and compromise the computer.

[0003] In response, patent document CN110750794A discloses a BIOS secure boot method and system. This system uses a switch connected between the BIOS chip and the CPU, and connects the SPI terminal of a security module to the switch. Figure 1 As shown, the switch includes three signal terminals and one control terminal. One master signal terminal can be connected to the other two slave signal terminals. The switch receives control commands through the control terminal and selects one of the two slave signal terminals to connect to the master signal terminal, thus switching the circuit. The security module sends control commands to the control terminal of the switch through the power management module, instructing the switch to connect the circuit between the BIOS chip and the CPU, or the circuit between the BIOS chip and the security module. When the computer is powered on, the security module first commands the switch to disconnect the circuit between the BIOS chip and the CPU, and connect the circuit between the BIOS chip and the SPI terminal of the security module. This allows the security module to send an SPI signal to verify the BIOS chip. If the BIOS verification is successful, the security module then commands the switch to disconnect the circuit between the BIOS chip and the security module, and connect the circuit between the BIOS chip and the CPU, powering on the CPU and starting the BIOS to enter the boot process. If the verification fails, the computer does not boot. This method avoids the risk of remotely controlling the computer by starting the BIOS first during startup.

[0004] However, computers do not only have BIOS firmware; they also include embedded controllers (EC). If a hacker writes malicious code into the EC firmware, there is still a risk of being attacked if the EC is not properly monitored. Furthermore, the BIOS chip and the EC chip need to be monitored sequentially, while the security monitoring system provided in the aforementioned document can only monitor the BIOS firmware. Summary of the Invention

[0005] In view of this, the present invention provides a security detection device for BIOS and EC firmware, thereby enabling security detection of both the BIOS chip and the EC chip computer firmware before the computer is powered on.

[0006] According to a first aspect, embodiments of the present invention provide a security detection device for BIOS and EC firmware, including a security module, a CPU, an EC chip, an EC flash memory, a BIOS chip, and a switching circuit; the switching circuit is connected to the security module, CPU, EC chip, EC flash memory, and BIOS chip respectively, and is a composite circuit composed of multiple switching switches; when the computer is powered on, the switching circuit, according to a first control instruction from the security module, sequentially controls the connection of the lines between the security module and the BIOS chip and the lines between the security module and the EC flash memory in a preset order, so that the security module sends an SPI signal to sequentially verify the BIOS chip and the EC flash memory; if the verification passes, the switching circuit, according to a second control instruction from the security module, simultaneously connects the lines between the CPU and the BIOS chip and the lines between the EC chip and the EC flash memory, so that the EC chip and the CPU are started by the information inside the EC flash memory and the BIOS chip respectively.

[0007] Optionally, the switching circuit includes a first switching switch, a second switching switch, and a third switching switch. Each of the first, second, and third switching switches includes a control terminal, a master signal terminal, a first slave signal terminal, and a second slave signal terminal. The control terminals of all three switches are connected to the control command terminal of the security module. The master signal terminal of the first switching switch is connected to the SPI terminal of the security module. The first slave signal terminal of the first switching switch is connected to the second slave signal terminal of the second switching switch, and the second slave signal terminal of the first switching switch is connected to the second slave signal terminal of the third switching switch. The first slave signal terminal of the second switch is connected to the CPU, the master signal terminal of the second switch is connected to the BIOS chip, the first slave signal terminal of the third switch is connected to the EC chip, and the master signal terminal of the third switch is connected to the EC flash memory. When the control terminals of the first, second, and third switches receive a first-level signal sent by the control command terminal of the security module, they all turn on the master signal terminal and the first slave signal terminal. When the control terminals of the first, second, and third switches receive a second-level signal sent by the control command terminal of the security module, they all turn on the master signal terminal and the second slave signal terminal.

[0008] Optionally, the control command terminal of the safety module includes a first command terminal and a second command terminal. The first command terminal is connected to the control terminal of the first switching switch, and the second command terminal is connected to the control terminals of the second switching switch and the third switching switch, respectively.

[0009] Optionally, when the computer is powered on, the first control instruction output by the security module includes a first sub-instruction and a second sub-instruction output in a preset order. The first sub-instruction is that the first instruction terminal outputs a first level signal, and the second instruction terminal outputs a second level signal; the second sub-instruction is that the first instruction terminal outputs a second level signal, and the second instruction terminal outputs a second level signal.

[0010] Optionally, the CPU is a Phytium D2000, and the security detection device further includes a level conversion chip connected between the CPU and the second switching switch.

[0011] Optionally, the level conversion chip is model SGM4562 from Saint-Gobain Microelectronics.

[0012] Optionally, the safety detection device further includes a first pull-up resistor, a second pull-up resistor, and a third pull-up resistor. The first pull-up resistor, the second pull-up resistor, and the third pull-up resistor are respectively connected to the control terminals of the first switch, the second switch, and the third switch, and are connected to a preset voltage signal.

[0013] Optionally, the first switch, the second switch, and the third switch are all of the Silergy TPW3257-TS3R model.

[0014] Optionally, the security module is a TPCM chip.

[0015] The technical solution provided in this application has the following advantages:

[0016] The technical solution provided in this application connects a security module to a switching circuit, which is composed of multiple switching switches connected together. This allows the CPU, EC chip, EC flash memory, and BIOS chip to all be connected to the switching circuit. When the computer is powered on, the security module controls the switching circuit to sequentially connect the lines between the security module and the BIOS chip, and then between the security module and the EC flash memory. This allows the security module to sequentially perform security checks on the instruction programs in the BIOS chip and EC flash memory. If the security checks pass, the security module then controls the switching circuit to simultaneously connect the lines between the CPU and the BIOS chip, and between the EC chip and the EC flash memory. At this point, the system powers on the CPU, enabling booting with both the BIOS and EC firmware having undergone security checks, further ensuring the security of computer startup. Attached Figure Description

[0017] The features and advantages of the invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the invention in any way. In the drawings:

[0018] Figure 1 A schematic diagram of the structure of a switching switch in the prior art is shown;

[0019] Figure 2 This diagram illustrates the structure of a security detection device for BIOS and EC firmware according to one embodiment of the present invention.

[0020] Figure 3 This diagram illustrates another structural schematic of a security detection device for BIOS and EC firmware according to one embodiment of the present invention;

[0021] The numbers in the diagram are as follows:

[0022] 01-Security module, 02-CPU, 03-EC chip, 04-EC flash memory, 05-BIOS chip, 06-Switch circuit, 07-Level conversion chip, S1-First switch, S2-Second switch, S3-Third switch, R0-First pull-up resistor, R1-Second pull-up resistor, R2-Third pull-up resistor. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please see Figure 2 In one embodiment, a security detection device for BIOS and EC firmware specifically includes a security module 01, a CPU 02, an EC chip 03, an EC flash memory 04, a BIOS chip 05, and a switching circuit 06. The switching circuit 06 is connected to the security module 01, CPU 02, EC chip 03, EC flash memory 04, and BIOS chip 05, and is a composite circuit composed of multiple switching switches.

[0025] In this embodiment, multiple switching switches are connected according to a preset structure to obtain a composite switching switch circuit 06, which interfaces with the security module 01, CPU 02, EC chip 03, EC flash memory 04, and BIOS chip 05. The security module 01 sends control commands and SPI signals to the switching switch circuit 06. The control commands control the switching switch circuit 06 to select two components from the above components according to preset logic and connect the lines between them. The SPI signal is used to perform security verification on the preset instruction program in the BIOS chip 05 or EC flash memory 04 to identify whether its internal instruction program has been modified by attack code.

[0026] When the computer is powered on, the switching circuit 06, according to the first control command of the security module 01, sequentially controls the circuit between the security module 01 and the BIOS chip 05, and the circuit between the security module 01 and the EC flash memory 04 to be connected in a preset order. All other circuits are deactivated. When a circuit is connected, the security module 01 sends SPI signals twice to sequentially perform security verification on the instruction programs in the BIOS chip 05 and the EC flash memory 04. If the verification passes, the security module 01 issues a second control command, controlling the switching circuit 06 to simultaneously connect the circuit between the CPU 02 and the BIOS chip 05, and the circuit between the EC chip 03 and the EC flash memory 04, and controls the CPU 02 to power on and start up, so that the EC chip 03 and the CPU 02 can start using the information inside the EC flash memory 04 and the BIOS chip 05, respectively. Thus, the security detection device provided in this embodiment enables startup after both the BIOS and EC firmware have undergone security verification, further ensuring the security of computer startup.

[0027] Specifically, such as Figure 3As shown, in one embodiment, the switching circuit 06 includes a first switching switch S1, a second switching switch S2, and a third switching switch S3. Each of the first, second, and third switching switches S1 and S2 includes a control terminal SEL, a master signal terminal A, a first slave signal terminal B1, and a second slave signal terminal B2. The control terminal SEL of each of the three switches is connected to the control command terminal of the security module 01, enabling all three switches to respond to control commands issued by the security module 01 and switch the line. The master signal terminal A of the first switching switch S1 is connected to the SPI terminal of the security module 01, thus splitting the SPI signal of the security module 01 into two, achieving the purpose of verifying the BIOS chip 05 and the EC flash memory 04 separately in two stages. To further achieve this objective, this embodiment also requires connecting the first slave signal terminal B1 of the first switch S1 and the second slave signal terminal B2 of the second switch S2, and connecting the second slave signal terminal B2 of the first switch S1 and the second slave signal terminal B2 of the third switch S3. Then, the first slave signal terminal B1 of the second switch S2 is connected to the CPU 02, the master signal terminal A of the second switch S2 is connected to the BIOS chip 05, the first slave signal terminal B1 of the third switch S3 is connected to the EC chip 03, and the master signal terminal A of the third switch S3 is connected to the EC flash memory 04.

[0028] The control logic of the switching switches is as follows: when the control terminals SEL of the first switching switch S1, the second switching switch S2, and the third switching switch S3 receive the first level signal sent by the control command terminal of the safety module 01, the main signal terminal A and the first slave signal terminal B1 are turned on. When the control terminals SEL of the first switching switch S1, the second switching switch S2, and the third switching switch S3 receive the second level signal sent by the control command terminal of the safety module 01, the main signal terminal A and the second slave signal terminal B2 are turned on.

[0029] Based on the connection relationship of the switching circuit 06, the control command terminal of the safety module 01 includes a first command terminal GPIO1 and a second command terminal GPIO2, wherein the first command terminal GPIO1 is connected to the control terminal SEL of the first switching switch S1, and the second command terminal GPIO2 is connected to the control terminals SEL of the second switching switch S2 and the third switching switch S3 respectively.

[0030] Based on the above overall circuit structure and the control logic of the switching switch, this embodiment of the invention also provides a security detection instruction running in the security module 01. By running the security detection instruction, the security module 01 can perform verification on the BIOS chip 05 and the EC flash memory 04 respectively. The specific steps of the security module 01 running the security detection instruction are as follows:

[0031] The security module 01 issues a first control command, which consists of two parts. The first part (the first sub-instruction) involves the security module 01 sending a first-level signal to the first switch S1 and simultaneously sending second-level signals to the second switch S2 and the third switch S3. This causes the master signal terminal A and the first slave signal terminal B1 of the first switch S1 to be turned on, and the master signal terminal A and the second slave signal terminal B2 of both the second switch S2 and the third switch S3 to be turned on. The SPI signal of the security module 01 can then reach the second switch S2 through the line between the master signal terminal A and the first slave signal terminal B1 of the first switch S1, and then reach the BIOS chip 05 through the line between the second slave signal terminal B2 and the master signal terminal A of the second switch S2. This verifies the program code in the BIOS chip 05. At the same time, the line between the security module 01 and the EC flash memory 04 is disconnected, and the line between the EC flash memory 04 and the EC chip 03 is also disconnected. This prevents the BIOS chip 05 and the EC flash memory 04 from simultaneously verifying the code, thus avoiding any impact on the working logic of the security module 01.

[0032] Similarly, another part of the first control instruction (the second sub-instruction) is that the security module 01 sends a second level signal to the first switch S1 and simultaneously sends a second level signal to the second switch S2 and the third switch S3. At this time, the master signal terminal A and the slave signal terminal B2 of both the second switch S2 and the third switch S3 are turned on. Since the first switch S1 and the second slave signal terminal B2 are turned on, the security module 01 can send an SPI signal through the first switch S1 to the third switch S3 to verify the instruction program in the EC flash memory 04.

[0033] The first and second sub-instructions are executed in a preset order. In this embodiment, the preset order can be set to execute the first sub-instruction first and then the second sub-instruction, or vice versa. As long as the conditions for sequential verification are met for BIOS chip 05 and EC flash memory 04, this embodiment does not impose any special limitations.

[0034] Finally, if the verification fails, the boot process is not executed, further ensuring computer security. If the verification passes, security module 01 sends a second control command to the three switches. The second control command includes sending a first-level signal to both the second switch S2 and the third switch S3, causing both switches S2 and S3 to be connected at their master signal terminal A and first slave signal terminal B1. This establishes a connection between the BIOS chip 05 and the CPU 02, EC chip 03, and EC flash memory 04. At this point, the computer power supply can power on the CPU 02, and the computer can operate normally. Furthermore, the second control command sent by security module 01 to the first switch S1 can be either a first-level signal or a second-level signal. Since both the second switch S2 and the third switch S3 are disconnected from the first switch S1 at this time, regardless of the signal received by the first switch S1, security module 01 will not establish a connection with either the BIOS chip 05 or the EC flash memory 04, ensuring circuit logic stability.

[0035] Through the aforementioned circuit connections and control logic, the BIOS and EC firmware security detection device provided in this embodiment of the invention only requires the cooperation of three switching switches to split the SPI signal of the security module 01 into two. Following a specific sequence, the security module 01 sequentially performs security verification on the instruction programs in the BIOS chip 05 and EC flash memory 04. After verification, the security module 01 can control two of the switching switches to connect the BIOS chip 05 to the CPU 02 and the EC chip 03 to the EC flash memory 04, allowing the computer to power on and operate normally. This method uses fewer components, is easy to assemble, and effectively detects both the BIOS and EC firmware. The solution is low-cost and easy to implement, ensuring secure boot regardless of whether the attack code is in the BIOS or EC firmware, further enhancing computer security.

[0036] In this embodiment of the invention, the first, second and third switching switches S3 are selected from Silergy TPW3257-TS3R. This chip adopts TSSOP packaging, which occupies a small area on the motherboard. SOP packaging is convenient for rework debugging and has high self-controllability.

[0037] Specifically, in one embodiment, to apply the security monitoring device provided by this invention to the Phytium platform, when the CPU02 is a Phytium D2000, the security detection device further includes a level conversion chip 07, which is connected between the CPU02 and the second switching switch S2. Considering that the Phytium D2000 processor uses a 1.8V level I / O, to make the security monitoring device of this embodiment compatible with the Phytium platform, the level conversion chip 07 is used to convert it to a common 3.3V level and connect it to the second switching switch S2. In this embodiment, the level conversion chip 07 can be a Sanbang Microelectronics SGM4562, which offers stronger independent controllability.

[0038] Specifically, such as Figure 3 As shown, in one embodiment, the security detection device further includes a first pull-up resistor R0, a second pull-up resistor R1, and a third pull-up resistor R2. The first pull-up resistor R0, the second pull-up resistor R1, and the third pull-up resistor R2 are respectively connected to the control terminals SEL of the first switch S1, the second switch S2, and the third switch S3, and are connected to a preset voltage signal. Specifically, in this embodiment, the preset voltage signal is 3.3V. The purpose is to preset a 3.3V signal to the three switches so that, before power-on, CPU02 and BIOS chip 05 are not connected, and EC chip 03 and EC flash memory 04 are not connected by default. This prevents the computer system from directly starting due to SPI conduction caused by a short circuit, thereby further ensuring the computer's security.

[0039] Specifically, in one embodiment, the security module 01 used in this embodiment of the invention is a TPCM (Trusted Platform Control Module). This module is a PCIe x8 standard-sized card with custom signals. The card uses an FPGA chip. The TPCM adds a root of trust control function on the basis of TCM, realizing the combination of cryptography and control. It realizes the active control of the entire platform by the TPCM, which can be used to establish and protect the source of trust, and provide a series of trusted computing functions such as trusted platform control, integrity measurement, secure storage, trusted reporting and cryptographic services.

[0040] Through the aforementioned components, the technical solution provided in this application connects the security module 01 to a switching circuit 06, which is composed of multiple switching switches connected together. This allows the CPU 02, EC chip 03, EC flash memory 04, and BIOS chip 05 to be connected to the switching circuit 06. When the computer is powered on, the security module 01 controls the switching circuit 06 to sequentially connect the lines between the security module 01 and the BIOS chip 05, and between the security module 01 and the EC flash memory 04. This allows the security module 01 to sequentially perform security checks on the instruction programs in the BIOS chip 05 and the EC flash memory 04. If the security check passes, the security module 01 then controls the switching circuit 06 to simultaneously connect the lines between the CPU 02 and the BIOS chip 05, and between the EC chip 03 and the EC flash memory 04. At this point, the system powers on the CPU 02, enabling startup with security checks performed on both the BIOS and EC firmware, further ensuring the security of computer startup.

[0041] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A security detection device for BIOS and EC firmware, characterized in that, Includes a security module, CPU, EC chip, EC flash memory, BIOS chip, and switching circuitry; The switching circuit is connected to the security module, CPU, EC chip, EC flash memory and BIOS chip respectively, and is a composite circuit composed of multiple switching switches; When the computer is powered on, the switching circuit, according to the first control instruction of the security module, sequentially controls the connection of the lines between the security module and the BIOS chip, and between the security module and the EC flash memory, in a preset order. This causes the security module to send SPI signals to verify the BIOS chip and the EC flash memory in sequence. If the verification passes, the switching circuit, according to the second control instruction of the security module, simultaneously connects the lines between the CPU and the BIOS chip, and between the EC chip and the EC flash memory, so that the EC chip and the CPU can start up using the information inside the EC flash memory and the BIOS chip, respectively.

2. The safety detection device according to claim 1, characterized in that, The switching circuit includes a first switching switch, a second switching switch, and a third switching switch. Each of the first switching switch, the second switching switch, and the third switching switch includes a control terminal, a master signal terminal, a first slave signal terminal, and a second slave signal terminal. The control terminals of the first switch, the second switch, and the third switch are all connected to the control command terminal of the security module. The master signal terminal of the first switch is connected to the SPI terminal of the security module. The first slave signal terminal of the first switch is connected to the second slave signal terminal of the second switch. The second slave signal terminal of the first switch is connected to the second slave signal terminal of the third switch. The first slave signal terminal of the second switch is connected to the CPU. The master signal terminal of the second switch is connected to the BIOS chip. The first slave signal terminal of the third switch is connected to the EC chip. The master signal terminal of the third switch is connected to the EC flash memory. Specifically, when the control terminals of the first, second, and third switching switches receive a first-level signal sent by the control command terminal of the safety module, they all turn on the main signal terminal and the first slave signal terminal. When the control terminals of the first, second, and third switching switches receive a second-level signal sent by the control command terminal of the safety module, they all turn on the main signal terminal and the second slave signal terminal.

3. The safety detection device according to claim 2, characterized in that, The control command terminal of the safety module includes a first command terminal and a second command terminal. The first command terminal is connected to the control terminal of the first switching switch, and the second command terminal is connected to the control terminals of the second switching switch and the third switching switch, respectively.

4. The safety detection device according to claim 3, characterized in that, When the computer is powered on, the first control command output by the security module includes a first sub-instruction and a second sub-instruction output in a preset order. The first sub-instruction is that the first instruction terminal outputs a first level signal and the second instruction terminal outputs a second level signal; the second sub-instruction is that the first instruction terminal outputs a second level signal and the second instruction terminal outputs a second level signal.

5. The safety detection device according to claim 2, characterized in that, The CPU is a Phytium D2000, and the security detection device also includes a level conversion chip, which is connected between the CPU and the second switching switch.

6. The safety detection device according to claim 5, characterized in that, The level conversion chip is model SGM4562 from Saint-Gobain Microelectronics.

7. The safety detection device according to claim 2, characterized in that, The safety detection device further includes a first pull-up resistor, a second pull-up resistor, and a third pull-up resistor. The first pull-up resistor, the second pull-up resistor, and the third pull-up resistor are respectively connected to the control terminals of the first switch, the second switch, and the third switch, and are connected to a preset voltage signal.

8. The safety detection device according to claim 2, characterized in that, The first switch, the second switch and the third switch are all of the model number Silergy TPW3257-TS3R.

9. The safety detection device according to claim 1, characterized in that, The security module is a TPCM chip.

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