Display panel and driving method thereof, and display device

Abstract

The present invention discloses a display panel and a driving method and a display device thereof. Every n rows of sub-pixels are divided into a group of sub-pixels, n≥2; in a column of sub-pixels, sub-pixels located at the same relative position in different groups of sub-pixels are connected to the same data line; a multiplexer includes a plurality of selection circuits, each selection circuit includes n*n selection units, the input ends of the selection units in the same selection circuit are all connected to the same data signal output end of the driving chip, and the data signal output ends connected to the selection units in different selection circuits are different; the selection unit includes at least m control ends, m≥n, and the selection unit is used to turn on or off according to the selection signal received by its control end, and the selection signal controls each of the selection units to be turned on in time-sharing manner. In this embodiment, the display panel can reduce the number of signal lines in the fan-out area, reduce the wiring difficulty of the display panel, and reduce the border area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) is widely used in the display field due to its fast response speed, high contrast and wide viewing angle.

[0003] However, in the existing AMOLED MUX driving scheme, the number of signal lines in the fan-out area is large, which makes the display panel wiring difficult and the border area large. Summary of the invention

[0004] The present invention provides a display panel and a driving method thereof, and a display device, so as to reduce the number of signal lines in a fan-out area, reduce the wiring difficulty of the display panel, and reduce the area of ​​a frame.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising: a display area and a non-display area at least partially surrounding the display area, wherein the display area is provided with a plurality of sub-pixels and a plurality of data lines; and the non-display area is provided with a multiplexer and a plurality of shift registers;

[0006] Each continuous or non-continuous n rows of sub-pixels are divided into a group of sub-pixels, each group of sub-pixels is connected to one shift register, and n≥2; each sub-pixel is connected to one data line, and in a column of sub-pixels, sub-pixels located at the same relative position in different groups of sub-pixels are connected to the same data line;

[0007] The multiplexer includes a plurality of selection circuits, each of which includes n*n selection units, the input ends of the selection units in the same selection circuit are all connected to the same data signal output end of the driver chip, the selection units in different selection circuits are connected to different data signal output ends of the driver chip, and the output end of each selection unit is connected to the corresponding data line; the selection unit includes at least m control ends, m≥n, and the selection unit is used to turn on or off according to the selection signal received by its control end, and the selection signal is used to control each of the selection units to be turned on in time-sharing manner.

[0008] Optional, when n=2, m=n; when n>2, m>n.

[0009] Optionally, the selection units of different selection circuits are arranged in the same manner.

[0010] Optionally, n=2, each of the selection circuits includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the first selection unit, the second selection unit, the third selection unit and the fourth selection unit all include a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to a data signal output terminal of the driving chip, a second electrode of the first transistor is electrically connected to a first electrode of the second transistor, a second electrode of the second transistor is electrically connected to a corresponding data line, and the gates of the first transistor and the second transistor of the same selection unit are connected to different selection signals;

[0011] The first transistor of the first selection unit, the second transistor of the first selection unit, the first transistor of the second selection unit and the second transistor of the third selection unit are all transistors of the first channel type, the second transistor of the second selection unit, the first transistor of the third selection unit, the first transistor of the fourth selection unit and the second transistor of the fourth selection unit are all transistors of the second channel type, the gates of the second transistor of the first selection unit, the second transistor of the second selection unit, the second transistor of the third selection unit and the second transistor of the fourth selection unit are all connected to the first selection signal, and the gates of the first transistor of the first selection unit, the first transistor of the second selection unit, the first transistor of the third selection unit and the first transistor of the fourth selection unit are all connected to the second selection signal.

[0012] Optionally, the display panel further includes at least m selection control lines, wherein the selection control lines are used to provide a selection signal to the control end of the selection unit, and one control end of each selection unit is connected to one selection control line. Different control ends in the same selection unit are connected to different selection control lines, and control ends at the same relative position in different selection units are connected to the same selection control line.

[0013] Optionally, in the data lines connected to a column of sub-pixels, the sub-pixels connected to each data line have the same color.

[0014] Optionally, the colors of the sub-pixels in different groups are arranged in the same manner.

[0015] Optionally, the display panel further comprises a plurality of gate lines, each of the shift registers is connected to one of the gate lines, and n rows of sub-pixels in a group of sub-pixels are connected to the same gate line;

[0016] Alternatively, each of the shift registers is connected to n gate lines, each row of the sub-pixels is connected to one gate line, and the n gate lines corresponding to a same group of sub-pixels are connected to the same shift register.

[0017] According to another aspect of the present invention, a method for driving a display panel is provided, for driving any one of the above-mentioned display panels, the method for driving a display panel comprising:

[0018] Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels;

[0019] When the shift register outputs a valid scanning signal, a selection signal is simultaneously provided to at least m control terminals of each selection unit of the selection circuit in a time-sharing manner, so that each selection unit is turned on in a time-sharing manner, and a data signal input to the input terminal of the selection circuit is transmitted to the corresponding sub-pixel in a time-sharing manner, wherein, at one moment, only one selection unit in a selection circuit is turned on.

[0020] According to another aspect of the present invention, a display device is provided, comprising any one of the display panels described above.

[0021] The display panel of the embodiment of the present invention includes a display area and a non-display area at least partially surrounding the display area, wherein the display area is provided with a plurality of sub-pixels and a plurality of data lines; the non-display area is provided with a multiplexer and a plurality of shift registers; each continuous or non-continuous n rows of sub-pixels are divided into a group of sub-pixels, each group of sub-pixels is connected to a shift register, n≥2; each sub-pixel is connected to a data line, and in a column of sub-pixels, sub-pixels located at the same relative position in different groups of sub-pixels are connected to the same data line; the multiplexer includes a plurality of selection circuits, each selection circuit includes n*n selection units, the input ends of the selection units belonging to the same selection circuit are all connected to the same data signal output end of the driving chip, the selection units in different selection circuits are connected to different data signal output ends of the driving chip, and the output end of each selection unit is connected to the corresponding data line; the selection unit includes at least m control ends, m≥n, the selection unit is used to turn on or off according to the selection signal received by its control end, and the selection signal is used to control each selection unit to be turned on in time-sharing manner. By setting a multiplexer, and setting the multiplexer to include multiple selection circuits, each selection circuit includes multiple selection units, and the multiple selection units included in the same selection circuit are connected to different data lines, the selection signals connected to the m control terminals in the same selection circuit are different, and the time-sharing conduction of the selection unit is realized by controlling the selection signals of the m control terminals at the same time, and then the data signal is transmitted to different sub-pixels in a time-sharing manner. Because all the selection units in the same selection circuit are connected to the data signal output terminal of the same driver chip, that is, n*n data lines only need one signal line in the fan-out area to be connected to the data signal output terminal of the driver chip, the number of signal lines in the fan-out area is saved, the wiring difficulty of the display panel is reduced, the area of ​​the fan-out area is reduced, and then the area of ​​the non-display area, i.e., the frame, is reduced. At the same time, n*n data lines only need one output terminal to realize the time-sharing writing of data signals, which reduces the number of output ports of the driver chip, and is conducive to reducing the production cost of the driver chip. At the same time, one shift register can control n rows of sub-pixels in a group, which is conducive to saving the number of shift registers and simplifying the display panel structure.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1is a schematic diagram of the structure of a display panel;

[0025] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0026] Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0027] Figure 4 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0028] Figure 5 is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0029] Figure 6 is another driving timing diagram of a display panel provided by an embodiment of the present invention;

[0030] Figure 7 is a flow chart of a method for driving a display panel provided by an embodiment of the present invention;

[0031] Figure 8 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] As described in the background art, in the prior art AMOLED MUX driving solution, the number of signal lines in the fan-out area is large, which makes it difficult to wire the display panel. Figure 1 , Figure 1 It is a structural schematic diagram of a display panel, which includes multiple sub-pixels 10, multiple data lines 11 and multiple gate lines 12. The sub-pixels 10 are arranged in an array, each row of sub-pixels 10 is connected to a gate line 12, each column of sub-pixels 10 is connected to a data line 11, and each data line 11 is correspondingly connected to a port of a driver chip 01, so that the driver chip 01 transmits a data signal to the corresponding sub-pixel 10 through the data line 11. Figure 1 The display panel exemplarily shows that it includes four rows and five columns of sub-pixels 10, and the four gate lines 12 connecting the sub-pixels 10 in the first row to the sub-pixels 10 in the fourth row are respectively used to transmit the first control signal Gate1, the second control signal Gate2, the third control signal Gate3 and the fourth control signal Gate4, and the five data lines 11 connecting the sub-pixels 10 in the first column to the sub-pixels 10 in the fifth column are respectively used to transmit the first data signal Source1, the second data signal Source2, the third data signal Source3, the fourth data signal Source4 and the fifth data signal Source5. When the display panel is working, the first control signal Gate1 first controls the sub-pixels 10 of the first row to turn on, and the first data signal Source1 to the fifth data signal Source5 write data signals to the sub-pixels of the first row respectively, and then the second control signal Gate2, the third control signal Gate3 and the fourth control signal Gate4 control the sub-pixels 10 of the second row to turn on, the sub-pixels 10 of the third row to turn on and the sub-pixels 10 of the fourth row to turn on respectively, and the first data signal Source1 to the fifth data signal Source5 write data signals to the sub-pixels 10 of the second row, the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row respectively. In this scheme, each row of sub-pixels 10 uses a corresponding control signal, and each column of sub-pixels 10 uses a corresponding data signal, that is, each column of sub-pixels 10 corresponds to a port of a driver chip, and each column of sub-pixels 10 has a signal line in the fan-out area 02 to connect to the corresponding port on the driver chip 01. The ports of the driver chip 01 corresponding to sub-pixels 10 in different columns are different, resulting in a large number of signal lines in the fan-out area 02, and a large length of the fan-out area 02 along the row direction of the sub-pixels 10 in the display panel. The fan-out area 02 is generally arranged at the lower frame of the display panel, which leads to a large area of ​​the lower frame, which is not conducive to the miniaturization of the display panel.

[0035] In view of the above technical problem, the present invention provides a new type of display panel. Figure 2 A schematic diagram of a display panel according to an embodiment of the present invention is provided. Figure 2The display panel includes a display area AA and a non-display area NAA at least partially surrounding the display area AA, the display area AA is provided with a plurality of sub-pixels 10 and a plurality of data lines 11; the non-display area NAA is provided with a multiplexer 13 and a plurality of shift registers 14;

[0036] Each continuous or non-continuous n rows of sub-pixels 10 are divided into a group of sub-pixels 10, each group of sub-pixels 10 is connected to a shift register 14, n≥2; each sub-pixel 10 is connected to a data line 11, and in a column of sub-pixels 10, sub-pixels 10 at the same relative position in different groups of sub-pixels 10 are connected to the same data line 11;

[0037] The multiplexer 13 includes a plurality of selection circuits 131, each selection circuit 131 includes n*n selection units 1311, the input ends of the selection units 1311 in the same selection circuit 131 are all connected to the same data signal output end of the driver chip 01, the selection units 1311 in different selection circuits 131 are connected to different data signal output ends of the driver chip 01, and the output end of each selection unit 1311 is connected to the corresponding data line 11; the selection unit 1311 includes at least m control ends, m≥n, and the selection unit 1311 is used to turn on or off according to the selection signal received by its control end, and the selection signal is used to control each selection unit 1311 to be turned on in a time-sharing manner.

[0038] The display area AA is the area in the display panel where the image is displayed. The display area AA is provided with a plurality of sub-pixels 10. For example, the sub-pixels include red sub-pixels R, green sub-pixels G, and blue sub-pixels B. Sub-pixels 10 of different colors are written with different data signals via correspondingly connected data lines 11 to cooperate with the image display. The non-display area NAA may be the border area of ​​the display panel. A multiplexer 13 and a shift register 14 are provided in the non-display area NAA to avoid affecting the light emitted in the display area AA.

[0039] In this embodiment, four rows and four columns of sub-pixels 10 are exemplarily shown, and each continuous or non-continuous n rows of sub-pixels 10 are divided into a group of sub-pixels 10. For example, when n=2, the sub-pixels of the first and second rows are divided into one group, and the sub-pixels of the third and fourth rows are divided into another group, or the sub-pixels of the first and third rows are divided into one group, and the sub-pixels of the second and fourth rows are divided into one group. Exemplarily, the display panel includes a first group of sub-pixels and a second group of sub-pixels. The sub-pixels 10 located at the same relative position in the sub-pixels 10 of different groups can be understood as that the number of rows and columns of the sub-pixels 10 at a certain position in the first group of sub-pixels relative to the first group of sub-pixels are the same as the number of rows and columns of the sub-pixels at the corresponding position in the second group of sub-pixels relative to the second group of sub-pixels. For example, the sub-pixels 10 in the first and second rows are divided into one group, and the sub-pixels 10 in the third and fourth rows are divided into another group. The sub-pixels 10 in the first row and the first column are located at a row number of 1 and a column number of 1 relative to the sub-pixels 10 in the group, and the sub-pixels 10 in the first row and the first column are located at a row number of 1 and a column number of 1 relative to the sub-pixels 10 in the group. Therefore, the sub-pixels 10 in the first row and the first column and the sub-pixels in the first row and the first column belong to sub-pixels 10 in the same relative position in different groups of sub-pixels 10. When the sub-pixels 10 in the first and second rows are one group, and the sub-pixels 10 in the third and fourth rows are one group, the sub-pixels 10 in the first row and the sub-pixels 10 in the third row of each column of sub-pixels 10 can be connected to the same data line 11, and the sub-pixels in the second row and the sub-pixels 10 in the fourth row of each column of sub-pixels can be connected to the same data line 11. Alternatively, the first and third rows of sub-pixels 10 are a group, and the second and fourth rows of sub-pixels 10 are a group, and the sub-pixels 10 of the first row and the sub-pixels of the second row of each column of sub-pixels 10 can be connected to the same data line 11, and the sub-pixels of the third row and the sub-pixels of the fourth row of each column of sub-pixels 10 can be connected to the same data line 11. When n is 3 or more, the above rules are followed and so on, and this embodiment is not repeated here. The shift register 14 is used to transmit a control signal to each corresponding group of sub-pixels to control the corresponding group of sub-pixels 10 to turn on, so as to facilitate the subsequent writing of data signals. Optionally, the driving chip is used to simultaneously provide a selection signal to at least m control terminals of each selection unit 1311 of the selection circuit 131 in a time-sharing manner, so that each selection unit 1311 is turned on in a time-sharing manner, and the data signal input to the input terminal of the selection circuit 131 is transmitted to the corresponding sub-pixel 10 in a time-sharing manner, wherein, at a moment, only one selection unit 1311 in a selection circuit 131 is turned on. At a moment, a certain selection unit 1311 in a selection circuit 131 is turned on under the control of a selection signal, and the turned-on selection unit 1311 transmits the data signal to the corresponding sub-pixel 10 via the data line 11 connected to itself.

[0040] In this embodiment, the first and second rows of sub-pixels 10 are a group of sub-pixels, the third and fourth rows of sub-pixels 10 are a group of sub-pixels, and the sub-pixels 10 of the first row and the sub-pixels 10 of each column of sub-pixels 10 are connected to the same data line 11, and the sub-pixels 10 of the second row and the sub-pixels 10 of each column of sub-pixels 10 are connected to the same data line 11. In this embodiment, two selection circuits 131 are included, each selection circuit 131 corresponds to an output terminal of the driver chip 01, and the two output terminals of the driver chip 01 in this embodiment are respectively used to transmit the first data line signal Source1 and the second data signal Source2. As an optional way, the selection signals connected to the at least m control terminals included in each selection unit 1311 can be different. When the display panel is working, the shift registers 14 corresponding to the first and second rows of sub-pixels 10 control the sub-pixels 10 of the first and second rows to turn on, and the shift registers 14 corresponding to the sub-pixels 10 of the third and fourth rows to control the sub-pixels 10 of the third and fourth rows to turn off. During the period when the sub-pixels 10 in the first and second rows are turned on, the selection unit 1311 corresponding to the sub-pixels 10 in the first row and the first column and the selection unit 1311 corresponding to the sub-pixels 10 in the first row and the third column can be turned on by the selection signal, so as to transmit the first data signal Source1 outputted from the output end of the driving core 01 to the sub-pixels 10 in the first row and the first column, and transmit the second data signal Source2 to the sub-pixels 10 in the first row and the third column. Then, the selection unit 1311 corresponding to the sub-pixels 10 in the first row and the second column and the selection unit 1311 corresponding to the sub-pixels 10 in the first row and the fourth column can be turned on by the selection signal, so as to transmit the first data signal Source1 to the sub-pixels 10 in the first row and the second data signal Source1 to the sub-pixels 10 in the first row and the fourth column. Then, the selection unit 1311 corresponding to the sub-pixel 10 in the first column of the second row and the selection unit 1311 corresponding to the sub-pixel 10 in the third column of the second row are controlled to be turned on by the selection signal, so as to transmit the first data signal Source1 to the sub-pixel 10 in the first column of the second row and the second data signal Source2 to the sub-pixel 10 in the third column of the second row. Finally, the selection unit 1311 corresponding to the sub-pixel 10 in the second column of the second row and the selection unit 1311 corresponding to the sub-pixel 10 in the fourth column of the second row are controlled to be turned on by the selection signal, so as to transmit the first data signal Source1 to the sub-pixel 10 in the second column of the second row and the second data signal Source2 to the sub-pixel 10 in the fourth column of the second row. After the data signal is written into the sub-pixels 10 in the first and second rows, the sub-pixels 10 in the first and second rows are controlled to be turned off and the sub-pixels 10 in the third and fourth rows are controlled to be turned on, so as to write the data signal to the sub-pixels 10 in the third and fourth rows in time division. The specific process is the same as the writing process of the first and second rows, which will not be repeated here. Finally, the data signal is written into the sub-pixel 10 in a time-division manner by time-division conduction of the selection unit 1311 .In this embodiment, there are two signal lines in the fan-out area 02 for the sub-pixels of four rows and four columns, compared with the prior art, such as. Figure 1 In the display panel, the sub-pixels have four rows and four columns, and the fan-out area 02 includes four signal lines, which greatly reduces the number of signal lines in the fan-out area 02 of the display panel.

[0041] By setting a multiplexer, and setting the multiplexer to include multiple selection circuits, each selection circuit includes multiple selection units, and the multiple selection units included in the same selection circuit are connected to different data lines, the selection signals connected to the m control terminals in the same selection circuit are different, and the time-sharing conduction of the selection unit is realized by controlling the selection signals of the m control terminals at the same time, and then the data signal is transmitted to different sub-pixels in a time-sharing manner. Because the selection units in the same selection circuit are all connected to the data signal output terminal of the same driver chip, that is, n*n data lines only need one signal line in the fan-out area to be connected to the data signal output terminal of the driver chip, the number of signal lines in the fan-out area is saved, the wiring difficulty of the display panel is reduced, the area of ​​the fan-out area is reduced, and then the area of ​​the non-display area, i.e., the frame, is reduced. At the same time, n*n data lines only need one output terminal to realize the time-sharing writing of data signals, which reduces the number of output ports of the driver chip, and is conducive to reducing the production cost of the driver chip. At the same time, one shift register can control n rows of sub-pixels in a group, which is conducive to saving the number of shift registers and simplifying the display panel structure.

[0042] Continue to refer Figure 2 Optionally, the selection units 1311 of different selection circuits 131 are arranged in the same manner.

[0043] by Figure 2Taking the display panel including four rows and four columns of sub-pixels 10 as an example, the display panel includes two selection circuits 131, each selection circuit 131 includes four selection units 1311, and the four selection units 1311 are arranged in staggered rows. Specifically, taking the selection circuits 131 corresponding to the sub-pixels 10 in the first column and the second column as an example, the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the first column, the first row and the first column and the third row are located in the first row of the setting area of ​​the selection circuit 131, the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the second column, the first row and the second column and the third row are located in the second row of the setting area of ​​the selection circuit 131, the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the first column, the second row and the first column and the fourth row are located in the third row of the setting area of ​​the selection circuit 131, and the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the second column, the second row and the second column and the fourth row are located in the fourth row of the setting area of ​​the selection circuit 131. The arrangement of the four selection units 1311 included in another selection circuit 131 is the same. The arrangement of the n*n selection units 1311 included in different selection circuits 131 is the same, which can make the layout devices and signal lines of the display panel distributed regularly, which is conducive to simplifying the manufacturing process of the display panel.

[0044] Continue to refer Figure 2 Optionally, in the data lines 11 corresponding to a column of sub-pixels 10, the sub-pixels 10 connected to each data line 11 have the same color. Since the relationship between the grayscale and the data voltage corresponding to the sub-pixels 10 of different colors is different, it is necessary to output data voltages to the sub-pixels 10 of different colors based on different references. In the display panel of this embodiment, in a column, the sub-pixels 10 connected to each data line 11 have the same color, and the output data voltage output by the driver chip 01 to one data line 11 can be based on the same reference, which is conducive to simplifying the internal program of the driver chip 01.

[0045] Continue to refer Figure 2 Optionally, the colors of the sub-pixels 10 in different groups are arranged in the same manner.

[0046] In this embodiment, Figure 2Taking the structure of the display panel shown as an example, it is exemplarily shown that the sub-pixels 10 in the first row and the first column and the sub-pixels 10 in the first row and the third column are all red sub-pixels R, the sub-pixels 10 in the first column and the second row and the sub-pixels 10 in the first column and the fourth row are blue sub-pixels B, the four sub-pixels in the second column are all green sub-pixels G, the sub-pixels 10 in the third column and the first row and the third row are all blue sub-pixels B, the sub-pixels 120 in the third column and the second row and the sub-pixels 10 in the third column and the fourth row are all red sub-pixels R, and the sub-pixels 10 in the fourth column are all green sub-pixels G. Since the relationship between the grayscale and the data voltage corresponding to the sub-pixels 10 of different colors is different, it is necessary to output the data voltage to the sub-pixels 10 of different colors based on different references. In the display panel of this embodiment, the color arrangement of the sub-pixels 10 of different groups connected to each selection circuit 131 is the same. When the driver chip 01 outputs the data voltage to the selection circuit 131 connected to each output terminal, the change rule of the relationship between the grayscale and the data voltage is the same, which is also conducive to simplifying the internal program of the driver chip 01.

[0047] Continue to refer Figure 2 Optionally, the display panel further includes a plurality of gate lines 12 , each shift register 14 is connected to a gate line 12 , and n rows of sub-pixels 10 in a group of sub-pixels 10 are connected to the same gate line 12 .

[0048] by Figure 2 For example, the display panel includes two gate lines 12, one gate line 12 connects the sub-pixels 10 in the first row and the second row, and is used to transmit the first control signal Gate1. The other gate line 12 connects the sub-pixels 10 in the third row and the fourth row, and is used to transmit the second control signal Gate2. The shift register 14 transmits a signal to the sub-pixels 10 in the corresponding row through the corresponding gate line 12 to control the sub-pixels 10 in the corresponding row to turn on or off.

[0049] Figure 3 A schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 3 Optionally, each shift register 14 is connected to n gate lines 12 , each row of sub-pixels 10 is connected to a gate line 12 , and the n gate lines 12 corresponding to the same group of sub-pixels 10 are connected to the same shift register 14 .

[0050] Figure 3 The display panel shown is Figure 2 The difference is that each row of sub-pixels 10 is connected to a corresponding gate line 12, and the n gate lines 12 connected to the sub-pixels 10 in the same group are connected to the same shift register 14, that is, the signals on the n gate lines 12 connected to the sub-pixels 10 in the same group are the same. Figure 3The gate lines 12 connected to the sub-pixels 10 in the first row and the gate lines 12 connected to the sub-pixels 10 in the second row are both used to transmit the first control signal Gate1, and the gate lines 12 connected to the sub-pixels 10 in the third row and the gate lines 12 connected to the sub-pixels 10 in the fourth row are both used to transmit the second control signal Gate2.

[0051] Figure 4 A schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 4 , optionally, n=2, each selection circuit 131 includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the first selection unit, the second selection unit, the third selection unit and the fourth selection unit all include a first transistor and a second transistor, the first electrode of the first transistor is electrically connected to the output end of the driving chip 01, the second electrode of the first transistor is electrically connected to the first electrode of the second transistor, the second electrode of the second transistor is electrically connected to the corresponding data line 11, and the gates of the first transistor and the second transistor of the same selection unit are connected to different selection signals;

[0052] The first transistor T1 of the first selection unit, the second transistor T2 of the first selection unit, the first transistor T3 of the second selection unit and the second transistor T6 of the third selection unit are all transistors of the first channel type, the second transistor T4 of the second selection unit, the first transistor T5 of the third selection unit, the first transistor T7 of the fourth selection unit and the second transistor T8 of the fourth selection unit are all transistors of the second channel type, the gates of the second transistor T2 of the first selection unit, the second transistor T4 of the second selection unit, the second transistor T6 of the third selection unit and the second transistor T8 of the fourth selection unit are all connected to the first selection signal MUX1, and the gates of the first transistor T1 of the first selection unit, the first transistor T3 of the second selection unit, the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit are all connected to the second selection signal MUX2.

[0053] The first transistors included in each selection unit 1311 are all located in the same row, the second transistors included in each selection unit 1311 are all located in the same row, and the first transistor and the second transistor included in the same selection unit 1311 are located in different rows. Exemplarily, the transistor of the first channel type may be a P-type transistor, and the transistor of the second channel type may be an N-type transistor.

[0054] Continue to refer Figure 4Optionally, the display panel further includes at least m selection control lines 15, the selection control lines 15 are used to provide a selection signal to the control end of the selection unit 1311, one control end of each selection unit 1311 is connected to a selection control line 15, different control ends in the same selection unit 1311 are connected to different selection control lines 15, and control ends at the same relative position in different selection units 1311 are connected to the same selection control line 15. Optionally, when n=2, m=n; when n>2, m>n.

[0055] When n=2, the display panel includes at least two selection control lines 15. In this embodiment, when n=2, two selection control lines 15 are included, one for transmitting the first selection signal MUX1, and the other selection control line 15 for transmitting the second selection signal MUX2. The first selection signal MUX1 and the second selection signal MUX2 jointly control different selection units 1311 in the selection circuit 131 to be turned on in time division, so as to write data signals to the sub-pixels 10 in the display panel in time division.

[0056] When n>2, for example, when n=3, each sub-pixel group includes 9 sub-pixels 10, and a selection circuit 131 is used to control the time-sharing writing of data signals to the 9 sub-pixels 10. The corresponding selection circuit 131 includes 9 selection units 1311. If m=3, that is, the selection unit 1311 includes 3 control terminals, and correspondingly, each selection unit 1311 includes three transistors, the types of transistors included in the selection unit 1311 and the positions of the transistors are different, and there are 8 transistor arrangements in the selection unit 1311. Accordingly, the three control terminals of each selection unit 1311 of the same selection circuit 131 are simultaneously provided with a selection signal, and only the data writing of 8 sub-pixels 10 can be realized in a time-sharing manner. Therefore, at this time, the three selection control lines 15 cannot write data signals to the 9 sub-pixels 10 in a time-sharing manner through the 9 selection units 1311. Therefore, when n=3, the number of the selection control lines 15 should be greater than 3. Exemplarily, when n=3, m=4, at this time, each selection unit 1311 includes four transistors, and in the same selection circuit 131, different selection units 1311 are different, that is, among the 9 selection units 1311, there are no two selection units 1311, wherein the channel types of the four transistors included in one selection unit 1311 and the four transistors in the corresponding positions of another selection unit 1311 are the same. Exemplarily, the display panel includes four selection control lines, the first selection control line is used to transmit a first selection signal, the second selection control line is used to transmit a second selection signal, the third selection control line is used to transmit a third selection signal, and the fourth selection control line is used to transmit a fourth selection signal, and the four selection control lines are arranged in sequence along the column direction of the sub-pixels 120. Therefore, according to the type of transistors included in the selection unit 1311 and the position of the transistors, there can be 16 different forms of arrangement, and only 9 of the 16 forms need to be selected to form 9 different selection units 1311 of a selection circuit 131. Exemplarily, the arrangement of the transistors of the nine selection units 1311 is N-type transistor, N-type transistor, N-type transistor, N-type transistor; N-type transistor, P-type transistor, P-type transistor, P-type transistor; P-type transistor, N-type transistor, P-type transistor, P-type transistor; P-type transistor, P-type transistor, N-type transistor, P-type transistor; P-type transistor, P-type transistor, P-type transistor, N-type transistor; N-type transistor, N-type transistor, P-type transistor, P-type transistor; N-type transistor, P-type transistor, N-type transistor, P-type transistor; N-type transistor, P-type transistor, P-type transistor, N-type transistor; P-type transistor, P-type transistor, N-type transistor, N-type transistor. It is worth noting that the four transistors in the above order from front to back are respectively connected to the first selection control line to the fourth selection control line in sequence. Figure 5 A driving timing diagram of a display panel provided by an embodiment of the present invention, Figure 5 The drive timing diagram shown applies to Figure 4 The display panel shown. Figure 4 In the embodiment, the first transistor T1 of the first selection unit, the second transistor T2 of the first selection unit, the first transistor T3 of the second selection unit and the second transistor T6 of the third selection unit are all P-type transistors, and the second transistor T4 of the second selection unit, the first transistor T5 of the third selection unit, the first transistor T7 of the fourth selection unit and the second transistor T8 of the fourth selection unit are all N-type transistors.

[0057] refer to Figure 4 and Figure 5, taking the first writing stage t1 of the display panel as an example, in the first writing stage t1, the first control signal Gate1 is at a low level, and the second control signal Gate2 is at a high level. In the first writing stage t1, the first control signal Gate1 controls the sub-pixels 10 of the first row and the sub-pixels 10 of the second row to be turned on, and the second control signal Gate2 controls the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row to be turned off. The first writing stage t1 includes a first sub-stage t11, a second sub-stage t12, a third sub-stage t13, and a fourth sub-stage t14. In the first sub-stage t1, the first selection signal MUX1 is at a low level, and the second selection signal MUX2 is at a low level. The first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to be turned on, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to be turned off. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to be turned on, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to be turned off. The first data signal Source1 is written into the sub-pixel 10 of the first row and the first column through the first transistor T1 of the first selection unit and the second transistor T2 of the first selection unit that are turned on. In the second sub-stage t2, the first selection signal MUX1 is at a low level, and the second selection signal MUX2 is at a high level. The first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to be turned on, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to be turned off. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to be turned off, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to be turned on. The first data signal Source1 is written into the sub-pixel 10 of the first row and the second column through the first transistor T5 of the third selection unit and the second transistor T6 of the third selection unit that are turned on. In the third sub-phase t3, the first selection signal MUX1 is at a high level, and the second selection signal MUX2 is at a low level. The first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to be turned off, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to be turned on. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to be turned on, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to be turned off. The first data signal Source1 is written into the sub-pixel 10 of the second row and the first column via the turned-on first transistor T3 of the second selection unit and the second transistor T4 of the second selection unit.In the fourth sub-phase t4, the first selection signal MUX1 is at a high level, the second selection signal MUX2 is at a high level, the first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to be turned off, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to be turned on. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to be turned off, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to be turned on. The first data signal Source1 is written into the sub-pixel 10 of the second row and the second column through the turned-on first transistor T7 of the fourth selection unit and the second transistor T8 of the fourth selection unit. It is worth noting that in this embodiment, only the working process of the selection circuit 131 connected to the first data signal Source1 is taken as an example. All the selection circuits 131 included in the multiplexer 13 work simultaneously, and the working process is the same as above, that is, in the first sub-stage t1, the first data signal Source1 is written into the sub-pixel 10 of the first row and the first column, and the second data signal Source2 is written into the sub-pixel 10 of the first row and the third column. In the second sub-stage t2, the first data signal Source1 is written into the sub-pixel 10 of the first row and the second data signal Source2 is written into the sub-pixel 10 of the first row and the fourth column. In the third sub-stage t3, the first data signal Source1 is written into the sub-pixel 10 of the second row and the first column, and the second data signal Source2 is written into the sub-pixel 10 of the second row and the third column. In the fourth sub-stage t4, the first data signal Source1 is written into the sub-pixel 10 of the second row and the second data signal Source2 is written into the sub-pixel 10 of the second row and the fourth column. In this embodiment, the sub-pixels 10 of the first row and the second row are written with data signals in a time-sharing manner through the above 16 transistors. The working process of the display panel also includes a second writing stage. The difference between the second writing stage and the first writing stage t1 is that the first control signal Gate1 is at a high level and the second control signal Gate2 is at a low level. In the second writing stage, the first control signal Gate1 controls the sub-pixels 10 of the first row and the sub-pixels 10 of the second row to be turned off, and the second control signal Gate2 controls the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row to be turned on. The other processes are the same as the first writing stage and will not be repeated here, so as to realize the time-sharing writing of data signals to the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row.

[0058] Figure 6 Another driving timing diagram of a display panel provided by an embodiment of the present invention, Figure 6 The timing diagram shown also applies to Figure 4The display panel shown. In the first sub-stage t1, the first selection signal MUX1 is at a low level, the second selection signal MUX2 is at a low level, the first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to turn on, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to turn off. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to turn on, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to turn off. The first data signal Source1 is written into the sub-pixel 10 of the first row and the first column through the first transistor T1 of the first selection unit and the second transistor T2 of the first selection unit that are turned on. In the second sub-stage t2, the first selection signal MUX1 is at a high level, the second selection signal MUX2 is at a low level, the first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to turn off, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to turn on. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to be turned on, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to be turned off. The first data signal Source1 is written into the sub-pixel 10 of the second row and the first column through the first transistor T3 of the second selection unit and the second transistor T4 of the second selection unit that are turned on. In the third sub-stage t3, the first selection signal MUX1 is at a low level, and the second selection signal MUX2 is at a high level. The first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to be turned on, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to be turned off. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to be turned off, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to be turned on. The first data signal Source1 is written into the sub-pixel 10 of the first row and the second column through the first transistor T5 of the third selection unit and the second transistor T6 of the third selection unit that are turned on. In the fourth sub-phase t4, the first selection signal MUX1 is at a high level, the second selection signal MUX2 is at a high level, the first selection signal MUX1 controls the second transistor T2 of the first selection unit and the second transistor T6 of the third selection unit to be turned off, and controls the second transistor T4 of the second selection unit and the second transistor T8 of the fourth selection unit to be turned on. The second selection signal MUX2 controls the first transistor T1 of the first selection unit and the first transistor T3 of the second selection unit to be turned off, and controls the first transistor T5 of the third selection unit and the first transistor T7 of the fourth selection unit to be turned on.The first data signal Source1 is written into the sub-pixel 10 in the second row and the second column via the first transistor T7 of the fourth selection unit and the second transistor T8 of the fourth selection unit. It is worth noting that in this embodiment, only the working process of the selection circuit 131 connected to the first data signal Source1 is taken as an example, and all the selection circuits 13 included in the multiplexer 13 work simultaneously, and the working process is the same as above, that is, in the first sub-stage t1, the first data signal Source1 is written into the sub-pixel 10 in the first row and the first column, and the second data signal Source2 is written into the sub-pixel 10 in the first row and the third column, in the second sub-stage t2, the first data signal Source1 is written into the sub-pixel 10 in the second row and the first column, and the second data signal Source2 is written into the sub-pixel 10 in the second row and the third column, in the third sub-stage t3, the first data signal Source1 is written into the sub-pixel 10 in the first row and the second data signal Source2 is written into the sub-pixel 10 in the first row and the fourth column, and in the fourth sub-stage t4, the first data signal Source1 is written into the sub-pixel 10 in the second row and the second data signal Source2 is written into the sub-pixel 10 in the second row and the fourth column. In this embodiment, the 16 transistors are used to write the data signals to the sub-pixels 10 in the first row and the second row in a time-sharing manner. The operation process of the display panel also includes a second writing stage. The difference between the second writing stage and the first writing stage t1 is that the first control signal Gate1 is at a high level and the second control signal Gate2 is at a low level. In the second writing stage, the first control signal Gate1 controls the sub-pixels 10 in the first row and the sub-pixels 10 in the second row to be turned off, and the second control signal Gate2 controls the sub-pixels 10 in the third row and the sub-pixels 10 in the fourth row to be turned on. The other processes are the same as those in the first writing stage and will not be repeated here, so as to realize the time-sharing writing of the data signals to the sub-pixels 10 in the third row and the sub-pixels 10 in the fourth row.

[0059] The above takes the working process of the display panel when n=2 as an example. When n=3, the display panel may include 4 selection control lines, and each selection unit may include four transistors connected in series. The 4 selection control lines are used to jointly control the time-sharing conduction of different selection units in the same selection circuit, thereby writing the data signal into the sub-pixel 10 in a time-sharing manner.

[0060] The embodiment of the present invention further provides a method for driving a display panel. Figure 7 A flow chart of a method for driving a display panel provided in an embodiment of the present invention, wherein the display panel is used to drive the display panel described above, and the method for driving the display panel includes:

[0061] S10: Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels.

[0062] The effective scanning signal is a signal that turns on the sub-pixel. Figure 2 In the display panel shown, the shift registers 14 corresponding to the sub-pixels 10 in the first and second rows first output valid scan signals to control the sub-pixels 10 in the first and second rows to turn on. After the sub-pixels 10 in the first and second rows complete writing of data signals, the shift registers 14 corresponding to the sub-pixels 10 in the third and fourth rows then output valid scan signals to control the sub-pixels 10 in the third and fourth rows to turn on, thereby completing writing of data signals to the sub-pixels 10 in the third and fourth rows.

[0063] S20: When the shift register outputs a valid scan signal, a selection signal is provided to at least m control terminals of each selection unit of the selection circuit in a time-sharing manner, so that each selection unit is turned on in a time-sharing manner, and the data signal input to the input terminal of the selection circuit is transmitted to the corresponding sub-pixel 10 in a time-sharing manner, wherein, at one moment, only one selection unit in a selection circuit is turned on.

[0064] When the shift register outputs a valid scanning signal, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the first row and third row of the first column, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the first row and third row of the second column, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and fourth row of the first column, and the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and fourth row of the second column can be controlled to be turned on in sequence to write data signals to the sub-pixels 10 in the first row and the second row in time. Alternatively, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the first row and the third row of the first column, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and the fourth row of the first column, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the first row and the third row of the second column, and the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and the fourth row of the second column may be controlled to be turned on in sequence, so as to write data signals to the sub-pixels 10 in the first row and the second row in time division. Among them, the selection unit 1311 corresponding to the sub-pixel 10 in the first row and the third row of the first column and the selection unit 1311 corresponding to the sub-pixel 10 in the first row and the third row of the third column may be turned on at the same time. The selection unit 1311 corresponding to the sub-pixel 10 in the first row and the third row of the second column may be turned on at the same time as the selection unit 1311 corresponding to the sub-pixel 10 in the first row and the third row of the fourth column. The selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and fourth row of the first column can be turned on simultaneously with the selection unit 1311 corresponding to the sub-pixel 10 in the second row and fourth row of the third column, and the selection unit 1311 corresponding to the sub-pixel 10 in the second row and fourth row of the second column can be turned on simultaneously with the selection unit 1311 corresponding to the sub-pixel 10 in the second row and fourth row of the fourth column. Through the above control, data signals can be written to two sub-pixels in four rows and four columns of sub-pixels 10 at the same time.

[0065] The beneficial effects of this embodiment are the same as those of the display panel, and will not be described in detail here.

[0066] An embodiment of the present invention further provides a display device, Figure 8 A schematic diagram of a display device according to an embodiment of the present invention is provided. Figure 8 The display device 03 includes the display panel 04 described in any of the above embodiments. The display device 03 may be Figure 8 The mobile phone shown may also be a computer, a television, a smart wearable display device, etc., and the embodiments of the present invention do not specifically limit this.

[0067] The beneficial effects of the display device are the same as those of the display panel, and will not be described in detail in this embodiment.

[0068] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0069] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A display area and a non-display area at least partially surrounding the display area, wherein the display area is provided with a plurality of sub-pixels and a plurality of data lines; and the non-display area is provided with a multiplexer and a plurality of shift registers; Each continuous or non-continuous n rows of sub-pixels are divided into a group of sub-pixels, each group of sub-pixels is connected to one shift register, and n≥2; each sub-pixel is connected to one data line, and in a column of sub-pixels, sub-pixels located at the same relative position in different groups of sub-pixels are connected to the same data line; The multiplexer comprises a plurality of selection circuits, each of which comprises n*n selection units, the input ends of the selection units in the same selection circuit are all connected to the same data signal output end of the driver chip, the selection units in different selection circuits are connected to different data signal output ends of the driver chip, and the output end of each selection unit is connected to the corresponding data line; the selection unit comprises at least m control ends, m≥n, the selection unit is used to turn on or off according to the selection signal received by its control end, and the selection signal is used to control the time-sharing conduction of each selection unit; n=2, each of the selection circuits comprises a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the first selection unit, the second selection unit, the third selection unit and the fourth selection unit all comprise a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to a data signal output terminal of the driving chip, a second electrode of the first transistor is electrically connected to a first electrode of the second transistor, a second electrode of the second transistor is electrically connected to a corresponding data line, and the gates of the first transistor and the second transistor of the same selection unit are connected to different selection signals; The first transistor of the first selection unit, the second transistor of the first selection unit, the first transistor of the second selection unit and the second transistor of the third selection unit are all transistors of the first channel type, the second transistor of the second selection unit, the first transistor of the third selection unit, the first transistor of the fourth selection unit and the second transistor of the fourth selection unit are all transistors of the second channel type, the gates of the second transistor of the first selection unit, the second transistor of the second selection unit, the second transistor of the third selection unit and the second transistor of the fourth selection unit are all connected to the first selection signal, and the gates of the first transistor of the first selection unit, the first transistor of the second selection unit, the first transistor of the third selection unit and the first transistor of the fourth selection unit are all connected to the second selection signal.

2. The display panel according to claim 1, characterized in that: When n=2, m=n.

3. The display panel according to claim 1, characterized in that: The selection units of different selection circuits are arranged in the same manner.

4. The display panel according to claim 3, characterized in that: It also includes at least m selection control lines, which are used to provide a selection signal to the control end of the selection unit. One control end of each selection unit is connected to one selection control line. Different control ends in the same selection unit are connected to different selection control lines, and control ends at the same relative position in different selection units are connected to the same selection control line.

5. The display panel according to claim 1, characterized in that: In the data lines corresponding to the connection of the sub-pixels in a column, the sub-pixels connected to each data line have the same color.

6. The display panel according to claim 1, characterized in that: The colors of the sub-pixels in different groups are arranged in the same manner.

7. The display panel according to any one of claims 1 to 6, characterized in that: It also includes a plurality of gate lines, each of the shift registers is connected to one of the gate lines, and n rows of sub-pixels in a group of sub-pixels are connected to the same gate line; Alternatively, each of the shift registers is connected to n gate lines, each row of the sub-pixels is connected to one gate line, and the n gate lines corresponding to a same group of sub-pixels are connected to the same shift register.

8. A method for driving a display panel, characterized in that: Used to drive the display panel according to any one of claims 1 to 7, the driving method of the display panel comprising: Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels; When the shift register outputs a valid scanning signal, a selection signal is simultaneously provided to at least m control terminals of each selection unit of the selection circuit in a time-sharing manner, so that each selection unit is turned on in a time-sharing manner, and a data signal input to the input terminal of the selection circuit is transmitted to the corresponding sub-pixel in a time-sharing manner, wherein, at one moment, only one selection unit in a selection circuit is turned on.

9. A display device, characterized in that: A display panel comprising any one of claims 1 to 7.

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