Display device, display charging method
By adjusting the potential difference and phase of the scanning signal, the problem of a smooth falling edge of the scanning signal in the gate drive circuit was solved, achieving more efficient pixel charging and improving the charging effect of the display device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2022-10-11
- Publication Date
- 2026-05-19
AI Technical Summary
In display technology, the falling edge of the scan signal in the gate drive circuit is relatively flat, which reduces the charging time of the pixel and makes it impossible to achieve the ideal state.
By adjusting the timing controller and gate drive circuit, the voltage difference between different potentials of the scan signal is increased, and the phase of the scan signal is adjusted so that the falling edge of the scan signal is closer to the ideal vertical falling edge, covering more data signal pulse duration.
It improves the effective charging time of the scan signal, increases the charging time of the data signal, and improves the charging efficiency of the display device.
Smart Images
Figure CN115620657B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to a display device and a display charging method. Background Technology
[0002] In display technology, gate drive circuits are typically used to output control data signals to the scanning signal of the pixel. However, due to various reasons, the falling edge of this scanning signal is relatively flat and cannot approach or reach the ideal vertical falling edge, which seriously reduces the pixel charging time. Summary of the Invention
[0003] This application provides a display device and a display charging method to alleviate the technical problem that the relatively flat falling edge of the scan signal leads to a reduction in charging time.
[0004] In a first aspect, this application provides a display device, which includes a timing controller and a gate driving circuit. The timing controller is used to transmit a clock signal, the clock signal having an alternating and continuous first potential and a second potential, the first potential being less than the second potential. The gate driving circuit is used to output a scan signal according to the received clock signal, the scan signal having a portion of the clock signal, the scan signal changing in the order of the first potential, the second potential, and the first potential again within a first preset time period. The display device increases the voltage difference between the first potential and the second potential of the scan signal and adjusts the phase of the scan signal to improve the effective charging time of the scan signal for the corresponding pixel.
[0005] In some implementations, the timing controller changes a first potential and / or a second potential of the clock signal to increase the voltage difference between the different potentials of the clock signal.
[0006] In some implementations, the timing controller maintains the second potential of the clock signal unchanged and decreases the first potential of the clock signal.
[0007] In some embodiments, the display device is configured such that the voltage difference is positively correlated with the phase change of the clock signal.
[0008] In some implementations, the timing controller shifts the phase of the clock signal backward and / or the gate drive circuit shifts the phase of the scan signal backward.
[0009] In some embodiments, the scan signal is used to control the effective charging time of the data signal; the end time of the effective charging time is earlier than or equal to the start time of the end edge of the data signal, and the end edge is the falling edge of a positive pulse or the rising edge of a negative pulse.
[0010] In some implementations, at the beginning of the end edge and before, the scan signal controls the thin-film transistors in the pixel to be turned on in order to write the pulse amplitude of the data signal to the corresponding pixel.
[0011] In some embodiments, the display device further includes a first low-potential line for transmitting a first low-potential signal; the scan signal also includes a portion of the first low-potential signal before and after a first preset time period.
[0012] In some embodiments, the first low-potential signal has a third potential, which is greater than the first potential and less than the second potential; the scanning signal has a third potential during a second preset time period, and the second preset time period and the first preset time period alternate continuously in time.
[0013] Secondly, this application provides a display charging method, which includes: a gate driving circuit outputting a corresponding scanning signal according to an input clock signal, the clock signal having an alternating continuous first potential and a second potential, the first potential being less than the second potential; configuring the scanning signal to have a portion of the clock signal, the scanning signal changing in the order of the first potential, the second potential, and the first potential again within a first preset time period; the display device increasing the voltage difference between the first potential and the second potential of the scanning signal, and adjusting the phase of the scanning signal to improve the effective charging time of the scanning signal for the corresponding pixel.
[0014] The display device and display charging method provided in this application can make the falling edge of the scanning signal closer to the ideal vertical falling edge by increasing the voltage difference between different potentials of the scanning signal. At the same time, by adjusting the phase of the scanning signal in terms of timing, the pulse duration of the scanning signal can cover more of the pulse duration of the data signal, thereby increasing the effective charging time of the data signal. Attached Figure Description
[0015] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0016] Figure 1 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.
[0017] Figure 2 for Figure 1 A schematic diagram of the gate driving unit in the gate driving circuit.
[0018] Figure 3 for Figure 2 The timing diagram of the gate drive unit is shown.
[0019] Figure 4 for Figure 3The waveform diagram of the scanning signal in the related technology is shown.
[0020] Figure 5 This is a schematic diagram of charging under ideal conditions provided for an embodiment of this application.
[0021] Figure 6 This is a schematic diagram of charging in related technologies.
[0022] Figure 7 This is a waveform diagram of the scanning signal provided in an embodiment of this application.
[0023] Figure 8 In order to be in Figure 7 The diagram shows a charging process controlled by a scanning signal.
[0024] Figure 9 In order to be in Figure 8 The diagram shows the charging process after phase shifting.
[0025] Figure 10 This is a schematic diagram illustrating the relationship between the effective charging time and the absolute value of the first potential, as provided in the embodiments of this application.
[0026] Figure 11 Based on Figure 6 The diagram shows the charging time distribution under the given charging effect.
[0027] Figure 12 Based on Figure 9 The diagram shows the charging time distribution under the given charging effect.
[0028] Figure 13 This is a schematic diagram of a pixel-driven architecture provided in an embodiment of this application.
[0029] Figure 14 This is a schematic diagram of another pixel-driven architecture provided in an embodiment of this application. Detailed Implementation
[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0031] In view of the aforementioned technical problem of reduced charging time due to the relatively flat falling edge of the scan signal, this embodiment provides a display device. Please refer to [link to relevant documentation]. Figures 1 to 14 ,like Figure 1 , Figure 3 , Figure 4 as well as Figure 7As shown, the display device includes a timing controller 100, a clock line 200, and a gate driving circuit 300. One end of the clock line 200 is connected to the timing controller 100, and the other end of the gate driving circuit 300 is connected to the clock line 200. The timing controller 100 is used to send a clock signal CK(N). The clock line 200 is used to transmit the clock signal CK(N). The gate driving circuit 300 may include multiple cascaded gate driving units 310. Each gate driving unit 310 is used to output a corresponding scan signal Gate(N) according to the input clock signal CK(N). The scan signal Gate(N) has a portion of the clock signal CK(N). The clock signal CK(N) has an alternating and continuous first potential V1 and a second potential V2, where the first potential V1 is smaller than the second potential V2. The scan signal Gate(N) changes in the order of the first potential V1, the second potential V2, and the first potential V1 again within a first preset time period. The display device increases the voltage difference between the first and second potentials of the scan signal Gate(N) and adjusts the phase of the scan signal Gate(N) to improve the effective charging time of the scan signal Gate(N) for the corresponding pixel.
[0032] It is understood that the display device provided in this embodiment can make the falling edge of the scanning signal Gate(N) closer to the ideal vertical falling edge by increasing the voltage difference between different potentials of the scanning signal Gate(N). At the same time, by adjusting the phase of the scanning signal Gate(N) in timing, the pulse duration of the scanning signal Gate(N) can cover more of the pulse duration of the data signal Data, thereby increasing the effective charging time of the data signal Data.
[0033] It should be noted that the voltage difference between the first potential V1 and the second potential V2 of the scan signal Gate(N) in the display device can be achieved by the timing controller 100 changing the first potential V1 and / or the second potential V2 of the clock signal CK(N). For example, the voltage difference of the scan signal Gate(N) can be increased by increasing the second potential V2 of the clock signal CK(N) while decreasing the first potential V1, or by maintaining the second potential V2 of the clock signal CK(N) while decreasing the first potential V1, or by increasing the second potential V2 of the clock signal CK(N) while maintaining the first potential V1.
[0034] In one embodiment, the gate driving unit 310 includes a first transistor T21, one of the source / drain of the first transistor T21 is connected to the clock line 200, the gate of the first transistor T21 is connected to the first node Q(N), and the other of the source / drain of the first transistor T21 is connected to the scan line; wherein the scan line is used to transmit the scan signal Gate(N).
[0035] It should be noted that in this embodiment, the first transistor T21 not only transmits the first potential V1 of the clock signal CK(N) as part of the scan signal Gate(N), but also transmits the second potential V2 of the clock signal CK(N) as part of the scan signal Gate(N). In this way, by adjusting the voltage difference between different potentials of the clock signal CK(N), the voltage difference between the first potential V1 and the second potential V2 of the scan signal Gate(N) can be changed accordingly, so that the falling edge of the scan signal Gate(N) is closer to the vertical shape.
[0036] In one embodiment, the gate driving unit 310 further includes a second transistor T32, one of the source / drain of the second transistor T32 is connected to the other of the source / drain of the first transistor T21 and the scan line, the other of the source / drain of the second transistor T32 is connected to a first low-potential line, and the gate of the second transistor T32 is connected to a second node; wherein the potential of the first node Q(N) is either a high potential or a low potential, and the potential of the second node is either a high potential or a low potential; the first low-potential line is used to transmit a first low-potential signal VSSG, the third potential V3 of the first low-potential signal VSSG is greater than the first potential V1 and less than the second potential V2; the scan signal Gate(N) has the third potential V3, the first potential V1, the second potential V2, the first potential V1, and the third potential V3 of the first low-potential signal VSSG in a sequential order.
[0037] It should be noted that, in this embodiment, the third potential V3 of the first low-potential signal VSSG can be provided as part of the scan signal Gate(N) by the second transistor T32. Specifically, the third potential V3 of the first low-potential signal VSSG in the scan signal Gate(N) can be entirely provided by the second transistor T32 to save on the number of transistors used in the gate drive circuit 300; alternatively, it can be partially provided by the second transistor T32 to reduce the operating time of the second transistor T32, thereby extending its lifespan.
[0038] In one embodiment, the gate driving unit 310 further includes a third transistor T33, one of the source / drain of the third transistor T33 is connected to the other of the source / drain of the first transistor T21, the scan line, and one of the source / drain of the second transistor T32, the other of the source / drain of the third transistor T33 is connected to the first low potential line, and the gate of the third transistor T33 is connected to the third node; wherein the third transistor T33 and the second transistor T32 are time-divisionally turned on.
[0039] It should be noted that in this embodiment, the first low-potential signal VSSG can be transmitted by the second transistor T32 and the third transistor T33 alternately being turned on as part of the scan signal Gate(N). This can improve the electrical stress caused by a single transistor being in the on or off state for a long time, and improve the working stability of the second transistor T32 and the third transistor T33.
[0040] In one embodiment, the gate driving unit 310 further includes a first inverting module, which is connected to the first node Q(N) and the second node.
[0041] It should be noted that in this embodiment, when the potential of the first node Q(N) is high, the potential of the second node is low; when the potential of the first node Q(N) is low, the potential of the second node is high.
[0042] In one embodiment, the first inverting module includes transistors T51, T52, T53, and T54. One of the source / drain terminals of transistor T51 is connected to one of the source / drain terminals of transistor T53 and a first control line; the other of the source / drain terminals of transistor T51 is connected to the gate of transistor T53 and one of the source / drain terminals of transistor T52; the other of the source / drain terminals of transistor T53 is connected to a second node, the gate of a second transistor T32, and one of the source / drain terminals of transistor T54; a second low-potential line is connected to the other of the source / drain terminals of transistor T52 and the other of the source / drain terminals of transistor T54; and the first node Q(N) is connected to the gate of transistor T52 and the gate of transistor T54.
[0043] The first control line is used to transmit a first control signal, which is a low-frequency control signal. The second low-potential line is used to transmit a second low-potential signal VSSQ.
[0044] In one embodiment, the gate driving unit 310 further includes a transistor T11, one of the source / drain of the transistor T11 is connected to a second control line, the gate of the transistor T11 is connected to a third control line, and the other of the source / drain of the transistor T11 is connected to a first node Q(N).
[0045] It should be noted that the second control line is used to transmit the second control signal, which can be the (N-6)th level scan signal Gate(N-6). The third control line is used to transmit the third control signal, which can be the (N-6)th level cascaded signal ST(N-6).
[0046] In one embodiment, the gate driving unit 310 further includes a transistor T22, one of the source / drain of the transistor T22 being connected to the clock line 200, the gate of the transistor T22 being connected to the first node Q(N), and the other of the source / drain of the transistor T22 being connected to the cascade line.
[0047] It should be noted that cascade lines are used to transmit cascaded signals ST(N).
[0048] In one embodiment, the gate driving unit 310 further includes a transistor T72, one of the source / drain of transistor T72 being cascaded to the other of the source / drain of transistor T22, the other of the source / drain of transistor T72 being connected to a second low-potential line, and the gate of transistor T72 being connected to a second node.
[0049] In one embodiment, the gate driving unit 310 further includes a transistor T42, one of the source / drain of the transistor T42 being connected to a scan line, the other of the source / drain of the transistor T42 being connected to a second low-potential line, and the gate of the transistor T42 being connected to a second node.
[0050] In one embodiment, the gate driving unit 310 further includes a capacitor C, one end of which is connected to the first node Q(N), and the other end of which is connected to the scan line.
[0051] In one embodiment, the gate driving unit 310 further includes a second inverting module, which is connected to the first node Q(N) and the third node.
[0052] It should be noted that in this embodiment, when the potential of the first node Q(N) is high, the potential of the third node is low; when the potential of the first node Q(N) is low, the potential of the third node is high.
[0053] In one embodiment, the second inverting module includes transistors T61, T62, T63, and T64. One of the source / drain terminals of transistor T61 is connected to one of the source / drain terminals of transistor T63 and a fourth control line; the other of the source / drain terminals of transistor T61 is connected to the gate of transistor T63 and one of the source / drain terminals of transistor T62; the other of the source / drain terminals of transistor T63 is connected to a third node, the gate of a third transistor T33, and one of the source / drain terminals of transistor T64; a second low-potential line is connected to the other of the source / drain terminals of transistor T62 and the other of the source / drain terminals of transistor T64; and a first node Q(N) is connected to the gate of transistor T62 and the gate of transistor T64.
[0054] The fourth control line is used to transmit a fourth control signal, which is a low-frequency control signal. When the first control signal is at a low level, the fourth control signal is at a high level; when the first control signal is at a high level, the fourth control signal is at a low level.
[0055] In one embodiment, the gate driving unit 310 further includes a transistor T43, one of the source / drain of the transistor T43 being connected to a scan line, the other of the source / drain of the transistor T43 being connected to a second low-potential line, and the gate of the transistor T43 being connected to a third node.
[0056] In one embodiment, the gate driving unit 310 further includes a transistor T73, one of the source / drain of the transistor T73 being connected to a cascade line, the other of the source / drain of the transistor T73 being connected to a second low-potential line, and the gate of the transistor T73 being connected to a third node.
[0057] In one embodiment, the gate driving unit 310 further includes a transistor T41, one of the source / drain of the transistor T41 being connected to the first node Q(N), the other of the source / drain of the transistor T41 being connected to the second low potential line, and the gate of the transistor T41 being connected to the fifth control line.
[0058] The fifth control line is used to transmit the fifth control signal, which can be the N+8th level scan signal Gate(N+8).
[0059] Figure 3 for Figure 2The timing diagram of the gate driving unit 310 shown shows that the waveforms of the (N-6)th stage scan signal Gate(N-6) and the (N-6)th stage cascade signal ST(N-6) are the same. When both are at low potentials, transistor T11 is in the off state. At this time, the potential of the first node Q(N) is low, and one of the second or third nodes is at a high potential. One of the second transistor T32 or the third transistor T33 is in the on state. At this time, the first low potential signal VSSG is part of the scan signal Gate(N) and G(N).
[0060] When both the (N-6)th level scan signal Gate(N-6) and the (N-6)th level cascade signal ST(N-6) switch to a high potential, the potential of the first node Q(N) begins to rise, and the first transistor T21 is turned on. At this time, the clock signal CK(N) is part of the scan signal Gate(N).
[0061] When the N+8th level scan signal Gate(N+8) switches to a high potential, transistor T41 pulls down the potential of the first node Q(N) to a low potential. At this time, one of the second or third nodes is at a high potential, and one of the second transistor T32 / third transistor T33 is in the on state. At this time, the first low potential signal VSSG is part of the scan signal Gate(N), i.e., G(N).
[0062] Therefore, the scan signal Gate(N) can be said to be composed of the clock signal CK(N) and the first low potential signal VSSG. For example, the potential of the scan signal Gate(N) in time is the third potential V3 of the first low potential signal VSSG, the first potential V1 of the clock signal CK(N), the second potential V2 of the clock signal CK(N), the first potential V1 of the clock signal CK(N), and the third potential V3 of the first low potential signal VSSG in sequence.
[0063] Figure 4 for Figure 3 The diagram shows the waveform of the scanning signal Gate(N) in the related technology. The first potential V1 (VGL) of the clock signal CK(N) can be -10V, and the second potential V2 (VGH) of the clock signal CK(N) can be 30V. The third potential V3 of the first low-potential signal VSSG can be -6V. In this state, because the voltage difference between the first potential V1 and the second potential V2 of the clock signal CK(N) is small, the actual falling edge of the scanning signal Gate(N) is relatively gentle, differing significantly from the ideal vertical falling edge.
[0064] Figure 5This is a schematic diagram of charging under ideal conditions provided in the embodiments of this application. In this case, the rising and falling edges of the scan signal Gate(N) and the data signal Data are both vertical, and the pulse of the scan signal Gate(N) can completely cover the pulse of the data signal Data, so that the maximum charging time under ideal conditions can be achieved.
[0065] Figure 6 The diagram illustrates the charging process in the relevant technology. However, the waveforms of both the scanning signal Gate(N) and the data signal Data are not ideal, resulting in effective charging only occurring in the shaded area. Charging cannot be achieved within the time corresponding to the blank area on the right, thus reducing the charging time.
[0066] Figure 7 This is a waveform diagram of the scanning signal Gate(N) provided in an embodiment of this application. Changing the first potential V1 and / or the second potential V2 of the clock signal CK(N) increases the voltage difference between different potentials of the clock signal CK(N). For example, the second potential V2 of the clock signal CK(N) can be kept constant while the first potential V1 of the clock signal CK(N) is decreased. This improves the verticality of the falling edge of the scanning signal Gate(N). For example, when the second potential V2, i.e., VGH, of the clock signal CK(N) remains constant, and the first potential V1, i.e., VGL, of the clock signal CK(N) drops from -10V to -15V, it can be seen that the falling edge of the clock signal CK(N) becomes closer to the ideal state.
[0067] Figure 8 In order to be in Figure 7 The diagram shows a charging process controlled by the scan signal Gate(N). Because the falling edge of the scan signal Gate(N) becomes steeper, the pulse of the scan signal Gate(N) can cover less of the pulse of the data signal Data, which leads to a reduction in charging time.
[0068] Figure 9 In order to be in Figure 8 The diagram illustrates the charging process after phase shifting. By shifting the phase of the clock signal CK(N), the pulses of the scan signal Gate(N) can cover more of the pulses of the data signal Data, which increases the charging time and thus increases the writing time of the data signal Data.
[0069] It should be noted that the greater the voltage difference between the first point and the second potential V2 of the clock signal CK(N), the more vertical the falling edge of the scan signal Gate(N) will be. Correspondingly, the phase change of the clock signal CK(N) also needs to be increased to increase the timing overlap between the pulses of the scan signal Gate(N) and the pulses of the data signal Data. In other words, the voltage difference is positively correlated with the phase change of the clock signal CK(N), which can maximize the charging time.
[0070] In another embodiment, the phase of the scan signal Gate(N) can be shifted backward directly by the gate drive circuit 300 while keeping the phase of the clock signal CK(N) unchanged. For example, a phase adjustment module or shift module for phase shifting can be added to each gate drive unit 310 of the gate drive circuit 300 to shift the phase of the scan signal Gate(N).
[0071] It should be noted that the end time of the effective charging time is earlier than or equal to the start time of the end edge of the data signal. The end edge is the falling edge of a positive pulse or the rising edge of a negative pulse. The end time of the effective charging time can be when the potential of the scan signal Gate(N) drops to a level insufficient to maintain the conduction state of the thin-film transistor in the pixel, allowing the pulse amplitude of the data signal Data to pass through the thin-film transistor without loss; or, at or before the start time of the end edge, the scan signal Gate(N) controls the thin-film transistor in the pixel to be in the conduction state to write the pulse amplitude of the data signal Data to the corresponding pixel. This maximizes the effective charging time and improves the situation of insufficient charging time.
[0072] Figure 10 This diagram illustrates the relationship between the effective charging time and the absolute value of the first potential V1 provided in this embodiment. The horizontal axis X represents the absolute value of the first potential V1, or VGL, of the clock signal CK(N), in volts (V). The vertical axis Y represents the effective charging time, in nanoseconds (ns). The relationship between the two satisfies: Y = -3.3333X 2 +143.33X-400ns.
[0073] Figure 11 Based on Figure 6 The diagram shows the charging time distribution under the given charging effect. Figure 12 Based on Figure 9 The diagram shows the charging time distribution under the given charging effect. Compared to... Figure 11 , Figure 12With the phase shift of the clock signal CK(N) and its falling edge adjusted to be more vertical, the charging time at the same location on the display panel is correspondingly increased. For example, in the display panel, the charging time of the pixels in the upper left increases from 700ns to 1200ns, the charging time of the pixels in the middle left increases from 1150ns to 1400ns, and the charging time of the pixels in the lower left increases from 1500ns to 1800ns; the charging time of the pixels in the upper center increases from 700ns to 900ns, the charging time of the pixels in the center increases from 700ns to 1100ns, and the charging time of the pixels in the lower center increases from 1250ns to 1500ns; the charging time of the pixels in the upper right increases from 700ns to 1000ns, the charging time of the pixels in the middle right increases from 950ns to 1300ns, and the charging time of the pixels in the lower right increases from 1450ns to 1700ns.
[0074] It should be noted that the method for increasing charging time provided in this application is applicable to various types of display panels, such as liquid crystal displays or self-emissive display panels. It is also applicable to various pixel driving architectures, such as... Figure 13 The pixel driving architecture shown is 1G1D, meaning one scan line drives one row of pixels, and one data line provides data signals (Data) to one column of pixels; for example... Figure 14 The Tri-gate (three-dimensional transistor) pixel driving architecture shown, etc.
[0075] The aforementioned display device may include a display panel, which includes a plurality of pixels arranged in an array. Each pixel includes a thin-film transistor, the gate of which is connected to a scan signal Gate(N), and one of the source or drain of the thin-film transistor is connected to a data signal Data. Thus, the scan signal Gate(N) can control the effective charging time of the data signal Data.
[0076] In one embodiment, this embodiment provides a display charging method, which includes: a gate driving circuit 300 outputting a corresponding scan signal Gate(N) according to an input clock signal CK(N), the clock signal CK(N) having an alternating first potential V1 and a second potential V2, the first potential V1 being less than the second potential V2; configuring the scan signal Gate(N) to have a portion of the clock signal CK(N), the scan signal Gate(N) changing in the order of the first potential V1, the second potential V2, and the first potential V1 again within a first preset time period; the display device increasing the voltage difference between the first potential V1 and the second potential V2 of the scan signal Gate(N), and adjusting the phase of the scan signal Gate(N) to increase the effective charging time of the scan signal Gate(N) for the corresponding pixel.
[0077] It is understood that the display charging method provided in this embodiment can make the falling edge of the scanning signal Gate(N) closer to the ideal vertical falling edge by increasing the voltage difference between different potentials of the scanning signal Gate(N). At the same time, by adjusting the phase of the scanning signal Gate(N) in timing, the pulse duration of the scanning signal Gate(N) can cover more of the pulse duration of the data signal Data, thereby increasing the effective charging time of the data signal Data.
[0078] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0079] The display device and display charging method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A display device, characterized in that, The display device includes: A timing controller for transmitting a clock signal having an alternating, continuous first potential and a second potential, wherein the first potential is less than the second potential; A gate driving circuit includes multiple cascaded gate driving units, each of which is configured to output a corresponding scan signal according to the received clock signal. The scan signal has a portion of the clock signal and changes in the order of the first potential, the second potential, and the first potential within a first preset time period. The display device increases the voltage difference between the first potential and the second potential of the scanning signal and adjusts the phase of the scanning signal to increase the overlap time between the pulse of the scanning signal and the pulse of the data signal in the timing, thereby improving the effective charging time of the scanning signal for the corresponding pixel. The voltage difference is positively correlated with the phase change of the clock signal.
2. The display device according to claim 1, characterized in that, The timing controller changes the first potential of the clock signal and / or the second potential of the clock signal to increase the voltage difference between the different potentials of the clock signal.
3. The display device according to claim 2, characterized in that, The timing controller maintains the second potential of the clock signal unchanged and decreases the first potential of the clock signal.
4. The display device according to claim 1, characterized in that, The timing controller shifts the phase of the clock signal backward and / or the gate drive circuit shifts the phase of the scan signal backward.
5. The display device according to claim 1, characterized in that, The scanning signal is used to control the effective charging time of the data signal; the end time of the effective charging time is earlier than or equal to the start time of the end edge of the data signal, and the end edge is the falling edge of a positive pulse or the rising edge of a negative pulse.
6. The display device according to claim 5, characterized in that, At and before the start of the end edge, the scan signal controls the thin-film transistor in the pixel to be turned on in order to write the pulse amplitude of the data signal to the corresponding pixel.
7. The display device according to claim 1, characterized in that, The display device further includes a first low-potential line, which is used to transmit a first low-potential signal. The scanning signal also contains a portion of the first low-potential signal before and after the first preset time period.
8. The display device according to claim 7, characterized in that, The first low-potential signal has a third potential, which is greater than the first potential and less than the second potential; The scanning signal has the third potential during the second preset time period, and the second preset time period and the first preset time period alternate continuously in time.
9. A display charging method, characterized in that, The display charging method includes: In the gate driving circuit, each gate driving unit outputs a corresponding scan signal according to the input clock signal. The clock signal has an alternating and continuous first potential and a second potential, wherein the first potential is less than the second potential. The scan signal is configured to have a portion of the clock signal, and the scan signal changes in the order of the first potential, the second potential, and the first potential again within a first preset time period; and The display device increases the voltage difference between the first potential and the second potential of the scanning signal and adjusts the phase of the scanning signal to increase the overlap time between the pulse of the scanning signal and the pulse of the data signal in the timing, thereby improving the effective charging time of the scanning signal for the corresponding pixel. The voltage difference is positively correlated with the phase change of the clock signal.