Signal processing method and signal processing apparatus

Abstract

A signal processing method includes: dividing a bit sequence into multiple groups of bit segments, generating extended bit segments according to the bit segments and a cyclic redundancy check code, interleaving each group of the extended bit segments into a sub-block group, and modulating each sub-block into a modulated symbol sub-block; compressing all the modulated symbol sub-blocks into multiple sparse regression code words using a preset compression matrix, and transmitting a wireless signal according to the multiple sparse regression code words. After encoding in combination of the CRC code and the sparse regression code, using approximate message passing decoding and list decoding during decoding can effectively reduce the frame error rate and the bit error rate.

Description

Technical Field

[0001] The present application relates to the field of wireless communications, and in particular to a signal processing method and a signal processing device. Background Art

[0002] Coding schemes for wireless channels include turbo codes, low-density parity-check codes (LDPC), polar codes, spatially coupled LDPC codes, and sparse regression codes (SPARCs).

[0003] A signal processing method generally involves dividing an original bit sequence into a first subsequence and a second subsequence, encoding subblocks of the second subsequence using LDPC codes, modulating and compressing the subblocks of the first subsequence and the LDPC-encoded subblocks to obtain Gaussian codewords, and transmitting the Gaussian codewords. Upon receiving the Gaussian codewords, the receiver undergoes approximate message passing decoding and LDPC decoding. If LDPC decoding fails to produce an accurate result, the number of approximate message passing decoding iterations is increased until the LDPC decoding achieves an accurate result or the maximum number of LDPC decoding attempts is reached.

[0004] When LDPC decoding cannot output accurate results, approximate message passing decoding and LDPC decoding are repeated more times. Due to the high complexity of LDPC decoding, this will result in longer decoding time. Summary of the Invention

[0005] In view of this, the present application provides a signal processing method and a signal processing device, which can reduce decoding time.

[0006] The first aspect provides a signal processing method, which includes: dividing a bit sequence into multiple groups of bit segments; generating extended bit segments based on the bit segments and CRC codes; interleaving each group of extended bit segments into a sub-block group; modulating each sub-block of all sub-block groups into a modulation symbol sub-block; compressing all modulation symbol sub-blocks into multiple sparse recursive codewords using a preset compression matrix; and sending multiple sparse recursive codewords. Each group of bit segments includes at least one bit segment, the bit segments and CRC codes have a one-to-one correspondence, and the sub-block group includes multiple sub-blocks. After using the CRC code and the sparse recursive code for channel coding, approximate message passing decoding and list decoding are used during decoding, which can reduce the frame error rate and bit error rate. Since the complexity of list decoding is lower than that of LDPC decoding, it can reduce the decoding time.

[0007] In one possible implementation, before modulating each subblock into a modulation symbol subblock, all subblock groups are subjected to subblock interleaving. Subblock interleaving involves reorganizing subblocks in identical positions within each subblock group into a single subblock group, thereby distributing consecutive subblocks to different subblock groups. After subblock interleaving, if several subblocks are lost during transmission, this is equivalent to losing one subblock in each of the several subblock groups before subblock interleaving. The lost subblocks can then be recovered based on the remaining subblocks in the subblock group. Therefore, subblock interleaving can reduce both the frame error rate and the bit error rate.

[0008] In another possible implementation, using a preset compression matrix to compress all modulation symbol subblocks into multiple sparse recursive codewords includes: weighting each modulation symbol subblock using a preset coding power matrix; and compressing all weighted subblocks obtained by weighting into multiple sparse recursive codewords using a preset compression matrix. The coding power matrix includes multiple power values, one power value corresponding to each modulation symbol subblock. It should be noted that the coding power matrix does not change the total transmit power. After assigning a power value to each subblock, the values ​​of some subblocks become larger, while the values ​​of some subblocks become smaller. Subblocks with larger power values ​​can be decoded with a greater probability. Subblocks that are successfully decoded during iterative decoding can assist in decoding other subblocks, thereby reducing the frame error rate and bit error rate.

[0009] In another possible implementation, the compression matrix is ​​a sparse regression matrix, which is also called a sparse regression codebook.

[0010] In another possible implementation, the compression matrix is ​​a design matrix, which includes multiple sparse regressor submatrix groups arranged in a staircase manner. Each sparse regressor submatrix group includes sparse regressor submatrices arranged consecutively vertically. In the design matrix, all elements except the sparse regressor submatrices are 0. Codewords compressed using the design matrix can be treated as spatially coupled codewords during transmission, thereby reducing frame error rates and bit error rates.

[0011] The second aspect provides a signal processing method, which includes: receiving a sparse recursive codeword; performing approximate message passing decoding on the sparse recursive codeword according to a preset compression matrix and a credibility table to obtain multiple modulation symbol sub-block groups; generating a first set of candidate segment lists based on the modulation symbol sub-block groups; when each candidate segment list in the first set of candidate segment lists includes a target candidate segment, determining a first set of bit segments based on the target candidate segment in the first set of candidate segment lists; generating a second set of candidate segment lists based on the first set of bit segments and the modulation symbol sub-block groups; when each candidate segment list in the second set of candidate segment lists includes a target candidate segment, determining a second set of bit segments based on the target candidate segment in the second set of candidate segment lists; and generating a bit sequence based on the first set of bit segments and the second set of bit segments. Each modulation symbol sub-block group includes multiple modulation symbol sub-blocks, and the target candidate segment is a candidate segment that passes a cyclic redundancy check. For codewords encoded using CRC codes and sparse recursive codes, approximate message passing decoding and list decoding can be used during decoding to reduce frame error rate and bit error rate. Compared with LDPC decoding, list decoding has lower complexity and can therefore reduce decoding time.

[0012] In one possible implementation, when at least one candidate segment list in the first set of candidate segment lists does not include the target candidate segment, a credibility table is updated based on the bits in the first set of candidate segment lists that have passed verification, triggering the steps of performing approximate message passing decoding of the sparse recursive codeword based on a preset compression matrix and credibility table, and generating the first set of candidate segment lists based on the modulation symbol subblock groups. The credibility table has a dimension equal to the total number of subblocks multiplied by the total number of candidate bit subblocks corresponding to each subblock. The credibility table has a preset initial value, with each row of initial values ​​corresponding to a subblock and each column of initial values ​​corresponding to a candidate bit subblock. The initial value may be, but is not limited to, 0. The credibility table is iteratively updated until every candidate segment list in the first set of candidate segment lists includes the target candidate segment or the number of iterations reaches a preset number. When every candidate segment list in the first set of candidate segment lists includes the target candidate segment, it indicates that the first set of candidate segment lists has been successfully decoded. If the first set of candidate segment lists still fails to be decoded after the number of iterations reaches the preset number, the bit sequence or the bits corresponding to the first set of candidate segment lists are retransmitted.

[0013] In another possible implementation, when at least one candidate segment list in the second group of candidate segment lists does not include the target candidate segment, the credibility table is updated according to the bits in the second group of candidate segment lists that have passed the check, triggering the step of approximate message passing decoding of the sparse regressive codeword according to the preset compression matrix and credibility table to the step of generating the second group of candidate segment lists according to the first group of bit segments and modulation symbol sub-block groups. The credibility table is iteratively updated in this way until each candidate segment list in the second group of candidate segment lists includes the target candidate segment or the number of iterations reaches a preset number. When each candidate segment list in the second group of candidate segment lists includes the target candidate segment, it indicates that the second group of candidate segment lists is decoded successfully. When the number of iterations reaches the preset number and the second group of candidate segment lists is still not decoded successfully, the bit sequence or the bits corresponding to the second group of candidate segment lists are retransmitted.

[0014] In another possible implementation, before generating the first set of candidate segment lists based on the modulation symbol subblock groups, all modulation symbol subblock groups are de-subblocked. The modulation symbol subblock groups correspond to the subblock groups after subblock interleaving, and the de-subblocking is performed to restore the order between the modulation symbol subblocks.

[0015] In another possible implementation, the first set of candidate segment lists includes a position mapping candidate segment list, and the second set of candidate segment lists includes a modulation candidate segment list. In this implementation, the position mapping bits are decoded first, and the modulation bits are more likely to be decoded based on the decoded position mapping bits.

[0016] In another possible implementation, the first set of candidate segment lists includes a modulation candidate segment list, and the second set of candidate segment lists includes a position mapping candidate segment list. In this implementation, the modulation bits are decoded first, and the position mapping bits can be decoded with a higher probability based on the decoded modulation bits. This provides an alternative decoding method and increases the flexibility of the solution implementation.

[0017] In another possible implementation, performing approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and a credibility table to obtain multiple modulation symbol sub-block groups includes: performing approximate message passing decoding on the sparse regressive codeword according to the preset compression matrix, the credibility table, and a preset decoding power matrix to obtain multiple weighted sub-block groups; and weighting each weighted sub-block in the multiple weighted sub-block groups using a power value of a preset decoding power matrix to obtain multiple modulation symbol sub-block groups. The weighted sub-block groups include multiple weighted sub-blocks, and the decoding power matrix includes multiple power values, one power value corresponding to each weighted sub-block.

[0018] In another possible implementation, the compression matrix is ​​a sparse regression matrix, which is also called a sparse regression codebook.

[0019] In another possible implementation, the compression matrix is ​​a design matrix, which includes multiple sparse regression submatrix groups arranged in a staircase manner. Each sparse regression submatrix group includes sparse regression submatrices arranged consecutively vertically. In the design matrix, all elements except the sparse regression submatrices are 0. For codewords compressed using the design matrix, the design matrix is ​​also used for decompression in approximate message passing decoding.

[0020] The third aspect provides a signal processing method, which includes: receiving a sparse regression codeword; performing approximate message passing decoding on the sparse regression codeword according to a preset compression matrix and a credibility table to obtain multiple modulation symbol sub-block groups; selecting a first target modulation symbol and a second target modulation symbol from each modulation symbol sub-block of the modulation symbol sub-block group; determining multiple modulation candidate segment lists according to the phase of the modulation symbol sub-block group and the first target modulation symbol; when each modulation candidate segment list includes a target candidate segment, determining a modulation bit segment according to the target candidate segment of the modulation candidate segment list; determining multiple position mapping candidate segment lists according to the modulation symbol sub-block group and the second target modulation symbol; when each position mapping candidate segment list includes a target candidate segment, determining a position mapping bit segment according to the target candidate segment of the position mapping candidate segment list; and generating a bit sequence according to the modulation bit segment and the position mapping bit segment. Each modulation symbol sub-block group includes multiple modulation symbol sub-blocks, the first target modulation symbol is the position mapping modulation symbol with the highest credibility in the modulation symbol sub-block, the second target modulation symbol is the modulation symbol with the highest credibility in the modulation symbol sub-block, and the target candidate segment is the candidate segment that passes the cyclic redundancy check. For codewords encoded according to CRC codes and sparse regression codes, approximate message passing decoding and list decoding can be used during decoding, which can reduce the frame error rate and bit error rate. Compared with LDPC decoding, list decoding has lower complexity and can therefore reduce decoding time. During list decoding, position mapping bits and modulation bits can be decoded in parallel, which improves decoding flexibility.

[0021] In one possible implementation, when at least one modulation candidate segment list does not include the target candidate segment, a credibility table is updated based on the bits that have passed the verification in multiple modulation candidate segment lists, triggering the step of performing approximate message passing decoding on the sparse recursive codeword based on the preset compression matrix and the credibility table, and the step of determining multiple modulation candidate segment lists based on the modulation symbol sub-block group and the phase of the first target modulation symbol. When each candidate segment list in the modulation candidate segment list includes the target candidate segment, it indicates that the modulation candidate segment list has been successfully decoded. When the number of iterations reaches a preset number and the modulation candidate segment list is still not successfully decoded, the bit sequence or the bits corresponding to the modulation candidate segment list are retransmitted.

[0022] In another possible implementation, when at least one position mapping candidate segment list does not include the target candidate segment, the credibility table is updated based on the bits that have passed the verification in the multiple position mapping candidate segment lists, triggering the step of approximate message passing decoding of the sparse regression codeword according to the preset compression matrix and the credibility table to the step of determining multiple position mapping candidate segment lists based on the modulation symbol sub-block group and the second target modulation symbol. When each candidate segment list in the position mapping candidate segment list includes the target candidate segment, it indicates that the position mapping candidate segment list is decoded successfully. When the number of iterations reaches the preset number, if the position mapping candidate segment list is still not decoded successfully, the bit sequence or the bits corresponding to the position mapping candidate segment list are retransmitted.

[0023] In another possible implementation, the signal processing method further includes removing sub-block interleaving from all modulation symbol sub-block groups. The modulation symbol sub-block groups correspond to sub-block groups after sub-block interleaving, and removing sub-block interleaving is to restore the order between modulation symbol sub-blocks.

[0024] In another possible implementation, the compression matrix is ​​a sparse regression matrix.

[0025] In another possible implementation, the compression matrix is ​​a design matrix, which includes multiple sparse regression submatrix groups arranged in a staircase manner. Each sparse regression submatrix group includes sparse regression submatrices arranged consecutively vertically. In the design matrix, all elements except the sparse regression submatrices are 0. For codewords compressed using the design matrix, the design matrix is ​​also used for decompression in approximate message passing decoding.

[0026] A fourth aspect provides a signal processing method, the method comprising: dividing a bit sequence into a first subsequence and a second subsequence; dividing the first subsequence and the second subsequence into multiple groups of bit segments respectively; generating a first extended bit segment based on the bit segment of the first subsequence and a first CRC code; generating a second extended bit segment based on the bit segment of the second subsequence and the second CRC code; interleaving the first extended bit segment of each group into a first sub-block group; interleaving the second extended bit segment of each group into a second sub-block group; modulating the first sub-block group into a first modulation symbol sub-block group, and modulating the second sub-block group into a second modulation symbol sub-block group; performing a weighted operation on the first modulation symbol sub-block group using a preset first coding power matrix; performing a weighted operation on the second modulation symbol sub-block group using a preset second coding power matrix; compressing all modulation symbol sub-blocks into multiple sparse recursive codewords using a preset compression matrix; and sending the multiple sparse recursive codewords. The length of the first CRC code is less than the length of the second CRC code, the power values ​​included in the first coding power matrix are greater than or equal to a preset power threshold, and the power values ​​included in the second coding power matrix are less than the preset power threshold. After encoding using CRC codes of different lengths, two sub-block groups are generated. The first sub-block group includes fewer CRC code sub-blocks than the second sub-block group. Assigning a higher power value to the first sub-block group can reduce the bit error rate of transmitting the first sub-block group. Because the second sub-block group includes more CRC code sub-blocks, it has a higher probability of successful decoding during list decoding, thereby reducing the bit error rate of the second sub-block group. Compared with LDPC decoding, list decoding can also reduce decoding time because its complexity is lower than LDPC decoding.

[0027] The fifth aspect provides a signal processing method, which comprises: receiving a sparse regression code word; performing approximate message passing decoding on the sparse regression code word according to a preset first decoding power matrix, a preset second decoding power matrix, a preset compression matrix and a reliability table to obtain a first modulation symbol sub-block group and a second modulation symbol sub-block group; generating a first group of candidate segment lists according to the first modulation symbol sub-block group; when each candidate segment list in the first group of candidate segment lists comprises a target candidate segment, determining a first group of bit segments according to the target candidate segment of the first group of candidate segment lists; generating a second group of candidate segment lists according to the first group of bit segments and the first modulation symbol sub-block group; when each candidate segment list in the second group of candidate segment lists comprises a target candidate segment, determining a second group of bit segments according to the target candidate segment; determining a first sub-sequence according to the first group of bit segments and the second group of bit segments; generating a third group of candidate segment lists according to the second modulation symbol sub-block group; when each candidate segment list in the third group of candidate segment lists comprises a target candidate segment, determining a third group of bit segments according to the target candidate segment of the third group of candidate segment lists; generating a fourth group of candidate segment lists according to the third group of bit segments and the second modulation symbol sub-block group; when each candidate segment list in the fourth group of candidate segment lists comprises a target candidate segment, determining a fourth group of bit segments according to the target candidate segment of the fourth group of candidate segment lists; determining a second sub-sequence according to the third group of bit segments and the fourth group of bit segments; and generating a bit sequence according to the first sub-sequence and the second sub-sequence. The target candidate segment is a candidate segment that passes a cyclic redundancy check, the first modulation symbol sub-block group comprises fewer modulation symbol sub-blocks than the second modulation symbol sub-block group, the power value corresponding to the first modulation symbol sub-block group is greater than the power value corresponding to the second modulation symbol sub-block group, and the probability of decoding the first modulation symbol sub-block group is greater. Because the second modulation symbol sub-block group comprises more modulation symbol sub-blocks, more CRC codes can be obtained during list decoding, thereby improving the success rate of decoding. Compared with LDPC decoding, the complexity of list decoding is lower, and therefore the decoding time can be reduced.

[0028] In a possible implementation, the candidate segment lists in the first group of candidate segment lists are modulation candidate segment lists, the candidate segment lists in the second group of candidate segment lists are position mapping candidate segment lists, the candidate segment lists in the third group of candidate segment lists are modulation candidate segment lists, and the candidate segment lists in the fourth group of candidate segment lists are position mapping candidate segment lists. In this way, modulation bits can be decoded first, and then position mapping bits can be decoded according to the modulation bits, thereby improving the success rate of decoding the position mapping bits.

[0029] In another possible implementation, the first group of candidate segment lists comprises a position mapping candidate segment list, the second group of candidate segment lists comprises a modulation candidate segment list, the third group of candidate segment lists comprises a position mapping candidate segment list, and the fourth group of candidate segment lists comprises a modulation candidate segment list. In this way, the position mapping bits can be decoded first, and then the modulation bits can be decoded according to the position mapping bits, so that the success rate of decoding the modulation bits can be improved.

[0030] The sixth aspect provides a signal processing method, which comprises: dividing a bit sequence into a first subsequence and a second subsequence, dividing the first subsequence into a plurality of subblocks and dividing the second subsequence into a plurality of groups of bit segments, generating an extended bit segment according to each bit segment of the second subsequence and a cyclic redundancy check code, interleaving each group of extended bit segments into a subblock group, modulating each subblock into a modulation symbol subblock, compressing all modulation symbol subblocks into a plurality of sparse regression code words using a preset compression matrix, and transmitting the plurality of sparse regression code words. In this way, part of the bits are not added with CRC codes, and another part of the bits are added with CRC codes, so that the part of the bits can be subjected to CRC encoding and sparse regression encoding, and the flexibility of signal processing is improved.

[0031] In a possible implementation, the signal processing method further comprises: performing subblock interleaving on all subblock groups. Subblock interleaving can disperse continuous subblocks into different subblock groups, so that the frame error rate and the bit error rate can be reduced.

[0032] In another possible implementation, the compression matrix is a sparse regression matrix. The sparse regression matrix is also referred to as a sparse regression codebook.

[0033] In another possible implementation, the compression matrix is a design matrix, and the design matrix comprises a plurality of sparse regression submatrix groups. The plurality of sparse regression submatrix groups are arranged in steps, each sparse regression submatrix group comprises sparse regression submatrices arranged in a continuous vertical direction, and elements other than the sparse regression submatrices in the design matrix are all 0. The code word obtained by compressing the modulation symbols using the design matrix can be regarded as a spatially coupled code word when being transmitted, so that the frame error rate and the bit error rate can be reduced.

[0034] The seventh aspect provides a signal processing method, which comprises: receiving a sparse regression code word, performing approximate message passing decoding on the sparse regression code word according to a preset compression matrix and a reliability table to obtain a first modulation symbol subblock group and a second modulation symbol subblock group, generating a first subsequence according to the first modulation symbol subblock group, generating a second subsequence according to the second modulation symbol subblock group, and generating a bit sequence according to the first subsequence and the second subsequence.

[0035] In a possible implementation, the signal processing method further includes removing sub-block interleaving from the second modulation symbol sub-block group. The modulation symbol sub-block group corresponds to the sub-block group after sub-block interleaving, and removing the sub-block interleaving is to restore the order between the modulation symbol sub-blocks.

[0036] In one possible implementation, a method for generating a second subsequence based on a second modulation symbol block group includes: generating a first set of candidate segment lists based on the second modulation symbol subblock group; when each candidate segment list in the first set of candidate segment lists includes a target candidate segment, determining a first set of bit segments based on the target candidate segment in the first set of candidate segment lists; generating a second set of candidate segment lists based on the first set of bit segments and the second modulation symbol subblock group; when each candidate segment list in the second set of candidate segment lists includes a target candidate segment, determining a second set of bit segments based on the target candidate segment in the second set of candidate segment lists; and determining a second subsequence based on the first set of bit segments and the second set of bit segments. The candidate segment lists included in the first set of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the second set of candidate segment lists are modulation candidate segment lists, or the candidate segment lists included in the first set of candidate segment lists are modulation candidate segment lists, and the candidate segment lists included in the second set of candidate segment lists are position mapping candidate segment lists. Decoding first to obtain the first group of bit segments, and decoding the second group of bit segments based on the first group of bit segments can improve the success rate of decoding the second group of bit segments.

[0037] In another possible implementation, a first set of candidate segment lists and a second set of candidate segment lists are generated based on the second modulation symbol sub-block group; a first set of bit segments are determined based on the target candidate segments in the first set of candidate segment lists; a second set of bit segments are determined based on the target candidate segments in the second set of candidate segment lists; and a second subsequence is determined based on the first set of bit segments and the second set of bit segments. The candidate segment lists included in the first set of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the second set of candidate segment lists are modulation candidate segment lists, or the candidate segment lists included in the first set of candidate segment lists are modulation candidate segment lists, and the candidate segment lists included in the second set of candidate segment lists are position mapping candidate segment lists. In this way, the first set of bit segments and the second set of bit segments can be decoded in parallel, thereby improving the flexibility of decoding.

[0038] In an eighth aspect, a signal processing device is provided, which has the function of implementing the signal processing method of each of the above aspects. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0039] The ninth aspect provides a signal processing device, which includes a processor and a memory, wherein the memory is used to store a program; the processor is used to implement the signal processing methods of the above aspects by executing the program.

[0040] The tenth aspect provides a computer-readable storage medium, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer executes the signal processing methods of the above aspects.

[0041] In the eleventh aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the signal processing methods in the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a power grid communication scenario;

[0043] Figure 2 A schematic diagram of a smart home scenario;

[0044] Figure 3 A flowchart of a signal processing method in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of a design matrix in an embodiment of the present application;

[0046] Figure 5 This is another flow chart of the signal processing method in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of bit error rates of multiple signal processing schemes under different signal-to-noise ratio conditions in the embodiments of the present application;

[0048] Figure 7 A schematic diagram of a frame error rate of multiple signal processing schemes under different signal-to-noise ratio conditions in the embodiments of the present application;

[0049] Figure 8 Another schematic diagram of bit error rates of multiple signal processing schemes under different signal-to-noise ratio conditions in the embodiments of the present application;

[0050] Figure 9 Another schematic diagram of frame error rates under different signal-to-noise ratio conditions for multiple signal processing schemes in the embodiments of the present application;

[0051] Figure 10 This is another flow chart of the signal processing method in an embodiment of the present application;

[0052] Figure 11 This is another flow chart of the signal processing method in an embodiment of the present application;

[0053] Figure 12This is another flow chart of the signal processing method in an embodiment of the present application;

[0054] Figure 13 This is another flow chart of the signal processing method in an embodiment of the present application;

[0055] Figure 14 This is another flow chart of the signal processing method in an embodiment of the present application;

[0056] Figure 15 This is another flow chart of the signal processing method in an embodiment of the present application;

[0057] Figure 16 This is another flow chart of the signal processing method in an embodiment of the present application;

[0058] Figure 17 This is a structural diagram of a signal processing device in an embodiment of the present application;

[0059] Figure 18 This is another structural diagram of the signal processing device in an embodiment of the present application;

[0060] Figure 19 This is another structural diagram of the signal processing device in an embodiment of the present application;

[0061] Figure 20 This is another structural diagram of the signal processing device in an embodiment of the present application;

[0062] Figure 21 This is a structural diagram of a communication device in an embodiment of the present application. DETAILED DESCRIPTION

[0063] The signal processing method of the present application can be applied to wireless communication scenarios, which may be but are not limited to massive machine type communication (mMTC) scenarios or ultra-reliable low latency communication (URLLC) scenarios.

[0064] mMTC scenarios include, but are not limited to, smart grids, agricultural environmental monitoring, and wildlife monitoring. In these scenarios, each device sporadically uploads data, but the potential number of devices is massive, placing high demands on the overall transmission rate.

[0065] Figure 1 A schematic diagram of a smart grid scenario. Figure 1The smart grid scenario includes a network device 11, a photovoltaic power generation device 12, a wind power generation device 13, a hydroelectric power generation device 14, a thermal power generation device 15, and a power transmission device 16. The network device 11 is connected to the photovoltaic power generation device 12, the wind power generation device 13, the hydroelectric power generation device 14, the thermal power generation device 15, and the power transmission device 16 through a wireless link. The network device 11 can be, but is not limited to, a base station or an access point. The base station can be a macro base station, a micro base station, a pico base station, and the like.

[0066] It should be understood that the smart grid scenario can include one or more of the above-mentioned devices, and the devices included in the smart grid scenario are not limited to the above examples. The number of network devices 11, photovoltaic power generation devices 12, wind power generation devices 13, hydroelectric power generation devices 14, thermal power generation devices 15, and power transmission devices 16 can be one or more.

[0067] The URLLC scenario includes, but is not limited to, an industrial asset detection scenario, a smart home and security scenario, a personal wearable device, a smart logistics, and a critical infrastructure detection scenario.

[0068] Figure 2 An example of a smart home scenario is shown in FIG. 2. The smart home scenario includes a router 21, a television 22, a refrigerator 23, a washing machine 24, a dishwasher 25, and a microwave oven 26. The router 21 is connected to the television 22, the refrigerator 23, the washing machine 24, the dishwasher 25, and the microwave oven 26 through a wireless link.

[0069] It should be understood that the smart home scenario can include one or more of the above-mentioned devices, and the devices included in the smart home scenario are not limited to the above examples. The number of routers 21, televisions 22, refrigerators 23, washing machines 24, dishwashers 25, and microwave ovens 26 can be one or more.

[0070] These scenarios have relatively high requirements for reliability and low delay, and too high delay can result in catastrophic consequences. In the mMTC scenario or the URLLC scenario, each communication device can perform signal encoding or signal decoding according to the signal processing method of the present application, thereby meeting the requirements of low frame error rate and low delay of these scenarios.

[0071] In existing signal processing methods, the decoding time is long due to the high complexity of using LDPC codes for encoding and decoding. The method of using cyclic redundancy check (CRC) code encoding and list decoding proposed in the present application can reduce the decoding complexity and reduce the bit error rate. For details, see Figure 3 One embodiment of the signal processing method of the present application includes:

[0072] Step 301, dividing the bit sequence into multiple groups of bit segments.

[0073] In this embodiment, the bit sequence includes B bits, and the B bits can be divided into N g Group bit segments, each group bit segment can include J bit segments, each bit segment includes L g bits. B, N g , J, L g All of them are positive integers. The values ​​of the above parameters can be set according to actual conditions.

[0074] Step 302: Generate an extended bit segment according to the bit segment and the cyclic redundancy check code.

[0075] After adding a CRC code to each bit segment, an extended bit segment can be obtained. The CRC code length is L crc , L crc The value of can be set according to the actual situation. The code length of the extended bit segment is equal to L g +L crc .

[0076] Step 303: Interleave each group of extended bits into sub-block groups.

[0077] Specifically, interleave J bits into L segments g +L crc sub-blocks, each sub-block includes log2K modulation bits and log2M position mapping bits, and the sub-block is a bit sub-block. The i-th group of extended bit segments can be interleaved into the i-th sub-block group, where i can be [0,N g -1]. K is the modulation order corresponding to the modulation bit, M is the mapping order corresponding to the position mapping bit, K and M are both positive integers, and the values ​​of K and M can be set according to actual conditions, and this application does not limit them.

[0078] In one example, the bits included in the i-th group of extended bit segments and the i-th sub-block group are as shown in Table 1:

[0079]

[0080] Table 1

[0081] L=N g ×L g .

[0082] Step 304: Modulate each sub-block into a modulation symbol sub-block.

[0083] Optionally, Gray code mapping and quadrature phase shift keying (QPSK) modulation are performed on the modulation bits in all sub-blocks to obtain modulation symbol sub-blocks corresponding to the modulation bits. Optionally, Gray code mapping and position mapping are performed on the position mapping bits in all sub-blocks to obtain modulation symbol sub-blocks corresponding to the position mapping bits. The number of all modulation symbol sub-blocks is L T *M, L T =N g ×(L g +L crc It should be noted that Gray code mapping of the modulated bits in all sub-blocks is an optional step, which can reduce the bit error rate in the case of medium and high code rates. The method for modulating the sub-blocks can be, but is not limited to, QPSK.

[0084] Step 305: Use a preset compression matrix to compress all modulation symbol sub-blocks into multiple sparse recursive codewords.

[0085] Optionally, the compression matrix is ​​a sparse regression matrix, which is a sparse regression codebook.

[0086] Alternatively, the compression matrix is ​​a design matrix, the design matrix includes multiple sparse regression sub-matrix groups, the multiple sparse regression sub-matrix groups are arranged in a stepped manner, each sparse regression sub-matrix group includes multiple sparse regression sub-matrices arranged continuously vertically, and in the design matrix, all elements except the sparse regression sub-matrix are 0.

[0087] Figure 4 A schematic diagram of the design matrix in this application. Figure 4 In one example, the design matrix has L columns. c *L m , the number of rows is L r *n,L c , L m , L r and n are positive integers, and their sizes can be set according to actual conditions. The design matrix includes L c A group of sparse regression submatrices, L c The sparse regression sub-matrix groups are arranged in a ladder-like manner, and each sparse regression sub-matrix group includes 3 sparse regression sub-matrices. Figure 4 The sparse regression submatrix is ​​represented by a patterned square grid, and the number of columns of the sparse regression submatrix is ​​L m , the number of rows is n. The number of sparse regression submatrices in the sparse regression submatrix group can be, but is not limited to, 3, and can be set according to actual conditions.

[0088] When all modulation symbol sub-blocks are compressed into multiple sparse recursive codewords using a design matrix, the multiple sparse recursive codewords can be considered to have achieved spatial coupling, which can reduce the bit error rate and improve decoding performance at medium and high bit rates.

[0089] Step 306: Send multiple sparse regressive codewords.

[0090] A plurality of sparse recursive codewords are transmitted via a wireless channel. The wireless channel may be a discrete channel or a continuous channel. The continuous channel may be, but is not limited to, an additive white Gaussian noise (AWGN) channel.

[0091] In this embodiment, after adding CRC codes to bit segments, the CRC codes can be used to recover the bits of the bit segments during decoding, thereby enhancing error correction capabilities and reducing the bit error rate (BER) and frame error rate (FER). BER, also known as bit error rate, refers to the ratio of decoded bits to the total number of bits in a single encoding-transmission-decoding process. FER, also known as frame error rate, indicates the probability of decoding errors in a wireless frame during a single encoding-transmission-decoding process. Whether 1% or 99% of the bits in a wireless frame fail to decode, the result will be retransmission.

[0092] Secondly, after segmenting the bits, adding CRC codes, interleaving, modulation, and compression, the resulting sparse recursive codewords have a high bit rate, effectively reducing the amount of data transmitted over the channel. Because the modulation symbol sub-blocks before compression are sparse, this sparsity is exploited during approximate message passing decoding of the sparse recursive codewords to enhance decoding capabilities, resulting in excellent decoding speed and error correction performance. This strong decoding capability enables sparse recursive codes to operate at high bit rates, with each sparse recursive codeword symbol corresponding to an average of greater than or equal to 3.8 bits.

[0093] For ease of understanding, the signal processing method of this application is introduced below using a specific application scenario:

[0094] After obtaining a 10,500-bit bit sequence, divide it equally into 70 bit segments, each containing 150 bits. An 8-bit CRC code is added to each bit segment, resulting in a 158-bit extended bit segment. The 70 extended bit segments are evenly distributed into 10 groups, and each group of bit segments is interleaved to obtain 158 sub-blocks. This results in 10 sub-block groups, for a total of 1,580 sub-blocks. Each sub-block contains 7 bits, 2 of which are modulation bits, and the remaining 5 bits are position mapping bits. Within a sub-block, the positions of the modulation bits and the position mapping bits can be set according to actual conditions.

[0095] After subblock interleaving of the subblocks in the 10 subblock groups, all subblocks are modulated to obtain 1580 modulation symbol subblocks, each of which occupies 32 bits. When all modulation symbol subblocks are compressed and encoded into 10500-bit Gaussian codewords using the design matrix, the code rate R is 1. When all modulation symbol subblocks are compressed and encoded into 2763-bit Gaussian codewords using the sparse regression matrix, the code rate is 3.8. Finally, the Gaussian codewords are transmitted.

[0096] based on Figure 3 In the illustrated embodiment, in an optional embodiment, after step 303 and before step 304, the signal processing method further includes: performing sub-block interleaving on all sub-block groups.

[0097] In this embodiment, the total number of sub-block groups is N g .

[0098] The first sub-block group before interleaving is:

[0099]

[0100] The i-th sub-block group before interleaving is:

[0101]

[0102] The last sub-block group before interleaving is:

[0103]

[0104] The first sub-block group after interleaving is:

[0105]

[0106] The i-th sub-block group after interleaving is:

[0107]

[0108] The final sub-block group after interleaving is:

[0109]

[0110] In this embodiment, some sub-blocks may be lost or altered when passing through a wireless channel. Losing multiple consecutive sub-blocks can make it impossible to correct errors. Sub-block interleaving can disperse multiple consecutive sub-blocks into different sub-block groups. Losing several consecutive sub-blocks after sub-block interleaving is equivalent to losing one sub-block from several sub-block groups before sub-block interleaving. During decoding, the lost sub-blocks can be recovered based on the CRC of other sub-blocks, thereby reducing the bit error rate of medium and high bit rate signals. It should be noted that the lower the bit error rate, the higher the probability that list decoding can correct errors, thereby reducing the frame error rate.

[0111] In some optional embodiments, sub-block interleaving is performed on some of the sub-block groups, and during decoding, the modulation symbol sub-block groups corresponding to the above-mentioned partial sub-block groups are de-sub-block interleaved.

[0112] based on Figure 3 In the illustrated embodiment, in another optional embodiment, step 305 includes: weighting each modulation symbol sub-block using a preset coding power matrix; and compressing all weighted sub-blocks obtained by weighting into multiple sparse recursive codewords using a preset compression matrix.

[0113] In this embodiment, the coding power matrix includes multiple power values, one for each modulation symbol subblock. After weighting each subblock in the subblock group using a preset coding power matrix, the power of some modulation symbols is amplified, while the power of the remaining modulation symbols is reduced. High-power modulation symbol subblocks have a greater probability of being correctly decoded. The more modulation symbol subblocks decoded, the higher the success rate of decoding the remaining modulation symbol subblocks, thereby reducing the bit error rate and improving decoding accuracy.

[0114] The decoding process of the present application can be implemented in a variety of ways. In a first decoding method, the position mapping bit segment is decoded first, and then the modulation bit segment is decoded.

[0115] See Figure 5 , another embodiment of the signal processing method of the present application includes:

[0116] Step 501: Receive a sparse regression codeword.

[0117] For multiple sparse recursive codewords sent by the transmitting end, the receiving end may receive the multiple sparse recursive codewords.

[0118] Step 502: Perform approximate message passing decoding on the sparse recursive codeword according to the preset compression matrix and credibility table to obtain a plurality of modulation symbol sub-block groups.

[0119] The compressed matrix is ​​a sparse regression matrix. Alternatively, the compressed matrix is ​​a design matrix, the design matrix includes multiple sparse regression submatrix groups, the multiple sparse regression submatrix groups are arranged in a staircase manner, each sparse regression submatrix group includes sparse regression submatrices arranged consecutively vertically, and all elements in the design matrix except the sparse regression submatrix are 0.

[0120] The credibility table's dimensions are the total number of sub-blocks multiplied by the total number of bit sequences corresponding to each sub-block. The credibility table's initial values ​​are pre-set, with each row corresponding to a sub-block and each column corresponding to a candidate bit sub-block. The initial values ​​can be, but are not limited to, 0. During approximate message passing decoding of the credibility table, the credibility table is iteratively updated.

[0121] Approximate message passing decoding can obtain N g Each modulation symbol sub-block group includes L g +L crc modulation symbol sub-blocks, each modulation symbol sub-block including J modulation symbols. Approximate message passing decoding includes but is not limited to orthogonal approximate message passing decoding.

[0122] Step 503: Generate a first set of candidate segment lists according to the modulation symbol sub-block groups, where the first set of candidate segment lists includes multiple position mapping candidate segment lists.

[0123] Each modulation symbol sub-block group corresponds to J candidate segment lists, and the J candidate segment lists can be divided into a first group of candidate segment lists and a second group of candidate segment lists. In this embodiment, the candidate segment lists included in the first group of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the second group of candidate segment lists are modulation candidate segment lists.

[0124] The first set of candidate segment lists and the second set of candidate segment lists each include multiple candidate segment lists. For any candidate segment list, L can be generated according to the modulation symbol sub-block group. list Optionally, when step 503 is performed for the first time, L list When step 503 is executed for the second time, L′ can be generated. list candidate segments, L′ list is a positive integer and L′ list >L list Similarly, more candidate segments can be generated when step 503 is subsequently executed. Performing cyclic redundancy check on the newly added candidate segments can improve the decoding success rate and reduce the bit error rate.

[0125] Step 504 : Determine whether each candidate segment list in the first set of candidate segment lists includes the target candidate segment. If so, execute step 506 ; if not, execute step 505 .

[0126] The target candidate segment refers to a candidate segment that passes the cyclic redundancy check. For the candidate segment list in the first group of candidate segment lists, candidate segments are selected from them in turn for cyclic redundancy check. When the selected candidate segment fails the cyclic redundancy check, the bits that pass the check in the candidate segment are obtained. When the selected candidate segment passes the cyclic redundancy check, it indicates that the candidate segment is the target candidate segment. It should be noted that each candidate segment has a corresponding probability. In the candidate segment list, the candidate segments can be arranged according to the probability size, and the candidate segments are subjected to cyclic redundancy check in order from high probability to low probability.

[0127] Step 505 : Update the credibility table according to the bits that pass the check in the first set of candidate segment lists, and jump to step 502 .

[0128] Specifically, after performing a CRC check on the first candidate segment list, it can be divided into multiple sub-blocks to be processed, with each sub-block corresponding to a sub-block. The number of bits that pass the check in the i-th sub-block to be processed can be any integer value in [0, J], where i is a positive integer variable. Each sub-block to be processed corresponds to K*M candidate bit sub-blocks, and the credibility of each candidate bit sub-block is in [0, 1].

[0129] When one or more bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block including the above bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is increased, and the credibility of the remaining candidate bit sub-blocks is updated to 0. When all bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block consisting of the above bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is updated to 1, and the credibility of the remaining candidate bit sub-blocks is updated to 0.

[0130] In one example, the total number of sub-blocks to be processed is 1580, and each sub-block to be processed includes 7 bits. The partial credibility of the updated credibility table is shown in Table 2:

[0131] 0000000 0000001 … 1111110 1111111 Sub-block 0 to be processed 0 0 … 1 0 Sub-block 1 to be processed 0 0 … 0.3 0.3 … … … … … … Sub-blocks to be processed 1579 0 0 … 0.3 0.2

[0132] Table 2

[0133] The updated credibility table is more accurate than the credibility table before the update, and more position mapping bits may be recovered according to the updated credibility table.

[0134] The application also provides another credibility table including credibility of candidate modulation symbol sub-blocks. After the passing check bits are obtained, the process of updating the credibility table according to the passing check bits is similar to step 502, which will not be described here.

[0135] Step 506, determining a first group of bit segments according to the target candidate segment of the first group of candidate segment lists, the first group of bit segments including the position mapping segment.

[0136] Step 507, generating a second group of candidate segment lists according to the first group of bit segments and the modulation symbol sub-block group.

[0137] Specifically, step 507 can include determining the phase of a plurality of modulation bits according to the position mapping bits in the first group of bit segments, and generating the second group of candidate segment lists according to the modulation symbol sub-block group and the phase of the plurality of modulation bits. The second group of candidate segment lists include modulation candidate segments.

[0138] Step 508, determining whether each candidate segment list in the second group of candidate segment lists includes the target candidate segment, if yes, executing step 510, and if no, executing step 509.

[0139] When at least one candidate segment list in the second group of candidate segment lists does not include the target candidate segment, that is, all candidate segments of one or more candidate segment lists cannot pass the cyclic redundancy check. When each candidate segment list in the second group of candidate segment lists includes the target candidate segment, that is, each candidate segment of the second group of candidate segment lists is correctly decoded.

[0140] Step 509, updating the credibility table according to the passing check bits in the second group of candidate segment lists, and jumping to execute step 502.

[0141] Specifically, after the second group of candidate segment lists are subjected to CRC check, they can be divided into a plurality of to-be-processed sub-blocks, each to-be-processed sub-block corresponding to a sub-block. The number of passing check bits in the i-th to-be-processed sub-block can be any integer value in [0, J], i being a positive integer variable. Each to-be-processed sub-block corresponds to K*M candidate bit sub-blocks, and the credibility of each candidate bit sub-block belongs to [0, 1].

[0142] When one or more bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block including the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is increased, and the credibility of the remaining candidate bit sub-blocks is updated to 0. When all bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block consisting of the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is updated to 1, and the credibility of the remaining candidate bit sub-blocks is updated to 0. The updated credibility table is more accurate than the credibility table before the update, and more modulated bits can be recovered based on the updated credibility table.

[0143] Step 510: Determine a second group of bit segments according to the target candidate segments in the second group of candidate segment list, where the bit segments included in the second group of bit segments are modulation bit segments.

[0144] Step 511: Generate a bit sequence according to the first group of bit segments and the second group of bit segments.

[0145] The first group of bit segments includes multiple position-mapped bit segments, and the second group of bit segments includes multiple modulation bit segments. A portion of the bit sequence can be recovered based on the first group of bit segments and the second group of bit segments. As can be seen from steps 503 to 510, a first group of bit segments and a second group of bit segments can be generated based on each modulation symbol subblock group. Similarly, the bit sequence can be recovered based on the first group of bit segments and the second group of bit segments corresponding to each modulation symbol subblock group.

[0146] In this embodiment, the position mapping candidate segment list and the modulation candidate segment list can be updated through iteration, which can improve the accuracy of the position mapping candidate segment list and the modulation candidate segment list, thereby reducing the bit error rate.

[0147] Secondly, recovering the modulated bit segments or position-mapped bit segments based on the CRC code is less complex than LDCP decoding and can reduce decoding time.

[0148] Thirdly, after decoding the position mapping bits first, the success rate of decoding the modulated bits can be improved according to the position mapping bits.

[0149] based on Figure 5 In an optional embodiment of the illustrated embodiment, the signal processing method further includes removing sub-block interleaving from all modulation symbol sub-block groups. The transmitting end and the receiving end may negotiate a codec mode. In the specified codec mode, the transmitting end performs sub-block interleaving, while the receiving end removes sub-block interleaving. After removing sub-block interleaving, the order of the modulation symbol sub-block groups is consistent with the order of the sub-block groups during encoding.

[0150] based on Figure 5In another optional embodiment of the embodiment shown, step 502 includes: performing approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix, a credibility table and a preset decoding power matrix to obtain multiple weighted sub-block groups; and weighting each weighted sub-block of the multiple weighted sub-block groups using a power value of the preset decoding power matrix to obtain multiple modulation symbol sub-block groups.

[0151] In this embodiment, the decoding power matrix includes multiple power values, and each weighted sub-block corresponds to a power value. The transmitting end and the receiving end can negotiate the encoding and decoding mode. In the specified encoding and decoding mode, the transmitting end weights the modulation symbol sub-block according to the coding power matrix, and the receiving end weights the weighted sub-block according to the decoding power matrix. It should be noted that the decoding power matrix is ​​different from the coding power matrix. For the i-th modulation symbol sub-block and the i-th weighted sub-block, the product of the i-th element of the coding power matrix and the i-th element of the decoding power matrix is ​​equal to 1, and i is a positive integer. The influence of the power value is removed for each weighted sub-block during decoding. It should be understood that the elements in the coding power matrix and the decoding power matrix are power values.

[0152] The following introduces the simulation process of several encoding schemes and decoding performance:

[0153] In Scheme 1, the bit sequence length is 10,500 bits. The bit sequence is divided into 1,500 subblocks, and power is allocated to the subblocks. When using QPSK modulation, K = 4 and M = 32. A sparse recursive code matrix is ​​used to compress the coded bits. Hard decision decoding is used for decoding.

[0154] In Scheme 2, the bit sequence length is 10,500 bits. The bit sequence is divided into 1,500 subblocks, and power is allocated to the subblocks. When using QPSK modulation, K = 4 and M = 32. Compression encoding is performed using a designed matrix. Hard decision decoding is used for decoding.

[0155] In Scheme 3, the bit sequence length is 10,500 bits, divided into 70 segments, and eight CRC codes are added to each segment. All segments are then interleaved into 1,580 subblocks, and power allocation is performed on the subblocks. QPSK modulation is used with K = 4 and M = 32. Sparse recursive code matrices are used for compression encoding. List decoding is used for decoding.

[0156] In Scheme 4, the bit sequence length is 10,500 bits, divided into 70 segments, and eight CRC codes are added to each segment. All segments are then interleaved into 1,580 subblocks, and power allocation, subblock interleaving, and Gray code mapping are performed on the subblocks. When using QPSK modulation, K = 4 and M = 32. List decoding is used for decoding.

[0157] The following is an introduction to the decoding performance of low bit rate signals. Figure 6 The following is a schematic diagram of the bit error rate of multiple signal processing schemes under different signal-to-noise ratio conditions when the bit rate is 1. Figure 7 Figure 2 shows the frame error rate (FER) of various signal processing schemes under different signal-to-noise ratio (SNR) conditions, with a bit rate of 1. The SNR is Eb / N0, which is the ratio of the energy per bit to the noise power spectral density. Eb represents the received bit energy, and N0 represents the noise power spectral density. The unit of SNR is decibel (dB).

[0158] from Figure 6 It can be seen that under the low bit rate condition, the bit error rates of Scheme 1 and Scheme 2 are similar, and the bit error rates of Scheme 3 and Scheme 4 are similar. The bit error rates of Scheme 3 and Scheme 4 are significantly lower than those of Scheme 1 and Scheme 2.

[0159] from Figure 7 It can be seen that under low bit rate conditions, the frame error rates of Scheme 1 and Scheme 2 are similar, and the frame error rates of Scheme 3 and Scheme 4 are similar. The frame error rates of Scheme 3 and Scheme 4 are significantly lower than those of Scheme 1 and Scheme 2.

[0160] The following introduces the decoding performance of medium and high bit rate signals. Figure 8 Schematic diagram of bit error rates of multiple signal processing methods under different signal-to-noise ratio conditions when the bit rate is 3.8. Figure 9 FIG. 1 is a schematic diagram of the frame error rate of multiple signal processing methods under different signal-to-noise ratio conditions when the bit rate is 3.8.

[0161] from Figure 8 It can be seen that when the signal-to-noise ratio is [7.5, 9.4], the bit error rate of scheme 1 is less than the bit error rate of scheme 4, the bit error rate of scheme 3, and the bit error rate of scheme 2.

[0162] from Figure 9 It can be seen that when the signal-to-noise ratio is [8.0, 8.6], the frame error rate of solution 4 is less than that of solution 2, less than that of solution 3, and less than that of solution 1. In the decibel range of [8.7, 9.4], the frame error rate of solution 4 is less than that of solution 3, less than that of solution 2, and less than that of solution 1.

[0163] Schemes 1 and 2 do not use list decoding, while Schemes 3 and 4 do. It can be seen that list decoding significantly reduces the bit error rate and frame error rate at low bit rates. At medium and high bit rates, list decoding also maintains low bit error rates and frame error rates, and the use of sub-block interleaving and Gray code mapping can further reduce the bit error rate and frame error rate.

[0164] In the second decoding method, the modulated bit segments are decoded first, and then the position mapping bit segments are decoded. Figure 10 , another embodiment of the signal processing method of the present application includes:

[0165] Step 1001: Receive a sparse regression codeword.

[0166] Step 1002: Perform approximate message passing decoding on the sparse recursive codeword according to a preset compression matrix and credibility table to obtain a plurality of modulation symbol sub-block groups.

[0167] Step 1003: Generate a first set of candidate segment lists according to the modulation symbol sub-block groups, where the candidate segments in the first set of candidate segment lists are modulation candidate segments.

[0168] Step 1004 : Determine whether each candidate segment list in the first set of candidate segment lists includes the target candidate segment. If so, execute step 1006 ; if not, execute step 1005 .

[0169] For each modulation candidate segment list, a candidate segment is selected in turn for a cyclic redundancy check. If the candidate segment passes the cyclic redundancy check, it is considered the target candidate segment. If the candidate segment fails the cyclic redundancy check, it is not the target candidate segment. The target candidate segment in the modulation candidate segment list includes the modulation bits and the CRC code.

[0170] Step 1005 : Update the credibility table according to the bits that pass the check in the first set of candidate segment lists, and jump to step 1002 .

[0171] Specifically, after performing a CRC check on the first candidate segment list, it can be divided into multiple sub-blocks to be processed, with each sub-block corresponding to a sub-block. The number of bits that pass the check in the i-th sub-block to be processed can be any integer value in [0, J], where i is a positive integer variable. Each sub-block to be processed corresponds to K*M candidate bit sub-blocks, and the credibility of each candidate bit sub-block is in [0, 1].

[0172] When one or more bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block including the aforementioned bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is increased, and the credibility of the remaining candidate bit sub-blocks is updated to 0. When all bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block consisting of the aforementioned bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is updated to 1, and the credibility of the remaining candidate bit sub-blocks is updated to 0. The updated credibility table is more accurate than the credibility table before the update, and more modulated bits can be recovered based on the updated credibility table.

[0173] Step 1006: Determine a first group of bit segments according to the target candidate segments in the first group of candidate segment list, where the bit segments included in the first group of bit segments are modulation bit segments.

[0174] Step 1007: Generate a second set of candidate segment lists according to the first set of bit segments and modulation symbol sub-block groups, where the candidate segments included in the second set of candidate segment lists are position mapping candidate segments.

[0175] The credibility of each mapping position is determined according to the modulation bit segmentation, and a second candidate segmentation list is generated according to the modulation symbol sub-block group and the credibility of each mapping position.

[0176] Step 1008 : Determine whether each candidate segment list in the second set of candidate segment lists includes the target candidate segment. If so, execute step 1010 ; if not, execute step 1009 .

[0177] For each position mapping candidate segment list, select one candidate segment in turn for a cyclic redundancy check. If the candidate segment passes the cyclic redundancy check, it is considered the target candidate segment. If the candidate segment fails the cyclic redundancy check, it is not the target candidate segment. The target candidate segment in the position mapping candidate segment list includes the position mapping bits and the CRC code.

[0178] Step 1009 : Update the credibility table according to the bits that pass the check in the second set of candidate segment lists, and jump to step 1002 .

[0179] Specifically, after performing a CRC check on the second candidate segment list, it can be divided into multiple sub-blocks to be processed, with each sub-block corresponding to a sub-block. The number of bits that pass the check in the i-th sub-block to be processed can be any integer value in [0, J], where i is a positive integer variable. Each sub-block to be processed corresponds to K*M candidate bit sub-blocks, and the credibility of each candidate bit sub-block is in [0, 1].

[0180] When one or more bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block including the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is increased, and the credibility of the remaining candidate bit sub-blocks is updated to 0. When all bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block consisting of the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is updated to 1, and the credibility of the remaining candidate bit sub-blocks is updated to 0. The updated credibility table is more accurate than the credibility table before the update, and more position mapping bits can be recovered based on the updated credibility table.

[0181] Step 1010: Determine a second group of bit segments according to the target candidate segments in the second group of candidate segment list, where the bit segments included in the second group of bit segments are position mapping bit segments.

[0182] Step 1011: Generate a bit sequence according to the first group of bit segments and the second group of bit segments.

[0183] It should be noted that, during iterative execution, for segments that pass the cyclic redundancy check, the cyclic redundancy check may no longer be performed to reduce decoding time.

[0184] In this embodiment, a modulation candidate segment list can be generated through list decoding, the modulation bit segment can be determined through the CRC code, and then a position mapping candidate segment list is generated based on the modulation symbol sub-block group and the modulation bit segment. This can improve the credibility of the candidate bits in the position mapping candidate segment list and thereby reduce the bit error rate.

[0185] Secondly, recovering the modulated bit segments or position-mapped bit segments based on the CRC code is less complex than LDCP decoding and can reduce decoding time.

[0186] based on Figure 10 In an optional embodiment of the embodiment shown, the signal processing method further includes: removing sub-block interleaving from all modulation symbol sub-block groups. The process of removing sub-block interleaving can refer to the process of removing sub-block interleaving described above and will not be repeated here.

[0187] based on Figure 10 In another optional embodiment of the illustrated embodiment, step 1002 includes: performing approximate message passing decoding on the sparse recursive codeword according to a preset compression matrix, a credibility table, and a preset decoding power matrix to obtain multiple weighted sub-block groups; and weighting each weighted sub-block in the multiple weighted sub-block groups using a power value of the preset decoding power matrix to obtain multiple modulation symbol sub-block groups. The specific execution steps and beneficial effects of the decoding power matrix in this embodiment can be found in step 502 and are not further described here.

[0188] In the third decoding method, the modulated bit segments and the position-mapped bit segments are decoded in parallel. Figure 11 , another embodiment of the signal processing method of the present application includes:

[0189] Step 1101: Receive a sparse regression codeword.

[0190] Step 1102: Perform approximate message passing decoding on the sparse recursive codeword according to the preset compression matrix and the credibility table to obtain a plurality of modulation symbol sub-block groups.

[0191] Each modulation symbol sub-block group includes a plurality of modulation symbol sub-blocks.

[0192] Step 1103: Select a first target modulation symbol and a second target modulation symbol from each modulation symbol subblock in the modulation symbol subblock group, where the first target modulation symbol is the position mapping modulation symbol with the highest credibility in the modulation symbol subblock, and the second target modulation symbol is the modulation symbol with the highest credibility in the modulation symbol subblock.

[0193] Step 1104: Determine multiple modulation candidate segment lists according to the modulation symbol sub-block group and the phase of the first target modulation symbol.

[0194] Specifically, multiple modulation candidate segment lists can be determined based on the modulation symbol subblock group and the phase of the first target modulation symbol in each modulation symbol subblock. The number of modulation candidate segment lists determined in this step is equal to the number of modulation bits in a subblock.

[0195] Step 1105 : Determine whether each modulation candidate segment list includes the target candidate segment. If so, execute step 1107 ; if not, execute step 1106 .

[0196] For each modulation candidate segment list, a candidate segment is selected in turn for a cyclic redundancy check. If the candidate segment passes the cyclic redundancy check, it is considered the target candidate segment. If the candidate segment fails the cyclic redundancy check, it is not the target candidate segment. The target candidate segment in the modulation candidate segment list includes the modulation bits and the CRC code.

[0197] Step 1106 : Update the credibility table according to the bits that pass the verification in the multiple modulation candidate segment lists, and jump to step 1102 .

[0198] Specifically, after performing CRC checks on multiple modulation candidate segment lists, they can be divided into multiple to-be-processed sub-blocks, each corresponding to a sub-block. The number of bits that pass the check in the i-th to-be-processed sub-block can be any integer value in the range [0, J], where i is a positive integer variable. Each to-be-processed sub-block corresponds to K*M candidate bit sub-blocks, and the credibility of each candidate bit sub-block is in the range [0, 1].

[0199] When one or more bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block including the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is increased, and the credibility of the remaining candidate bit sub-blocks is updated to 0. When all bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block consisting of the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is updated to 1, and the credibility of the remaining candidate bit sub-blocks is updated to 0. The updated credibility table is more accurate than the credibility table before the update, and more modulated bits can be recovered based on the updated credibility table.

[0200] Step 1107: Determine the modulation bit segmentation according to the target candidate segmentation in the modulation candidate segmentation list.

[0201] Step 1108: Determine multiple position mapping candidate segment lists according to the modulation symbol sub-block group and the second target modulation symbol.

[0202] Step 1109 : Determine whether each position mapping candidate segment list includes the target candidate segment. If so, execute step 1111 ; if not, execute step 1110 .

[0203] For each position mapping candidate segment list, select one candidate segment in turn for a cyclic redundancy check. If the candidate segment passes the cyclic redundancy check, it is considered the target candidate segment. If the candidate segment fails the cyclic redundancy check, it is not the target candidate segment. The target candidate segment in the position mapping candidate segment list includes the position mapping bits and the CRC code.

[0204] Step 1110 : Update the credibility table according to the bits that pass the check in the multiple position mapping candidate segment lists, and jump to step 1102 .

[0205] Specifically, after performing a CRC check on multiple position mapping candidate segment lists, they can be divided into multiple sub-blocks to be processed, with each sub-block corresponding to a sub-block. The number of bits that pass the check in the i-th sub-block to be processed can be any integer value in [0, J], where i is a positive integer variable. Each sub-block to be processed corresponds to K*M candidate bit sub-blocks, and the credibility of each candidate bit sub-block is in [0, 1].

[0206] When one or more bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block including the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is increased, and the credibility of the remaining candidate bit sub-blocks is updated to 0. When all bits in the i-th sub-block to be processed pass the CRC check, the credibility of the candidate bit sub-block consisting of the bits in all candidate bit sub-blocks corresponding to the i-th sub-block to be processed is updated to 1, and the credibility of the remaining candidate bit sub-blocks is updated to 0. The updated credibility table is more accurate than the credibility table before the update, and more modulated bits can be recovered based on the updated credibility table.

[0207] Step 1111: Determine a position mapping bit segment according to target candidate segments in multiple position mapping candidate segment lists.

[0208] Specifically, a position mapping bit segment may be determined according to a target candidate segment in a position mapping candidate segment list.

[0209] Step 1112: Generate a bit sequence according to the modulation bit segmentation and the position mapping bit segmentation.

[0210] After each modulation symbol sub-block group is successfully decoded, a bit sequence is generated according to the modulation bit segment and position mapping bit segment obtained by decoding.

[0211] It should be noted that steps 1104 to 1107 are the process of decoding to obtain modulated bit segments, and steps 1108 to 1111 are the process of decoding to obtain position mapping bit segments. There is no fixed order for the two processes.

[0212] In this embodiment, the position mapping candidate segment list and the modulation candidate segment list are decoded in parallel, thereby improving decoding flexibility.

[0213] Secondly, recovering the modulated bit segments or position-mapped bit segments based on the CRC code is less complex than LDCP decoding and can reduce decoding time.

[0214] based on Figure 11 In an optional embodiment of the illustrated embodiment, the signal processing method further includes removing sub-block interleaving from all modulation symbol sub-block groups. After removing the sub-block interleaving, the order of the modulation symbol sub-block groups is consistent with the order of the sub-block groups during encoding. The transmitting end and the receiving end can negotiate a codec mode. In the specified codec mode, the transmitting end performs sub-block interleaving, while the receiving end removes sub-block interleaving.

[0215] based on Figure 11 In another optional embodiment of the embodiment shown, step 1102 includes: performing approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix, a credibility table and a preset decoding power matrix to obtain multiple weighted sub-block groups; and weighting each weighted sub-block of the multiple weighted sub-block groups using a power value of a preset decoding power matrix to obtain multiple modulation symbol sub-block groups.

[0216] In this embodiment, the decoding power matrix includes multiple power values, and each modulation symbol sub-block corresponds to a power value. The transmitting end and the receiving end can negotiate the encoding and decoding mode. In the specified encoding and decoding mode, the transmitting end weights the modulation symbol sub-blocks according to the encoding power matrix, and the receiving end weights the weighted sub-blocks according to the decoding power matrix. It should be noted that the decoding power matrix is ​​different from the encoding power matrix. For the i-th modulation symbol sub-block and the i-th weighted sub-block, the product of the i-th element of the encoding power matrix and the i-th element of the decoding power matrix is ​​equal to 1, where i is a positive integer. The influence of the power value is removed for each weighted sub-block during decoding.

[0217] In the above signal processing method, CRC codes of the same length are added to different bit segments. This application can also add CRC codes of different lengths to different bit segments. Figure 12 , another embodiment of the signal processing method of the present application includes:

[0218] Step 1201: Divide a bit sequence into a first subsequence and a second subsequence.

[0219] Step 1202: Divide the first subsequence and the second subsequence into multiple groups of bit segments respectively.

[0220] Step 1203: Generate a first extended bit segment according to the bit segment of the first subsequence and the first cyclic redundancy check code.

[0221] Step 1204: Generate a second extended bit segment according to the bit segment of the second subsequence and the second cyclic redundancy check code.

[0222] The length of the first cyclic redundancy check code is smaller than the length of the second cyclic redundancy check code.

[0223] Step 1205: Interleave the first extended bit segments of each group into first sub-block groups.

[0224] Each subblock in the first subblock group includes a modulation bit and a position mapping bit.

[0225] Step 1206: Interleave the second extended bit segments of each group into second sub-block groups.

[0226] Each subblock in the second subblock group includes a modulation bit and a position mapping bit.

[0227] Step 1207: Modulate the first sub-block group into a first modulation symbol sub-block group.

[0228] Step 1208: Modulate the second sub-block group into a second modulation symbol sub-block group.

[0229] Step 1209: Use a preset first coding power matrix to perform a weighted operation on the first modulation symbol sub-block group.

[0230] Step 1210: Use a preset second coding power matrix to perform a weighted operation on the second modulation symbol sub-block group.

[0231] The power values ​​included in the first coding power matrix are greater than or equal to a preset power threshold, and the power values ​​included in the second coding power matrix are less than the preset power threshold. Specifically, each modulation symbol subblock of the first modulation symbol subblock group is multiplied by a power value of the first coding power matrix to obtain a weighted subblock. Each modulation symbol subblock of the second modulation symbol subblock group is multiplied by a power value of the second coding power matrix to obtain a weighted subblock. The first coding power matrix and the second coding power matrix can be submatrices extracted from the same coding power matrix.

[0232] Step 1211: Use a preset compression matrix to compress all modulation symbol sub-blocks into multiple sparse recursive codewords.

[0233] The compressed matrix is ​​a sparse regression matrix or a design matrix. The design matrix includes multiple sparse regression submatrix groups, which are arranged in a staircase manner. Each sparse regression submatrix group includes sparse regression submatrices arranged consecutively in a vertical direction. In the design matrix, all elements except the sparse regression submatrix are 0.

[0234] Step 1212: Send multiple sparse regression codewords.

[0235] It should be noted that step 1203, step 1205, step 1207, and step 1209 are the process of generating weighted sub-blocks based on the first sub-sequence, and step 1204, step 1206, step 1208, and step 1210 are the process of generating weighted sub-blocks based on the second sub-sequence. The two processes are independent and there is no fixed order.

[0236] In this embodiment, after CRC is added to the bit segments, the bits of the bit segments can be restored using CRC during decoding, thereby enhancing the error correction capability and thus reducing the BER and FER.

[0237] Secondly, assigning high power values ​​to sub-blocks with short CRC codes can improve the transmission accuracy of short CRC code bits. In addition, long CRC code bits have better error correction capabilities, which can improve decoding performance under limited code length conditions.

[0238] Thirdly, the bit segments can be encoded and decoded according to CRC codes of different lengths, thus improving the flexibility of the scheme implementation.

[0239] based on Figure 12 In an optional embodiment of the embodiment shown, the signal processing method further includes: performing sub-block interleaving on all first sub-block groups; and performing sub-block interleaving on all second sub-block groups. The process of performing sub-block interleaving on the first sub-block groups and the second sub-block groups is similar to the sub-block interleaving process described above and is not further described here.

[0240] for Figure 12The sparse regression codeword in the embodiment shown is decoded by the following method. Figure 13 Another embodiment of the signal processing method provided by the present application includes:

[0241] Step 1301: Receive a sparse regression codeword.

[0242] Step 1302: perform approximate message passing decoding on the sparse regressive codeword according to the preset first decoding power matrix, the preset second decoding power matrix, the preset compression matrix and the credibility table to obtain a first modulation symbol subblock group and a second modulation symbol subblock group.

[0243] The first modulation symbol subblock group includes fewer modulation symbol subblocks than the second modulation symbol subblock group. The first modulation symbol subblock group corresponds to a subblock of a short CRC code, and the second modulation symbol subblock group corresponds to a subblock of a long CRC code.

[0244] Step 1303: Generate a first candidate segment list according to the first modulation symbol sub-block group.

[0245] Step 1304: When each candidate segment list in the first set of candidate segment lists includes a target candidate segment, determine a first group of bit segments according to the target candidate segment in the first set of candidate segment lists.

[0246] The target candidate segment is a candidate segment that passes the cyclic redundancy check.

[0247] Step 1305: Generate a second set of candidate segment lists according to the first set of bit segments and the first set of modulation symbol sub-blocks.

[0248] Step 1306: When each candidate segment list in the second set of candidate segment lists includes the target candidate segment, determine a second set of bit segments according to the target candidate segment.

[0249] Step 1307: Determine a first subsequence according to the first group of bit segments and the second group of bit segments.

[0250] When the candidate segment list included in the first group of candidate segment lists is a modulation candidate segment list and the candidate segment list included in the second group of candidate segment lists is a position mapping candidate segment list, the bit segments included in the first group of bit segments are modulation bit segments, and the bit segments included in the second group of bit segments are position mapping bit segments.

[0251] When the candidate segment list included in the first group of candidate segment lists is a position mapping candidate segment list and the candidate segment list included in the second group of candidate segment lists is a modulation candidate segment list, the bit segments included in the first group of bit segments are position mapping bit segments, and the bit segments included in the second group of bit segments are modulation bit segments.

[0252] Step 1308: Generate a third candidate segment list according to the second modulation symbol sub-block group.

[0253] Step 1309: When each candidate segment list in the third group of candidate segment lists includes a target candidate segment, determine a third group of bit segments according to the target candidate segment in the third group of candidate segment lists.

[0254] Step 1310: Generate a fourth group of candidate segment lists according to the third group of bit segments and the second group of modulation symbol sub-blocks.

[0255] Step 1311: When each candidate segment list in the fourth group of candidate segment lists includes a target candidate segment, determine a fourth group of bit segments according to the target candidate segment in the fourth group of candidate segment lists.

[0256] When the candidate segment list included in the third group of candidate segment lists is a modulation candidate segment list and the candidate segment list included in the fourth group of candidate segment lists is a position mapping candidate segment list, the bit segments included in the third group of bit segments are modulation bit segments, and the bit segments included in the fourth group of bit segments are position mapping segments.

[0257] When the candidate segment list included in the third group of candidate segment lists is a position mapping candidate segment list and the candidate segment list included in the fourth group of candidate segment lists is a modulation candidate segment list, the bit segments included in the third group of bit segments are position mapping bit segments, and the bit segments included in the fourth group of bit segments are modulation bit segments.

[0258] Step 1312: Determine a second subsequence according to the third group of bit segments and the fourth group of bit segments.

[0259] Steps 1303 to 1307 are the process of obtaining the first subsequence, and steps 1308 to 1312 are the process of obtaining the second subsequence. The two processes are independent of each other and have no fixed order.

[0260] Step 1313: Generate a bit sequence according to the first subsequence and the second subsequence.

[0261] In this embodiment, the position mapping candidate segment list and the modulation candidate segment list can be updated through iteration, which can improve the accuracy of the position mapping candidate segment list and the modulation candidate segment list, thereby reducing the bit error rate.

[0262] Secondly, recovering the modulated bit segments or position-mapped bit segments based on the CRC code is less complex than LDCP decoding and can reduce decoding time.

[0263] based on Figure 13In an optional embodiment of the embodiment shown, after step 1302 and before step 1303, the signal processing method further includes: removing sub-block interleaving from the first modulation symbol sub-block group and the second modulation symbol sub-block group. The process of removing sub-block interleaving can refer to the process of removing sub-block interleaving described above and will not be repeated here.

[0264] for Figure 12 The sparse regression codeword in the embodiment shown, another decoding method is introduced below. Figure 14 , another embodiment of the signal processing method of the present application includes:

[0265] Step 1401: Receive a sparse regression codeword.

[0266] Step 1402: Perform approximate message passing decoding on the sparse regressive codeword according to the preset first decoding power matrix, the preset second decoding power matrix, the preset compression matrix and the credibility table to obtain a first modulation symbol subblock group and a second modulation symbol subblock group.

[0267] Optionally, step 1402 includes: performing approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix, a credibility table, a preset first decoding power matrix and a second preset decoding power matrix to obtain a first weighted sub-block group and a second weighted sub-block group; weighting each sub-block of the first weighted sub-block group according to the preset first decoding power matrix to obtain a first modulation symbol sub-block group; and weighting each sub-block of the second weighted sub-block group according to the preset second decoding power matrix to obtain a second modulation symbol sub-block group.

[0268] Step 1403: Generate a first set of candidate segment lists and a second set of candidate segment lists according to the first modulation symbol sub-block group.

[0269] Step 1404: Determine a first group of bit segments according to the first group of candidate segment lists.

[0270] Step 1405: Determine a second group of bit segments according to the second group of candidate segment lists.

[0271] Specifically, for the first candidate segment list, bit segments are determined based on the candidate segment with the highest credibility to obtain the first set of bit segments. For the second candidate segment list, bit segments are determined based on the candidate segment with the highest credibility to obtain the second set of bit segments.

[0272] Step 1406: Determine a first subsequence according to the first group of bit segments and the second group of bit segments.

[0273] Step 1407: Generate a third candidate segment list according to the second modulation symbol sub-block group.

[0274] Step 1408: Determine a third group of bit segments according to the third group of candidate segment lists.

[0275] Step 1409: Determine a fourth group of bit segments according to the fourth group of candidate segment lists.

[0276] Specifically, for the third candidate segment list, bit segments are determined based on the candidate segment with the highest credibility to obtain the third set of bit segments. For the fourth candidate segment list, bit segments are determined based on the candidate segment with the highest credibility to obtain the fourth set of bit segments.

[0277] Step 1410: Determine a second subsequence according to the third group of bit segments and the fourth group of bit segments.

[0278] Step 1411: Generate a bit sequence according to the first subsequence and the second subsequence.

[0279] In this embodiment, the position mapping candidate segment list and the modulation candidate segment list are decoded in parallel, thereby improving decoding flexibility.

[0280] Secondly, recovering the modulated bit segments or position-mapped bit segments based on the CRC code is less complex than LDCP decoding and can reduce decoding time.

[0281] based on Figure 14 In an optional embodiment of the embodiment shown, before step 1403, the signal processing method further includes: removing sub-block interleaving from all modulation symbol sub-block groups. The process of removing sub-block interleaving can refer to the process of removing sub-block interleaving described above and will not be repeated here.

[0282] In the encoding method of the present application, after the bit sequence is divided into the first subsequence and the second subsequence, CRC may not be added to the segments of one subsequence, while CRC code may be added to the bit segments of the other subsequence. Figure 15 , another embodiment of the signal processing method of the present application includes:

[0283] Step 1501: Divide a bit sequence into a first subsequence and a second subsequence.

[0284] Step 1502: Divide the first subsequence into multiple sub-blocks.

[0285] Each sub-block includes modulation bits and position mapping bits.

[0286] Step 1503: Divide the second subsequence into multiple groups of bit segments.

[0287] Step 1504: Generate an extended bit segment according to each bit segment of the second subsequence and a cyclic redundancy check code.

[0288] Step 1505: Interleave each group of extended bits into sub-block groups.

[0289] Each subblock in the subblock group includes modulation bits and position mapping bits.

[0290] Step 1506: Modulate each sub-block into a modulation symbol sub-block.

[0291] Step 1507: Use a preset compression matrix to compress all modulation symbol sub-blocks into multiple sparse recursive codewords.

[0292] The compressed matrix is ​​a sparse regression matrix or a design matrix. The design matrix includes multiple sparse regression submatrix groups, which are arranged in a staircase manner. Each sparse regression submatrix group includes sparse regression submatrices arranged consecutively in a vertical direction. In the design matrix, all elements except the sparse regression submatrix are 0.

[0293] Step 1508: Send multiple sparse regressive codewords.

[0294] In this embodiment, a portion of bits are not added with a CRC code, and another portion of bits are added with a CRC code, which improves the flexibility of signal processing.

[0295] based on Figure 15 In an optional embodiment of the embodiment shown, after step 1505 and step 1506, the signal processing method further includes: performing sub-block interleaving on all sub-block groups. The sub-block interleaving process is similar to the sub-block interleaving process described above and will not be repeated here.

[0296] based on Figure 15 In an optional embodiment of the illustrated embodiment, step 1507 includes weighting the first modulation symbol subblock group using a preset first decoding power matrix, weighting the second modulation symbol subblock group using a preset second decoding power matrix, and compressing all weighted subblocks into multiple sparse recursive codewords using a preset compression matrix. The specific process of generating sparse recursive codewords from the modulation symbol subblocks described in step 1507 is similar to steps 1209 to 1211 and is not further described here.

[0297] for Figure 15 The codeword of the embodiment shown is described below. Figure 16 , another embodiment of the signal processing method in the present application includes:

[0298] Step 1601: Receive a sparse regression codeword.

[0299] Step 1602: Perform approximate message passing decoding on the sparse regressive codeword according to the preset compression matrix and credibility table to obtain a first modulation symbol sub-block group and a second modulation symbol sub-block group.

[0300] Optionally, step 1602 includes performing approximate message passing decoding on the sparse regressive codeword based on a preset first decoding power matrix, a preset second decoding power matrix, a preset compression matrix, and a credibility table to obtain a first modulation symbol sub-block group and a second modulation symbol sub-block group. The specific process is similar to step 1302 and is not further described here. The first modulation symbol sub-block group includes fewer modulation symbol sub-blocks than the second modulation symbol sub-block group.

[0301] Step 1603: Generate a first subsequence according to the first modulation symbol subblock group.

[0302] Specifically, the first modulation symbol sub-block group is hard-decoded to obtain the first sub-sequence.

[0303] Step 1604: Generate a second subsequence according to the second modulation symbol subblock group.

[0304] In an optional embodiment, step 1604 includes: generating a first group of candidate segment lists based on the second modulation symbol sub-block group; when each candidate segment list in the first group of candidate segment lists includes a target candidate segment, determining a first group of bit segments based on the target candidate segment of the first group of candidate segment lists; generating a second group of candidate segment lists based on the first group of bit segments and the second modulation symbol sub-block group; when each candidate segment list in the second group of candidate segment lists includes a target candidate segment, determining a second group of bit segments based on the target candidate segment of the second group of candidate segment lists; and determining a second subsequence based on the first group of bit segments and the second group of bit segments.

[0305] In another optional embodiment, step 1604 includes: generating a first group of candidate segment lists and a second group of candidate segment lists based on the second modulation symbol sub-block group; determining a first group of bit segments based on the target candidate segments of the first group of candidate segment lists; determining a second group of bit segments based on the target candidate segments of the second group of candidate segment lists; and determining a second subsequence based on the first group of bit segments and the second group of bit segments.

[0306] In the above optional embodiment, when the candidate segment list included in the first group of candidate segment lists is a modulation candidate segment list and the candidate segment list included in the second group of candidate segment lists is a position mapping candidate segment list, the bit segments included in the first group of bit segments are modulation bit segments, and the bit segments included in the second group of bit segments are position mapping bit segments.

[0307] When the candidate segment list included in the first group of candidate segment lists is a position mapping candidate segment list and the candidate segment list included in the second group of candidate segment lists is a modulation candidate segment list, the bit segments included in the first group of bit segments are position mapping bit segments, and the bit segments included in the second group of bit segments are modulation bit segments.

[0308] Step 1605: Generate a bit sequence according to the first subsequence and the second subsequence.

[0309] In this embodiment, the first subsequence and the second subsequence can be decoded in parallel, which improves the flexibility of solution implementation.

[0310] based on Figure 16 In an optional embodiment of the embodiment shown, before step 1603, the signal processing method further includes: removing sub-block interleaving from the second modulation symbol sub-block group. The process of removing sub-block interleaving is similar to the process of removing sub-block interleaving described above and will not be repeated here.

[0311] This application also provides a signal processing device that can implement the above signal processing method. The following are introduced respectively:

[0312] See Figure 17 , an embodiment of the signal processing device 1700 of the present application includes:

[0313] The encoding unit 1701 is configured to divide the bit sequence into a plurality of groups of bit segments, each group of bit segments including at least one bit segment;

[0314] The encoding unit 1701 is further configured to generate an extended bit segment according to the bit segment and the CRC code, wherein the bit segment and the CRC code correspond one to one;

[0315] An interleaving unit 1702 is configured to segmentally interleave each group of extended bits into sub-block groups;

[0316] a modulation unit 1703, configured to modulate each sub-block into a modulation symbol sub-block;

[0317] A compression unit 1704 is configured to compress all modulation symbol sub-blocks into multiple sparse recursive codewords using a preset compression matrix;

[0318] The sending unit 1705 is configured to send multiple sparse recursive codewords.

[0319] The signal processing device 1700 of this embodiment can realize Figure 3 The signal processing method of the embodiment shown or the optional embodiment. The steps and beneficial effects performed by each unit in the signal processing device 1700 can be found in Figure 3 The corresponding description of the illustrated embodiment or the alternative embodiment.

[0320] In an optional embodiment, the interleaving unit 1702 is further configured to perform sub-block interleaving on all sub-block groups.

[0321] In another optional embodiment, the compression unit 1704 is specifically used to weight each modulation symbol sub-block using a preset coding power matrix, the coding power matrix includes multiple power values, and each modulation symbol sub-block corresponds to a power value; and all weighted sub-blocks obtained by weighting are compressed into multiple sparse regression codewords using a preset compression matrix.

[0322] In another optional embodiment, the compression matrix is ​​a sparse regression matrix or a design matrix, the design matrix includes multiple sparse regression sub-matrix groups, the multiple sparse regression sub-matrix groups are arranged in a stepped manner, each sparse regression sub-matrix group includes sparse regression sub-matrices arranged continuously vertically, and the elements in the design matrix except the sparse regression sub-matrix are all 0.

[0323] See Figure 18 , an embodiment of the signal processing device 1800 of the present application includes:

[0324] Receiving unit 1801, configured to receive a sparse regressive codeword;

[0325] an approximate message passing decoding unit 1802, configured to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and a credibility table to obtain a plurality of modulation symbol sub-block groups, each modulation symbol sub-block group including a plurality of modulation symbol sub-blocks;

[0326] A list generating unit 1803 is configured to generate a first set of candidate segment lists according to the modulation symbol sub-block groups;

[0327] a list decoding unit 1804 for determining a first group of bit segments according to the target candidate segment in the first group of candidate segment lists when each candidate segment list in the first group of candidate segment lists includes a target candidate segment, the target candidate segment being a candidate segment that passes a cyclic redundancy check;

[0328] The list generating unit 1803 is further configured to generate a second set of candidate segment lists according to the first set of bit segments and the modulation symbol sub-block groups;

[0329] The list decoding unit 1804 is further configured to determine a second group of bit segments according to the target candidate segment in the second group of candidate segment lists when each candidate segment list in the second group of candidate segment lists includes the target candidate segment;

[0330] The generating unit 1805 is configured to generate a bit sequence according to the first group of bit segments and the second group of bit segments.

[0331] In an alternative embodiment,

[0332] The approximate message passing decoding unit 1802 is also used to, when at least one candidate segment list in the first group of candidate segment lists does not include the target candidate segment, update the credibility table based on the bits that have passed the check in the first group of candidate segment lists, triggering the approximate message passing decoding unit 1802 to perform the step of approximate message passing decoding of the sparse regression codeword according to the preset compression matrix and the credibility table; and / or, when at least one candidate segment list in the second group of candidate segment lists does not include the target candidate segment, update the credibility table based on the bits that have passed the check in the second group of candidate segment lists, triggering the approximate message passing decoding unit 1802 to perform the step of approximate message passing decoding of the sparse regression codeword according to the preset compression matrix and the credibility table.

[0333] In another optional embodiment, the list generating unit 1803 is further configured to remove sub-block interleaving from all modulation symbol sub-block groups.

[0334] In another optional embodiment, the candidate segment lists included in the first group of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the second group of candidate segment lists are modulation candidate segment lists.

[0335] In another optional embodiment, the candidate segment lists included in the first group of candidate segment lists are modulation candidate segment lists, and the candidate segment lists included in the second group of candidate segment lists are position mapping candidate segment lists.

[0336] In another optional embodiment, the approximate message passing decoding unit 1802 is further used to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix, a credibility table and a preset decoding power matrix to obtain multiple weighted sub-block groups; and use the power value of the preset decoding power matrix to weight each weighted sub-block of the multiple weighted sub-block groups to obtain multiple modulation symbol sub-block groups.

[0337] In another optional embodiment, the compression matrix is ​​a sparse regression matrix.

[0338] In another optional embodiment, the compression matrix is ​​a design matrix, the design matrix includes multiple sparse regression sub-matrix groups, the multiple sparse regression sub-matrix groups are arranged in a stepped manner, each sparse regression sub-matrix group includes sparse regression sub-matrices arranged continuously vertically, and all elements in the design matrix except the sparse regression sub-matrix are 0.

[0339] In another alternative embodiment,

[0340] Receiving unit 1801, configured to receive a sparse regressive codeword;

[0341] an approximate message passing decoding unit 1802, configured to perform approximate message passing decoding on the sparse recursive codeword according to a preset compression matrix and a credibility table to obtain a plurality of modulation symbol sub-block groups, each modulation symbol sub-block group including a plurality of modulation symbol sub-blocks;

[0342] a list generating unit 1803 configured to select a first target modulation symbol and a second target modulation symbol from each modulation symbol subblock in the modulation symbol subblock group, wherein the first target modulation symbol is a position-mapped modulation symbol with the highest credibility in the modulation symbol subblock, and the second target modulation symbol is a modulation symbol with the highest credibility in the modulation symbol subblock;

[0343] The list generating unit 1803 is further configured to determine a plurality of modulation candidate segment lists according to the modulation symbol sub-block group and the phase of the first target modulation symbol;

[0344] The list decoding unit 1804 is further configured to, when each modulation candidate segment list includes a target candidate segment, determine the modulation bit segment according to the target candidate segment in the modulation candidate segment list, the target candidate segment being a candidate segment that passes a cyclic redundancy check;

[0345] The list generating unit 1803 is further configured to determine a plurality of position mapping candidate segment lists according to the modulation symbol sub-block group and the second target modulation symbol;

[0346] The list decoding unit 1804 is further configured to determine the position mapping bit segment according to the target candidate segment of the position mapping candidate segment list when each position mapping candidate segment list includes a target candidate segment;

[0347] The generating unit 1805 is configured to generate a bit sequence according to the modulation bit segmentation and the position mapping bit segmentation.

[0348] The signal processing device 1800 of this embodiment can realize Figure 5 、 Figure 10 or Figure 11 The signal processing method of the embodiment shown or the optional embodiment. The steps and beneficial effects performed by each unit in the signal processing device 1800 can be referred to Figure 5 、 Figure 10 or Figure 11 The corresponding description of the illustrated embodiment or the alternative embodiment.

[0349] In an alternative embodiment,

[0350] Approximate message passing 1802 is also used to, when at least one modulation candidate segment list does not include a target candidate segment, update the credibility table based on the bits that have passed the check in multiple modulation candidate segment lists, triggering the approximate message passing decoding unit 1802 to perform the step of approximate message passing decoding of the sparse regression codeword according to the preset compression matrix and the credibility table; and / or, when at least one position mapping candidate segment list does not include a target candidate segment, update the credibility table based on the bits that have passed the check in multiple position mapping candidate segment lists, triggering the approximate message passing decoding unit 1802 to perform the step of approximate message passing decoding of the sparse regression codeword according to the preset compression matrix and the credibility table.

[0351] See Figure 19 , an embodiment of the signal processing device 1900 of the present application includes:

[0352] Coding unit 1901 is configured to divide a bit sequence into a first subsequence and a second subsequence; divide the first subsequence and the second subsequence into a plurality of bit segments respectively; generate a first extended bit segment based on the bit segments of the first subsequence and a first CRC code; and generate a second extended bit segment based on the bit segments of the second subsequence and a second CRC code, wherein a length of the first CRC code is less than a length of the second CRC code.

[0353] an interleaving unit 1902, configured to segmentally interleave the first extended bits of each group into a first sub-block group, and segmentally interleave the second extended bits of each group into a second sub-block group;

[0354] The modulation unit 1903 is configured to modulate the first sub-block group into a first modulation symbol sub-block group, and modulate the second sub-block group into a second modulation symbol sub-block group;

[0355] A power allocation unit 1904 is configured to perform a weighted operation on the first modulation symbol sub-block group using a preset first coding power matrix; and perform a weighted operation on the second modulation symbol sub-block group using a preset second coding power matrix, wherein the power values ​​included in the first coding power matrix are greater than or equal to a preset power threshold, and the power values ​​included in the second coding power matrix are less than the preset power threshold.

[0356] A compression unit 1905 is configured to compress all modulation symbol sub-blocks into multiple sparse recursive codewords using a preset compression matrix;

[0357] The sending unit 1906 is configured to send multiple sparse recursive codewords.

[0358] The signal processing device 1900 of this embodiment can realize Figure 12 The signal processing method of the embodiment shown or the optional embodiment. The steps and beneficial effects performed by each unit in the signal processing device 1900 can be found in Figure 12The corresponding description in the illustrated embodiment.

[0359] See Figure 20 , an embodiment of the signal processing device 2000 of the present application includes:

[0360] The receiving unit 2001 is configured to receive a sparse regressive codeword;

[0361] an approximate message passing decoding unit 2002, configured to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix, a preset first decoding power matrix, a preset second decoding power matrix, and a credibility table, to obtain a first modulation symbol sub-block group and a second modulation symbol sub-block group, wherein the first modulation symbol sub-block group includes fewer modulation symbol sub-blocks than the second modulation symbol sub-block group.

[0362] A list generating unit 2003 is configured to generate a first candidate segment list according to the first modulation symbol sub-block group;

[0363] a list decoding unit 2004 configured to determine a first group of bit segments according to the target candidate segment in the first group of candidate segment lists when each candidate segment list in the first group of candidate segment lists includes a target candidate segment, the target candidate segment being a candidate segment that passes a cyclic redundancy check;

[0364] The list generating unit 2003 is further configured to generate a second group of candidate segment lists according to the first group of bit segments and the first group of modulation symbol sub-blocks;

[0365] The list decoding unit 2004 is further configured to determine a second group of bit segments according to the target candidate segment in the second group of candidate segment lists when each candidate segment list in the second group of candidate segment lists includes the target candidate segment;

[0366] A generating unit 2005 is configured to determine a first subsequence according to the first group of bit segments and the second group of bit segments;

[0367] The list generating unit 2003 is further configured to generate a third candidate segment list according to the second modulation symbol sub-block group;

[0368] The list decoding unit 2004 is further configured to determine a third group of bit segments according to the target candidate segment in the third group of candidate segment lists when each candidate segment list in the third group of candidate segment lists includes the target candidate segment;

[0369] The list generating unit 2003 is further configured to generate a fourth group of candidate segment lists according to the third group of bit segments and the second group of modulation symbol sub-blocks;

[0370] The list decoding unit 2004 is further configured to determine a fourth group of bit segments according to the target candidate segment in the fourth group of candidate segment lists when each candidate segment list in the fourth group of candidate segment lists includes the target candidate segment;

[0371] The generating unit 2005 is further configured to determine a second subsequence according to the third group of bit segments and the fourth group of bit segments; and generate a bit sequence according to the first subsequence and the second subsequence.

[0372] The signal processing device 2000 of this embodiment can realize Figure 13 or Figure 14 The signal processing method of the embodiment or the optional embodiment shown. The steps and beneficial effects performed by each unit in the signal processing device 2000 can be found in Figure 13 or Figure 14 The corresponding description in the illustrated embodiment.

[0373] In an optional embodiment, the candidate segment list included in the first group of candidate segment lists is a modulation candidate segment list, the candidate segment list included in the second group of candidate segment lists is a position mapping candidate segment list, the candidate segment list included in the third group of candidate segment lists is a modulation candidate segment list, and the candidate segment list included in the fourth group of candidate segment lists is a position mapping candidate segment list.

[0374] In another optional embodiment, the candidate segment list included in the first group of candidate segment lists is a position mapping candidate segment list, the candidate segment list included in the second group of candidate segment lists is a modulation candidate segment list, the candidate segment list included in the third group of candidate segment lists is a position mapping candidate segment list, and the candidate segment list included in the fourth group of candidate segment lists is a modulation candidate segment list.

[0375] See Figure 21 In one example, the communication device 2100 of the present application includes a memory 2101, a processor 2102, a communication interface 2103, and a bus 2104. The memory 2101, the processor 2102, and the communication interface 2103 are connected to each other via the bus 2104.

[0376] The memory 2101 may be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 2101 may store programs. When the program stored in the memory 2101 is executed by the processor 2102, the processor 2102 and the communication interface 2103 are used to perform the various steps of the signal processing method in the embodiment of the present application. Specifically, the processor 2102 may perform the signal processing method described above.

[0377] Processor 2102 can be a general-purpose central processing unit (CPU), an artificial intelligence processor, a microprocessor, an application-specific integrated circuit (ASIC), a graphics processor or one or more integrated circuits, used to execute relevant programs to implement the functions performed by the units in the communication device of the embodiment of the present application, or to execute the signal processing method of the method embodiment of the present application.

[0378] The steps of the method in conjunction with the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 2101, and the processor 2102 reads the information in the memory 2101 and, in combination with its hardware, completes the functions required to be performed by the units included in the communication device of the embodiment of the present application, or performs the signal processing method of the method embodiment of the present application.

[0379] The processor 2102 may also be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the signal processing method of the present application may be completed by hardware integrated logic circuits in the processor 2102 or software instructions.

[0380] The communication interface 2103 uses a transceiver device such as, but not limited to, a transceiver to implement communication between the apparatus 2100 and other devices or a communication network.

[0381] The bus 2104 may include a path for transmitting information between various components of the communication device 2100 (eg, the memory 2101, the processor 2102, the communication interface 2103). The steps performed by the signal processing device in the above embodiment may be based on Figure 21 The communication device structure shown.

[0382] The present application discloses a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer is enabled to execute the signal processing method in the above-mentioned embodiment.

[0383] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0384] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be stored by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0385] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal processing method, characterized in that: include: dividing the bit sequence into a plurality of groups of bit segments, each group of bit segments comprising at least one bit segment; generating an extended bit segment according to the bit segment and the cyclic redundancy check (CRC) code, wherein the bit segment and the CRC code correspond one to one; Interleaving each group of extended bits into sub-block groups, wherein the sub-block groups include a plurality of sub-blocks; Modulating the modulation bits in all sub-blocks to obtain modulation symbol sub-blocks corresponding to the modulation bits; Performing Gray code mapping and position mapping on the position mapping bits in all sub-blocks to obtain modulation symbol sub-blocks corresponding to the position mapping bits; Compressing all modulation symbol sub-blocks into multiple sparse recursive codewords using a preset compression matrix; The plurality of sparse regressive codewords are sent.

2. The method according to claim 1, characterized in that Before modulating each sub-block into a modulation symbol sub-block, the method further includes: All sub-block groups are sub-block interleaved.

3. The method according to claim 1, characterized in that The compressing all modulation symbol sub-blocks into multiple sparse recursive codewords using a preset compression matrix includes: weighting each modulation symbol subblock using a preset coding power matrix, wherein the coding power matrix includes a plurality of power values, one power value corresponding to each modulation symbol subblock; All weighted sub-blocks obtained by weighting are compressed into multiple sparse regression codewords using a preset compression matrix.

4. The method according to any one of claims 1 to 3, characterized in that The compressed matrix is ​​a sparse regression matrix or a design matrix, the design matrix includes multiple sparse regression sub-matrix groups, the multiple sparse regression sub-matrix groups are arranged in a stepped manner, each of the sparse regression sub-matrix groups includes sparse regression sub-matrices arranged continuously vertically, and the elements in the design matrix except the sparse regression sub-matrix are all 0.

5. A signal processing method, characterized in that: include: Step A: receiving a sparse regression codeword; Step B: performing approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and a credibility table to obtain a plurality of modulation symbol sub-block groups, each modulation symbol sub-block group including a plurality of modulation symbol sub-blocks; Step C: generating a first set of candidate segment lists according to the modulation symbol sub-block group; Step D: when each candidate segment list in the first set of candidate segment lists includes a target candidate segment, determining a first set of bit segments according to the target candidate segment in the first set of candidate segment lists, the target candidate segment being a candidate segment that passes a cyclic redundancy check; Step E: generating a second set of candidate segment lists according to the first set of bit segments and the modulation symbol sub-block groups; Step F: when each candidate segment list in the second set of candidate segment lists includes a target candidate segment, determining a second set of bit segments according to the target candidate segment in the second set of candidate segment lists; Step G: Generate a bit sequence according to the first group of bit segments and the second group of bit segments.

6. The method according to claim 5, characterized in that The method further comprises: When at least one candidate segment list in the first set of candidate segment lists does not include the target candidate segment, updating the credibility table according to the bits that pass the check in the first set of candidate segment lists, triggering steps B to C; and / or, When at least one candidate segment list in the second group of selected segment lists does not include the target candidate segment, the credibility table is updated according to the bits that pass the check in the second group of candidate segment lists, triggering steps B to E.

7. The method according to claim 5, characterized in that Before generating a first set of candidate segment lists according to the modulation symbol sub-block groups, the method further includes: All modulation symbol subblock groups are desubblocked.

8. The method according to claim 5, characterized in that The candidate segment lists included in the first group of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the second group of candidate segment lists are modulation candidate segment lists; or, The candidate segment lists included in the first group of candidate segment lists are modulation candidate segment lists, and the candidate segment lists included in the second group of candidate segment lists are position mapping candidate segment lists.

9. The method according to claim 5, characterized in that The performing approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and a credibility table to obtain a plurality of modulation symbol sub-block groups includes: performing approximate message passing decoding on the sparse regression codeword according to a preset compression matrix, a credibility table, and a preset decoding power matrix to obtain a plurality of weighted sub-block groups; Each weighted sub-block of the plurality of weighted sub-block groups is weighted using a power value of a preset decoding power matrix to obtain a plurality of modulation symbol sub-block groups.

10. The method according to any one of claims 5 to 9, characterized in that The compressed matrix is ​​a sparse regression matrix or a design matrix, the design matrix includes multiple sparse regression sub-matrix groups, the multiple sparse regression sub-matrix groups are arranged in a stepped manner, each of the sparse regression sub-matrix groups includes sparse regression sub-matrices arranged continuously vertically, and the elements in the design matrix except the sparse regression sub-matrix are all 0.

11. A signal processing method, characterized in that: include: Step A: receiving a sparse regression codeword; Step B: performing approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and a credibility table to obtain a plurality of modulation symbol sub-block groups, each modulation symbol sub-block group including a plurality of modulation symbol sub-blocks; Step C: selecting a first target modulation symbol and a second target modulation symbol from each modulation symbol sub-block of the modulation symbol sub-block group, wherein the first target modulation symbol is a position-mapped modulation symbol with the highest credibility in the modulation symbol sub-block, and the second target modulation symbol is a modulation symbol with the highest credibility in the modulation symbol sub-block; Step D: determining a plurality of modulation candidate segment lists according to the modulation symbol sub-block group and the phase of the first target modulation symbol; Step E: when each of the modulation candidate segment lists includes a target candidate segment, determining a modulation bit segment according to the target candidate segment in the modulation candidate segment list, the target candidate segment being a candidate segment that passes a cyclic redundancy check; Step F: determining a plurality of position mapping candidate segment lists according to the modulation symbol sub-block group and the second target modulation symbol; Step G: when each of the position mapping candidate segment lists includes a target candidate segment, determining a position mapping bit segment according to the target candidate segment in the position mapping candidate segment list; Step H: Generate a bit sequence according to the modulation bit segment and the position mapping bit segment.

12. The method according to claim 11, characterized in that When at least one of the modulation candidate segment lists does not include the target candidate segment, updating the credibility table according to the bits that pass the check in the multiple modulation candidate segment lists, triggering steps B to D; and / or, When at least one of the position mapping candidate segment lists does not include the target candidate segment, the credibility table is updated according to the bits that pass the check in the multiple position mapping candidate segment lists, triggering steps B to F.

13. A signal processing method, characterized in that: include: dividing the bit sequence into a first subsequence and a second subsequence; dividing the first subsequence and the second subsequence into a plurality of groups of bit segments respectively; generating a first extended bit segment according to the bit segment of the first subsequence and a first cyclic redundancy check (CRC) code, and generating a second extended bit segment according to the bit segment of the second subsequence and a second CRC code, wherein a length of the first CRC code is less than a length of the second CRC code; Interleaving the first extended bit segment of each group into a first sub-block group, and interleaving the second extended bit segment of each group into a second sub-block group; Modulating the first sub-block group into a first modulation symbol sub-block group, and modulating the second sub-block group into a second modulation symbol sub-block group; Performing a weighted operation on the first modulation symbol sub-block group using a preset first coding power matrix, and performing a weighted operation on the second modulation symbol sub-block group using a preset second coding power matrix, wherein the power values ​​included in the first coding power matrix are greater than or equal to a preset power threshold, and the power values ​​included in the second coding power matrix are less than the preset power threshold; Compressing all modulation symbol sub-blocks into multiple sparse recursive codewords using a preset compression matrix; The plurality of sparse regressive codewords are sent.

14. A signal processing method, characterized in that: include: receiving a sparse regression codeword; performing approximate message passing decoding on the sparse regressive codeword according to a preset first decoding power matrix, a preset second decoding power matrix, a preset compression matrix, and a credibility table to obtain a first modulation symbol sub-block group and a second modulation symbol sub-block group, wherein the first modulation symbol sub-block group includes fewer modulation symbol sub-blocks than the second modulation symbol sub-block group; generating a first set of candidate segment lists according to the first modulation symbol sub-block group; When each candidate segment list in the first set of candidate segment lists includes a target candidate segment, determining a first set of bit segments according to the target candidate segment in the first set of candidate segment lists, the target candidate segment being a candidate segment that passes a cyclic redundancy check; generating a second set of candidate segment lists based on the first set of bit segments and the first set of modulation symbol sub-blocks; When each candidate segment list in the second set of candidate segment lists includes a target candidate segment, determining a second set of bit segments according to the target candidate segment in the second set of candidate segment lists; determining a first subsequence based on the first group of bit segments and the second group of bit segments; generating a third set of candidate segment lists according to the second modulation symbol sub-block group; When each candidate segment list in the third set of candidate segment lists includes a target candidate segment, determining a third set of bit segments according to the target candidate segment in the third set of candidate segment lists; generating a fourth set of candidate segment lists according to the third set of bit segments and the second set of modulation symbol sub-blocks; When each candidate segment list in the fourth set of candidate segment lists includes a target candidate segment, determining a fourth set of bit segments according to the target candidate segment in the fourth set of candidate segment lists; Determining a second subsequence according to the third group of bit segments and the fourth group of bit segments; A bit sequence is generated according to the first subsequence and the second subsequence.

15. The method according to claim 14, characterized in that The candidate segment lists included in the first group of candidate segment lists are modulation candidate segment lists, the candidate segment lists included in the second group of candidate segment lists are position mapping candidate segment lists, the candidate segment lists included in the third group of candidate segment lists are modulation candidate segment lists, and the candidate segment lists included in the fourth group of candidate segment lists are position mapping candidate segment lists; or, The candidate segment lists included in the first group of candidate segment lists are position mapping candidate segment lists, the candidate segment lists included in the second group of candidate segment lists are modulation candidate segment lists, the candidate segment lists included in the third group of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the fourth group of candidate segment lists are modulation candidate segment lists.

16. A signal processing device, characterized in that: include: an encoding unit, configured to divide the bit sequence into a plurality of groups of bit segments, each group of bit segments including at least one bit segment; The encoding unit is further configured to generate an extended bit segment according to the bit segment and a cyclic redundancy check (CRC) code, wherein the bit segment and the CRC code have a one-to-one correspondence; an interleaving unit, configured to segmentally interleave each group of extended bits into sub-block groups; a modulation unit, configured to modulate the modulation bits in all sub-blocks to obtain modulation symbol sub-blocks corresponding to the modulation bits; Performing Gray code mapping and position mapping on the position mapping bits in all sub-blocks to obtain modulation symbol sub-blocks corresponding to the position mapping bits; A compression unit, configured to compress all modulation symbol sub-blocks into a plurality of sparse recursive codewords using a preset compression matrix; The sending unit is configured to send multiple sparse regressive codewords.

17. The device according to claim 16, characterized in that The interleaving unit is further configured to perform sub-block interleaving on all sub-block groups.

18. The device according to claim 16, characterized in that The compression unit is specifically used to weight each modulation symbol sub-block using a preset coding power matrix, where the coding power matrix includes multiple power values, and each modulation symbol sub-block corresponds to a power value; and all weighted sub-blocks obtained by weighting are compressed into multiple sparse regression codewords using the preset compression matrix.

19. The device according to any one of claims 16 to 18, characterized in that The compressed matrix is ​​a sparse regression matrix or a design matrix, the design matrix includes multiple sparse regression sub-matrix groups, the multiple sparse regression sub-matrix groups are arranged in a stepped manner, each of the sparse regression sub-matrix groups includes sparse regression sub-matrices arranged continuously vertically, and the elements in the design matrix except the sparse regression sub-matrix are all 0.

20. A signal processing device, characterized in that: include: A receiving unit, configured to receive a sparse regression codeword; an approximate message passing decoding unit, configured to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and a credibility table to obtain a plurality of modulation symbol sub-block groups, each modulation symbol sub-block group including a plurality of modulation symbol sub-blocks; a list generating unit, configured to generate a first set of candidate segment lists according to the modulation symbol sub-block group; a list decoding unit configured to determine a first group of bit segments according to the target candidate segment in the first group of candidate segment lists when each candidate segment list in the first group of candidate segment lists includes a target candidate segment, the target candidate segment being a candidate segment that passes a cyclic redundancy check; The list generating unit is further configured to generate a second group of candidate segment lists according to the first group of bit segments and the modulation symbol sub-block groups; The list decoding unit is further configured to determine a second group of bit segments according to the target candidate segment in the second group of candidate segment lists when each candidate segment list in the second group of candidate segment lists includes a target candidate segment; A generating unit is configured to generate a bit sequence according to the first group of bit segments and the second group of bit segments.

21. The device according to claim 20, characterized in that The approximate message passing decoding unit is further configured to, when at least one candidate segment list in the first group of candidate segment lists does not include a target candidate segment, update the credibility table according to bits that pass the check in the first group of candidate segment lists, thereby triggering the approximate message passing decoding unit to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and the credibility table; And / or, when at least one candidate segment list in the second group of selected segment lists does not include the target candidate segment, the credibility table is updated according to the bits that pass the check in the second group of candidate segment lists, triggering the approximate message passing decoding unit to perform the step of approximate message passing decoding of the sparse regression codeword according to the preset compression matrix and the credibility table.

22. The device according to claim 20, characterized in that The list generating unit is further configured to remove sub-block interleaving from all modulation symbol sub-block groups.

23. The device according to claim 20, characterized in that The candidate segment lists included in the first group of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the second group of candidate segment lists are modulation candidate segment lists; or, The candidate segment lists included in the first group of candidate segment lists are modulation candidate segment lists, and the candidate segment lists included in the second group of candidate segment lists are position mapping candidate segment lists.

24. The device according to claim 20, characterized in that The approximate message passing decoding unit is further configured to perform approximate message passing decoding on the sparse regression codeword according to a preset compression matrix, a credibility table, and a preset decoding power matrix to obtain a plurality of weighted sub-block groups; Each weighted sub-block of the plurality of weighted sub-block groups is weighted using a power value of a preset decoding power matrix to obtain a plurality of modulation symbol sub-block groups.

25. The device according to any one of claims 20 to 24, characterized in that The compressed matrix is ​​a sparse regression matrix or a design matrix, the design matrix includes multiple sparse regression sub-matrix groups, the multiple sparse regression sub-matrix groups are arranged in a stepped manner, each of the sparse regression sub-matrix groups includes sparse regression sub-matrices arranged continuously vertically, and the elements in the design matrix except the sparse regression sub-matrix are all 0.

26. A signal processing device, characterized in that: include: A receiving unit, configured to receive a sparse regression codeword; an approximate message passing decoding unit, configured to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and a credibility table to obtain a plurality of modulation symbol sub-block groups, each modulation symbol sub-block group including a plurality of modulation symbol sub-blocks; a list generating unit, configured to select a first target modulation symbol and a second target modulation symbol from each modulation symbol subblock of the modulation symbol subblock group, wherein the first target modulation symbol is a position-mapped modulation symbol with the greatest credibility in the modulation symbol subblock, and the second target modulation symbol is a modulation symbol with the greatest credibility in the modulation symbol subblock; The list generating unit is further configured to determine a plurality of modulation candidate segment lists according to the modulation symbol sub-block group and the phase of the first target modulation symbol; The list decoding unit is further configured to determine the modulation bit segment according to the target candidate segment in the modulation candidate segment list when each of the modulation candidate segment lists includes a target candidate segment, the target candidate segment being a candidate segment that passes a cyclic redundancy check; The list generating unit is further configured to determine a plurality of position mapping candidate segment lists according to the modulation symbol sub-block group and the second target modulation symbol; The list decoding unit is further configured to determine the position mapping bit segment according to the target candidate segment of the position mapping candidate segment list when each of the position mapping candidate segment lists includes a target candidate segment; The generating unit is configured to generate a bit sequence according to the modulation bit segment and the position mapping bit segment.

27. The device according to claim 26, characterized in that The approximate message passing decoding unit is further configured to, when at least one of the modulation candidate segment lists does not include a target candidate segment, update the credibility table according to the bits that pass the check in the multiple modulation candidate segment lists, thereby triggering the approximate message passing decoding unit to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix and the credibility table; And / or, when at least one of the position mapping candidate segment lists does not include the target candidate segment, the credibility table is updated according to the bits that have passed the check in the multiple position mapping candidate segment lists, triggering the approximate message passing decoding unit to perform the step of approximate message passing decoding of the sparse regression codeword according to the preset compression matrix and the credibility table.

28. A signal processing device, characterized in that: include: an encoding unit, configured to divide the bit sequence into a first subsequence and a second subsequence; dividing the first subsequence and the second subsequence into a plurality of groups of bit segments respectively; generating a first extended bit segment based on the bit segment of the first subsequence and a first cyclic redundancy check (CRC) code; generating a second extended bit segment based on the bit segment of the second subsequence and a second CRC code, wherein a length of the first CRC code is less than a length of the second CRC code; an interleaving unit, configured to segmentally interleave the first extended bits of each group into a first sub-block group, and segmentally interleave the second extended bits of each group into a second sub-block group; a modulation unit, configured to modulate the first sub-block group into a first modulation symbol sub-block group, and modulate the second sub-block group into a second modulation symbol sub-block group; a power allocation unit, configured to perform a weighted operation on the first modulation symbol sub-block group using a preset first coding power matrix; and perform a weighted operation on the second modulation symbol sub-block group using a preset second coding power matrix, wherein the power values ​​included in the first coding power matrix are greater than or equal to a preset power threshold, and the power values ​​included in the second coding power matrix are less than the preset power threshold; A compression unit, configured to compress all modulation symbol sub-blocks into a plurality of sparse recursive codewords using a preset compression matrix; A sending unit is configured to send the multiple sparse regressive codewords.

29. A signal processing device, characterized in that: include: A receiving unit, configured to receive a sparse regression codeword; an approximate message passing decoding unit, configured to perform approximate message passing decoding on the sparse regressive codeword according to a preset compression matrix, a preset first decoding power matrix, a preset second decoding power matrix, and a credibility table, to obtain a first modulation symbol sub-block group and a second modulation symbol sub-block group, wherein the first modulation symbol sub-block group includes fewer modulation symbol sub-blocks than the second modulation symbol sub-block group; a list generating unit, configured to generate a first set of candidate segment lists according to the first modulation symbol sub-block group; a list decoding unit configured to determine a first group of bit segments according to the target candidate segment in the first group of candidate segment lists when each candidate segment list in the first group of candidate segment lists includes a target candidate segment, the target candidate segment being a candidate segment that passes a cyclic redundancy check; The list generating unit is further configured to generate a second group of candidate segment lists according to the first group of bit segments and the first group of modulation symbol sub-blocks; The list decoding unit is further configured to determine a second group of bit segments according to the target candidate segment in the second group of candidate segment lists when each candidate segment list in the second group of candidate segment lists includes a target candidate segment; a generating unit, configured to determine a first subsequence according to the first group of bit segments and the second group of bit segments; The list generating unit is further configured to generate a third candidate segment list according to the second modulation symbol sub-block group; The list decoding unit is further configured to determine a third group of bit segments according to the target candidate segment in the third group of candidate segment lists when each candidate segment list in the third group of candidate segment lists includes a target candidate segment; The list generating unit is further configured to generate a fourth group of candidate segment lists according to the third group of bit segments and the second group of modulation symbol sub-blocks; The list decoding unit is further configured to determine a fourth group of bit segments according to the target candidate segment of the fourth group of candidate segment lists when each candidate segment list in the fourth group of candidate segment lists includes a target candidate segment; The generating unit is further configured to determine a second subsequence according to the third group of bit segments and the fourth group of bit segments; and generate a bit sequence according to the first subsequence and the second subsequence.

30. The device according to claim 29, characterized in that The candidate segment lists included in the first group of candidate segment lists are modulation candidate segment lists, the candidate segment lists included in the second group of candidate segment lists are position mapping candidate segment lists, the candidate segment lists included in the third group of candidate segment lists are modulation candidate segment lists, and the candidate segment lists included in the fourth group of candidate segment lists are position mapping candidate segment lists; or, The candidate segment lists included in the first group of candidate segment lists are position mapping candidate segment lists, the candidate segment lists included in the second group of candidate segment lists are modulation candidate segment lists, the candidate segment lists included in the third group of candidate segment lists are position mapping candidate segment lists, and the candidate segment lists included in the fourth group of candidate segment lists are modulation candidate segment lists.

31. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed on a computer, enables the computer to execute the signal processing method according to any one of claims 1 to 15.

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