In-memory computing device for parallel vector multiplier-adder and electronic device

Abstract

The embodiment of the application provides a kind of in-memory computing device of parallel vector multiplier-accumulator and electronic equipment, it is related to in-memory computing technical field, can improve the computing speed.The in-memory computing device of parallel vector multiplier-accumulator, comprising: L multiplication module, each multiplication module includes q multiplication unit and an adder, q>1, L>1;Multiplication unit includes memory and multiplication circuit;The adder includes q addition input, the output of the a multiplication unit is electrically connected to the a addition input, a is 1, 2, …, q;Shift accumulator, shift accumulator includes L accumulation input, the output of the b multiplication module is electrically connected to the b accumulation input, b is 1, 2, …, L;Each accumulation input has corresponding weight value, and shift accumulator is used for carrying out shift accumulation calculation based on the weight value corresponding to each accumulation input value of L accumulation input.

Description

Technical Field

[0001] This application relates to the field of in-memory computing technology, and in particular to an in-memory computing device and electronic device with a parallel vector multiplier-accumulator. Background Technology

[0002] In traditional von Neumann architectures, a significant portion of performance and power consumption is spent on data transmission and read / write operations, resulting in relatively low efficiency. To address this issue, computing-in-memory (CIM) architecture emerged. CIM integrates computing and storage units onto a single chip, forming a storage unit with computing capabilities where computation is performed. This extremely close proximity eliminates latency and power consumption during data movement, mitigating the "memory wall" and "power wall" problems, thus improving computational energy efficiency compared to traditional architectures. However, current CIM architecture chips exhibit slow computation speeds when processing large amounts of data. Summary of the Invention

[0003] An in-memory computing device and electronic device for a parallel vector multiplier-accumulator, which can improve computing speed.

[0004] In a first aspect, an in-memory computation device for a parallel vector multiply-adder is provided, comprising: L multiply-add modules, each multiply-add module including q multiplication units and an adder, where q > 1 and L > 1; each multiplication unit includes a memory and a multiplication circuit, the multiplication circuit including a first multiplication input terminal and a second multiplication input terminal, the second multiplication input terminal being electrically connected to the output terminal of the memory, the multiplication circuit being used to perform multiplication calculations on the values ​​of the first multiplication input terminal and the second multiplication input terminal and outputting the result through the output terminal of the multiplication unit; the adder includes q addition inputs. The a-th adder input is electrically connected to the output of the a-th multiplication unit, where a takes the value 1, 2, ..., q. The output of each adder is the output of the corresponding multiply-accumulate module. The shift accumulator has L accumulation inputs, with the b-th accumulation input electrically connected to the output of the b-th multiply-accumulate module, where b takes the value 1, 2, ..., L. Each accumulation input has a corresponding weight value, and the shift accumulator is used to perform shift and accumulation calculations on the values ​​of the L accumulation inputs based on the weight value corresponding to each accumulation input.

[0005] In one possible implementation, the in-memory computing device further includes: an input module corresponding to at least one multiply-accumulate module, the input module including q-1 input units cascaded in sequence, the input units being used to output the value input in the previous cycle in the current cycle; the output terminal of the a-th input unit is electrically connected to the first multiplication input terminal of the (a+1)-th multiplication unit of the corresponding multiply-accumulate module; the input terminal of the first input unit is electrically connected to the first multiplication input terminal of the first multiplication unit of the corresponding multiply-accumulate module; the input terminal of the c-th input unit is electrically connected to the output terminal of the (c-1)-th input unit, where c takes the value 2, 3, ..., q.

[0006] In one possible implementation, the in-memory computing device includes: m groups of multiply-accumulate modules, each group including p multiply-accumulate modules and an input module, where p > 1; in the d-th group of multiply-accumulate modules, the output terminal of the a-th input unit is electrically connected to the first multiplication input terminal of the (a+1)-th multiplication unit of each multiply-accumulate module, and the input terminal of the first input unit is electrically connected to the first multiplication input terminal of the first multiplication unit of each multiply-accumulate module, where d takes the value 1, 2, ..., m.

[0007] In one possible implementation, the weight value corresponding to the accumulation input terminal electrically connected to the output terminal of the f-th multiply-accumulate module in the e-th multiply-accumulate module group is 2. (m-e+p-f) The values ​​of e are 1, 2, ..., m, and the values ​​of f are 1, 2, ..., p.

[0008] In one possible implementation, the in-memory computing device is a finite-unit impulse response filter.

[0009] In one possible implementation, the multiplication circuit is an AND gate multiplication circuit.

[0010] In one possible implementation, the multiplication circuit is a NAND gate multiplication circuit; the adder is an inverted adder.

[0011] In one possible implementation, the shift accumulator is also used to perform two's complement calculation on the result of the shift accumulation calculation.

[0012] In one possible implementation, the multiplication circuit includes: a first transistor, the first terminal of which is electrically connected to the multiplication output terminal and the control terminal of which is electrically connected to the first multiplication input terminal; a second transistor, the first terminal of which is electrically connected to the second terminal of the first transistor, the second terminal of which is electrically connected to the low-level output terminal and the control terminal of which is electrically connected to the second multiplication input terminal; the first transistor and the second transistor are n-type transistors.

[0013] In a second aspect, an electronic device is provided, including the aforementioned in-memory computing device.

[0014] The in-memory computing device and electronic device of the parallel vector multiply-accumulator in this application embodiment realize the multiplication calculation of one bit through the cooperation of the memory and multiplication circuit in the multiplication unit. The adder obtains the output from different multiplication units, performs addition calculation and uses it as the output of the multiply-accumulator module. The shift accumulator obtains the output of multiple multiply-accumulator modules and performs shift accumulation calculation based on the corresponding weight values. The multiplication of two binary numbers by multiple multiplication units is completed in parallel. All multiplications can be completed in 1 clock cycle and shift accumulation can be completed in 2 clock cycles. That is, the calculation speed is improved by parallelism. Attached Figure Description

[0015] Figure 1 This is a structural block diagram of an in-memory computing device for a parallel vector multiplier-accumulator according to an embodiment of this application;

[0016] Figure 2 This is a block diagram of the in-memory computing device for another parallel vector multiplier-accumulator in this application embodiment;

[0017] Figure 3 This is a structural block diagram of a multiplication unit in an embodiment of this application;

[0018] Figure 4 This is a structural block diagram showing the relationship between an adder and other modules in an embodiment of this application;

[0019] Figure 5 This is a simplified calculation diagram of an FIR filter;

[0020] Figure 6 This is a schematic diagram of the structure of a multiply-accumulate module group in an embodiment of this application;

[0021] Figure 7 This is a block diagram of the in-memory computing device for another parallel vector multiplier-accumulator in this application embodiment;

[0022] Figure 8 for Figure 7 A schematic diagram of the structure of the second multiply-accumulate module group;

[0023] Figure 9 for Figure 7 A structural diagram of the 14th multiply-accumulate module group;

[0024] Figure 10 This is a simplified schematic diagram of the algorithm matrix corresponding to a parallel vector multiplier-accumulator in an embodiment of this application. Detailed Implementation

[0025] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.

[0026] This application provides an in-memory computation device for a parallel vector multiply-adder, comprising: L multiply-adder modules 1, each multiply-adder module 1 including q multiplication units 11 and an adder 12, where q > 1 and L > 1; as shown Figure 2 and Figure 3 As shown, the multiplication unit 11 includes a memory 111 and a multiplication circuit 112. The multiplication circuit 112 includes a first multiplication input terminal MIN1 and a second multiplication input terminal MIN2. The second multiplication input terminal MIN2 is electrically connected to the output terminal of the memory 111. The multiplication circuit 112 is used to perform multiplication calculations on the values ​​of the first multiplication input terminal MIN1 and the second multiplication input terminal MIN2 and outputs the result through the output terminal of the multiplication unit 11. The multiplication circuit 112 can perform single-bit multiplication calculations, specifically it can be an AND gate or a NAND gate. The detailed structure and principle of the multiplication circuit 112 will be introduced later. The memory 111 can be, for example, a read-only memory (ROM) or a static random-access memory (SRAM). Since memory 111 is SRAM, the multiplication circuit 112 can be implemented not only through AND gates or NAND gates, but also by utilizing the structural characteristics of SRAM itself. The multiplication unit 11 multiplies two binary numbers bit by bit and then outputs the result to adder 12. Adder 12 includes q addition inputs, with the a-th addition input electrically connected to the output of the a-th multiplication unit. The value of a is 1, 2, ..., q. The output of each adder 12 is the output of the corresponding multiply-accumulate module 1. Shift accumulator 2 includes L accumulation inputs, with the b-th accumulation input electrically connected to the output of the b-th multiply-accumulate module 1. The value of b is 1, 2, ..., L. Each accumulation input has a corresponding weight value. Shift accumulator 2 is used to perform shift and accumulation calculations on the values ​​of the L accumulation inputs based on the weight value corresponding to each accumulation input.

[0027] Specifically, for the same multiply-add module 1, the first multiplication unit 11 is used to perform multiplication on X0 and W0 and output the calculation result Out0 to the first addition input terminal A0 of the adder 12; the second multiplication unit 11 is used to perform multiplication on X1 and W1 and output the calculation result Out1 to the second addition input terminal A1 of the adder 12; and so on, the qth multiplication unit 11 is used to perform multiplication on X1 and W1. q-1 and W q-1 Perform multiplication and output the result. q-1 The output is sent to the qth addition input A of adder 12. q-1The output of the first multiply-accumulate module 1 outputs the multiply-accumulate result S0 to the first accumulation input of the shift accumulator 2; the output of the second multiply-accumulate module 1 outputs the multiply-accumulate result S1 to the second accumulation input of the shift accumulator 2; and so on, with the output of the Lth multiply-accumulate module 1 outputting the multiply-accumulate result SL-1 to the Lth accumulation input of the shift accumulator 2. The shift accumulator 2 performs shift and accumulation calculations on the values ​​of the L accumulation inputs based on the weight value corresponding to each accumulation input. The weight value can correspond to the number of bits in the binary number; for example, the weight value of the least significant bit is 2. 0 The weight of the second lowest position is 2. 1 And so on. Based on the number of bits corresponding to the output value of the multiply-accumulate module 1, the weight value of the accumulation input terminal corresponding to the output terminal of the multiply-accumulate module 1 can be determined. Therefore, the weight value corresponding to each accumulation input terminal can be preset.

[0028] The in-memory computing device of the parallel vector multiply-accumulator in this embodiment achieves a one-bit multiplication calculation through the cooperation of the memory and multiplication circuit in the multiplication unit. The adder obtains the outputs from different multiplication units, performs addition calculations, and uses them as the outputs of the multiply-accumulator module. The shift accumulator obtains the outputs of multiple multiply-accumulator modules and performs shift accumulation calculations based on the corresponding weight values. The multiplication of two binary numbers by multiple multiplication units is completed in parallel. All multiplications can be completed in 1 clock cycle, and shift accumulation can be completed in 2 clock cycles. That is, the calculation speed is improved by parallelism.

[0029] In one possible implementation, such as Figure 2 As shown, the multiplication circuit 112 is a NAND gate multiplication circuit. Since the output of the multiplication circuit 112 implemented by the NAND gate is inverted, an inverting circuit is needed in subsequent circuits to restore it. For example, the adder 12 is an inverting adder.

[0030] In other possible implementations, the multiplication circuit 112 can be an AND gate multiplication circuit.

[0031] In one possible implementation, the shift accumulator 2 is also used to perform binary two's complement calculation on the result of the shift accumulation calculation to achieve signed bit calculation.

[0032] In some embodiments, such as Figure 2As shown, each multiplication unit 11 includes a memory 111 and a corresponding multiplication circuit 112. The memory 111 can be a register. The input terminal D of the register is electrically connected to the external input coefficient W signal line to realize the writing of coefficient W. The clock signal terminal clk of the register is electrically connected to the clock signal line clk. The output terminal Q of the register is electrically connected to the second multiplication input terminal of the corresponding multiplication circuit 112. The first multiplication input terminal of the multiplication circuit 112 is electrically connected to the signal line of the external input signal X. The output terminal of the multiplication circuit 112 is electrically connected to one addition input terminal of the corresponding adder 12. The output of the adder 12 is a multi-bit binary number. Figure 2 In the example, multiplication circuit 112 is a NAND gate.

[0033] In some embodiments, adder 12 is a digital adder.

[0034] In some embodiments, such as Figure 4 As shown, adder 12 includes an analog adder circuit and an analog-to-digital converter (ADC). The analog adder circuit includes q capacitors C, with the first terminal of the a-th capacitor C serving as the a-th first adder input, and the second terminals of the n capacitors C connected to the input of the ADC. The output of the ADC serves as the output of adder 12. The analog adder circuit can perform single-bit addition calculations using electrical charges. This calculation method utilizes capacitors, which saves more space compared to digital adders. However, an ADC is needed to perform analog-to-digital conversion on the addition result so that subsequent digital addition results can be shifted and accumulated.

[0035] In one possible implementation, such as Figure 3 As shown, the multiplication circuit 112 includes: a first transistor m1, whose first terminal is electrically connected to the multiplication output terminal MOUT, and whose control terminal is electrically connected to the first multiplication input terminal MIN1; a second transistor m2, whose first terminal is electrically connected to the second terminal of the first transistor m1, whose second terminal is electrically connected to the low-level output terminal V1, and whose control terminal is electrically connected to the second multiplication input terminal MIN2; the first transistor m1 and the second transistor m2 are n-type transistors.

[0036] Specifically, the multiplication circuit 112 composed of the first transistor m1 and the second transistor m2 is actually a NAND gate. When either the first transistor m1 or the second transistor m2 is turned off, the multiplication output terminal MOUT remains at a high level, i.e., outputting 1. In this embodiment, a high level represents 1, and a low level represents 0. The low-level output terminal V1 is used to output a low level representing 0. Only when both the first transistor m1 and the second transistor m2 are turned on will the multiplication output terminal MOUT be pulled low by the low-level output terminal V1, thus becoming a low level, i.e., outputting 0. The first transistor m1 and the second transistor m2 are both n-type transistors, meaning they will conduct under the control of a high level and be turned off under the control of a low level, as shown in Table 1.

[0037] Table 1

[0038] MIN1 MIN2 MOUT 1 1 0 1 0 1 0 1 1 0 0 1

[0039] Table 1 illustrates... Figure 3 The values ​​corresponding to each terminal of the multiplication circuit 112 under different states show that the value output by the multiplication output terminal MOUT is actually the inverted value of the multiplication result of the first multiplication input terminal MIN1 and the second multiplication input terminal MIN2. This inverted value can be recovered in subsequent circuits, for example, by inverting it at the adder. Therefore, the multiplication function can be implemented using the multiplication circuit 112 composed of the first transistor m1 and the second transistor m2. It should be noted that... Figure 3 The structure of the multiplication circuit 112 in the example is only for illustration. The specific structure of the multiplication circuit in this application is not limited, as long as it can realize the multiplication calculation of a single bit binary value.

[0040] In one possible implementation, such as Figure 3As shown, the memory 111 includes: a third transistor m3, whose first terminal is electrically connected to a high-level output terminal V2, which is used to output a high level representing 1; a fourth transistor m4, whose first terminal is electrically connected to the second terminal of the third transistor m3, whose second terminal is electrically connected to a low-level output terminal V1, and whose control terminal is electrically connected to the control terminal of the third transistor m3; a fifth transistor m5, whose first terminal is electrically connected to the high-level output terminal V2, whose second terminal is the output terminal of the memory 20, and whose control terminal is electrically connected to the second terminal of the third transistor m3, i.e., the second terminal of the fifth transistor m5 is electrically connected to the second multiplication input terminal MIN2 of the multiplication circuit 30; a sixth transistor m6, whose first terminal is electrically connected to the second terminal of the fifth transistor m5, whose second terminal is electrically connected to the low-level output terminal V1, and whose control terminal is electrically connected to the control terminal of the fifth transistor m5, and whose control terminal is electrically connected to node Q; and a seventh transistor m7, whose first terminal is electrically connected to the write bit line. The first transistor m8 has its first terminal connected to the reverse write bit line WBLB, its second terminal connected to the second terminal of the third transistor m3, and its control terminal connected to the write word line (WWL). The reverse write bit line WBLB has the opposite signal to the write bit line WBL. The third transistor m3 and the fifth transistor m5 are p-type transistors, while the fourth transistor m4, the sixth transistor m6, the seventh transistor m7, and the eighth transistor m8 are n-type transistors.

[0041] Specifically, Figure 3 The memory 111 shown is a Static Random Access Memory (SRAM). However, when input data is written to memory 111, the write word line WWL is high, controlling the seventh transistor m7 and the eighth transistor m8 to conduct. The data on the write bit line WBL is then transferred to node Q through the seventh transistor m7, thus realizing data writing. Additionally, the first multiplication input terminal MIN1 can also be called the read word line (RWL), and the multiplication output terminal MOUT can also be called the read bit line (RBL). It should be noted that... Figure 3 The circuit structure of memory 111 shown is only an example. The specific structure of memory 111 is not limited in this application embodiment, as long as it can realize the storage function.

[0042] In one possible implementation, such as Figure 3As shown, the in-memory computing device further includes q pre-charge transistors m0 corresponding to adder 12. The a-th addition input terminal Aa of adder 12 is electrically connected to the first terminal of the a-th pre-charge transistor m0, and the second terminal of pre-charge transistor m0 is electrically connected to the high-level output terminal V2. Before each multiplication calculation, the pre-charge transistor m0 is turned on to charge the multiplication output terminal MOUT with a high level. Then, the pre-charge transistor m0 is turned off, and the multiplication circuit 112 can perform multiplication calculation. If at least one of the first transistor m1 and the second transistor m2 is turned off, the multiplication output terminal MOUT outputs the previously pre-charged high level, i.e., outputs 1; if both the first transistor m1 and the second transistor m2 are turned on, the multiplication output terminal MOUT is pulled low by the low-level output terminal V1, becoming a low level, i.e., outputs 0.

[0043] In one possible implementation, the in-memory computing device is a finite unit impulse response (FIR) filter. For example... Figure 5 As shown, W0 to W14 are the 15 tap coefficients of the filter, each a 14-bit binary number. X0 is the input signal, which is also a 14-bit binary number. X*W is actually a bit multiplication of two 14-bit binary numbers, with a total of 15 such multiplications. The results of the multiplications are then summed to obtain the result y. This embodiment of the application can implement the calculation of the FIR filter in a fully parallel manner.

[0044] In one possible implementation, such as Figure 6 As shown, the in-memory computing device further includes: an input module 3 corresponding to at least one multiply-accumulate module 1. The input module 3 includes q-1 input units 30 cascaded in sequence. The input units 30 are used to output the value input in the previous cycle in the current cycle. The output terminal of the a-th input unit 30 is electrically connected to the first multiplication input terminal of the (a+1)-th multiplication unit of the corresponding multiply-accumulate module 1. The input terminal of the first input unit 30 is electrically connected to the first multiplication input terminal of the first multiplication unit of the corresponding multiply-accumulate module 1. The input terminal of the c-th input unit 30 is electrically connected to the output terminal of the (c-1)-th input unit 30, where c takes the value 2, 3, ..., q. In this structure, the input signal X corresponding to the same multiply-accumulate module 1 can be converted based on the input module 3.

[0045] For example, input module 3 includes 14 input units 30 cascaded in sequence, and multiply-add module 1 includes 15 multiplication units and 15 corresponding addition input terminals A0 to A1. 14The output terminal of the first input unit 30 is electrically connected to the first multiplication input terminal of the second multiplication unit, the output terminal of the second input unit 30 is electrically connected to the first multiplication input terminal of the third multiplication unit, and so on, with the output terminal of the fourteenth input unit 30 being electrically connected to the first multiplication input terminal of the fifteenth multiplication unit. The first multiplication input terminal of the first multiplication unit is electrically connected to the input terminal of the first input unit 30.

[0046] In one possible implementation, such as Figures 6 to 9 As shown, the in-memory computing device includes: m multiply-accumulate module groups 10, each multiply-accumulate module group 10 including p multiply-accumulate modules 1 and one input module 3, where p > 1; in the d-th multiply-accumulate module group 10, the output terminal of the a-th input unit 30 is electrically connected to the first multiplication input terminal of the (a+1)-th multiplication unit of each multiply-accumulate module 1 in the d-th multiply-accumulate module group 10, and the input terminal of the first input unit 30 is electrically connected to the first multiplication input terminal of the first multiplication unit of each multiply-accumulate module 1 in the d-th multiply-accumulate module group 10, where d takes the values ​​1, 2, ..., m. Figure 6 for Figure 7 A schematic diagram of the structure of the first multiply-accumulate module group 101 of the in-memory computing device. Figure 8 for Figure 7 The structural diagram of the second multiply-accumulate module group 102 in the middle. Figure 9 for Figure 7 A schematic diagram of the structure of the 14th multiply-accumulate module group 1014.

[0047] In one possible implementation, such as Figures 6 to 9 As shown, the weight value corresponding to the accumulation input terminal electrically connected to the output terminal of the f-th multiply-accumulate module in the e-th multiply-accumulate module group is 2. (m-e+p-f) The values ​​of e are 1, 2, ..., m, and the values ​​of f are 1, 2, ..., p.

[0048] Specifically, the following describes the working process and principle of the in-memory computing device in the embodiments of this application based on a specific algorithm. For example, the formula to be calculated is:

[0049] Among them, c j and x n-j Both are 14 bits.

[0050] c j =W j,13 W j,12 W j,11 W j,10 W j,9 W j,8 W j,7 W j,6 W j,5 W j,4 Wj,3 W j,2 W j,1 W j,0 In this context, each W represents a binary number. j,0 The least significant bit, or the first bit, W j,13 It is the highest bit, or the 14th bit, i.e., c. j This represents a 14-bit binary number. The calculation process for this binary number can be represented as:

[0051] c j =2 13 W j,13 +2 12 W j,12 +…+2 1 W j,1 +2 0 W j,0 Each binary number W needs to be multiplied by a corresponding weight to determine the number of bits, with the first bit W... j,0 The corresponding weight is 2 0 The second W j,1 The corresponding weight is 2 1 And so on, the fourteenth W j,13 Corresponding weight bit 2 13 .

[0052] x n-j =X n-j,13 X n-j,12 X n-j,11 X n-j,10 X n-j,9 X n-j,8 X n-j,7 X n-j,6 X n-j,5 X n-j,4 X n-j,3 X n-j,2 X n-j,1 X n-j,0 In this case, each X represents a binary number, X n-j,0 The least significant bit, or the first bit, X n-j,13 The highest bit, or the 14th bit, is x. n-j This represents a 14-bit binary number. The calculation process for this binary number can be represented as:

[0053] x n-j =2 13 X n-j,13 +2 12 X n-j,12 +…+2 1 X n-j,1 +2 0 X n-j,0Each binary number X needs to be multiplied by a corresponding weight to determine the number of bits, with the first bit X being... n-j,0 The corresponding weight is 2 0 The second X n-j,1 The corresponding weight is 2 1 And so on, the fourteenth X n-j,13 The corresponding weight is 2 13 .

[0054] c j x n-j The final result is the sum of 14*14, or 196 multiplications, c. j x n-j The calculation process is shown below:

[0055] c j x n-j =2 13 X n-j,13 (2 13 W j,13 +…+20W j,0 )+2 12 X n-j,12 (2 13 W j,13 +…+2 0 W j,0 )+…+2 0 X n-j,0 (2 13 W j,13 +…+2 0 W j,0 ),

[0056] c j x n-j =(2 26 X n-j,13 W j,13 +…+2 13 X n-j,13 w j,0 )+(2 25 X n-j,12 W j,13 +…+2 12 X n-j,12 W j,0 )+…+(2 13 X n-j,0 w j,13 +…+2 0 X n-j,0 w j,0 ).

[0057] y n The calculation process is shown below:

[0058]

[0059] In this embodiment of the application, q = 15, L = 196, m = 14, and p = 14 are set. Memory ( Figures 6 to 8 (Not shown in the diagram) is used to store W, and the second multiplication input of the first multiply-accumulate module 1 in each multiply-accumulate module group 10 is input to c. j The first W in j,0 For the same multiply-accumulate module 1, the 15 second multiplication input terminals input W respectively correspond to the values ​​of j being 0, 1, 2, ..., 14, i.e., j = a - 1; the input terminal of the first input unit 30 of the input module 3 in the first multiply-accumulate module group 101 inputs x n-j The 14th X in n-j,13 The first input unit 30 of the input module 3 in the second multiply-accumulate module group 102 inputs x. n-j The 13th X in n-j,12 Similarly, in the 14th multiply-accumulate module group 1014, the first input unit 30 of input module 3 inputs x. n-j The first X in n-j,0 In each input module 3, X is sequentially input through cascaded input units 30. n Convert to X n-1 X n-2 ... X n-14 And output them respectively to the 2nd to 15th first multiplication input terminals of each multiply-accumulate module 1 in the same multiply-accumulate module group 10. That is, when j is greater than or equal to 1, X n-j It is obtained through the conversion of input unit 30, so the external input interface can only be X. n The embodiments in this application do not limit X. n The number of [items] can be determined as needed. Additionally, besides inputting X via module 3 as mentioned above... n Transform to obtain X n-j In addition to this method, in other possible implementations, each X can also be set n-j All of these are obtained through external input.

[0060] Combination Figures 6 to 10 The output of each multiplication unit corresponds to Figure 10 The product of an X and a W is given, and the output of each multiply-accumulate module 1 corresponds to... Figure 10 The result of multiplying and adding a column of data is output as a 4-bit output. The last 196 4-bit outputs are sent to shift accumulator 2, which finally outputs a 32-bit result.

[0061] Among them, X n-j <13:0> and W j<13:0> The product is multiplied bit by bit, requiring 196 multiplications. Each multiplication result has a different weight, which is implemented using shift accumulator 2. There are 15 such multiplications. Multiplications with the same weight are directly summed before being input into shift accumulator 2. All these multiplications and additions are processed in parallel, requiring only one clock cycle to complete. In addition, the shift accumulator requires at least two clock cycles to complete the accumulation.

[0062] The weights in shift accumulator 2 can be predetermined according to the formula above. For example, the value obtained by the accumulator input terminal electrically connected to the output terminal of the first multiply-accumulate module 1 in the first multiply-accumulate module group 101 is S0, and the multiply-accumulate result corresponding to S0 is... Therefore, its corresponding weight can be determined to be 2. 26 =2 (14-1+14-1) The value obtained by connecting the accumulation input terminal of the second multiply-accumulate module 1 in the first multiply-accumulate module group 101 to the first multiply-accumulate module group 101 is S1, and the multiply-accumulate result corresponding to S1 is... Therefore, its corresponding weight can be determined to be 2. 25 =2 (14-1+14-2) Similarly, the value obtained by the accumulation input terminal of the first multiply-accumulate module 1 in the second multiply-accumulate module group 102 is S14, and the multiply-accumulate result corresponding to S14 is... Therefore, its corresponding weight can be determined to be 2. 25 =2 (14-2+14-1) The value obtained by connecting the accumulation input terminal of the second multiply-accumulate module 1 in the second multiply-accumulate module group 102 to the output terminal is S15, and the multiply-accumulate result corresponding to S15 is... Therefore, its corresponding weight can be determined to be 2. 24 =2 (14-2+14-2) Similarly, the weight value corresponding to the accumulation input terminal of the output terminal of the f-th multiply-accumulate module in the e-th multiply-accumulate module group is 2. (m-e+p-f) .

[0063] This application also provides an electronic device, including the in-memory computing device described in any of the above embodiments. This electronic device can be a mobile phone, tablet computer, personal computer (PC), personal digital assistant (PDA), smartwatch, netbook, wearable electronic device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle device, smart car, smart speaker, robot, smart glasses, smart TV, etc. The in-memory computing device can be a chip within the electronic device.

[0064] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0065] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An in-memory computing device for a parallel vector multiply-accumulator, characterized in that, include: There are L multiply-accumulate modules, each of which includes q multiplication units and an adder, where q > 1 and L > 1; The multiplication unit includes a memory and a multiplication circuit. The multiplication circuit includes a first multiplication input terminal and a second multiplication input terminal. The second multiplication input terminal is electrically connected to the output terminal of the memory. The multiplication circuit is used to perform multiplication calculations on the values ​​of the first multiplication input terminal and the second multiplication input terminal and output the result through the output terminal of the multiplication unit. The adder includes q addition input terminals, the a-th addition input terminal is electrically connected to the output terminal of the a-th multiplication unit, and the value of a is 1, 2, ..., q. The output terminal of each adder is the output terminal of the corresponding multiply-add module. A shift accumulator, comprising L accumulator inputs, wherein the b-th accumulator input is electrically connected to the output of the b-th multiply-accumulate module, and the value of b is 1, 2, ..., L; Each of the accumulator inputs has a corresponding weight value, and the shift accumulator is used to perform shift and accumulation calculations on the values ​​of the L accumulator inputs based on the weight value corresponding to each of the accumulator inputs. An input module corresponding to at least one of the multiply-accumulate modules, the input module comprising q-1 input units cascaded in sequence, the input units being used to output the value input in the previous cycle in the current cycle; The output terminal of the a-th input unit is electrically connected to the first multiplication input terminal of the (a+1)-th multiplication unit of the corresponding multiplication-accumulation module; The input terminal of the first input unit is electrically connected to the first multiplication input terminal of the first multiplication unit of the corresponding multiply-accumulate module; The input terminal of the c-th input unit is electrically connected to the output terminal of the (c-1)-th input unit, where the value of c is 2, 3, ..., q; There are m multiply-accumulate module groups, each multiply-accumulate module group including p multiply-accumulate modules and one input module, where p > 1; In the d-th multiply-accumulate module group, the output terminal of the a-th input unit is electrically connected to the first multiplication input terminal of the (a+1)-th multiplication unit of each multiply-accumulate module, and the input terminal of the first input unit is electrically connected to the first multiplication input terminal of the first multiplication unit of each multiply-accumulate module. The value of d is 1, 2, ..., m. The weight value corresponding to the accumulation input terminal electrically connected to the output terminal of the f-th multiply-accumulate module in the e-th multiply-accumulate module group is 2. （m-e+p-f） The values ​​of e are 1, 2, ..., m, and the values ​​of f are 1, 2, ..., p.

2. The apparatus according to claim 1, characterized in that, The in-memory computing device is a finite-unit impulse response filter.

3. The apparatus according to claim 1, characterized in that, The multiplication circuit is an AND gate multiplication circuit.

4. The apparatus according to claim 1, characterized in that, The multiplication circuit is a NAND gate multiplication circuit; The adder is an inverted adder.

5. The apparatus according to claim 1, characterized in that, The shift accumulator is also used to perform binary two's complement calculation on the result of the shift accumulation calculation.

6. The apparatus according to claim 1, characterized in that, The multiplication circuit includes: The first transistor has its first terminal electrically connected to the multiplication output terminal of the multiplication circuit, and its control terminal electrically connected to the first multiplication input terminal. The second transistor has its first terminal electrically connected to the second terminal of the first transistor, its second terminal electrically connected to the low-level output terminal, and its control terminal electrically connected to the second multiplication input terminal. The first transistor and the second transistor are n-type transistors.

7. An electronic device, characterized in that, Includes the in-memory computing device as described in any one of claims 1 to 6.

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