BIOS boot method, BMC, electronic device and mainboard thereof

Abstract

The embodiment of the application provides a BIOS starting method, a BMC, an electronic device and a mainboard thereof. In the embodiment of the application, a new type of device mainboard is provided, the device mainboard comprising a CPU and a BMC simultaneously, and the BMC is interconnected with a BIOS memory for storing a BIOS firmware program, the BIOS firmware program can be read from the BIOS memory in advance, the BIOS firmware program is preprocessed to obtain executable code instructions and the executable code instructions are written into the shared memory of the BMC; in addition, the CPU is interconnected with the BMC through a bridge chip, so that in the starting process, the CPU can directly read the executable code instructions from the shared memory of the BMC through the bridge chip and execute the executable code instructions, and the CPU no longer executes the preprocessing process of the BIOS firmware program in the starting process, so that the starting time can be saved and the starting speed can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, and particularly relates to a BIOS booting method, a BMC, an electronic device and a mainboard thereof. BACKGROUND

[0002] With the increasing powerful and complex functions of a server, a Basic Input Output System (BIOS) firmware program thereof is increasingly large, and the BIOS firmware program is usually stored in a flash memory (Flash). In a booting process of the server, a Central Processing Unit (CPU) reads the BIOS firmware program from the Flash storing the BIOS firmware program by accessing the Flash, and executes the BIOS firmware program to complete a booting operation.

[0003] At present, a booting time based on the BIOS is always a big pain point in the server field, and how to further optimize the booting process of the server and shorten the booting time is a problem that is increasingly concerned by cloud manufacturers and server hardware manufacturers, and is also a technical problem to be solved in the industry. SUMMARY

[0004] Aspects of the present application provide a BIOS booting method, a BMC, an electronic device and a mainboard thereof, to reduce BIOS execution time and improve the booting speed of the server.

[0005] The embodiment of the present application provides a device mainboard, which comprises a processor CPU, a bridge chip interconnected with the CPU through a first bus interface, a BIOS memory interconnected with the bridge chip through a second bus interface and used for storing a BIOS firmware program, a Baseboard Management Controller (BMC) interconnected with the BIOS memory through the second bus interface and interconnected with the bridge chip through a third bus interface and used for reading the BIOS firmware program from the BIOS memory, preprocessing the BIOS firmware program to obtain executable code instructions and writing the executable code instructions into a shared memory of the BMC, and the bridge chip used for reading the executable code instructions from the shared memory of the BMC through the third bus interface in a booting process and providing the executable code instructions to the CPU through the first bus interface, so that the CPU executes the executable code instructions to complete a booting operation.

[0006] The embodiment of the present application further provides a BIOS booting method, which is suitable for a device motherboard, the device motherboard comprising a processor CPU, a bridge chip, a BIOS memory and a baseboard management controller BMC, the bridge chip being interconnected with the CPU, the BMC and the BIOS memory through a first bus interface, a third bus interface and a second bus interface respectively, the method comprising the following steps: before booting, the BMC reads a BIOS firmware program from the BIOS memory, pre-processes the BIOS firmware program to obtain executable code instructions, and writes the executable code instructions into a shared memory of the BMC; during the booting process, the bridge chip reads the executable code instructions from the shared memory of the BMC through the third bus interface, and provides the first bus interface to the CPU, so that the CPU executes the executable code instructions to complete the booting operation.

[0007] The embodiment of the present application further provides a BIOS booting method, which is suitable for a baseboard management controller BMC, the BMC being interconnected with a bridge chip and a BIOS memory storing a BIOS firmware program through a third bus interface and a second bus interface respectively, the method comprising the following steps: before booting, the BIOS firmware program is read from the BIOS memory through the second bus interface, the BIOS firmware program is pre-processed to obtain executable code instructions, and the executable code instructions are written into a shared memory; during the booting process, the executable code instructions are read from the shared memory according to a read request of the bridge chip, and the executable code instructions are provided to a CPU through the third bus interface via the bridge chip, so that the CPU executes the executable code instructions to complete the booting operation.

[0008] The embodiment of the present application further provides a baseboard management controller BMC, which is interconnected with a bridge chip and a BIOS memory storing a BIOS firmware program through a third bus interface and a second bus interface respectively, the BMC comprising: a reading module, configured to read the BIOS firmware program from the BIOS memory through the second bus interface before booting;

[0009] a pre-processing module, configured to pre-process the BIOS firmware program to obtain executable code instructions, and write the executable code instructions into a shared memory; the reading module is further configured to read the executable code instructions from the shared memory according to a read request of the bridge chip during the booting process; and a sending module, configured to provide the executable code instructions to a CPU through the third bus interface via the bridge chip, so that the CPU executes the executable code instructions to complete the booting operation.

[0010] The embodiment of the present application further provides an electronic device comprising any device motherboard provided by the embodiment of the present application.

[0011] In the embodiment of the present application, a new device mainboard is provided, which comprises a CPU and a BMC, and the BMC is interconnected with a BIOS memory storing a BIOS firmware program, and the BIOS firmware program can be read from the BIOS memory in advance, and the BIOS firmware program is preprocessed to obtain executable code instructions and written into the shared memory of the BMC; in addition, the CPU is interconnected with the BMC through a bridge chip, so that during the booting process, the CPU can directly read the executable code instructions from the shared memory of the BMC through the bridge chip and execute, and the CPU no longer executes the preprocessing process of the BIOS firmware program during the booting process, so that the booting time can be saved and the booting speed can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application. In the drawings:

[0013] Figure 1a A structural schematic diagram of a device mainboard provided for the exemplary embodiment of the present application;

[0014] Figure 1b A process schematic diagram of BIOS loading in the time division phase when redirection is realized from the software level;

[0015] Figure 2 A schematic diagram of the internal structure of a flash memory provided for the embodiment of the present application;

[0016] Figure 3 A flowchart of a BIOS booting method provided for the exemplary embodiment of the present application;

[0017] Figure 4 A flowchart of another BIOS booting method provided for the exemplary embodiment of the present application;

[0018] Figure 5 A structural schematic diagram of a baseboard management controller (BMC) provided for the exemplary embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described below in connection with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0020] Currently, BIOS-based boot time has been a major pain point in the server industry. How to further optimize the server boot process and shorten boot time is an increasingly important issue for major cloud providers and server hardware manufacturers, and also a technical challenge that the industry needs to solve. To address this, this application provides a BIOS boot method, a BMC, an electronic device, and its motherboard. In this application, a novel device motherboard is provided, which includes both a CPU and a BMC. The BMC is interconnected with a BIOS memory storing the BIOS firmware program. It can pre-read the BIOS firmware program from the BIOS memory, pre-process the BIOS firmware program to obtain executable code instructions, and write them into its shared memory. Furthermore, the CPU is interconnected with the BMC through a bridge chip. Thus, during the boot process, the CPU can directly read and execute executable code instructions from the BMC's shared memory through the bridge chip. The CPU no longer needs to perform the BIOS firmware program pre-processing process during boot, saving boot time and improving boot speed.

[0021] Further optionally, in some embodiments, the transmission rate of the bus interface interconnecting the bridge chip with the BMC is higher than the transmission rate of the bus interface interconnecting the bridge chip with the BIOS memory. In this way, during the boot process, the bridge chip can read executable code instructions from the shared memory of the BMC and give them to the CPU for execution by means of the bus interface with a higher transmission rate. Compared with the reading method through the bus interface with a lower transmission rate, the time overhead of loading executable code instructions can be further reduced, and the boot speed can be further improved.

[0022] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0023] Figure 1a This is a schematic diagram of a device motherboard provided as an exemplary embodiment of this application. This device motherboard can be applied to any electronic device, such as, but not limited to, server devices, terminal devices, smart wearable devices, home appliances, and other electronic devices. The server device can be a conventional server, a cloud server, a server array, etc. Figure 1a As shown, the device motherboard 100 includes: a CPU 101, a bridge chip 102, a BIOS memory 103, and a Baseboard Management Controller (BMC) 104. It should be noted that the CPU 101 can be considered an in-band processor, and the BMC 104 can be considered an out-of-band processor. In this embodiment, the BMC 104 is used as an example of an out-of-band processor, but it is not limited thereto; various out-of-band processors are applicable to this embodiment.

[0024] In the embodiment, the implementation of the bridge chip 102 is not limited, for example, it can be implemented as a new PCH, i.e., a South Bridge, or as another chip with a bridge function. The bridge chip 102 is a bridge between the CPU 101, the BIOS memory 103, and the BMC 104, and is responsible for interconnecting the CPU 101, the BIOS memory 103, and the BMC 104. As shown in FIG. 1, the bridge chip 102 is interconnected with the CPU 101 through a first bus interface. In addition, the bridge chip 102 is interconnected with the BIOS memory 103 through a second bus interface, and is interconnected with the BMC 104 through a third bus interface, so as to achieve the interconnection of the CPU 101, the BIOS memory 103, and the BMC 104. In addition, the BMC 104 is interconnected with the BIOS memory 103 through the second bus interface. Figure 1a

[0025] In the embodiment, the BIOS memory 103 is used to store a BIOS firmware program, which can be any non-volatile memory, for example, a flash memory. The BIOS firmware program is a set of system programs fixed in the BIOS memory 103 on the device mainboard, which plays an indispensable role in the normal initialization, startup, and operating system boot of the electronic device to which the device mainboard belongs. The BIOS firmware program contains initialization programs that need to be run when the electronic device is powered on. The BIOS firmware program is the first software run by the CPU. The entire life cycle of the BIOS firmware program is from the power-on of the device to the running of the operating system.

[0026] In the embodiment, the BIOS firmware program contains code data, rather than executable code instructions. The code data is obtained by performing some operations on executable code instructions, including but not limited to compression operations, encryption, and digital signature data security operations. In the embodiment, the executable code instructions refer to code instructions that can be directly executed by the CPU in the boot process. In the conventional scheme, the CPU 101 on the device mainboard can gradually load the code data in the BIOS firmware program from the BIOS memory 103 through the bridge chip 102, pre-process the code data to obtain executable code instructions, and execute the executable code instructions to gradually complete the boot operation of the electronic device.

[0027] ​However, unlike the conventional solution, in the present embodiment, the bridge chip 102 can serve as a bridge between the CPU 101 and the BMC 104, and in cooperation with the BMC 104, the bridge chip 102 reads executable code instructions from the BMC 104 and provides them to the CPU 101 during the booting process, instead of reading code data from the BIOS memory 103 and providing them to the CPU 101 during the booting process as in the conventional solution, so that the CPU 101 no longer performs the pre-processing of code data during the booting process, saving code execution time and thus improving the booting speed. In the present embodiment, the pre-processing of code data is completed by the out-of-band processor, i.e., the BMC 104, in advance before the booting.

[0028] Specifically, the BMC 104 has its basic baseboard management functions, such as system health monitoring, secure remote reboot, secure power on, LAN alert, BIOS protection and selection, etc. In addition, in the present embodiment, the BMC 104 can read the BIOS firmware program from the BIOS memory 103, pre-process the BIOS firmware program to obtain executable code instructions, and write them into the shared memory of the BMC for use by the CPU during booting, through the second bus interface between the BMC 104 and the BIOS memory 103. In addition, the BMC 104 is also responsible for maintaining the synchronization of the BIOS firmware program in the BIOS memory 103 and the BIOS firmware program in the shared memory. Further optionally, the BMC 104 can read the BIOS firmware program from the BIOS memory 103 in an asynchronous manner.

[0029] In the present embodiment, the BMC 104 can migrate all or part of the code data in the BIOS firmware program from the BIOS memory 103 to the shared memory of the BMC, without limitation. Correspondingly, the BMC can pre-process all or part of the code data in the BIOS firmware program. It is worth noting that the BMC 104 pre-processes all the code data migrated from the BIOS memory 103 to obtain executable code instructions, so that the BMC 104 can replace the CPU to perform the pre-processing task, reducing the workload of the CPU during the booting process, so that the CPU can directly run the executable code instructions, accelerating the booting speed. Among them, according to different operating systems, the BIOS firmware program and the booting process based on the BIOS firmware program will include different stages. In an optional embodiment, taking the firmware booting process of the Unified Extensible Firmware Interface (UEFI) version as an example, as shown in FIG. 2, the firmware booting process includes the following stages: the pre-boot stage, the early boot stage, the late boot stage, and the post-boot stage. Figure 1bAs shown, the process sequentially includes: Security Validation (SEC) phase, Early Entity Initialization (PEI) phase, Driver Execution Environment (DXE), Boot Device Selection (BDS), Operating System Pre-Loading (TSL), Run Time (RT), and Disaster Recovery (AL). Further, as... Figure 1b As shown, the initial EFI initialization phase further includes, in sequence: CPU initialization, chip initialization, and motherboard initialization. Regarding... Figure 1b For detailed implementation of each stage shown, please refer to existing UEFI documentation, which will not be repeated here.

[0030] Based on the above, in practical applications, each stage of the boot process is associated with executable code instructions that implement its functional logic. Since each stage of the boot process performs different tasks, some stages require a large amount of executable code instructions. To conserve storage resources, these large executable code instructions are typically compressed before generating the BIOS firmware. Other stages require smaller executable code instructions, which do not require compression. Of course, depending on the storage capacity supported by the BIOS memory 103 and actual needs, it is possible to flexibly select which executable code instructions required for each boot stage need compression and which do not. In other words, all or part of the executable code instructions required for the boot process can be compressed. Furthermore, in practical applications, to improve data security, encryption and digital signatures can be performed on the uncompressed and / or compressed executable code instructions before generating the BIOS firmware. Finally, the code instructions, after undergoing data security and compression operations, are used to generate the BIOS firmware program, which is then stored in the BIOS memory 103. Furthermore, according to the various stages of the boot process, the BIOS firmware program can be divided into multiple code data segments, each containing executable code instructions responsible for completing a different boot stage. During storage, these multiple code data segments are stored in different memory locations within the BIOS memory 103.

[0031] See Figure 2 As an example, the code instructions in the SEC and PEI stages are stored directly in flash memory without compression but after data security operations. The code instructions in the DXE, BDS, TSL, RT, and AL stages can be compressed and stored in flash memory after data security operations. Figure 2The storage space of the flash memory is divided into a plurality of storage units, wherein the storage unit 5 is used to store code data of the BIOS firmware program, the storage unit 5 is further divided into an FV0 storage block and an FV1 storage block, code instructions of the SEC stage and the PEI stage are directly stored into the FV0 storage block as two pieces of code data after data security operation, and code instructions of the DXE stage, the BDS stage, the TSL stage, the RT stage and the AL stage are stored into the FV1 storage block as five pieces of code data after compression processing and data security operation.

[0032] In some optional embodiments, the BIOS memory 103 also maintains and manages a storage description file, which is used to describe layout information reflecting the layout of the internal storage units of the BIOS memory 103, describe the storage location of data in the BIOS memory 103 and data attribute information. When the data is code data, the data attribute information includes, but is not limited to, the stage name in the boot process to which the code data is associated, whether the code data is compressed, the code amount of the code data, and the like.

[0033] Based on the above, the code data can be understood as code instructions that need to be processed in some way, with respect to executable code instructions that can be directly executed by the CPU. For example, the code data refers to code instructions that have been subjected to data security operation but not compression, or code instructions that have been subjected to compression and data security operation, and the like. Accordingly, the BMC 104 pre-processes the BIOS firmware program before booting to obtain executable code instructions, and the pre-processing includes, but is not limited to, decompression and legality verification. The legality verification includes, but is not limited to, decryption and signature verification of the code data. Code data that passes the legality verification is relatively safe and reliable, and code data that fails the legality verification has a high risk of tampering.

[0034] In some embodiments, the BMC can identify code data that has not been compressed and code data that has been compressed from the storage description file of the BIOS memory before reading the BIOS firmware program, wherein the storage description file at least stores the storage location of the plurality of pieces of code data and attribute information of whether the code data has been compressed.

[0035] In some embodiments, the BIOS firmware program includes multi-segment code data, and the BMC pre-processes the BIOS firmware program, specifically for: performing legality verification on the code data that is not compressed in the multi-segment code data, performing legality verification and decompression on the code data that is compressed, to obtain executable code instructions. For example, the code data obtained by the BMC from the BIOS memory is obtained by sequentially compressing, encrypting, and digitally signing the code instructions, and the BMC needs to perform reverse operations, that is, perform legality verification operations such as decryption and signature verification on the code data, and then decompress the code data to obtain executable code instructions. For another example, the code data obtained by the BMC from the BIOS memory is obtained by sequentially encrypting and digitally signing the code instructions, and the BMC needs to perform reverse operations, that is, perform legality verification operations such as decryption and signature verification on the code data, and then decompress the code data to obtain executable code instructions.

[0036] In actual application, the BMC 104 can read the multi-segment code data from the BIOS memory 103 at one time and pre-process each segment of code data, or can read the multi-segment code data from the BIOS memory 103 in batches and pre-process each segment of code data, and no limitation is made in this regard.

[0037] In this embodiment, on the basis that the BMC 104 can pre-read the BIOS firmware program from the BIOS memory 103, pre-process the BIOS firmware program to obtain executable code instructions, and write the executable code instructions into the shared memory of the BMC, the bridge chip 102 can read the executable code instructions from the shared memory of the BMC through the third bus interface, and provide the executable code instructions to the CPU through the first bus interface, so that the CPU executes the executable code instructions to complete the boot operation. In the boot process, the CPU no longer performs the pre-processing process of the BIOS firmware program, which can save boot time and improve boot speed.

[0038] In the embodiments of the present application, the bridge chip 102 can be improved, and the bridge chip 102 is added with a redirection function, so that the bridge chip 102 can, in the boot process, before reading the executable code instructions from the shared memory of the BMC through the third bus interface, redirect the reading interface for reading the BIOS firmware program from the second bus interface to the third bus interface, and then after redirecting the reading interface for reading the BIOS firmware program to the third bus interface, read the executable code instructions from the shared memory of the BMC through the third bus interface, and provide the executable code instructions to the CPU through the first bus interface, so that the CPU executes the executable code instructions to complete the boot operation.

[0039] In the embodiments of the present application, the redirection function of the bridge chip 102 can be implemented from the software level or from the hardware level. The following will be introduced and explained respectively.

[0040] In the embodiment of implementing the redirection function from the software level, the address space of the third bus interface needs to be initialized as the storage space in the shared memory of the BMC 104. Based on this, the bridge chip 102 implements the redirection function in the following manner: in the case that the address space of the third bus interface is initialized as the storage space in the shared memory of the BMC 104, the address information of the next executable code instruction in the BIOS firmware program provided by the CPU 101 is mapped into the address space of the third bus interface, so as to achieve the purpose of redirecting the reading interface of the BIOS firmware program from the second bus interface to the third bus interface.

[0041] It should be noted that in the embodiment of implementing the redirection function from the software level, before the reading interface for reading the BIOS firmware program is redirected to the third bus interface, the bridge chip 102 needs to read the code data in the BIOS firmware program from the BIOS memory 103 through the second bus interface and provide the code data to the CPU 101 for execution through the first bus interface. For the CPU 101, after entering the execution logic of the BIOS firmware program, in the process of executing the current code instruction, the bridge chip 102 will be requested to read the next executable code instruction according to the execution logic set in the BIOS firmware program. For the CPU 101, it will not consider whether the executable code instruction currently executed by it is read from the BIOS memory 103 through the second bus interface or from the shared memory of the BMC 104 through the third bus interface. In the process of executing the current executable code instruction, if the code logic is set to need the next executable code instruction, the CPU 101 will provide the address information of the next executable code instruction to the bridge chip 102, so that the bridge chip 102 reads the next executable code instruction according to the address information of the next executable code instruction.

[0042] If the bridge chip 102 obtains the address information of the next executable code instruction in the BIOS firmware program provided by the CPU 101 before the redirection of the reading interface for reading the BIOS firmware program to the third bus interface, the bridge chip 102 reads the code data corresponding to the next executable code instruction from the BIOS memory 103 through the second bus interface according to the address information of the next executable code instruction provided by the CPU 101, and provides the code data to the CPU 101 through the first bus interface for execution. If the bridge chip 102 obtains the address information of the next executable code instruction in the BIOS firmware program provided by the CPU 101 after the redirection of the reading interface for reading the BIOS firmware program to the third bus interface, the bridge chip 102 reads the next executable code instruction from the shared memory of the BMC 104 through the third bus interface according to the address information of the next executable code instruction provided by the CPU 101, and provides the next executable code instruction to the CPU 101 through the first bus interface for execution.

[0043] In one embodiment, after the redirection of the reading interface for reading the BIOS firmware program to the third bus interface, the bridge chip 102 reads the next executable code instruction from the shared memory of the BMC 104 through the third bus interface according to the address information of the next executable code instruction provided by the CPU 101. The bridge chip 102 receives the address information of the next executable code instruction in the BIOS firmware program provided by the CPU 101 during the execution of the current executable code instruction. The bridge chip 102 sends a reading request to the BMC 104 according to the address information of the next executable code instruction provided by the CPU 101, so that the BMC 104 reads the next executable code instruction in the BIOS firmware program from its shared memory. The bridge chip 102 receives the next executable code instruction read by the BMC 104. The BMC also receives the reading request sent by the bridge chip 102 through the third bus interface, reads the next executable code instruction required by the CPU 101 from its shared memory according to the reading request, and returns the next executable code instruction to the bridge chip 102 through the third bus interface. After receiving the next executable code instruction returned by the BMC 104, the bridge chip 102 provides the next executable code instruction to the CPU 101 through the first bus interface for execution.

[0044] Further, the detailed implementation process of sending the read request to the BMC 104 according to the address information of the next executable code instruction provided by the CPU 101 includes: the bridge chip 102 parses the address information of the next executable code instruction provided by the CPU 101, and maps the address information of the next executable code instruction into the address space of the third bus interface according to its memory mapping logic; and then generates a read request according to the mapped address information in the address space of the third bus interface, and sends the read request to the BMC 104, so that the BMC 104 can read the next executable code instruction from its shared memory according to the address information in the read request. Since the address space of the third bus interface points to the storage space in the shared memory of the BMC 104, the address information mapped in the address space of the third bus interface points to a specific storage location in the shared memory of the BMC 104, and in this embodiment, it specifically points to the storage location storing the next executable code instruction in the shared memory.

[0045] In the above embodiment, before the redirection of the reading interface to the third bus interface, the address space of the third bus interface needs to be initialized to point to the storage space in the shared memory of the BMC 104. In this embodiment, the code instructions responsible for the chip initialization in the BIOS firmware program are executed by the CPU 101 to initialize the address space of the third bus interface from the software level and make it point to the storage space in the shared memory of the BMC 104. Specifically, the bridge chip 102 is further configured to: before the redirection of the reading interface to the third bus interface, read the code data responsible for the chip initialization from the BIOS memory through the second bus interface according to the address information of the next executable code instruction in the BIOS firmware program provided by the CPU, and provide the code data to the CPU through the first bus interface; and the CPU is configured to pre-process the code data responsible for the chip initialization to obtain executable code instructions responsible for the chip initialization and execute the executable code instructions responsible for the chip initialization to initialize the address space of the third bus interface to point to the storage space in the shared memory of the BMC. For the CPU 101, the execution of the executable code instructions responsible for the chip initialization can complete the initialization operation of each chip, at least including the initialization of the address space of the third bus interface on the bridge chip 102 to point to the storage space in the shared memory of the BMC 104. After the initialization of the address space of the third bus interface to point to the storage space in the shared memory of the BMC 104, the bridge chip 102 can map the address information of the next executable code instruction in the BIOS firmware program provided by the CPU 101 to the address space of the third bus interface to achieve the purpose of the redirection of the reading interface of the BIOS firmware program from the second bus interface to the third bus interface, and thus the executable code instructions in the BIOS firmware program can be read from the shared memory of the BMC 104 through the third bus interface.

[0046] Further, in the embodiment of implementing the redirection function from the software level, during the power-on process, the CPU 101 provides a first entry address of the BIOS program code after power-on, which points to the address space of the second bus interface by default, and the address space of the second bus interface points to the storage space in the BIOS memory 103 by default. In this way, in the initial stage of the power-on, the bridge chip 102 receives the first entry address of the BIOS program code provided by the CPU 101 after power-on; according to the first entry address, the first code data in the BIOS firmware program is read from the BIOS memory 103 through the second bus interface and provided to the CPU 101 through the first bus interface, and the CPU 101 pre-processes the first code data to obtain the first executable code instruction and executes the first executable code instruction to enter the execution logic of the BIOS firmware program. During the execution of the BIOS firmware program, the CPU 101 continuously provides the address information of the next executable code instruction to the bridge chip 102; before the read interface for reading the BIOS firmware program is redirected to the third bus interface, the bridge chip 102 reads the code data corresponding to the next executable code instruction from the BIOS memory 103 through the second bus interface according to the address information of the next executable code instruction provided by the CPU 101, and provides the code data to the CPU 101 through the first bus interface for execution; after the read interface for reading the BIOS firmware program is redirected to the third bus interface, the bridge chip 102 reads the next executable code instruction from the shared memory of the BMC 104 through the third bus interface according to the address information of the next executable code instruction provided by the CPU 101, and provides the code data to the CPU 101 through the first bus interface for execution. For the detailed implementation process, please refer to the foregoing embodiment, which will not be described here.

[0047] In an optional embodiment, in the stage before and after the chip initialization, the bridge chip 102 can read the code data in the BIOS firmware program from the BIOS memory 103 through the second bus interface; after the chip initialization is completed, the bridge chip 102 can be redirected to the third bus interface, so that in the stage after the chip initialization, the bridge chip 102 reads the executable code instruction in the BIOS firmware program from the shared memory in the BMC 104 through the third bus interface. However, it should be noted that in the embodiment shown in the figure, the chip initialization is taken as the dividing point, but it is not limited thereto, for example, any stage after the chip initialization can also be taken as the dividing point, and in the stage after the dividing point, the bridge chip 102 reads the executable code instruction in the BIOS firmware program from the shared memory in the BMC 104 through the third bus interface. Figure 1b In an optional embodiment, in the stage before and after the chip initialization, the bridge chip 102 can read the code data in the BIOS firmware program from the BIOS memory 103 through the second bus interface; after the chip initialization is completed, the bridge chip 102 can be redirected to the third bus interface, so that in the stage after the chip initialization, the bridge chip 102 reads the executable code instruction in the BIOS firmware program from the shared memory in the BMC 104 through the third bus interface. However, it should be noted that in the embodiment shown in the figure, the chip initialization is taken as the dividing point, but it is not limited thereto, for example, any stage after the chip initialization can also be taken as the dividing point, and in the stage after the dividing point, the bridge chip 102 reads the executable code instruction in the BIOS firmware program from the shared memory in the BMC 104 through the third bus interface.

[0048] It should be noted that in the above process, if the CPU 101 receives the code data provided by the bridge chip 102, the code data is preprocessed to obtain executable code instructions, and then the executable code instructions are executed; if the CPU 101 receives the executable code instructions provided by the bridge chip 102, the executable code instructions are directly executed. The way of preprocessing the code data includes but is not limited to: validity check, decompression. Further, taking the boot process shown in FIG. 8 as an example, since it is the boot process before the chip initialization, the bridge chip 102 needs to read the code data from the BIOS memory 103 and provide it to the CPU 101, so the preprocessing of the code data by the CPU 101 mainly refers to the validity check. Figure 1b

[0049] In the embodiment of realizing the redirection function from the hardware level, the CPU 101 and the bridge chip 102 can be improved from the hardware, so that the second entry address of the BIOS firmware program points to the address space of the third bus interface by default, and the initialization operation is completed at the hardware level, so that the address space of the third bus interface points to the storage space in the shared memory of the BMC 104 by default. On this basis, the CPU 101 can provide the second entry address of the BIOS firmware program to the bridge chip 102 after power-on; for the bridge chip 102, the bridge chip 102 can specifically redirect the reading interface for reading the BIOS firmware program from the second bus interface to the third bus interface according to the second entry address of the BIOS firmware program provided by the CPU 101 after power-on. In other words, in this embodiment, the reading interface of the bridge chip 102 for reading the BIOS firmware program is the third bus interface by default, that is, the redirection from the second bus interface to the third bus interface has been completed by default; then, the executable code instructions in the BIOS firmware program can be directly read from the shared memory of the BMC 104 through the third bus interface, and provided to the CPU 101 through the first bus interface for execution. In this embodiment, the other descriptions are the same as or similar to the foregoing embodiments, and can be referred to the foregoing embodiments, which will not be described here.

[0050] ​In the above embodiments of the present application, the implementation of the first bus interface, the second bus interface and the third bus interface is not limited. In an optional embodiment, the transmission rate of the third bus interface is higher than that of the second bus interface. Further optionally, the first bus interface can adopt a direct media interface (DMI), i.e., the CPU 101 is interconnected with the bridge chip 102 through the DMI. The second bus interface can adopt a serial peripheral interface (SPI), or a remote procedure call (RPC) interface, or an I2C interface, etc. Correspondingly, the third bus interface can adopt, but is not limited to, a peripheral component interconnect express (PCIE). In a preferred embodiment, as shown in Figure 1a the first bus interface is a DMI interface, the second bus interface is an SPI interface, and the third bus interface is a PCIE interface, wherein the transmission rate of the PCIE interface is higher than that of the SPI interface.

[0051] The transmission rate of the bus interface through which the bridge chip is interconnected with the BMC is higher than that of the bus interface through which the bridge chip is interconnected with the BIOS memory. In this way, during the booting process, the bridge chip can read the executable code instructions from the shared memory of the BMC to the CPU for execution by means of the bus interface with a higher transmission rate. Compared with the reading mode through the bus interface with a lower transmission rate, the time overhead of loading the executable code instructions can be further reduced, and the booting speed can be further improved. For example, the access speed to the BIOS memory (e.g., a flash) can be improved from the second bus interface (e.g., an SPI) to the speed of the third bus interface (e.g., a PCIE), which can bring several times or even tens of times of speed improvement, can shorten the time consumption of loading the BIOS, and can optimize the booting process and improve the booting speed.

[0052] Figure 3 A flowchart of a BIOS booting method provided by an exemplary embodiment of the present application is shown. The method is applicable to a device motherboard, and the device motherboard includes a processor CPU, a bridge chip, a BIOS memory and a baseboard management controller BMC. The bridge chip is interconnected with the CPU, the BMC and the BIOS memory through a first bus interface, a third bus interface and a second bus interface. The method can include the following steps:

[0053] 301. Before booting, the BMC reads a BIOS firmware program from the BIOS memory, pre-processes the BIOS firmware program to obtain executable code instructions, and writes the executable code instructions into the shared memory of the BMC.

[0054] 302. During the power-on process, the bridge chip reads executable code instructions from the shared memory of the BMC through the third bus interface and provides the first bus interface to the CPU so that the CPU can execute the executable code instructions to complete the power-on operation.

[0055] Optionally, the BIOS firmware program includes multiple code data segments. The BMC preprocesses the BIOS firmware program, including: performing validity checks on the uncompressed code data segments, and performing validity checks and decompression on the compressed code data segments to obtain executable code instructions.

[0056] Alternatively, before preprocessing the BIOS firmware, the BMC can read the storage description file of the BIOS memory from the BIOS memory. The storage description file stores at least the storage location of multiple code data segments and attribute information such as whether they are compressed. Based on the storage description file, the BMC can identify the uncompressed code data and the compressed code data among the multiple code data segments.

[0057] Alternatively, the bridge chip may redirect the BIOS firmware read interface from the second bus interface to the third bus interface before reading executable code instructions from the BMC's shared memory via the third bus interface.

[0058] Alternatively, when the address space of the third bus interface is initialized to point to the storage space in the shared memory of the BMC, the bridge chip maps the address information of the next executable code instruction in the BIOS firmware program provided by the CPU to the address space of the third bus interface, so as to redirect the reading interface of the BIOS firmware program from the second bus interface to the third bus interface.

[0059] Optionally, before redirecting the read interface to the third bus interface, the bridge chip reads the code data responsible for chip initialization from the BIOS memory through the second bus interface according to the address information of the next executable code instruction in the BIOS firmware program provided by the CPU, and provides it to the CPU through the first bus interface. The CPU preprocesses the code data responsible for chip initialization to obtain the executable code instruction responsible for chip initialization and executes the executable code instruction responsible for chip initialization to initialize the address space of the third bus interface so that it points to the storage space in the shared memory of the BMC.

[0060] Further, the bridge chip receives a first entry address of the BIOS firmware program provided by the CPU after power-on, the first entry address points to an address space of the second bus interface by default, and the address space of the second bus interface points to a storage space in the BIOS storage by default; according to the first entry address, the first code data in the BIOS firmware program is read from the BIOS storage through the second bus interface and provided to the CPU through the first bus interface. Correspondingly, the CPU pre-processes the first code data to obtain the first executable code instruction and executes the first executable code instruction to enter the execution logic of the BIOS firmware program.

[0061] Further, the bridge chip receives a second entry address of the BIOS firmware program provided by the CPU after power-on, the second entry address points to an address space of the third bus interface by default; according to the second entry address, the reading interface of the BIOS firmware program is redirected from the second bus interface to the third bus interface.

[0062] Further, the transmission rate of the third bus interface is higher than that of the second bus interface.

[0063] The specific implementation process of each step in the method provided in the embodiments of the present application can refer to the specific implementation process in the foregoing embodiments, which will not be described here.

[0064] In the embodiments of the present application, a new type of device mainboard is provided, which simultaneously includes a CPU and a BMC, and the BMC is interconnected with a BIOS storage storing a BIOS firmware program, and the BIOS firmware program can be pre-read from the BIOS storage, pre-processed to obtain executable code instructions and written into the shared memory thereof; in addition, the CPU is interconnected with the BMC through a bridge chip, so that in the process of starting up, the CPU can directly read the executable code instructions from the shared memory of the BMC through the bridge chip and execute them, and the CPU no longer needs to perform the pre-processing process of the BIOS firmware program in the process of starting up, thereby saving the starting-up time and improving the starting-up speed.

[0065] Further, in some embodiments, the transmission rate of the bus interface through which the bridge chip is interconnected with the BMC is higher than that of the bus interface through which the bridge chip is interconnected with the BIOS storage, so that in the process of starting up, the bridge chip can read the executable code instructions from the shared memory of the BMC to the CPU for execution through the bus interface with a higher transmission rate, compared with the reading mode through the bus interface with a lower transmission rate, the time overhead of loading the executable code instructions can be further reduced, and the starting-up speed is further improved.

[0066] Figure 4Another flowchart of a BIOS booting method is provided for the exemplary embodiments of the present application. The method is applicable to a BMC, the BMC is interconnected with a bridge chip and a BIOS memory storing a BIOS firmware program through a third bus interface and a second bus interface respectively, and the method can include the following steps:

[0067] 401. Before booting, reading the BIOS firmware program from the BIOS memory through the second bus interface, pre-processing the BIOS firmware program to obtain executable code instructions, and writing the executable code instructions into shared memory;

[0068] 402. During booting, reading the executable code instructions from the shared memory according to a read request of the bridge chip, and providing the executable code instructions to the CPU through the bridge chip via the third bus interface to enable the CPU to execute the executable code instructions to complete the booting operation.

[0069] Further optionally, the BIOS firmware program includes multiple code data, and the pre-processing of the BIOS firmware program includes: performing legality verification on the code data that is not compressed, and performing legality verification and decompression on the code data that is compressed to obtain the executable code instructions.

[0070] Further optionally, before the pre-processing of the BIOS firmware program, the method further includes: reading a storage description file of the BIOS memory from the BIOS memory, the storage description file at least storing storage locations of the multiple code data and attribute information of whether the code data is compressed; and identifying the code data that is not compressed and the code data that is compressed according to the storage description file.

[0071] In the embodiments of the present application, the BMC is interconnected with a BIOS memory storing a BIOS firmware program, and the BMC can read the BIOS firmware program from the BIOS memory in advance, pre-process the BIOS firmware program to obtain executable code instructions, and write the executable code instructions into shared memory thereof. In addition, the CPU is interconnected with the BMC through a bridge chip, so that during booting, the CPU can directly read the executable code instructions from the shared memory of the BMC through the bridge chip and execute the executable code instructions. During booting, the CPU no longer needs to perform the pre-processing of the BIOS firmware program, which can save booting time and improve booting speed.

[0072] Figure 5 A structure diagram of a baseboard management controller (BMC) is provided for the exemplary embodiments of the present application. The BMC is interconnected with a bridge chip and a BIOS memory storing a BIOS firmware program through a third bus interface and a second bus interface respectively, and the BMC includes:

[0073] The reading module 51 is configured to read the BIOS firmware program from the BIOS memory through the second bus interface before starting up;

[0074] The preprocessing module 52 is configured to preprocess the BIOS firmware program to obtain executable code instructions and write the executable code instructions into the shared memory;

[0075] The reading module 51 is further configured to read the executable code instructions from the shared memory according to a reading request of the bridge chip during the starting up process.

[0076] The sending module 53 is configured to provide the executable code instructions to the CPU through the bridge chip via the third bus interface, so that the CPU executes the executable code instructions to complete the starting up operation.

[0077] Further, the BIOS firmware program comprises a plurality of code data, and the preprocessing module 52 is configured to, when preprocessing the BIOS firmware program, perform legality verification on the code data that is not compressed, and perform legality verification and decompression on the code data that is compressed, to obtain the executable code instructions.

[0078] Further, the reading module 51 is further configured to read a storage description file of the BIOS memory from the BIOS memory, the storage description file at least storing storage positions of the plurality of code data and attribute information of whether the plurality of code data is compressed, and identify the code data that is not compressed and the code data that is compressed according to the storage description file. The preprocessing module 52 is configured to, according to the identification result of the reading module 51, perform legality verification on the code data that is not compressed, and perform legality verification and decompression on the code data that is compressed, to obtain the executable code instructions.

[0079] The BMC provided by the embodiment of the present application is interconnected with the BIOS memory storing the BIOS firmware program, can read the BIOS firmware program from the BIOS memory in advance, preprocess the BIOS firmware program to obtain executable code instructions and write the executable code instructions into the shared memory of the BMC. In addition, the CPU is interconnected with the BMC through the bridge chip, so that the CPU can directly read the executable code instructions from the shared memory of the BMC and execute the executable code instructions through the bridge chip during the starting up process. The CPU no longer needs to perform the preprocessing process of the BIOS firmware program during the starting up process, so that the starting up time can be saved and the starting up speed can be improved.

[0080] It should be noted that in some of the processes described in this specification, one or more operations have been described as occurring in a certain order. However, every embodiment can have different implementations that eliminate some operations or execute them in different orders. Furthermore, some operations can be performed in parallel. It should also be noted that, in some alternative implementations, operations can be executed in an order different from that described in this specification. Furthermore, some operations can be performed in parallel. Also, the illustrations in the drawings are for illustration only and can not be drawn to scale.

[0081] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In one embodiment, the present application can be implemented as a system-on-chip (SoC) that integrates components of a computing system into a single chip. It should be noted that the steps of the disclosed methods can be carried out in any order or simultaneously, except where the context under discussion excludes such an order.

[0082] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0083] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks.

[0084] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

[0085] In one typical arrangement, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0086] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) and / or cache memory, non-volatile memory, such as read-only memory (ROM), EPROM, and / or flash memory, etc. in the form of a computer-readable medium. The memory is an example of computer-readable media.

[0087] Computer-readable media includes permanent and non-permanent, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

[0088] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by an indefinite article "a" does not exclude the existence of additional identical elements in the process, method, article or apparatus including the element.

[0089] The above merely provides an example of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A device motherboard, characterized in that, include: Processor (CPU); The bridge chip is interconnected with the CPU via the first bus interface; The BIOS memory, interconnected with the bridge chip via a second bus interface, is used to store the BIOS firmware program; The baseboard management controller (BMC) is interconnected with the bridge chip via a third bus interface and with the BIOS memory via a second bus interface. Before power-on, it reads the BIOS firmware program from the BIOS memory, preprocesses the BIOS firmware program to obtain executable code instructions, and writes them into the shared memory of the BMC. The bridge chip is used to read the executable code instructions from the shared memory of the BMC through the third bus interface during the power-on process, and provide them to the CPU through the first bus interface, so that the CPU executes the executable code instructions to complete the power-on operation.

2. The device motherboard according to claim 1, characterized in that, The BIOS firmware program includes multiple code data segments. When the BMC preprocesses the BIOS firmware program, it specifically performs the following: The uncompressed code data in the multiple code segments is validated for legality, and the compressed code data is validated for legality and decompressed to obtain executable code instructions.

3. The device motherboard according to claim 2, characterized in that, The BMC is also used for: Read the storage description file of the BIOS memory from the BIOS memory. The storage description file stores at least the storage location of the multiple code data segments and attribute information such as whether they are compressed. Based on the storage description file, identify the uncompressed code data and the compressed code data in the multiple code data segments.

4. The device motherboard according to any one of claims 1-3, characterized in that, The bridging chip is also used for: Before reading the executable code instructions from the shared memory of the BMC via the third bus interface, the BIOS firmware read interface is redirected from the second bus interface to the third bus interface.

5. The device motherboard according to claim 4, characterized in that, The bridging chip is specifically used for: When the address space of the third bus interface is initialized to point to the storage space in the shared memory of the BMC, the address information of the next executable code instruction in the BIOS firmware program provided by the CPU is mapped to the address space of the third bus interface, so as to redirect the reading interface of the BIOS firmware program from the second bus interface to the third bus interface.

6. The device motherboard according to claim 5, characterized in that, The bridging chip is also used for: Before redirecting the read interface to the third bus interface, the code data responsible for chip initialization is read from the BIOS memory through the second bus interface according to the address information of the next executable code instruction in the BIOS firmware program provided by the CPU, and then provided to the CPU through the first bus interface. The CPU is used to preprocess the code data responsible for chip initialization to obtain executable code instructions responsible for chip initialization and execute the executable code instructions responsible for chip initialization to initialize the address space of the third bus interface so that it points to the storage space in the shared memory of the BMC.

7. The device motherboard according to claim 6, characterized in that, The bridging chip is also used for: The system receives the first entry address of the BIOS firmware program provided by the CPU after power-on. The first entry address points to the address space of the second bus interface by default, and the address space of the second bus interface points to the storage space in the BIOS memory by default. Based on the first entry address, the first line of code data in the BIOS firmware program is read from the BIOS memory through the second bus interface and provided to the CPU through the first bus interface; The CPU is further configured to: preprocess the first code data to obtain the first executable code instruction and execute the first executable code instruction to enter the execution logic of the BIOS firmware program.

8. The device motherboard according to claim 4, characterized in that, The bridging chip is specifically used for: Receive the second entry address of the BIOS firmware program provided by the CPU after power-on, the second entry address points to the address space of the third bus interface by default; Based on the second entry address, the BIOS firmware reading interface is redirected from the second bus interface to the third bus interface.

9. A BIOS boot method, characterized in that, Applicable to a device motherboard, the device motherboard includes a processor (CPU), a bridge chip, a BIOS memory, and a baseboard management controller (BMC). The bridge chip is interconnected with the CPU, BMC, and BIOS memory via a first bus interface, a third bus interface, and a second bus interface, respectively. The method includes: Before powering on, the BMC reads the BIOS firmware program from the BIOS memory, preprocesses the BIOS firmware program to obtain executable code instructions, and writes them into the shared memory of the BMC. During the power-on process, the bridge chip reads the executable code instructions from the shared memory of the BMC through the third bus interface and provides the first bus interface to the CPU so that the CPU executes the executable code instructions to complete the power-on operation.

10. A BIOS boot method, characterized in that, Applicable to a baseboard management controller (BMC), wherein the BMC is interconnected with a bridge chip and a BIOS memory storing BIOS firmware via a third bus interface and a second bus interface respectively, the method includes: Before powering on, the BIOS firmware program is read from the BIOS memory via the second bus interface, the BIOS firmware program is preprocessed to obtain executable code instructions, and then written into the shared memory. During the power-on process, the executable code instructions are read from the shared memory according to the read request of the bridge chip, and then provided to the CPU via the bridge chip through the third bus interface, so that the CPU can execute the executable code instructions to complete the power-on operation.

11. The method according to claim 10, characterized in that, The BIOS firmware program includes multiple code data segments. Preprocessing the BIOS firmware program specifically involves: The uncompressed code data in the multiple code segments is validated for legality, and the compressed code data is validated for legality and decompressed to obtain executable code instructions.

12. The method according to claim 11, characterized in that, Also includes: Read the storage description file of the BIOS memory from the BIOS memory. The storage description file stores at least the storage location of the multiple code data segments and attribute information such as whether they are compressed. Based on the storage description file, identify the uncompressed code data and the compressed code data in the multiple code data segments.

13. A baseboard management controller (BMC), characterized in that, The BMC is interconnected with the bridge chip and the BIOS memory storing the BIOS firmware via a third bus interface and a second bus interface, respectively. The reading module is used to read the BIOS firmware program from the BIOS memory via the second bus interface before power-on; A preprocessing module is used to preprocess the BIOS firmware program to obtain executable code instructions and write them into shared memory; The reading module is also used to: during the power-on process, read the executable code instructions from the shared memory according to the read request of the bridge chip; The sending module is used to provide the executable code instructions to the CPU via the third bus interface and the bridge chip, so that the CPU executes the executable code instructions to complete the power-on operation.

14. An electronic device, characterized in that, The device motherboard includes any one of claims 1-8.

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