A shift storage address mapping circuit based on SRAM
By using an SRAM-based shift memory address mapping circuit and logic gate circuits to implement address mapping, the problems of data loss and decoding logic complexity in existing technologies are solved, enabling flexible reading and low-complexity data storage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SG MICRO CORP
- Filing Date
- 2022-09-30
- Publication Date
- 2026-06-23
Smart Images
Figure CN115631778B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more specifically, to a shift memory address mapping circuit based on SRAM. Background Technology
[0002] With the continuous development of information technology, the demand for data shift storage applications is also increasing. As the bit width and data volume of shift storage continue to increase, the existing method of using discrete flip-flops to implement shift storage has led to increasingly complex decoding logic and increased circuit area consumption, making it difficult to meet the increasingly complex data processing application scenarios.
[0003] If a hardware stack or FIFO (First In First Out) memory is used to replace the shift memory for storing data with a large bit width W and a large number of data N, although the circuit area can be effectively reduced while preserving the data storage order, the data in the memory is lost after reading the data. This is not suitable for application scenarios that require data to be read without loss. In addition, if the user needs to read certain specific stored data, it is necessary to read the data sequentially starting from the top of the hardware stack or the first data stored in the FIFO. The inability to flexibly address and read the data results in a lot of wasted read time.
[0004] Furthermore, if SRAM is used alone to store data, although it can flexibly address and read the stored data, in closed systems where the number of times data is stored is unknown, the shift storage order of the data cannot be obtained when performing data reading operations, and it is impossible to distinguish between new and old stored data in the memory.
[0005] If the latest data is written to the initial address every time data is written to SRAM, then to preserve the data shifting and storage order and prevent the loss of old data, it is necessary to temporarily store all the old data and then sequentially write the old data back to the address following its original address in SRAM. In this method, the additional area overhead of register storage and the additional read / write operation time overhead each time new data is stored both increase with the increase of SRAM depth N, greatly limiting its application scenarios.
[0006] To address the above problems, this invention provides a shift memory address mapping circuit based on SRAM. Summary of the Invention
[0007] To address the shortcomings of existing technologies, this invention provides a shift storage address mapping circuit based on SRAM. By using an address queue mapping circuit, the processor's read operation address is cleverly mapped to the read address of different SRAM memories, thereby preserving the shift storage order of write data and ensuring that data is not lost after flexible data reading.
[0008] The present invention adopts the following technical solution.
[0009] This invention relates to a shift storage address mapping circuit based on SRAM. The address mapping circuit is connected to the SRAM and implemented using logic gate circuits. It is used to count the write data operations of the SRAM and to map the processor's read address to the actual read operation address of the SRAM based on the counting result and output it. The actual read operation address of the SRAM is used by the SRAM to perform read data operations.
[0010] Preferably, the address mapping circuit includes a write data counter, a subtractor, a constant adder, and a multiplexer; wherein, the write data counter is used to count the write data operations of the SRAM; the subtractor is a signed subtractor used to perform a subtraction operation between the processor's read address and the count result to obtain a first address; the constant adder is a half adder used to sum the calculation result of the subtractor with a preset constant to obtain a second address; and the multiplexer is used to select between the first address and the second address and generate the actual read operation address of the SRAM.
[0011] Preferably, the input terminal of the write data counter is connected to the write enable signal, and the output terminal is connected to the first input terminal of the subtractor; the second input terminal of the subtractor is connected to the processor's read address signal, the first output terminal generates a first address, and is connected to the second input terminal of the constant adder and the second input terminal of the multiplexer respectively; the second output terminal of the subtractor generates the sign of the subtraction operation and is connected to the selection port of the multiplexer; the first input terminal of the constant adder is connected to a constant N, and the output terminal is connected to the first input terminal of the multiplexer; the output terminal of the multiplexer outputs the actual read operation address of the SRAM.
[0012] Preferably, the first output of the signed subtractor is used to output the two's complement result of the subtraction operation, and the second output of the subtractor is used to output the two's complement sign bit of the subtraction operation.
[0013] Preferably, the value of the constant N at the first input terminal of the half-adder is determined based on the data storage depth of the SRAM.
[0014] Preferably, the multiplexer determines the signal at its first input or its second input as the output based on the sign of the subtraction operation in the selection port.
[0015] Preferably, the bit width of the write data counter, subtractor, constant adder, and multiplexer is determined based on the data storage depth N requirement of the SRAM, and the subtractor, constant adder, and multiplexer perform logical operations based on the processor's read address.
[0016] The beneficial effects of this invention are that, compared with the prior art, the SRAM-based shift memory address mapping circuit of this invention can cleverly map the processor's read address to different read operation addresses of the SRAM memory through an address queue mapping circuit, thereby achieving the purpose of preserving the shift memory order relationship of write data and ensuring that data is not lost after flexible reading. This invention is ingeniously conceived, making data reading more flexible. At the same time, compared with the methods of implementing shift memory through discrete flip-flops or using SRAM to move old data, it saves the processing time of read data operations, reduces the additional overhead of registers, and significantly reduces the complexity of the circuit. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of data access based on SRAM shift storage in the prior art;
[0018] Figure 2 This is a schematic diagram of a shift storage address mapping circuit structure based on SRAM according to the present invention;
[0019] Figure 3 This is a schematic diagram of data access for shift storage implemented by a shift storage address mapping circuit based on SRAM according to the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.
[0021] Figure 1 This is a schematic diagram of data access based on SRAM shift storage in the prior art. For example... Figure 1 As shown, in the prior art, when implementing shift storage based on SRAM, the newly written data needs to be stored at address ADDR0, while the data originally stored at ADDR0 will be moved to ADDR1 through a register temporary storage operation. Similarly, the data at other addresses will also be shifted accordingly.
[0022] As can be seen, in existing technologies, the write address (ram waddr) is automatically incremented by one each time data is stored, and automatically returns to 0 after the write address reaches N-1. Reading the corresponding addresses (ram raddr) 0 to N-1 of the SRAM sequentially yields stored data 1 to data N, where data 1 is the most recently written data to the SRAM and data N is the earliest written data. This scheme can preserve the shift storage order of write data and prevent data loss after reading. However, this scheme requires an additional (N-1)*W registers to temporarily store the read data, and still requires an additional N-1 read operations and N-1 write operations. Here, W is the data bit width of the SRAM. Therefore, the additional area and operation time overhead of the old scheme greatly limits its application scenarios.
[0023] Figure 2 This is a schematic diagram of a shift memory address mapping circuit structure based on SRAM according to the present invention. Figure 2 As shown, this invention provides a mapping circuit. Specifically, it is an SRAM-based shift memory address mapping circuit, connected to the SRAM and implemented using logic gates. It counts write data operations in the SRAM and maps the processor's read address to the actual read operation address of the SRAM based on the counting result, then outputs the result. The actual read operation address of the SRAM is used by the SRAM to perform read data operations.
[0024] Figure 3 This is a schematic diagram illustrating data access for shift storage implemented using an SRAM-based shift storage address mapping circuit according to the present invention. Figure 3 As shown, through the improvement of the method of the present invention, the processor's read address can be accurately mapped to the SRAM read operation address. Therefore, with just this circuit, the specific location of the user's required data can still be accurately obtained after a certain number of write operations, and the corresponding data in the required order can be flexibly extracted from the SRAM.
[0025] Preferably, the circuit includes a write data counter, a subtractor, a constant adder, and a multiplexer; wherein, the write data counter is used to count the write data operations of the SRAM; the subtractor is a signed subtractor used to perform a subtraction operation between the processor's read address and the count result to obtain a first address; the constant adder is a half adder used to sum the calculation result of the subtractor with a preset constant to obtain a second address; and the multiplexer is used to select between the first address and the second address and generate the actual read operation address of the SRAM.
[0026] It should be noted that the write data counter receives the SRAM write enable signal, as shown in the figure, the wen signal. This signal starts counting when the user performs a write operation. By sampling the high level state of the wen signal and the clock cycle signal, the write data counter can accurately obtain the exact number of write operations performed by the SRAM.
[0027] Since the SRAM (Static Random Access Memory) circuit in this application is a static storage circuit, data is not lost during the reading process. Therefore, the address order is calculated through virtual mapping in this invention to achieve the same effect as shift storage.
[0028] Furthermore, this invention also involves a processor read address (read addr), which is generated by the processor according to user requirements. This address is used to attempt to locate data in the corresponding storage order from the SRAM based on user instructions. During the process of locating the corresponding storage order data, the mapping circuit in this invention can accurately locate the actual read operation address of the data in the SRAM based on the read addr.
[0029] Specifically, in this invention, the SRAM can be a multi-row, multi-column static random access memory circuit. Assuming its stored data bit width is M and its depth is N, the circuit in this invention performs the mapping operation based on these parameters. Furthermore, a general-purpose SRAM can support one read address port (ren), one read data port (rdata), one write address port (wen), and one write data port (wdata). The read and write address ports are used to enable the processor to address the data or operation address stored in the SRAM. The read and write data ports are used to input and output the actual data content. Additionally, the processor's read address (readaddr) mentioned above is not directly input through the SRAM's read address port. Instead, it is first converted into an SRAM read operation address (ramraddr) through the address mapping circuit in this invention, and then input into the SRAM through the SRAM's read address port to read the data at the corresponding location. Here, ramraddr is the actual read operation address of the SRAM.
[0030] Preferably, the input terminal of the write data counter is connected to the write enable signal, and the output terminal is connected to the first input terminal of the subtractor; the second input terminal of the subtractor is connected to the processor's read address signal, the first output terminal generates a first address, and is connected to the second input terminal of the constant adder and the second input terminal of the multiplexer respectively; the second output terminal of the subtractor generates the sign of the subtraction operation and is connected to the selection port of the multiplexer; the first input terminal of the constant adder is connected to a constant N, and the output terminal is connected to the first input terminal of the multiplexer; the output terminal of the multiplexer outputs the actual read operation address of the SRAM.
[0031] Specifically, the write data counter marks the location where the latest data has been written to SRAM. Each time data is stored, the write address (ram waddr) is automatically incremented by one, and it automatically returns to 0 after reaching N-1; the write data counter write cnt counts sequentially from 0 to N-1, and automatically returns to 0 after reaching N-1.
[0032] Preferably, the first output of the subtractor is used to output the two's complement result of the subtraction operation, and the second output of the subtractor is used to output the two's complement sign bit of the subtraction operation.
[0033] Specifically, the subtractor in this invention not only calculates the subtraction value (sub frag) of the two signals, but also obtains the sign (sub sign) of the subtraction result. This invention represents the sign of the subtraction result using a single binary bit, while the subtraction value is output accordingly based on the number of bits of the signal acquired during the subtractor's operation.
[0034] For example, the subtractor calculates its result (sub result) using the following formula:
[0035] sub result=write cnt-read addr={sub sign,sub frag} (1)
[0036] As shown in formula (1), the minuend of the subtractor is the count value of the data counter, write cnt, and the subtrahend is the read address input by the user, read addr. The final result of the subtractor is sent to the next stage circuit in two's complement form, namely the sign bit of the subtraction result, sub sign, and the truncation bit of the subtraction result, sub frag.
[0037] Taking an SRAM depth of N=5 as an example, the values of the minuend (write cnt) and subtrahend (read addr) can be represented by 3-bit binary numbers. Therefore, the signed subtraction result needs to be represented by a 4-bit binary number. Taking the minuend (write cnt) as 1 and the subtrahend (read addr) as 2 as an example, the binary result of the subtraction is:
[0038] sub result=0b0001-0b0010=0b1111={sub sign,sub frag} (2)
[0039] As shown in formula (2), when calculating the result of the subtractor in Example 1, both the minuend and subtrahend can be padded with the sign bit '0'. In the example operation, the sign bit of the subtraction result is subsign = 0b1, and the data truncation bit of the subtraction result is subfrag = 0b111.
[0040] Preferably, the value of the constant N at the first input terminal of the half adder is determined based on the data storage depth of the SRAM.
[0041] It is understandable that the constant adder is an unsigned half adder, whose addends are the subfrag of the subtraction result and the SRAM memory depth N. The formula for calculating the add result is as follows:
[0042] add result=sub frag+N={0bX,add frag} (3)
[0043] As shown in formula (3), the addend of the half adder: the subtraction result data truncation sub frag and the SRAM depth N can be represented by 3 bits of binary numbers. The carry number 0bX of the half adder is not important. The calculation result is:
[0044] add result=0b111+0b101=0b1100={0bX,add frag} (4)
[0045] As shown in formula (4), the addition result data obtained by the unsigned half adder in Example 1 is truncated as add frag = 0b100.
[0046] Preferably, the multiplexer determines the signal at its first input or its second input as the output based on the sign of the subtraction operation in the selection port.
[0047] The multiplexer in the circuit is a 2-to-1 multiplexer, and its calculation formula is as follows:
[0048]
[0049] As shown in formula (5), when the subtraction result sign bit sub sign is 0, the read address ram raddr input to the SRAM memory will be mapped to the subtraction result data truncation bit sub frag; when the subtraction result sign bit sub sign is 1, the read address ram raddr input to the SRAM memory will be mapped to the addition result data truncation bit add frag.
[0050] In the example subtraction result, the sign bit `sub sign` is 0b1, so the mapped `ram raddr` is `add frag` and `0b100`. In the shift-order read sequence design, when the user reads at address `read addr` = 2, the desired data to be read is data 3. At this time, the write data count `write cnt` = 1 indicates that the latest data 1 is stored at SRAM address 1, data 2 is stored at SRAM address 0, and data 3 is stored at SRAM address 4, which matches the example mapped `ram raddr` result.
[0051]
[0052]
[0053] Table 1. Read address cyclic mapping relationship in the first embodiment.
[0054] As shown in Table 1, when the SRAM storage depth is set to N=5, the exact location of the storage order data required by the processor can be read from the corresponding SRAM read operation address according to the mapping relationship.
[0055]
[0056]
[0057]
[0058] Table 2. Read address cyclic mapping relationship in the second embodiment.
[0059] In the second embodiment of the present invention, when N is 8, the data storage depth is an integer power of 2. At this time, the mapping relationship changes accordingly. At this time, the first input terminal and the second input terminal of the multiplexer are equal, and a reasonable SRAM read operation address can be calculated and output according to the processor read address.
[0060] Preferably, the bit width of the write data counter, subtractor, constant adder, and multiplexer is determined based on the data storage depth N requirement of the SRAM, and the subtractor, constant adder, and multiplexer perform logical operations based on the processor's read address.
[0061] Specifically, for example, when the data bit width is up to 8, the write data counter, constant adder, and multiplexer can all be implemented with a 3-bit bit width. Since the signed subtractor requires an additional sign bit, it needs to be implemented with a 4-bit bit width. Similarly, the bit width bw in various components can be determined according to the required data storage depth N, such that 2 raised to the power of bw is greater than or equal to the data storage depth N, and 2 raised to the power of bw-1 is less than the data storage depth N.
[0062] In summary, when the storage circuit is a black box to the user, and the user reads shifted storage data of depth N without knowing the number of storage cycles, the shifted storage circuit described in this invention allows the user to flexibly read data in the corresponding shift order without data loss. This invention is applicable to all cases with different storage data bit widths W and different SRAM memory storage depths N. Furthermore, as the data storage depth N increases, this invention only needs to calculate the binary bit width of the storage depth value N-1 using powers of 2, and correspondingly increase the bit width of the data counter, subtractor, constant adder, and multiplexer in the address mapping circuit. Compared to the traditional shift register storage of W×N shift registers and W×N fan-in address decoding circuits, this invention achieves the same shift access effect with a smaller circuit area cost. This advantage becomes particularly pronounced as the data bit width W and storage depth N increase. This invention can always read the stored data in the corresponding shift storage order when the user sends a read address from 0 to N-1, making it widely applicable to various shifted storage application scenarios.
[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.
Claims
1. A shift memory address mapping circuit based on SRAM, characterized in that: The address mapping circuit is connected to the SRAM and is implemented using logic gate circuits. It is used to count the write data operations of the SRAM, and based on the counting result, to map the processor's read address to the actual read operation address of the SRAM and output it. The actual read operation address of the SRAM is used by the SRAM to perform read data operations. The address mapping circuit includes a write data counter, a subtractor, a constant adder, and a multiplexer; wherein... The write data counter is used to count the write data operations of the SRAM; The subtractor is a signed subtractor, used to perform a subtraction operation on the processor's read address and the counting result to obtain a first address; The constant adder is a half adder, used to sum the calculation result of the subtractor with a preset constant to obtain a second address; The multiplexer is used to select between the first address and the second address, and to generate the actual read operation address of the SRAM.
2. The SRAM-based shift memory address mapping circuit according to claim 1, characterized in that: The input terminal of the write data counter is connected to the write enable signal, and the output terminal is connected to the first input terminal of the subtractor. The second input of the subtractor is connected to the read address signal of the processor, and the first output generates the first address and is connected to the second input of the constant adder and the second input of the multiplexer, respectively. The second output of the subtractor generates the sign of the subtraction operation and is connected to the selection port of the multiplexer; The first input terminal of the constant adder is connected to a constant N, and the output terminal is connected to the first input terminal of the multiplexer. The output of the multiplexer outputs the actual read operation address of the SRAM.
3. The SRAM-based shift memory address mapping circuit according to claim 2, characterized in that: The first output of the signed subtractor is used to output the two's complement result of the subtraction operation, and the second output of the subtractor is used to output the two's complement sign bit of the subtraction operation.
4. The SRAM-based shift memory address mapping circuit according to claim 3, characterized in that: The value of the constant N at the first input terminal of the half adder is determined based on the data storage depth of the SRAM.
5. The SRAM-based shift memory address mapping circuit according to claim 4, characterized in that: The multiplexer determines the signal at its first input or its second input as the output based on the sign of the subtraction operation in the selection port.
6. The SRAM-based shift memory address mapping circuit according to claim 5, characterized in that: The bit width of the write data counter, subtractor, constant adder, and multiplexer is determined based on the data storage depth requirements of the SRAM, and the subtractor, constant adder, and multiplexer perform logical operations based on the processor's read address.