Method for avoiding pinhole generation in a high resistance process

Abstract

The application provides a method for avoiding pinhole in high-resistance process, which comprises the following steps: providing a Co layer; sequentially forming a cap layer, a TiN layer, a hard mask layer, an oxidation layer, an anti-reflection coating layer and a photoresist layer on the Co layer from bottom to top; the thickness of the oxidation layer is 50 angstroms, and the method for forming the oxidation layer is atomic layer deposition; the bond energy of the oxidation layer is greater than that of the hard mask layer; exposing the anti-reflection coating layer by opening the photoresist layer to form a groove; etching the anti-reflection coating layer along the groove by using chlorine to expose the upper surface of the oxidation layer; the oxidation layer prevents the chlorine from corroding the TiN layer through the hard mask layer with loose structure in the etching process to form pinholes; continuing to etch the exposed oxidation layer and the hard mask layer under the exposed oxidation layer along the groove sidewall until the upper surface of the TiN layer is exposed; etching the exposed TiN layer along the groove until the upper surface of the cap layer is exposed, and the uncorroded TiN layer prevents the exposed cap layer and the Co layer under the exposed cap layer from forming pinholes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for avoiding pinholes in high-resistivity processes. Background Technology

[0002] As the critical dimensions of integrated circuit processes continue to shrink, film structures become thinner, and process performance requirements increase, a high-resistivity structure is often needed in the entire circuit for voltage division. For nodes below 10nm, the high-resistivity process structure, from bottom to top, consists of Co, SiN, TiN, hard mask SiN, bottom anti-reflective coating, and PR. However, due to the porous structure of the hard mask SiN material and its poor etching resistance, chlorine gas used in etching the bottom anti-reflective coating can penetrate the SiN through the porous structure and ultimately transmit pinholes to the bottom layer Co, causing Co corrosion and affecting device performance. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method to avoid the generation of pinholes in high-resistivity processes, which solves the problem of corrosion of the bottom layer Co in high-resistivity processes in the prior art.

[0004] To achieve the above and other related objectives, the present invention provides a method for avoiding pinholes in a high-resistivity process, the method comprising at least:

[0005] Step 1: Provide a Co layer; on the Co layer, from bottom to top, form a cap layer, a TiN layer, a hard mask layer, an oxide layer, an anti-reflection coating, and a photoresist layer; the oxide layer has a thickness of 50 angstroms, and the oxide layer is formed by atomic layer deposition; the bond energy of the oxide layer is greater than the bond energy of the hard mask layer;

[0006] Step 2: Open the photoresist layer to expose the anti-reflective coating, forming a groove;

[0007] Step 3: Use chlorine gas to etch the anti-reflective coating along the groove to expose the upper surface of the oxide layer; the oxide layer prevents chlorine gas from corroding the TiN layer through the loosely structured hard mask layer during the etching process, thus preventing pinholes.

[0008] Step 4: Continue etching along the sidewall of the groove to expose the oxide layer and the hard mask layer below the exposed oxide layer until the upper surface of the TiN layer is exposed;

[0009] Step 5: Etch the exposed TiN layer along the groove until the upper surface of the cap layer is exposed, removing the un-etched TiN layer from Step 3 to prevent pinholes from forming in the exposed cap layer and the Co layer located beneath the exposed cap layer.

[0010] Preferably, the bond energy of the oxide layer in step one is 460 kJ / mol.

[0011] Preferably, the bond energy of the hard mask layer in step one is 360 KJ / mol.

[0012] Preferably, the material of the cap layer in step one is silicon nitride.

[0013] Preferably, the material of the hard mask layer in step one is silicon nitride.

[0014] Preferably, the oxide layer in step one is silicon oxide.

[0015] Preferably, this method is used for high-resistivity processes at nodes below 10nm.

[0016] As described above, the method for avoiding pinholes in the high-resistivity process of the present invention has the following beneficial effects: The present invention changes the film structure of the high-resistivity structure in the traditional process, depositing a 50A ALD layer on the hard mask layer. Since the bond energy of the oxide layer is higher than that of SIN, it has a stronger ability to block etching. At the same time, it is relatively dense, preventing chlorine gas from corroding the underlying TIN layer through pinholes, thereby improving the performance of the device. Attached Figure Description

[0017] Figures 1 to 4 The diagram shows the structural schematic of each step in the method for avoiding pinholes in the high-resistivity process of the present invention.

[0018] Figure 5 The diagram shows a flow chart of a method to avoid pinholes in the high-resistivity process of this invention. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] This invention provides a method for avoiding pinholes in high-resistivity processes, such as... Figure 5 As shown, Figure 5 The diagram shows a flow chart of a method for avoiding pinholes in the high-resistivity process of this invention. The method includes at least:

[0022] Step 1: Provide a Co layer; on the Co layer, from bottom to top, form a cap layer, a TiN layer, a hard mask layer, an oxide layer, an anti-reflection coating, and a photoresist layer; the oxide layer has a thickness of 50 angstroms, and the oxide layer is formed by atomic layer deposition; the bond energy of the oxide layer is greater than the bond energy of the hard mask layer;

[0023] Furthermore, in this embodiment, the bond energy of the oxide layer in step one is 460 KJ / mol.

[0024] Furthermore, in this embodiment, the bond energy of the hard mask layer in step one is 360 KJ / mol.

[0025] Furthermore, in this embodiment, the material of the cap layer in step one is silicon nitride.

[0026] Furthermore, in this embodiment, the material of the hard mask layer in step one is silicon nitride.

[0027] Furthermore, in this embodiment, the oxide layer in step one is silicon oxide.

[0028] like Figure 1 As shown, step one provides a Co layer (Co); on the Co layer (Co), from bottom to top, a cap layer (Co CAP SIN), a TiN layer (HiR TIN), a hard mask layer (HiR HM SIN), an oxide layer O1, an anti-reflective coating (Barc), and a photoresist layer (PR) are formed sequentially; the thickness of the oxide layer O1 is 50 angstroms, and the method for forming the oxide layer O1 is atomic layer deposition (ALD); the bond energy of the oxide layer O1 is greater than the bond energy of the hard mask layer (HiR HM SIN). In this embodiment, the bond energy of the oxide layer O1 is 460 kJ / mol; the bond energy of the hard mask layer (HiR HM SIN) is 360 kJ / mol; the material of the cap layer (Co CAP SIN) is silicon nitride; the material of the hard mask layer (HiR HM SIN) is silicon nitride; and the oxide layer O1 is silicon oxide.

[0029] Step 2: Open the photoresist layer to expose the anti-reflective coating, forming a groove;

[0030] like Figure 1 As shown, in step two, the photoresist layer (PR) is opened to expose the anti-reflective coating (Barc), forming a groove.

[0031] Step 3: Use chlorine gas to etch the anti-reflective coating along the groove to expose the upper surface of the oxide layer; the oxide layer prevents chlorine gas from corroding the TiN layer through the loosely structured hard mask layer during the etching process, thus preventing pinholes.

[0032] like Figure 2 As shown, step three uses chlorine gas (CL2) to etch the anti-reflective coating (Barc) along the groove, exposing the upper surface of the oxide layer 01. The oxide layer 01 prevents chlorine gas from corroding the TiN layer through the loosely structured hard mask layer (HiR HM SIN) during the etching process, thus preventing pinholes. In other words, the hard mask layer in this embodiment is SIN, which has a loose structure. Without the obstruction of the oxide layer during etching, chlorine gas could easily enter the loosely structured hard mask layer and then the underlying TiN layer, corroding it and forming pinholes. The oxide layer in this embodiment serves to prevent chlorine gas from corroding the TiN layer during the etching of the anti-reflective coating (Barc) and to prevent corrosion of the layers below the TiN layer in subsequent steps.

[0033] Step 4: Continue etching along the sidewalls of the groove to expose the oxide layer and the hard mask layer below it, until the upper surface of the TiN layer is exposed; Figure 3 As shown, in step four, the exposed oxide layer 01 and the hard mask layer (HiR HM SIN) below the exposed oxide layer 01 are etched along the sidewall of the groove until the upper surface of the TiN layer (HiR TIN) is exposed.

[0034] Step 5: Etch the exposed TiN layer along the groove until the upper surface of the cap layer is exposed, removing the un-etched TiN layer from Step 3 to prevent pinholes from forming in the exposed cap layer and the Co layer beneath it. Figure 4 As shown, in step five, the exposed TiN layer (HiR TIN) is etched along the groove until the upper surface of the cap layer is exposed. The TiN layer that was not etched in step three is used to prevent pinholes from forming in the exposed cap layer (Co CAP SIN) and the Co layer (Co) located under the exposed cap layer (Co CAP SIN).

[0035] This method is used for high-resistivity processes at nodes below 10nm.

[0036] In summary, this invention modifies the high-resistivity film structure in traditional processes by depositing a 50 Å ALD layer on a hard mask. Because the bond energy of the oxide layer is higher than that of SiN, it has a stronger ability to resist etching. Simultaneously, its relative density prevents chlorine gas from corroding the underlying TIN layer through pinholes, thus improving device performance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for avoiding pinhole generation in a high resistance process, characterized by, The method comprises at least: Step one, providing a Co layer; sequentially forming a cap layer, a TiN layer, a hard mask layer, an oxidation layer, an anti-reflection coating layer and a photoresist layer on the Co layer from bottom to top; the thickness of the oxidation layer is 50 angstroms, and the method for forming the oxidation layer is atomic layer deposition; the bond energy of the oxidation layer is greater than the bond energy of the hard mask layer; Step two, exposing the anti-reflection coating layer by opening the photoresist layer to form a groove; Step three, etching the anti-reflection coating layer along the groove by using chlorine to expose the upper surface of the oxidation layer; the oxidation layer prevents the chlorine from corroding the TiN layer to form a pinhole in the etching process through the hard mask layer which is loose in structure; Step four, continuing to etch the exposed oxidation layer and the hard mask layer under the exposed oxidation layer along the groove side wall until the upper surface of the TiN layer is exposed; Step five, etching the exposed TiN layer along the groove until the upper surface of the cap layer is exposed; the TiN layer which is not corroded in step three prevents the exposed cap layer and the Co layer under the exposed cap layer from forming a pinhole.

2. The method of avoiding pinhole generation in a high resistance process of claim 1, wherein: The bond energy of the oxidation layer in step one is 460 KJ / mol.

3. The method of avoiding pinhole generation in a high resistance process of claim 2, wherein: The bond energy of the hard mask layer in step one is 360 KJ / mol.

4. The method of avoiding pinhole generation in a high resistance process of claim 1, wherein: The material of the cap layer in step one is silicon nitride.

5. The method of avoiding pinhole generation in a high resistance process of claim 1, wherein: The material of the hard mask layer in step one is silicon nitride.

6. The method of avoiding pinhole generation in a high resistance process of claim 1, wherein: The oxidation layer in step one is silicon oxide.

7. The method of avoiding pinhole generation in a high resistance process of claim 1, wherein: The method is used for high resistance process in nodes below 10 nm.

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