Method of forming semiconductor structure

Abstract

A method of forming a semiconductor structure is provided. The method includes the following operations. A diamond-like carbon hard mask layer is formed on the substrate, wherein the absorbance of the diamond-like carbon hard mask layer is less than or equal to 0.5. A dielectric anti-reflective coating is formed over the diamond-like carbon hard mask layer. A bottom anti-reflective coating is formed over the dielectric anti-reflective coating. The hard mask has small absorbance, so that when light is used to find an etching position below the hard mask, the light irradiated to and reflected by the hard mask cannot be absorbed too much by the hard mask. The etching uniformity can be improved by finding the correct etching position, the semiconductor structure is prevented from being damaged, the etching pattern is prevented from being bent, and the etching is more favorable for having a higher length-width ratio.

Description

Technical Field

[0001] This invention relates to a method for forming a semiconductor structure. Background Technology

[0002] Kodiak carbon hard masks are the hardest known mask layers in semiconductor manufacturing processes. However, the disadvantages of using Kodiak carbon hard masks include their excessive thickness, low transmittance, and high absorbance. As etching evolves to form semiconductor structures with higher aspect ratios, the thickness of the Kodiak carbon hard mask must increase. Thicker Kodiak carbon hard masks result in even worse transmittance, leading to less light reflection when using light to locate the precise etching position. Incorrect etching placement can damage the semiconductor structure and prevent the acquisition of semiconductor structures with high aspect ratios. Therefore, there is a need to develop new methods for forming semiconductor structures that can meet more desired requirements. Summary of the Invention

[0003] This invention provides a method for forming a semiconductor structure. The method includes the following operations: forming a diamond-like carbon hard mask layer on a substrate, wherein the absorbance of the diamond-like carbon hard mask layer is less than or equal to 0.5; forming a dielectric antireflective coating on the diamond-like carbon hard mask layer; and forming a bottom antireflective coating on the dielectric antireflective coating.

[0004] In some embodiments, forming a diamond-like carbon hard mask layer includes: providing C2H2 and an inert gas; and reacting C2H2 to form a diamond-like carbon hard mask layer.

[0005] In some implementations, the ratio of the flow rate of C2H2 to the flow rate of the inert gas is 1:20 to 1:50.

[0006] In some implementations, the flow rate of C2H2 is 290 SCCM to 390 SCCM.

[0007] In some implementations, the formation of the diamond-like carbon hard masking layer is carried out under a pressure of 1.3 Torr to 3.1 Torr.

[0008] In some embodiments, the formation of the diamond-like carbon hard mask layer is carried out at a temperature of 150°C to 400°C.

[0009] In some implementations, the stress of the diamond-like carbon hard mask layer is -750 MPa to -350 MPa.

[0010] In some implementations, the thickness of the diamond-like carbon hard mask layer is less than or equal to 150 nm.

[0011] In some implementations, the etch selectivity of the oxide material relative to the diamond-like carbon hard mask layer is 15:1 to 25:1.

[0012] The present invention also provides a method for forming a semiconductor structure. The method includes the following operations: forming an amorphous carbon hard mask layer on a plurality of first electrodes of a plurality of capacitors on a substrate, wherein the absorbance of the amorphous carbon hard mask layer is less than or equal to 0.5, and an oxide layer is disposed between the first electrodes; forming a photoresist layer having an opening on the amorphous carbon hard mask layer; and etching the amorphous carbon hard mask layer through the opening of the photoresist layer.

[0013] In some embodiments, etching an amorphous carbon hard mask layer is performed to expose an oxide layer disposed between the first electrodes of the capacitor, and the method further includes etching the oxide layer and forming a plurality of dielectric layers and a plurality of second electrodes on the first electrodes.

[0014] In some embodiments, the method further includes: before or during the formation of a photoresist layer with openings on an amorphous carbon hard mask layer, using light to illuminate and reflect light from the amorphous carbon hard mask layer to determine multiple positions of the first electrodes, so as to align the openings of the photoresist layer with the positions between the two first electrodes.

[0015] In some implementations, etching the amorphous carbon hard mask layer includes using anisotropic dry etching.

[0016] In some implementations, the stress of the amorphous carbon hard mask layer is -750 MPa to -350 MPa.

[0017] In some implementations, the thickness of the amorphous carbon hard mask layer is less than or equal to 150 nm. Attached Figure Description

[0018] The invention can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings.

[0019] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to some embodiments of the present invention.

[0020] Figures 2 to 3 This is a cross-sectional schematic diagram of a structure during the process of forming a semiconductor structure using some embodiments of the present invention.

[0021] Figure 4 This is a flowchart of a method for forming a semiconductor structure according to some embodiments of the present invention.

[0022] Figures 5 to 10 This is a cross-sectional schematic diagram of a structure during the process of forming a semiconductor structure using some embodiments of the present invention.

[0023] Figure 11 This is a cross-sectional schematic diagram of a structure during the process of forming a semiconductor structure using some comparative embodiments of the present invention. Detailed Implementation

[0024] To make the description of the present invention more detailed and complete, various aspects of the embodiments are described below in an illustrative manner, but this does not limit the embodiments of the present invention to only one form. Embodiments of the present invention may be combined with or substituted for each other where advantageous, and other embodiments may be added without further explanation.

[0025] Furthermore, in this invention, spatial relative terms, such as below and above, may be used to describe the relationship between one element (or feature) and another element (or feature) in the figures. In addition to the directions depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. For example, the device may be oriented in other ways (e.g., rotated 90 degrees) and can be interpreted accordingly using spatial relative terms. In this invention, unless otherwise stated, the same element symbols in different figures refer to the same or similar elements formed from the same or similar materials by the same or similar methods.

[0026] The terms “about,” “approximately,” “approximately,” “substantially,” and “truly” used in this invention include, as understood by those skilled in the art, the values ​​(or characteristics) and deviations thereof. For example, taking into account errors in values ​​(or characteristics), these terms may indicate values ​​within one or more standard deviations (e.g., values ​​within ±30%, ±20%, ±15%, ±10%, or ±5%), or they may indicate deviations included in practical operation of the characteristic (e.g., “truly parallel” may indicate that practical operation is close to parallel, rather than ideally perfect parallel). Furthermore, an acceptable range of deviation may be selected based on the nature or other properties of the measurement, rather than applying only one range of deviation to all values ​​(or characteristics).

[0027] This invention provides a method 100 for forming a semiconductor structure, such as... Figure 1 As shown. The semiconductor structure includes stacked layers that serve as an etching mask, which can be applied to any suitable element in the semiconductor structure, thus enabling a more precise semiconductor etching process to form an improved semiconductor structure. Figures 2 to 3This is a cross-sectional schematic diagram showing the structural changes when using method 100. Method 100 includes operations 101 to 103. Operation 101 includes forming a diamond-like carbon hard mask layer 201 on a substrate 301, wherein the absorbance of the diamond-like carbon hard mask layer 201 is less than or equal to 0.5. Operation 102 includes forming a dielectric anti-reflective coating 202 on the diamond-like carbon hard mask layer 201. Operation 103 includes forming a bottom anti-reflective coating 203 on the dielectric anti-reflective coating 202. The diamond-like carbon hard mask layer 201, the dielectric anti-reflective coating 202, and the bottom anti-reflective coating 203 together serve as an improved etching mask on the substrate 301, enabling higher etching quality to be obtained by etching the substrate 301. For example, the etched pattern can have a higher aspect ratio, and the damage and wobbling of the etched pattern can be reduced, thereby improving the performance of the substrate 301 after etching. Next, the method 100 will be described in detail through the embodiments provided by the present invention.

[0028] In some embodiments, substrate 301 is configured to be etched by any suitable subsequent operation. In some embodiments, examples of substrate 301 may be as follows: Figure 5 As shown, for example, it includes a first electrode 507 disposed in an oxide layer and supported by a nitride layer. Figure 5 Details will be provided in the description below, and please refer to the following text. However, the present invention does not limit the substrate 301 as follows: Figure 5 As shown, the etching mask of the present invention can be applied to any suitable element in a semiconductor structure. In some embodiments, substrate 301 is a semiconductor substrate and may include semiconductor materials. In some embodiments, semiconductor materials include elemental semiconductor materials, such as carbon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, tin, sulfur, selenium, tellurium, etc.; compound semiconductor materials, such as silicon carbide, boron nitride, aluminum nitride, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, etc.; alloy semiconductor materials, such as SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, etc.; or combinations thereof.

[0029] When a diamond-like carbon hard mask layer 201 is used as a hard mask for etching, the diamond-like carbon hard mask layer 201 has a diamond-like structure to improve its hardness. Furthermore, the light absorption of the diamond-like carbon hard mask layer 201 is preferably less than or equal to 0.5, for example, 0.3 to 0.5, such as 0.3, 0.35, 0.4, 0.45, or 0.5, to avoid excessive light absorption by the diamond-like carbon hard mask layer 201, preventing it from being reflected back. Therefore, when the diamond-like carbon hard mask layer 201 is used to etch the substrate 301, the correct etching location can be found by utilizing light irradiation and reflection from the semiconductor structure. Figure 5 For example, after light is irradiated onto the first electrode 507 and the second oxide layer 505, the light reflected from the first electrode 507 and the second oxide layer 505 (e.g., angle and / or intensity) may be different. Therefore, the correct etching location can be found to etch the second oxide layer 505 without damaging the first electrode 507 and / or causing the first electrode 507 to bend after etching. In some embodiments, the transmittance of the diamond-like carbon hard mask layer 201 is preferably greater than or equal to 0.5, for example, 0.5 to 0.7, such as 0.5, 0.55, 0.6, 0.65, or 0.7, to avoid excessive light absorption by the diamond-like carbon hard mask layer 201, preventing it from being reflected back out. In some embodiments, the refractive index of the diamond-like carbon hard mask layer 201 is preferably between 1.80 and 2.00, such as 1.80, 1.85, 1.90, 1.95, or 2.00, to improve the accuracy of finding the correct etching location by providing suitable light refraction. In some embodiments, absorbance, transmittance, and refractive index are measured using light at wavelengths from 230 nm to 260 nm, such as 230 nm, 240 nm, 250 nm, or 260 nm.

[0030] In some embodiments, the diamond-like carbon hard masking layer 201 comprises amorphous carbon. In some embodiments, in the carbon-carbon bonds of the diamond-like carbon hard masking layer 201, sp 3The content of the hybrid orbitals is preferably 25% to 29%, such as 25%, 26%, 27%, 28%, or 29%, to give the diamond-like carbon hard mask layer 201 sufficiently high hardness and low stress, thereby ensuring that the etched pattern is transferred more precisely according to the expected shape and size, and ensuring that the structure is not easily bent when using the diamond-like carbon hard mask layer 201 as an etching hard mask. In some embodiments, the stress of the diamond-like carbon hard mask layer 201 is preferably -750 MPa to -350 MPa, such as -750 MPa, -650 MPa, -550 MPa, -450 MPa, or -350 MPa, to avoid the hardness of the diamond-like carbon hard mask layer 201 being correspondingly reduced due to excessively low stress, and to avoid excessively high stress. In some embodiments, the diamond-like carbon hard mask layer 201 is different from the Kodiak carbon hard mask. In some embodiments, the thickness 201T of the diamond-like carbon hard masking layer 201 can be reduced to save costs because the diamond-like carbon hard masking layer 201 is sufficiently hard and absorbs less light. For example, the thickness 201T of the diamond-like carbon hard masking layer 201 is preferably less than or equal to 150 nm, for example, from 50 nm to 150 nm, such as 50 nm, 70 nm, 90 nm, 110 nm, 130 nm or 150 nm.

[0031] In some embodiments, the etch selectivity of the oxide material relative to the diamond-like carbon hard mask layer 201 (i.e., the ratio of the etch rate of the oxide material to the etch rate of the diamond-like carbon hard mask layer 201) is preferably 15:1 to 25:1, for example 15:1, 17.5:1, 20:1, 22.5:1, or 25:1, to ensure that the diamond-like carbon hard mask layer 201 is more etch-resistant than the oxide material, so that it can act as an etch hard mask and etch the oxide material with higher etch quality. In some embodiments, the oxide material includes oxide layers commonly used in various semiconductor processes, such as silicon oxide, tetraethoxysilane, borosilicate glass, or combinations thereof.

[0032] In some embodiments, during operation 101, a diamond-like carbon hard masking layer 201 is formed using plasma, such as plasma-enhanced chemical vapor deposition. In some embodiments, forming the diamond-like carbon hard masking layer 201 includes using C2H2 as a precursor and using an inert gas as a carrier and / or increasing collisions with C2H2 to enhance the dissociation of C2H2. In some embodiments, the inert gas includes He, Ar, or combinations thereof. In some embodiments, the ratio of C2H2 flow rate to inert gas flow rate is preferably 1:20 to 1:50, for example, 1:20, 1:30, 1:40, or 1:50. If the C2H2 flow rate is too high or too low, the desired diamond-like carbon hard masking layer 201 may not be successfully formed. If the inert gas flow rate is too high or too low, the collisions with C2H2 may be too strong or too weak, thus affecting the final formation of the diamond-like carbon hard masking layer 201 and / or reducing the efficiency of forming the diamond-like carbon hard masking layer 201. In some implementations, the flow rate of C2H2 is preferably 290 SCCM to 390 SCCM, such as 290 SCCM, 310 SCCM, 330 SCCM, 350 SCCM, 370 SCCM or 390 SCCM.

[0033] In some embodiments, plasma formed from C2H2 and / or inert gases is generated using both low-frequency and high-frequency electromagnetic waves. In some embodiments, the high frequency is greater than the low frequency. In some embodiments, the low frequency is preferably from 30 Hz to 300 kHz, such as 30 Hz, 100 Hz, 500 Hz, 1000 Hz, 5000 Hz, 10000 Hz, 50000 Hz, 100000 Hz, 200000 Hz, or 300000 Hz. In some embodiments, the high frequency is preferably from 3 MHz to 30 MHz, such as 3 MHz, 10 MHz, 15 MHz, 20 MHz, 25 MHz, or 30 MHz. In some embodiments, the high frequency includes radio frequencies. In some embodiments, the power used to generate the low frequency is preferably from 1500 W to 3000 W, such as 1500 W, 1750 W, 2250 W, 2500 W, 2750 W, or 3000 W. In some implementations, the power that generates the high frequency is preferably between 100W and 800W, such as 100W, 250W, 500W, 650W, or 800W.

[0034] In some embodiments, the formation of the diamond-like carbon hard masking layer 201 is preferably performed at a pressure of 1.3 Torr to 3.1 Torr, such as 1.3 Torr, 2.0 Torr, 2.5 Torr, or 3.1 Torr. In some embodiments, the formation of the diamond-like carbon hard masking layer 201 is preferably performed at a temperature of 150°C to 400°C, such as 150°C, 200°C, 250°C, 300°C, 350°C, or 400°C.

[0035] In operation 102, forming the dielectric antireflective coating 202 includes performing the process by any suitable method, such as chemical vapor deposition or physical vapor deposition. In some embodiments, the dielectric antireflective coating 202 is an oxygen-rich dielectric antireflective coating to reduce the absorbance of the dielectric antireflective coating 202 relative to the absorbance of a silicon-rich dielectric antireflective coating. In some embodiments, in the oxygen-rich dielectric antireflective coating, the atomic ratio of oxygen is greater than the atomic ratio of silicon. In some embodiments, the atomic ratio of silicon in the oxygen-rich dielectric antireflective coating is preferably less than 50%. In some embodiments, the dielectric antireflective coating 202 comprises silicon oxynitride. In some embodiments, the thickness 202T of the dielectric antireflective coating 202 is preferably 25 nm to 45 nm, for example, 25 nm, 35 nm, or 45 nm.

[0036] In operation 103, forming the bottom antireflective coating 203 is performed by any suitable method, such as chemical vapor deposition or physical vapor deposition. In some embodiments, the bottom antireflective coating 203 comprises an organic material. In some embodiments, the refractive index of the bottom antireflective coating 203 is similar to or the same as that of the dielectric antireflective coating 202 to reduce light reflection during photolithography of a photoresist layer (e.g., photoresist layer 508 described below) that may be disposed on the bottom antireflective coating 203. In some embodiments, the thickness 203T of the bottom antireflective coating 203 is preferably from 1 nm to 10 nm, for example, 1 nm, 2.5 nm, 5 nm, 7.5 nm, or 10 nm.

[0037] The present invention also provides a method 400 for forming a semiconductor structure, such as... Figure 4 As shown. Method 400 uses an amorphous carbon hard mask layer (e.g., the diamond-like carbon hard mask layer 201 described above) as an etching hard mask to etch the surface disposed beneath the amorphous carbon hard mask layer, such as... Figure 5 The components shown, and Figures 5 to 10 This is a schematic diagram illustrating the structural changes when using method 400. Method 400 includes operations 401 to 403. Operation 401 includes forming an amorphous carbon hard mask layer 201' on a plurality of first electrodes 507 of a plurality of capacitors on a substrate 501, wherein the absorbance of the amorphous carbon hard mask layer 201' is less than or equal to 0.5. Operation 402 includes forming a photoresist layer 508 having an opening 508O on the amorphous carbon hard mask layer 201'. Operation 403 includes etching the amorphous carbon hard mask layer 201' through the opening 508O of the photoresist layer 508. Next, method 400 will be described in detail through embodiments provided by the present invention.

[0038] exist Figure 5In operation 401, an amorphous carbon hard masking layer 201' is formed on the first electrode 507 of a capacitor on a substrate 501. In some embodiments, the amorphous carbon hard masking layer 201' is the diamond-like carbon hard masking layer 201 described above, and therefore the material, absorbance, transmittance, refractive index, and sp... 3 Details regarding the content, stress, thickness 201'T, and formation method of the hybrid orbitals may not be elaborated here, but can be found in the description above. In some embodiments, the substrate 501, the first nitride layer 502, the first oxide layer 503, the second nitride layer 504, the second oxide layer 505, the third nitride layer 506, and the first electrode 507 are disposed below the amorphous carbon hard mask layer 201', such that the amorphous carbon hard mask layer 201' can be used as an etch hard mask to etch portions of the third nitride layer 506 and further etch the second oxide layer 505, the second nitride layer 504, and the first oxide layer 503 in subsequent operations, thereby exposing multiple surfaces of the first electrode 507. Once the surfaces of the first electrode 507 are exposed, multiple dielectric layers 509 and multiple second electrodes 510 can be formed on the first electrode 507 to form a capacitor. In some embodiments, substrate 501, first nitride layer 502, first oxide layer 503, second nitride layer 504, second oxide layer 505, third nitride layer 506 and first electrode 507 may be used together as substrate 301 as described above.

[0039] In some embodiments, substrate 501 includes a semiconductor material. In some embodiments, the semiconductor material includes elemental semiconductor materials, such as carbon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, tin, sulfur, selenium, tellurium, etc.; compound semiconductor materials, such as silicon carbide, boron nitride, aluminum nitride, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, etc.; alloy semiconductor materials, such as SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, etc.; or combinations thereof. In some embodiments, substrate 501 includes a metal, such as tungsten.

[0040] In some embodiments, a first electrode 507 is disposed on a substrate 501. In some embodiments, the first electrode 507 extends along a direction perpendicular to the surface of the substrate 501 to increase the aspect ratio and / or integration density of the capacitors on the substrate 501. In some embodiments, the height 507H of each of the first electrodes 507 (or each of the capacitors) is preferably 850 nm to 1250 nm, for example, 850 nm, 950 nm, 1050 nm, 1150 nm, or 1250 nm. In some embodiments, the first electrodes 507 are formed in a two-dimensional array on the substrate 501. In some embodiments, one of the first electrodes 507 (or one of the capacitors) is separated from the other of the first electrodes 507 (or the other of the capacitors) to prevent current leakage. In some embodiments, the first electrode 507 comprises a metal. In some embodiments, the first electrode 507 comprises TiSiN.

[0041] In some embodiments, the first nitride layer 502, the second nitride layer 504, and the third nitride layer 506 are respectively disposed around the bottom, middle, and top of the first electrode 507 to provide structural support for the first electrode 507. In some embodiments, the first nitride layer 502, the second nitride layer 504, and the third nitride layer 506 are silicon nitride. In some embodiments, the thickness 502T of the first nitride layer 502, the thickness 504T of the second nitride layer 504, and the thickness 506T of the third nitride layer 506 are preferably from 10 nm to 100 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 60 nm, 80 nm, or 100 nm.

[0042] In some embodiments, the first oxide layer 503 and the second oxide layer 505 serve as mold layers for forming the first electrode 507, and the first oxide layer 503 and the second oxide layer 505 are removed in subsequent operations to expose the surface of the first electrode 507 to form the dielectric layer 509 and the second electrode 510. In some embodiments, although Figure 5A cross-sectional view is not shown, but the first oxide layer 503 and the second oxide layer 505 extend continuously between the first electrodes 507. Therefore, the entire first oxide layer 503 and the entire second oxide layer 505 can be removed by removing only a portion of the first oxide layer 503 and a portion of the second oxide layer 505, for example, by a wet etching process. In some embodiments, the first oxide layer 503 is disposed between the first nitride layer 502 and the second nitride layer 504, and the second oxide layer 505 is disposed between the second nitride layer 504 and the third nitride layer 506. In some embodiments, the first oxide layer 503 and the second oxide layer 505 comprise silicon oxide, tetraethoxysilane, borosilicate glass, or combinations thereof.

[0043] In some embodiments, prior to performing operation 402, method 400 may further include forming a dielectric antireflective coating 202 on the amorphous carbon hard mask layer 201' and forming a bottom antireflective coating 203 on the dielectric antireflective coating 202 to improve the accuracy of photolithography on the photoresist layer 508 described below, thereby improving the accuracy of etching components disposed beneath the amorphous carbon hard mask layer 201'. Details of the dielectric antireflective coating 202 and the bottom antireflective coating 203 may not be repeated here, but can be found in the description above.

[0044] exist Figure 5 In operation 402, a photoresist layer 508 with an opening 508O is formed on an amorphous carbon hard mask layer 201'. The opening 508O defines the location of the etching. In some embodiments, the opening 508O is disposed above a portion of the second oxide layer 505 between two adjacent first electrodes 507. In some embodiments, method 400 may further include forming the opening 508O of the photoresist layer 508 by any suitable photolithography method. In some embodiments, before or between forming the opening 508O of the photoresist layer 508, method 400 may further include using light to illuminate the elements below the photoresist layer 508 and determining the position of the first electrode 507 from the reflected light, such that when forming the opening 508O of the photoresist layer 508, the opening 508O can be aligned with the position between two adjacent first electrodes 507. Since the element disposed beneath the photoresist layer 508 includes an amorphous carbon hard mask layer 201' with low light absorption, light illuminating and reflected from the amorphous carbon hard mask layer 201' can be measured, thus allowing the correct etching location to be found. In some embodiments, the number of openings 508O in the photoresist layer 508 is not limited. In some embodiments, the thickness 508T of the photoresist layer 508 is preferably 80 nm to 120 nm, for example, 80 nm, 90 nm, 100 nm, 110 nm, or 120 nm.

[0045] exist Figure 6 In operation 403, an amorphous carbon hard mask layer 201' is etched through the opening 508O of the photoresist layer 508. In some embodiments, the etching of the amorphous carbon hard mask layer 201' continues until the second oxide layer 505 is exposed. In some embodiments, the etching includes transferring the pattern of the opening 508O of the photoresist layer 508 into the amorphous carbon hard mask layer 201' and further into the third nitride layer 506, such that a portion of the third nitride layer 506 can be etched to form the opening 506O of the third nitride layer 506, as shown. Figure 6 As shown. In some embodiments, the width of the opening 508O of the photoresist layer 508 is substantially equal to the width of the opening 506O of the third nitride layer 506. In some embodiments, when the second oxide layer 505 is exposed by the opening 506O of the third nitride layer 506, components disposed above the third nitride layer 506, such as components including the amorphous carbon hard mask layer 201', may have been completely etched. In some embodiments, if components disposed above the third nitride layer 506 (such as components including the amorphous carbon hard mask layer 201') are not completely etched after the formation of the opening 506O of the third nitride layer exposing the second oxide layer 505, the method 400 may further include removing components disposed above the third nitride layer 506, such as removing the amorphous carbon hard mask layer 201'. In some embodiments, etching is preferably performed by anisotropic dry etching.

[0046] exist Figure 7 In this method 400, the second oxide layer 505 may be etched through an opening 506O in the third nitride layer 506. After etching the second oxide layer 505, an opening 505O is formed between the first electrodes 507 to expose the surfaces of the first electrodes 507 and the second nitride layer 504. In some embodiments, the second oxide layer 505 is etched by wet etching. In some embodiments, wet etching includes using an etchant comprising diluted HF.

[0047] exist Figure 8 In this method 400, the process may further include etching a portion of the second nitride layer 504 through an opening 506O in the third nitride layer 506 after etching the second oxide layer 505 to expose the second nitride layer 504. After etching the portion of the second nitride layer 504, an opening 504O is formed in the second nitride layer 504 to expose the first oxide layer 503. In some embodiments, the etching is preferably performed by anisotropic dry etching.

[0048] exist Figure 9In this method 400, the etching may further include etching the first oxide layer 503 through an opening 504O in the second nitride layer 504. After etching the first oxide layer 503, an opening 503O is formed between the first electrodes 507 to expose the surfaces of the first electrodes 507. In some embodiments, the first oxide layer 503 is etched by wet etching. In some embodiments, wet etching includes using an etchant comprising diluted HF.

[0049] exist Figure 10 In this method 400, the process may further include forming a dielectric layer 509 and a second electrode 510 on the exposed surface of the first electrode 507 to form a capacitor, wherein the dielectric layer 509 is disposed between the first electrode 507 and the second electrode 510. In some embodiments, the formation of the dielectric layer 509 and the second electrode 510 may be performed by any suitable method, such as chemical vapor deposition or physical vapor deposition. In some embodiments, the dielectric layer 509 comprises any suitable dielectric material used in a capacitor, and the second electrode 510 comprises any suitable electrode material used in a capacitor.

[0050] Figure 11 Provides etching using Kodiak carbon hard mask 601 as... Figure 5The same structure is shown in Comparative Embodiment 1. Due to the high absorbance of the Kodiak carbon hard mask 601, when the photoresist layer 508 is formed on the Kodiak carbon hard mask 601 to perform the operations described above to etch the structure disposed beneath the Kodiak carbon hard mask 601, it is difficult to ensure that the openings of the photoresist layer 508 are formed in the correct positions by illuminating the structure with light and measuring the reflected light. Therefore, openings 508O' may be formed in incorrect positions on the photoresist layer 508, for example, openings 508O' may be located above or too close to the first electrode 507, thereby damaging the first electrode 507 and / or causing the first electrode 507 to bend after etching. Another disadvantage of the Kodiak carbon hard mask 601 is that its thickness 601T is large when etching structures including capacitors with high aspect ratios (or structures including first electrodes 507 with high heights). For example, the thickness 601T of the Kodiak carbon hard mask 601 may be at least 200 nm. Furthermore, when positioned beneath the photoresist layer 508, the Kodiak carbon hard mask 601 is typically used in conjunction with a silicon-rich dielectric antireflective coating 602, a carbon-rich organic layer 603, and a silicon-rich organic layer 604. However, the absorbance of the silicon-rich dielectric antireflective coating 602 is greater than that of the oxygen-rich dielectric antireflective coating, and therefore, the silicon-rich dielectric antireflective coating 602 may be less effective than the oxygen-rich dielectric antireflective coating (e.g., dielectric antireflective coating 202) in finding the correct etching location using light. Furthermore, the thickness 602T of the silicon-rich dielectric antireflective coating 602 is at least 75 nm, the thickness 603T of the carbon-rich organic layer 603 is at least 200 nm, and the thickness 604T of the silicon-rich organic layer 604 is at least 32 nm. This results in the total thickness of the Kodiak carbon hard mask 601, the silicon-rich dielectric antireflective coating 602, the carbon-rich organic layer 603, and the silicon-rich organic layer 604 being significantly greater than the total thickness of the diamond-like carbon hard mask layer 201 (or the amorphous carbon hard mask layer 201'), the dielectric antireflective coating 202, and the bottom antireflective coating 203. Besides increasing costs, having a larger thickness and more layers as an etching mask may also reduce etching precision, especially when the pattern to be etched needs a higher aspect ratio.

[0051] Table 1 summarizes the comparison between the formation of the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201') in Embodiment 1 and the formation of the Kodiak carbon hard mask 601 in Comparative Embodiment 1. Table 2 summarizes the comparison of the features and properties of Embodiment 1 and Comparative Embodiment 1. The methods for forming the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201') and the Kodiak carbon hard mask 601 are very different, as shown in Table 1, resulting in different features and properties of the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201') and the Kodiak carbon hard mask 601. Although the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201') and the Kodiak carbon hard mask 601 may have lower stress to avoid pattern bending during etching and greater etching selectivity relative to oxide materials, the Kodiak carbon hard mask 601 has too much absorbance and too low a refractive index, thus affecting its ability to use light to find the correct etching location. In addition to the greater difficulty in finding the correct etching location, the uniformity of etching is also affected. For example, the three standard deviations (3σ) of the etching depth obtained using the Kodiak carbon hard mask 601 are greater than those obtained using the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201').

[0052] Table 1

[0053]

[0054] Table 2

[0055]

[0056] Table 3 summarizes the comparison between the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201') formed in Embodiment 1 and a similar but different layer formed in Comparative Embodiment 2. As long as the formation method differs from the method provided by this invention for forming the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201'), the characteristics of the formed layer and the diamond-like carbon hard mask layer 201 (or amorphous carbon hard mask layer 201') may differ significantly, as shown in Table 4. For example, the stress in the layer formed in Comparative Embodiment 2 is too high, which may cause the etched pattern to be easily bent. The absorbance and refractive index of the layer formed in Comparative Embodiment 2 are also too high and too low, respectively, thus affecting its ability to use light to find the correct etching position when used as an etching mask.

[0057] Table 3

[0058]

[0059] Table 4

[0060]

[0061] This invention provides a method for forming an improved semiconductor structure using an improved etch hard mask. For example, the etch hard mask has low light absorption, so when using light to locate the correct etching position below the etch hard mask, the light illuminating and reflected from it is not absorbed by the etch hard mask significantly. Therefore, an opening can be formed at the correct position in a photoresist layer disposed on the etch hard mask to align with the correct etching position. Furthermore, due to the low light absorption of the etch hard mask, the etching position can be adjusted using light throughout the etching process. Finding the correct etching position improves etching uniformity, avoids damage to the semiconductor structure, prevents etch pattern bending, and is particularly advantageous for etching with higher aspect ratios.

[0062] This invention has been described in considerable detail through some embodiments, but other embodiments may also be feasible. Therefore, the description of the embodiments is not intended to limit the scope and spirit of the appended claims. Those skilled in the art will be able to make modifications and alterations to this invention without departing from its scope and spirit. Such modifications and alterations are included in this invention when they fall within the scope and spirit of the appended claims.

[0063] [Symbol Explanation]

[0064] 100: Method

[0065] 101: Operation

[0066] 102: Operation

[0067] 103: Operation

[0068] 201: Diamond-like carbon hard masking layer

[0069] 201T: Thickness

[0070] 201': Amorphous carbon hard masking layer

[0071] 201'T: Thickness

[0072] 202: Dielectric anti-reflective coating

[0073] 202T: Thickness

[0074] 203: Bottom anti-reflective coating

[0075] 203T: Thickness

[0076] 301: Substrate

[0077] 400: Method

[0078] 401: Operation

[0079] 402: Operation

[0080] 403: Operation

[0081] 501: Substrate

[0082] 502: First nitride layer

[0083] 502T: Thickness

[0084] 503: First oxide layer

[0085] 503O: Opening

[0086] 504: Second nitride layer

[0087] 504O: Open

[0088] 504T: Thickness

[0089] 505: Second oxide layer

[0090] 505O: Open

[0091] 506: Third nitride layer

[0092] 506O: Opening

[0093] 506T: Thickness

[0094] 507: First electrode

[0095] 507H: Altitude

[0096] 508: Photoresist layer

[0097] 508O: Opening

[0098] 508O': Open

[0099] 508T: Thickness

[0100] 509: Dielectric layer

[0101] 510: Second electrode

[0102] 601: Kodiak carbon hard mask

[0103] 601T: Thickness

[0104] 602: Silicon-rich dielectric antireflective coating

[0105] 602T: Thickness

[0106] 603: Carbon-rich organic layer

[0107] 603T: Thickness

[0108] 604: Silicon-rich organic layer

[0109] 604T: Thickness.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A diamond-like carbon hard masking layer is formed on a substrate, wherein the absorbance of the diamond-like carbon hard masking layer is less than or equal to 0.

5. A dielectric antireflective coating is formed on the diamond-like carbon hard mask layer; as well as A bottom anti-reflective coating is formed on the dielectric anti-reflective coating.

2. The method of claim 1, wherein forming the diamond-like carbon hard mask layer comprises: Provide C2H2 and an inert gas; and react the C2H2 to form the diamond-like carbon hard masking layer.

3. The method according to claim 2, wherein the ratio of the flow rate of C2H2 to the flow rate of the inert gas is 1:20 to 1:

50.

4. The method according to claim 2, wherein the flow rate of C2H2 is 290 SCCM to 390 SCCM.

5. The method of claim 1, wherein the formation of the diamond-like carbon hard mask layer is performed under a pressure of 1.3 Torr to 3.1 Torr.

6. The method of claim 1, wherein the formation of the diamond-like carbon hard mask layer is performed at a temperature of 150°C to 400°C.

7. The method according to claim 1, wherein the stress of the diamond-like carbon hard masking layer is from -750 MPa to -350 MPa.

8. The method according to claim 1, wherein the thickness of the diamond-like carbon hard mask layer is less than or equal to 150 nm.

9. The method of claim 1, wherein the etch selectivity of the oxide material relative to the diamond-like carbon hard mask layer is 15:1 to 25:

1.

10. A method for forming a semiconductor structure, characterized in that, include: An amorphous carbon hard masking layer is formed on a plurality of first electrodes of a plurality of capacitors on a substrate, wherein the absorbance of the amorphous carbon hard masking layer is less than or equal to 0.5, and an oxide layer is disposed between the plurality of first electrodes. A photoresist layer with openings is formed on the amorphous carbon hard mask layer; as well as The amorphous carbon hard mask layer is etched through the opening in the photoresist layer.

11. The method of claim 10, wherein etching the amorphous carbon hard mask layer is performed to expose the oxide layer disposed between the plurality of first electrodes of the plurality of capacitors, and the method further comprises etching the oxide layer and forming a plurality of dielectric layers and a plurality of second electrodes on the plurality of first electrodes.

12. The method according to claim 10, wherein, Also includes: Before or between the formation of the photoresist layer having the opening on the amorphous carbon hard mask layer, light is irradiated onto the amorphous carbon hard mask layer and reflected from the amorphous carbon mask layer to determine multiple positions of the plurality of first electrodes, so as to align the opening of the photoresist layer with the position between two of the plurality of first electrodes.

13. The method of claim 10, wherein etching the amorphous carbon hard mask layer comprises using anisotropic dry etching.

14. The method of claim 10, wherein the stress of the amorphous carbon hard masking layer is from -750 MPa to -350 MPa.

15. The method of claim 10, wherein the thickness of the amorphous carbon hard mask layer is less than or equal to 150 nm.

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