Packet tracking processing methods, devices, switches, and storage media

Abstract

This application discloses a data packet tracking and processing method, apparatus, switch, and storage medium. The method includes: during the forwarding process of a data packet entering a switching chip, the switching chip records the trajectory information of the data packet within the switching chip; the switching chip adds the trajectory information of the data packet as supplementary data to the data packet, wherein the supplementary data is forwarded by the switching chip along with the data packet; the switching chip sends data packets to be sent to a processor according to pre-configured rules, wherein the data packets sent to the processor carry the supplementary data. This application solves the problem in the prior art that programmable switching chips cannot be debugged and fault located, resulting in low fault diagnosis efficiency. It provides data support for the debugging and fault location of programmable switching chips, and improves the fault diagnosis efficiency to a certain extent.

Description

Technical Field

[0001] This application relates to the field of packet processing, and more specifically, to packet tracking processing methods, apparatus, switches, and storage media. Background Technology

[0002] A programmable switching ASIC (ASIC) is a switch chip that improves processing power by allowing software-based network applications, originally dependent on a processor (CPU), to be ported (or offloaded) to the switch chip hardware through programming. In a programmable switching ASIC, packet processing logic can be customized using a dedicated programming language. A programmable switch is a switch equipped with a programmable switching ASIC, using the programmable switching ASIC and CPU as the core of packet processing. The two can be connected via a high-speed serial computer expansion bus standard (PCIe) bus, network interface card (NIC), etc.

[0003] With the development of programmable switch technology, more and more packet processing operations (i.e., processing packets according to processing logic, also known as packet processing logic) are offloaded to programmable switching chips. This leverages the high throughput and programmability of the switching chips to provide a higher-performance implementation for processing packets according to specific logic. However, due to the limitations of programmable switching chip programming capabilities, the packet processing logic running within the chip cannot output traditional logs and debugging information. When maintenance personnel suspect a defect in the chip's packet processing logic, they cannot perform debugging and fault location, increasing the time and manpower costs of troubleshooting. Summary of the Invention

[0004] This application provides a data packet tracing processing method, apparatus, switch, and storage medium to at least solve the problem in the prior art that programmable switching chips cannot be debugged and fault located, resulting in low fault diagnosis efficiency.

[0005] According to one aspect of this application, a data packet tracking processing method is provided, comprising: during the forwarding process of a data packet entering a switching chip, the switching chip records trajectory information of the data packet within the switching chip; the switching chip adds the trajectory information of the data packet as additional data to the data packet, wherein the additional data is forwarded by the switching chip along with the data packet; the switching chip sends data packets to be sent to a processor according to pre-configured rules, wherein the data packets sent to the processor carry the additional data, and both the switching chip and the processor are located within a switch.

[0006] According to another aspect of this application, a packet tracking processing method is also provided, comprising: a processor sending pre-configured rules to a switching chip, wherein the switching chip records trajectory information of a packet within the switching chip and adds the trajectory information of the packet as additional data to the packet, the additional data being forwarded by the switching chip along with the packet; the processor receiving a packet sent by the switching chip according to the rules, wherein the packet sent to the processor carries the additional data, and both the switching chip and the processor are located within a switch.

[0007] According to another aspect of this application, a packet tracking processing apparatus is provided, located in a switching chip, comprising:

[0008] A recording module is used to record the trajectory information of the data packet within the switching chip during the forwarding process of the data packet entering the switching chip; an append module is used to add the trajectory information of the data packet as append data to the data packet, wherein the append data is forwarded by the switching chip along with the data packet; a first sending module is used to send the data packet to be sent to the processor according to pre-configured rules, wherein the data packet sent to the processor carries the append data, and both the switching chip and the processor are located within the switch.

[0009] According to another aspect of this application, a packet tracking and processing apparatus is also provided, located in a processor, comprising: a second sending module for sending pre-configured rules to a switching chip, wherein the switching chip records trajectory information of the data packet within the switching chip and adds the trajectory information of the data packet as additional data to the data packet, the additional data being forwarded by the switching chip along with the data packet; and a receiving module for receiving data packets sent by the switching chip according to the rules, wherein the data packets sent to the processor carry the additional data, and both the switching chip and the processor are located within a switch.

[0010] According to another aspect of this application, a switch is also provided, including a switching chip and a processor; wherein the switching chip is used to perform the method steps described above, and the processor is used to perform the method steps described above.

[0011] According to another aspect of this application, a readable storage medium is also provided, on which computer instructions are stored, wherein the computer instructions, when executed by a processor, implement the above-described method steps.

[0012] In this embodiment, during the forwarding process of a data packet entering the switching chip, the switching chip records the trajectory information of the data packet within the switching chip. The switching chip adds the trajectory information of the data packet as supplementary data to the data packet, wherein the supplementary data is forwarded along with the data packet by the switching chip. The switching chip sends the data packets to be sent to the processor according to pre-configured rules, wherein the data packets sent to the processor carry the supplementary data. Both the switching chip and the processor are located within the switch. This application solves the problem of low fault diagnosis efficiency in the prior art due to the inability to debug and locate faults in programmable switching chips, and provides data support for the debugging and fault diagnosis of programmable switching chips, thereby improving the fault diagnosis efficiency to a certain extent. Attached Figure Description

[0013] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0014] Figure 1 This is a flowchart of the data packet tracing processing method according to an embodiment of this application. Figure 1 ;

[0015] Figure 2 This is a schematic diagram illustrating the transmission of data packets to the processing method via a pipeline according to an embodiment of this application;

[0016] Figure 3 This is a flowchart of the data packet tracing processing method according to an embodiment of this application. Figure 2 ;

[0017] Figure 4 This is a schematic diagram of a system including a storage server and a management server according to an embodiment of this application;

[0018] Figure 5 This is a schematic diagram of the structure of an on-chip information acquisition module according to an embodiment of this application; and,

[0019] Figure 6This is a schematic diagram of the reporting header format according to an embodiment of this application. Detailed Implementation

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0022] In related technologies, standard network events, such as packet loss due to congestion, can be reported. However, this method of reporting standard network events cannot cover all scenarios in programmable network environments. This is because, in programmable network environments, programming defects may cause switching chips to exhibit unexpected behaviors, which are not considered standard network events and therefore cannot be reported. Furthermore, some packet processing logic is offloaded to the switching chip, and related events cannot be reported when this part of the processing logic is executed. Another tracing method in related technologies can be used for packet tracing within the network, reporting the path at the device level, i.e., which switches the packet passed through within the network; however, it cannot trace the path of the packet within the switch, i.e., it cannot report which processing logic the packet passed through within each switching chip. Therefore, for programmable switching chips, once a fault occurs due to packet processing logic, the efficiency of locating and troubleshooting is relatively low.

[0023] To address this issue, a packet tracing processing method is provided in the following embodiments. Figure 1 This is a flowchart of the data packet tracing processing method according to an embodiment of this application. Figure 1 ,like Figure 1 As shown below, Figure 1 The methods and steps included are explained.

[0024] Step S102: During the process of the data packet entering the switching chip for forwarding, the switching chip records the trajectory information of the data packet within the switching chip.

[0025] In this step, the "trajectory" describes the processing steps a data packet has undergone. Therefore, trajectory information can include all the processing operations the data packet has experienced. Additionally, other information generated during these processing operations (such as the reason for packet loss when the packet is dropped) can also be recorded in the trajectory information. In other words, trajectory information can include various contents, such as the processing operations performed sequentially by the data packet within the programmable switching chip. If the processing operations are implemented by different modules, information for each module can be recorded. If different processing logics are set within the switching chip, each logic processes data packets according to a configured logical order, then the trajectory information can also include information for each processing logic, such as identification information, the processing operations included in that logic, and the reason for packet loss. Trajectory information can be configured as needed; configured information is recorded by the switching chip, while unconfigured information is not recorded. Of course, a default configuration can also be used, in which all information is recorded. The contents of the trajectory information and the contents that the switching chip needs to record can be flexibly configured as needed in practical applications.

[0026] In step S104, the switching chip adds the trajectory information of the data packet as additional data to the data packet, wherein the additional data is forwarded by the switching chip along with the data packet.

[0027] In step S106, the switching chip sends the data packets to be sent to the processor according to the pre-configured rules (the data packets sent to the processor are also referred to as information reporting packets below), wherein the data packets sent to the processor carry the additional data, and both the switching chip and the processor are located within the switch.

[0028] In the above steps, the switching chip can record trajectory information, which is directly added to the data packet and forwarded along with the data packet in the switching chip. Then, the switching chip sends the data packet carrying the trajectory information to the processor according to the corresponding rules. In this way, the processor can obtain the trajectory information of the problematic data packet. The trajectory information is used to trace the data packet to determine the path of the data packet in the switching chip, etc. This information can be used for debugging and fault location. Therefore, the above steps solve the problem that the existing technology cannot debug and locate programmable switching chips, resulting in low fault diagnosis efficiency. It provides data support for the debugging and fault location of programmable switching chips and improves the fault diagnosis efficiency to a certain extent.

[0029] In a switching chip, packet processing logic can be provided through pipelines. A pipeline refers to the logic executed as a packet passes through the switching chip. For example, a packet from switch interface 1 needs to undergo processing A and processing B. Processing A can be a pipeline A, and processing B can be a pipeline B. The packet then passes through pipelines A and B. Alternatively, processing A and B can be combined into a pipeline C, in which case the packet passes through pipeline C. In short, pipelines are used to process packets according to predetermined logic, and pipelines can be implemented using a hardware programming language. A pipeline can be divided into inbound and outbound directions, corresponding to the logic executed when a packet enters and leaves the current interface, respectively. In the following embodiments, pipelines refer to logical pipelines, and multiple logical pipelines can correspond to the same physical pipeline. When using pipelines to provide packet processing logic within the switching chip, the switching chip's recording of the trajectory information of the packet within the switching chip can include: the switching chip recording all pipelines the packet passes through within the switching chip.

[0030] A pipeline typically includes an inbound and an outbound direction. Data packets enter the pipeline from the inbound direction. In an optional embodiment, a buffer management unit (MMU) is added to the pipeline. This MMU can buffer data packets between the inbound and outbound directions. Furthermore, the MMU can forward the data packets to the outbound direction of the same pipeline or to another pipeline as needed. That is, after a data packet enters from the inbound direction of one pipeline, it may leave from the outbound direction of that pipeline, or it may enter another pipeline and leave from the outbound direction of that pipeline. Therefore, in this optional method, the switching chip records all the pipelines that the data packet passes through within the switching chip, including recording when the data packet passes through the inbound and outbound directions of each pipeline. This recording based on the inbound and outbound directions provides a detailed trajectory of the data packet, offering more detailed data for fault location and debugging.

[0031] When recording the pipeline path traversed by a data packet, a bitmap can be used. A bitmap uses each bit to store the state. For example, when recording the pipeline path of a data packet, each pipeline has an inbound and an outbound direction. Each pipeline requires two bits to record whether the data packet passed through that pipeline's inbound and outbound directions. It can be agreed that a bit value of 1 indicates that the data packet passed through the pipeline's inbound or outbound direction. If the switching chip supports a maximum of 16 pipelines, then 32 bits are needed to represent the inbound and outbound directions of the data packet. Using a bitmap clearly indicates all the pipelines the data packet passed through. Of course, other data structures can also be used to record the pipeline path. Regardless of the data structure used, as long as the data packet's path is recorded, the data packet's trajectory can be obtained, providing a data foundation for debugging and fault location.

[0032] When using a pipeline, a dedicated pipeline can be pre-configured to forward data packets to the processor. In this optional implementation, the switching chip sending the data packets to be sent to the processor may include the following steps: the switching chip sends the data packets to be sent to a predetermined pipeline, wherein the predetermined pipeline is pre-established; the switching chip sends the data packets to be sent to the processor through the predetermined pipeline. This predetermined pipeline is specifically designed to send the required data packets to the processor. Besides using a dedicated pipeline to send data packets to the processor, they can also be sent via multicast or digest. Digests are described below: for a piece of data, a one-way hash function is applied to generate a fixed-length hash value, which is the digest of the data. For data packets to be sent to the processor, a hash function can be used to generate a hash value, and then the data packet and / or digest are sent together to the processor. It should be noted that the hash value can be constructed by concatenating fields selected from the data packet and / or metadata, and does not necessarily involve cryptographic calculations.

[0033] Figure 2 This is a schematic diagram illustrating the transmission of data packets to the processing method via a pipeline according to an embodiment of this application, as shown below. Figure 2 As shown, in Figure 2 The configuration includes pipelines 1 through N, all of which are used for packet processing. Each pipeline can forward packets according to its processing logic. To distinguish them from pipelines 1 through N, in... Figure 2The pipeline used to send data packets to the processor is called pipeline X. Each pipeline can match data packets, forwarding or copying any packets that need to be sent to the processor and sending them to pipeline X. Then, pipeline X sends the received data packets to the processor. Alternatively, in another implementation, pipeline X can be omitted, and each pipeline can directly send data packets to the processor when needed. However, this approach lacks overall control over the data packets sent to the processor. Adding pipeline X allows for control over the number or rate of data packets sent to the processor.

[0034] For example, in an alternative implementation, the following function can be added: the switching chip determines the rate at which data packets are sent based on the processor's resource usage; the switching chip sends the required data packets according to the determined rate. After introducing pipeline X, the rate limiting function can be configured in the pipeline's MMU, controlling the rate at which data packets are sent to the processor. It should be noted that controlling the rate at which data packets are sent to the processor can be achieved by configuring pipeline X, or by other methods. For example, a buffer for storing data packets can be added between the switching chip and the processor, using this buffer to control the rate at which the switching chip sends data packets to the processor.

[0035] The switching chip can send data packets matching pre-configured rules to the processor. For example, for data packets discarded by the switching chip, it is generally desirable to obtain the reason for the packet's discarding. Therefore, a rule can be configured to instruct all discarded data packets to be sent to the processor. This rule can be a default rule, meaning it is executed by default when the switching chip starts running. Through this process, the switching chip can send all discarded data to the processor. When the switching chip sends discarded data packets, the reason for the discard can also be written into the additional data. That is, in this optional embodiment, the switching chip sending the data packets to be sent to the processor according to the pre-configured rules may include the following steps: the switching chip detects that a data packet has been discarded; the switching chip writes the reason for the data packet's discard into the additional data; the switching chip sends the discarded data packet to the processor. The additional data is appended to the data packet and forwarded as part of the data packet within the switching chip and between the switching chip and the processor. Therefore, after receiving a discarded data packet, the processor can obtain the reason for the data packet's discard through the additional data, thereby improving debugging and fault location.

[0036] In some cases, for debugging or fault location purposes, it is desirable to obtain data packets with specific attributes. For example, it may be desirable to obtain data packets sent from a predetermined source IP address. These data packets need to be forwarded within the switching chip, and also need to be sent to the processor for processing. Therefore, these types of data packets can be mirrored (also called copied), and the copied data packets can be sent to the processor. That is, in this optional embodiment, the switching chip sending the data packets to be sent to the processor according to pre-configured rules may include the following steps: the switching chip matches the data packets according to the attribute information of the data packets carried in the pre-configured rules; the switching chip copies the data packets whose attribute information is the same as the attribute information in the rules; the switching chip sends the copied data packets to the processor.

[0037] Data packet attributes can include various types of information. For example, network attributes can be used to identify network information such as the source and destination addresses of the data packet. These attributes may include the source network (IP) address, source port number, destination IP address, destination port number, and protocol type. The protocol type indicates the protocol used by the next packet header following this one. It can also include network attributes that identify the packet's priority: Type of Service (TOS). For ease of description, the source network (IP) address, source port number, destination IP address, destination port number, and protocol type will be referred to as the IP 5-tuple. Besides network attributes, the interface number through which the data packet enters the switching chip can also be used as attribute information. This attribute information allows for the replication of all data packets entering the switching chip from a specific interface. Data packet attributes can also include time attributes, such as the time the data packet entered the switching chip.

[0038] The attribute information of the aforementioned data packets can all be configured as rules. For example, the configured rules may include at least one of the following: source address range, source port range, destination address range, destination port range, protocol type, TOS, time range for entering the switching chip, and interface for entering the switching chip. When the attribute information of a data packet matches the configured rules, a copy of the data packet is sent to the processor.

[0039] These rules can all be sent to the switching chip via the processor. Figure 3 This is a flowchart of the data packet tracing processing method according to an embodiment of this application. Figure 2 ,like Figure 3 As shown below, Figure 3 The steps included in the method shown are explained.

[0040] In step S302, the processor sends the pre-configured rules to the switching chip, wherein the switching chip records the trajectory information of the data packet within the switching chip and adds the trajectory information of the data packet as additional data to the data packet, and the additional data is forwarded by the switching chip along with the data packet;

[0041] In step S304, the processor receives a data packet sent by the switching chip according to the rules, wherein the data packet sent to the processor carries the additional data, and both the switching chip and the processor are located within the switch.

[0042] In the above steps, the processor sends the rules to the switching chip. Since the switching chip internally records the trajectory information of the data packets and adds this trajectory information as additional data to the data packets, the data packets sent by the switching chip to the processor according to the rules all carry additional data. This trajectory information can be used for debugging and fault location. Therefore, the above steps solve the problem that the existing technology cannot debug and locate programmable switching chips, resulting in low fault diagnosis efficiency. It provides data support for the debugging and fault location of programmable switching chips and improves the fault diagnosis efficiency to a certain extent.

[0043] The processor is located within the switch. In one optional implementation, rules can be sent to the processor via an interface configured on the switch, which can be either a network interface or a local interface. If it is a network interface, a management server can also be configured to manage the switch. The management server sends the aforementioned rules to the switch's processor, and after receiving the rules from the management server, the processor configures the received rules to the switching chip.

[0044] In another alternative implementation, considering the limited capacity of the processor to store data packets, a server can be set up for storing the data packets. Furthermore, considering that the processor has computational capabilities, it can also summarize the data packets from the switching chip according to the additional data in the data packets and report them to the server used for data storage (also called a storage server).

[0045] Figure 4 This is a system diagram including a storage server and a management server according to an embodiment of this application, such as... Figure 4 As shown, the system includes a switch (also known as a programmable switch), a storage server, and a management server. The modules included are: a remote management module, a local management module, an on-chip information acquisition module, a local data processing module, and a data storage and consumption module. These modules are described in detail below.

[0046] Remote control module (in) Figure 4 The part marked ① runs in the management server and is responsible for receiving requests from users and sending the requests to the local management module of the corresponding programmable switch (in...). Figure 4 The request, marked as ②, is used to configure rules and other parameters used in the switching chip (also known as a programmable switching chip). It ultimately returns the execution result to the user; for example, if the rule configuration is successful, a configuration success message is returned; if the rule configuration fails, a configuration failure message is returned along with the reason for the failure. In one example, user requests can be categorized into active packet capture requests and packet loss reporting requests. In an active packet capture request, the user can provide attribute information of the data packets to be captured, such as IP 5-tuple information (including but not limited to source address range, destination address range, source port range, destination port range, priority control information, and the interface number entering the chip). The rule corresponding to this active packet capture request is sent to the local management module located in the processor via the management server, and then sent by the local management module to the on-chip information acquisition module of the programmable switching chip. The programmable switching chip completes data packet acquisition and reporting based on the received information. In a packet loss reporting request, the user does not need to provide additional information; the programmable switching chip will automatically collect and report actively dropped data packets. Of course, as another optional implementation, users can also configure packet loss types. Data packets that are dropped according to the user-configured packet loss type can be reported to the processor as high-priority data packets.

[0047] The local control module runs on the programmable switch's CPU and is responsible for translating requests from the remote control module into chip configurations, which are then sent to the programmable switch chip to trigger the on-chip information acquisition module. Figure 4 Data packets are collected using the method marked ③.

[0048] The on-chip information acquisition module runs in the programmable switching chip of the programmable switch. It is responsible for mirroring data packets that conform to the rules configured by the user to the CPU. At the same time, it attaches the trajectory information (also known as on-chip operation and maintenance information) involved in the processing of the data packet by the programmable switching chip as a special header (i.e., additional data) to the data packet and reports it to the CPU.

[0049] Local data processing module (in) Figure 4The component marked ④, running in the CPU of the programmable switch, is responsible for collecting data packets reported by the programmable switching chip, parsing the on-chip maintenance information carried in the data packets, and summarizing the on-chip maintenance information and the original messages to different degrees according to different user requests. It then periodically writes the summarized information to a remote storage server. There are many summarization methods; for example, the sketch method can be used. A sketch is a streaming data aggregation structure that can store a fixed number of entries, using multiple hash functions to linearly project streaming data into a lower-dimensional space that preserves the data aggregation characteristics. In this embodiment, the existing sketch algorithm can be used to summarize the data packets, and will not be elaborated further.

[0050] Data storage and consumption module (in) Figure 4 The module marked as ⑤ runs on the storage server and is responsible for storing the data written by the local data processing module. It also filters and processes the stored data according to user requests and sends the final processing result to the remote management module to return it to the user.

[0051] It should be noted that the above embodiments do not limit the connection methods between devices and between hardware; various interfaces and connection methods can be used between devices and between hardware. For example, the link between a programmable switch, a storage server, and a management server (i.e., Figure 4 The A, D, and E links in a programmable switch can be directly connected or indirectly connected via a local area network (LAN) or a wide area network (WAN); the link between the programmable switching chip and the CPU in the programmable switch (i.e., Figure 4 The B and C links can be either PCIe or local network links.

[0052] In this optional implementation, the main processing occurs within the switching chip. The programmable switching chip contains multiple pipelines, each with an inbound and outbound direction. The computational logic for both directions can be implemented through hardware programming. All pipelines are connected to the same MMU (Multi-Module Unit) for both inbound and outbound directions. The MMU can forward data packets from the inbound direction of one pipeline to the outbound direction of another. After a data packet enters the programmable switching chip, it will be forwarded between one or more pipelines according to the configuration issued by the programmable switch CPU (e.g., ...). Figure 5 (As shown by the gray solid line), and executes the logic in the corresponding direction of each pipeline path in sequence; the programmable switch chip allows users to attach a set of metadata to each data packet through programming, and the metadata can flow inside the switch chip along with the data packet. Metadata, also known as intermediary data or relay data, mainly describes information about data properties. In this optional embodiment, since the attached data records trajectory information, this trajectory information can be regarded as the attribute information of the data packet; therefore, the attached data is also called metadata.

[0053] Figure 5 This is a schematic diagram of the structure of the on-chip information acquisition module according to an embodiment of this application, such as... Figure 5 As shown, the on-chip information acquisition module manages multiple pipelines. Pipelines 1 to N include an inbound direction, an MMU, and an outbound direction. The marking submodule is located in the inbound direction of the first pipeline, while the logging and mirroring submodules are located in the inbound and outbound directions of each pipeline. The eccentricity module is located within the MMU. Figure 5 The process also includes pipeline X, which is used to send data packets to the processor. Pipeline X includes an MMU and an outgoing direction. The MMU includes a rate-limiting submodule, and the outgoing direction includes a reporting submodule. These modules are described below.

[0054] Mark submodule (in) Figure 5 The part marked ① is located at the beginning of the inbound direction of the first pipeline after the data packet enters the switch. Based on the configuration issued by the local management module, it matches the IP 5-tuple and other information of the data packet (including but not limited to source address range, destination address range, source port range, destination port range, protocol type, TOS, and interface number entering the chip), and records the matching status in the switch metadata (e.g., whether the current data packet hits a matching rule, or which matching rule it hits). Here, the metadata that records the matching status of this module can be called marking_info.

[0055] Log submodule (in) Figure 5 The module marked ② is located in each pipeline along the normal forwarding process of a data packet and records the processing logic that the data packet undergoes. When a branch occurs in the chip logic within a pipeline or a data packet is forwarded to another pipeline, the log submodule records the branch actually executed by the current data packet in a bitmap format. The bitmap uses each bit to store the state. For example, when recording the pipelines through which a data packet passes, each pipeline has an inbound and an outbound direction. Therefore, each pipeline requires two bits to record whether the data packet has passed through the inbound and outbound directions of that pipeline. It can be agreed that if the value of this bit is 1, it indicates that the data packet has passed through the inbound or outbound direction of that pipeline. If the switching chip supports a maximum of 16 pipelines, then at least 32 bits are needed to represent the inbound and outbound directions of the pipelines through which the data packet has passed.

[0056] When a pipeline actively drops a data packet, the logging submodule records the reason for the packet loss. Both are stored in the metadata and can be forwarded to other pipelines along with the data packet.

[0057] Mirror submodule (in) Figure 5The part marked ③ is located at the end of the inbound and outbound directions of each pipeline in the normal forwarding process of the data packet. Based on the configuration issued by the local control module, the following information is matched: [1] whether the current data packet is dropped (is_drop); [2] the reason for the current data packet loss (drop_reason); [3] the matching status of the current data packet in the marking submodule (marking_info); [4] the next pipeline to which the current data packet is planned to go and its corresponding interface (next_port). If the issued configuration is matched, the current data packet is mirrored (i.e. copied) to the interface connected to the CPU (corresponding to Figure 5 In the assembly line X), such as Figure 5 As shown by the gray dashed line, when mirroring occurs, the metadata recorded by the current pipeline logging submodule will be copied along with it. At the same time, the interface (current_port) corresponding to the current pipeline, the interface (next_port) corresponding to the next pipeline, and the timestamp of the data packet entering the chip will be written into the metadata of the copy data packet (i.e., the data packet obtained by copying or mirroring).

[0058] eccentric rotor module (in) Figure 5 The module marked ④ is located within the MMU and is triggered every time a data packet passes through the MMU during the normal forwarding process. The MMU can forward data packets from the pipeline in direction to the pipeline out direction or other target pipelines. When the MMU loses packets due to congestion in the target pipeline (or target interface), the deflection module will "deflect" (i.e., forward) the packets that should have been dropped to the interface connected to the CPU (corresponding to the CPU interface). Figure 5 The pipeline X in the middle is used to report MMU packet loss, such as Figure 5 As shown by the gray dashed line, pipeline X uses an independent queue and does not share queues with other interfaces, thus it is unaffected by congestion on other interfaces. When a deflection occurs, the metadata recorded by the current pipeline logging submodule will be forwarded along with it.

[0059] Rate limiting submodule (in) Figure 5 The part marked ⑤ is located within the MMU and sends data packets to the interface connected to the CPU (corresponding to) via "mirroring" or "deflection". Figure 5 The rate limiting submodule takes effect when the pipeline (X) is in progress. It can group packets based on mirroring parameters or deflection parameters (such as session sequence number, packet truncation, queue sequence number, etc.) and rate limit each group of packets separately to prevent excessively high-rate packets from entering the CPU and consuming system resources.

[0060] Reporting submodule (in) Figure 5 The interface marked ⑥ in the middle is located at the interface connected to the CPU (corresponding to...) Figure 5In the pipeline X) outbound direction, it represents the only processing logic that all data packets sent to the CPU via "mirroring" or "deflection" pass through before entering the CPU. The reporting submodule writes the metadata carried by the current data packet into the information reporting header and inserts the information reporting header at the beginning of the data packet, i.e., before the Ethernet header. In this optional embodiment, the specific format of the information reporting header is not limited, including field length and field arrangement. Figure 6 This is a schematic diagram of the reporting header format according to an embodiment of this application. Figure 6 This is just one example of a header format and is not limited to this. Figure 6 The meanings of the various fields in the header shown are as follows:

[0061] PATH: A bitmap (32 bits) that records the execution path of a data packet.

[0062] TIMESTAMP: A high-precision timestamp of the data packet entering the chip, used to identify multiple copies (48 bits) obtained from multiple mirroring of the same data packet. Since each data packet enters the chip at a different time, this high-precision timestamp can be used to uniquely identify a data packet.

[0063] ID: User Task ID (4 bits).

[0064] CURRENT_PORT: The port number (12 bits) of the current pipeline when the packet is mirrored.

[0065] FAKE_ETHER_TYPE: Takes a fixed value, indicating that the current data packet type is an information reporting packet (16 bits).

[0066] FLAGS: Flags (4 bits).

[0067] NEXT_PORT: The port number (12 bits) that the original data packet should have entered in the next pipeline when the data packet was mirrored.

[0068] Table 1 below shows the configuration and workflow of each submodule under two scenarios: active packet capture and packet loss reporting. It is assumed here that data packets will only pass through one pipeline, i.e. Figure 5 In pipeline 1, the mirrored or deflected data packets enter pipeline X.

[0069] Table 1

[0070]

[0071] Through the above optional implementation methods, basic operation and maintenance capabilities such as debugging and fault location are provided for packet processing operations offloaded to the programmable switch. The above optional implementation methods provide a "single-step debugging" mechanism within the programmable switch chip, which can obtain the execution path of a specified packet in each pipeline and the changes that occur after passing through each pipeline. The above optional implementation methods also provide a "all-cause packet loss reporting" mechanism, which can capture packets dropped by the programmable switch chip (including packets dropped due to processing logic reasons and packets dropped due to network reasons), and support the reporting of various statistics and raw dropped packets.

[0072] In this embodiment, an electronic device is provided, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the methods described in the above embodiments.

[0073] The aforementioned program can run on a processor or be stored in memory (or computer-readable medium). Computer-readable medium includes both permanent and non-permanent, removable and non-removable media, and information storage can be achieved by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable medium does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0074] These computer programs may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes can be implemented using different modules, and different steps can be implemented using different modules.

[0075] One embodiment provides such an apparatus. This apparatus, referred to as a packet tracking and processing apparatus, is located within a processor and includes: a second sending module (for implementing the functions of the aforementioned local control module), used to send pre-configured rules to a switching chip, wherein the switching chip records the trajectory information of the data packet within the switching chip and adds the trajectory information of the data packet as additional data to the data packet, the additional data following the data packet being forwarded by the switching chip; and a receiving module (for implementing the functions of the aforementioned local data processing module), used to receive data packets sent by the switching chip according to the rules, wherein the data packets sent to the processor carry the additional data, and both the switching chip and the processor are located within a switch.

[0076] Optionally, the second sending module is further configured to receive the rules from the management server, wherein the management server is used to manage the switch; and / or, the receiving module is further configured to summarize the data packets from the switching chip according to the additional data of the data packets and report them to the server for data storage.

[0077] In another embodiment, another packet tracking processing device is provided, located in a switching chip, comprising: a recording module for recording the trajectory information of the packet within the switching chip during the forwarding process of the packet entering the switching chip; an attachment module for adding the trajectory information of the packet as attachment data to the packet, wherein the attachment data is forwarded by the switching chip along with the packet; the recording module and the attachment module are used to implement the functions of the above-mentioned log submodule; a first sending module (used to implement the functions of the above-mentioned rate limiting submodule, mirror submodule, skew module, and / or reporting submodule), for sending the packets to be sent to the processor according to pre-configured rules, wherein the packets sent to the processor carry the attachment data, and both the switching chip and the processor are located within the switch.

[0078] The system or apparatus is used to implement the functions of the methods in the above embodiments. Each module in the system or apparatus corresponds to each step in the method, as has been described in the method and will not be repeated here.

[0079] Optionally, the recording module is used to record all pipelines through which the data packet passes within the switching chip, wherein the pipelines are used to process the data packet according to predetermined logic.

[0080] Optionally, the recording module is used to record the data packet as it passes through the inbound and outbound directions of each pipeline. Each pipeline of the switching chip includes an inbound direction, a buffer management unit (MMU), and an outbound direction. The data packet enters the pipeline from the inbound direction, and the MMU is used to forward the data packet to the outbound direction of the same pipeline or to another pipeline.

[0081] Optionally, the first sending module is configured to, after detecting that a data packet has been dropped, write the reason for the data packet being dropped into the additional data and send the dropped data packet to the processor.

[0082] Optionally, the first sending module is used to match data packets according to the attribute information of data packets carried in pre-configured rules; copy data packets whose attribute information is the same as the attribute information in the rules; and send the copied data packets to the processor.

[0083] Optionally, the first sending module is used to send the data packets to be sent to a predetermined pipeline, wherein the predetermined pipeline is pre-established; and the data packets to be sent are sent to the processor through the predetermined pipeline.

[0084] Optionally, the first sending module is configured to determine the rate used to send data packets based on the resource usage of the processor, and send the data packets to be sent according to the rate.

[0085] The above implementation method solves the problem that the existing technology cannot debug and locate faults in programmable switching chips, resulting in low fault diagnosis efficiency. It provides data support for debugging and locating faults in programmable switching chips and improves fault diagnosis efficiency to a certain extent.

[0086] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A packet tracing processing method, comprising: During the forwarding process of a data packet entering a switching chip, the switching chip records the trajectory information of the data packet within the switching chip; The switching chip adds the trajectory information of the data packet as additional data to the data packet, wherein the additional data is forwarded by the switching chip along with the data packet; The switching chip sends the data packets to be sent to the processor according to the pre-configured rules. The data packets sent to the processor carry the additional data. Both the switching chip and the processor are located inside the switch. The switching chip records the trajectory information of the data packet within the switching chip, including: the switching chip records the data packet as it passes through the inbound and outbound directions of each pipeline, wherein each pipeline of the switching chip includes an inbound direction, a buffer management unit (MMU), and an outbound direction, the data packet enters the pipeline from the inbound direction, the MMU is used to forward the data packet to the outbound direction of the same pipeline or to another pipeline, wherein the pipeline is used to process the data packet according to predetermined logic.

2. The method according to claim 1, wherein, The switching chip sends the data packets to be sent to the processor according to pre-configured rules, including: The switching chip detected that the data packet was dropped; The switching chip writes the reason why the data packet was dropped into the additional data; The switching chip sends the discarded data packets to the processor.

3. The method according to claim 1, wherein, The switching chip sends the data packets to be sent to the processor according to pre-configured rules, including: The switching chip matches data packets according to the attribute information of the data packets carried in the pre-configured rules; The switching chip copies data packets whose attribute information is the same as the attribute information in the rule; The switching chip sends the copied data packet to the processor.

4. The method according to claim 1, wherein, The switching chip sends the data packets that need to be sent to the processor, including: The switching chip sends the data packets to be sent to a predetermined pipeline, wherein the predetermined pipeline is pre-established; The switching chip sends the data packets to be sent to the processor through the predetermined pipeline.

5. The method according to claim 1, wherein, The switching chip sends the data packets that need to be sent to the processor, including: The switching chip determines the rate used to send data packets based on the processor's resource usage. The switching chip sends the data packets that need to be sent according to the stated rate.

6. A packet tracing processing method, comprising: The processor sends pre-configured rules to the switching chip, wherein the switching chip records the trajectory information of the data packet within the switching chip and adds the trajectory information of the data packet as additional data to the data packet, and the additional data is forwarded by the switching chip along with the data packet; The processor receives data packets sent by the switching chip according to the rules, wherein the data packets sent to the processor carry the additional data, and both the switching chip and the processor are located inside the switch; Before the processor receives the data packet sent by the switching chip according to the rules, the method further includes: the switching chip recording all pipelines through which the data packet passes within the switching chip, wherein the pipelines are used to process the data packet according to predetermined logic; the switching chip recording the data packet as it passes through the inbound and outbound directions of each pipeline, wherein each pipeline of the switching chip includes an inbound direction, a buffer management unit (MMU), and an outbound direction, the data packet enters the pipeline from the inbound direction, and the MMU is used to forward the data packet to the outbound direction of the same pipeline or to another pipeline.

7. The method according to claim 6, wherein, Also includes: The processor receives the rules from the management server, wherein the management server is used to manage the switch; And / or, The processor summarizes the data packets from the switching chip according to the additional data in the data packets, and then reports them to the server used for data storage.

8. The method according to claim 6 or 7, wherein, Before the processor receives the data packet sent by the switching chip according to the rules, the method further includes: the switching chip sending the data packet to be sent to the processor, wherein the switching chip sending the data packet to be sent to the processor includes at least one of the following: The switching chip detects that a data packet has been dropped, writes the reason for the data packet being dropped into the additional data, and then sends the dropped data packet to the processor. The switching chip matches data packets according to the attribute information of the data packets carried in the pre-configured rules. The switching chip copies the data packets whose attribute information is the same as the attribute information in the rules and sends the copied data packets to the processor. The switching chip sends the data packets to be sent to a predetermined pipeline, wherein the predetermined pipeline is pre-established, and the switching chip sends the data packets to be sent to the processor through the predetermined pipeline; The switching chip determines the rate at which to send data packets based on the processor's resource usage, and then sends the data packets that need to be sent according to the rate.

9. A packet tracking processing apparatus, located in a switching chip, comprising: The recording module is used to record the trajectory information of the data packet within the switching chip during the forwarding process of the data packet entering the switching chip; An additional module is used to add the trajectory information of the data packet as additional data to the data packet, wherein the additional data is forwarded by the switching chip along with the data packet; The first sending module is used to send data packets to be sent to the processor according to pre-configured rules, wherein the data packets sent to the processor carry the additional data, and both the switching chip and the processor are located inside the switch; The recording module is specifically used to record the inbound and outbound directions of the data packet as it passes through each pipeline. Each pipeline of the switching chip includes an inbound direction, a buffer management unit (MMU), and an outbound direction. The data packet enters the pipeline from the inbound direction. The MMU is used to forward the data packet to the outbound direction of the same pipeline or to another pipeline. The pipeline is used to process the data packet according to a predetermined logic.

10. A packet tracking processing apparatus, located in a processor, comprising: The second sending module is used to send pre-configured rules to the switching chip, wherein the switching chip records the trajectory information of the data packet within the switching chip and adds the trajectory information of the data packet as additional data to the data packet, and the additional data is forwarded by the switching chip along with the data packet; A receiving module is used to receive data packets sent by the switching chip according to the rules, wherein the data packets sent to the processor carry the additional data, and both the switching chip and the processor are located inside the switch; Before the processor receives the data packet sent by the switching chip according to the rules, the switching chip records all pipelines through which the data packet passes within the switching chip, wherein the pipelines are used to process the data packet according to predetermined logic; the switching chip records the data packet as it passes through the inbound and outbound directions of each pipeline, wherein each pipeline of the switching chip includes an inbound direction, a buffer management unit (MMU), and an outbound direction, the data packet enters the pipeline from the inbound direction, and the MMU is used to forward the data packet to the outbound direction of the same pipeline or to another pipeline.

11. A switch, comprising a switching chip and a processor; wherein, The switching chip is used to perform the method steps of any one of claims 1 to 5, and the processor is used to perform the method steps of any one of claims 6 or 7.

12. A readable storage medium having computer instructions stored thereon, wherein, When executed by a processor, the computer instructions implement the method steps of any one of claims 1 to 5 or any one of claims 6 or 7.

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