Word line driver circuit and memory

Abstract

Embodiments of the present application relate to the field of semiconductors, and provide a word line driver circuit and a memory. The word line driver circuit may at least include: a plurality of word line drivers, each of the word line drivers includes a corresponding PMOS transistor and an NMOS transistor. The plurality of PMOS transistors included in the plurality of word line drivers are arranged side by side, and the plurality of NMOS transistors included in the plurality of word line drivers are arranged side by side. In the arrangement direction of the PMOS transistors, the plurality of PMOS transistors are located on the same side of the plurality of NMOS transistors. Embodiments of the present invention are beneficial to improving the electrical performance of the word line driver circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, and in particular, to a word line driver circuit and a memory. Background Art

[0002] Various circuits in a memory need to use various signals, and signal drivers for applying signals to signal lines are widely used. A word line driver is used to apply a voltage to word lines in a memory cell array, and the word lines can extend from a sub-word line driver (SWD, Sub Wordline Driver) and pass through the entire column of memory cells. The sub-word line driver can selectively activate corresponding word lines in response to a row address corresponding to the word lines received by the storage device, and each memory cell connected to the activated word line can output or input data. Summary of the Invention

[0003] Embodiments of the present application provide a new word line driver circuit and a memory.

[0004] According to some embodiments of the present application, there is provided a word line driver circuit, including: a plurality of word line drivers, each of the word line drivers including a corresponding PMOS transistor and an NMOS transistor, the plurality of PMOS transistors included in the plurality of word line drivers being arranged side by side, the plurality of NMOS transistors included in the plurality of word line drivers being arranged side by side, and in the arrangement direction of the PMOS transistors, the plurality of PMOS transistors are located on the same side of the plurality of NMOS transistors.

[0005] According to some embodiments of the present application, there is also provided a memory including the above-mentioned word line driver circuit.

[0006] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0007] In the embodiments of the present application, in the arrangement direction of PMOS transistors, multiple PMOS transistors are located on the same side of multiple NMOS transistors. In this way, it is beneficial to avoid arranging PMOS transistors and NMOS transistors side by side in the direction perpendicular to the above arrangement direction, so that there is a larger space for PMOS transistors and NMOS transistors in the vertical direction, which is conducive to extending the channel length or gate width of PMOS transistors and NMOS transistors, and improving the electrical performance of the word line driver circuit. At the same time, controlling multiple PMOS transistors to be located on the same side of multiple NMOS transistors is beneficial to making the relative positional relationship between PMOS transistors and NMOS transistors in different word line drivers the same, and different word lines connected to different word line drivers extend in the same direction, thereby simplifying the layout complexity of the word line driver circuit and reducing the manufacturing cost. In addition, multiple PMOS transistors are located on the same side of multiple NMOS transistors. In the layout design, it is only necessary to control the arrangement pitch of multiple PMOS transistors to be equal to that of multiple NMOS transistors, without considering the pitch between the side-by-side NMOS transistors and the side-by-side PMOS transistors, which is beneficial to making the pitches of PMOS transistors and NMOS transistors in different word line drivers equal, so as to ensure that the driving capabilities of different word line drivers are the same or similar, and further making the word line driver circuit have good stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments unless otherwise stated. The figures in the drawings do not constitute a scale limitation.

[0009] Figure 1 Schematic structural diagram of a memory provided by an embodiment of the present application;

[0010] Figure 2 Schematic circuit diagram of a word line driver circuit provided by an embodiment of the present application;

[0011] Figures 3 to 9 Schematic layout diagram of a word line driver circuit provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented.

[0013] Figure 1 Schematic structural diagram of a memory provided by an embodiment of the present application; Figure 2 Schematic circuit diagram of a word line driver circuit provided by an embodiment of the present application;Figures 3 to 9 This is a schematic layout diagram of the word line driver circuit provided by an embodiment of the present application.

[0014] The word line driver circuit includes: a plurality of word line drivers, each word line driver includes a corresponding PMOS transistor and an NMOS transistor. The plurality of PMOS transistors included in the plurality of word line drivers are arranged side by side, and the plurality of NMOS transistors included in the plurality of word line drivers are arranged side by side. In the arrangement direction of the PMOS transistors, the plurality of PMOS transistors are located on the same side of the plurality of NMOS transistors.

[0015] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0016] Refer to Figure 1 , according to different connected word lines, the word line drivers can be divided into an odd word line driver SWD_ODD and an even word line driver SWD_EVEN. The odd word line driver SWD_ODD is used to connect odd-numbered word lines (such as WL1, WL3, WL5, and WL7), and the even word line driver SWD_EVEN is used to connect even-numbered word lines (such as WL0, WL2, WL4, and WL6). In a storage device, the odd word line driver SWD_ODD and the even word line driver SWD_EVEN are usually arranged at intervals, and the odd-numbered word lines and the even-numbered word lines are usually arranged at intervals.

[0017] Refer to Figure 1 and Figure 2 , taking the example that each word line driver circuit includes four word line drivers for illustration. According to the figure, the types of different word line drivers in the same word line driver circuit are the same, that is, they are all odd word line drivers or even word line drivers; each word line driver may include one PMOS transistor and two NMOS transistors, denoted as the zero PMOS transistor, the zero NMOS transistor, and the first NMOS transistor. The gates of the zero PMOS transistor and the zero NMOS transistor are used to receive the first control signal MWLB (such as MWLB <n>) The source of the zero-th PMOS transistor is used to receive the second control signal FX (such as FX0, FX2, FX4, and FX6). The drains of the zero-th PMOS transistor, the zero-th NMOS transistor, and the first NMOS transistor are used to connect to the corresponding word lines (such as WL0, WL2, WL4, and WL6). The sources of the zero-th NMOS transistor and the first NMOS transistor are grounded. The gate of the first NMOS transistor is used to receive the second control complementary signal FXB (such as FXB0, FXB2, FXB4, and FXB6). In some embodiments, the word line driver only includes one PMOS transistor and one NMOS transistor.

[0018] Wherein, the moment when the second control signal FX jumps to the high level is the same as the moment when the second control complementary signal FXB jumps to the low level and the moment when the first control signal MWLB jumps to the low level. The moment when the second control complementary signal FXB jumps to the high level is later than the moment when the second control signal FX jumps to the low level. The moment when the first control signal MWLB jumps to the high level is later than the moment when the second control complementary signal FXB jumps to the high level.

[0019] Exemplarily, the word line driver circuit includes a first word line driver SWD1, a second word line driver SWD2, a third word line driver SWD3, and a fourth word line driver SWD4. The first word line driver SWD1 includes a PMOS transistor P10 and NMOS transistors N10 and N11. The second word line driver SWD2 includes a PMOS transistor P20 and NMOS transistors N20 and N21. The third word line driver SWD3 includes a PMOS transistor P30 and NMOS transistors N30 and N31. The fourth word line driver SWD4 includes a PMOS transistor P40 and NMOS transistors N40 and N41. Wherein, P10, P20, P30, and P40 belong to the zero-th PMOS transistor, N10, N20, N30, and N40 belong to the zero-th NMOS transistor, and N11, N21, N31, and N41 belong to the first NMOS transistor.

[0020] In some embodiments, each PMOS transistor is composed of at least two sub-PMOS transistors; in some other embodiments, each NMOS transistor is composed of at least two sub-NMOS transistors; in yet another embodiment, each PMOS transistor is composed of at least two sub-PMOS transistors, and each NMOS transistor is composed of at least two sub-NMOS transistors. Exemplarily, the zero-th PMOS transistor is composed of the zero-one PMOS transistor and the zero-two PMOS transistor, the zero-th NMOS transistor is composed of the zero-one NMOS transistor and the zero-two NMOS transistor, and the first NMOS transistor is composed of the one-one NMOS transistor and the one-two NMOS transistor. It should be noted that in the embodiments of the present application, the zero-one PMOS transistor and the zero-two PMOS transistor are NMOS transistors with exactly the same physical characteristics, and the only differences are their own positions and their connection relationships with other components. Similarly, the one-one NMOS transistor and the one-two NMOS transistor, as well as the zero-one NMOS transistor and the zero-two NMOS transistor are NMOS transistors with exactly the same physical characteristics, and the only differences are their own positions and their connection relationships with other components. Arranging the PMOS transistor or NMOS transistor to be composed of two sub-MOS transistors together is beneficial to adjusting the layout of the layout.

[0021] In addition, for the sake of simplicity of illustration, Figures 3 to 9 each transistor or sub-transistor is not labeled in the figure, and those skilled in the art can determine Figure 2 which transistor or sub-transistor is represented by the transistors at different positions in the figure according to Figures 3 to 9 the signals received by the gates, sources, and drains of different transistors in the figure.

[0022] In some embodiments, referring to Figure 3 , P10, P20, P30, and P40 are arranged side by side along the first direction D1. In the first direction D1, N10 / N11 in the first word line driver, N20 / N21 in the second word line driver, N30 / N31 in the third word line driver, and N40 / N41 in the fourth word line driver are located on the same side of the above-mentioned multiple PMOS transistors.

[0023] In some embodiments, two sub-PMOS transistors share the same source. Taking the first word line driver as an example, the PMOS transistor P10 in the first word line driver is composed of two sub-PMOS transistors, P101 and P102. P101 and P102 share the same active region and are used to receive the first control signal FX, specifically FX0.

[0024] In some embodiments, the arrangement direction of multiple PMOS transistors (i.e., the first direction D1) is perpendicular to the channel length direction of the PMOS transistors (i.e., the second direction D2). Among them, the arrangement direction of two sub-PMOS transistors is parallel to the channel length direction of the PMOS transistors and perpendicular to the first direction D1. Continuing with the first embodiment as an example, the arrangement direction of P101 and P102 is parallel to the channel length direction and perpendicular to the first direction D1.

[0025] In some embodiments, each PMOS transistor includes a first sub-PMOS transistor and a second sub-PMOS transistor. The first sub-PMOS transistors corresponding to different PMOS transistors share the same gate, and the second sub-PMOS transistors corresponding to different PMOS transistors share the same gate. As Figure 3 shown, the PMOS transistor P20 includes P201 and P202, the PMOS transistor P30 includes P301 and P302, the PMOS transistor P40 includes P401 and P402. P101, P201, P301, and P401 are arranged side by side along the first direction D1 and share the same gate, and P102, P202, P302, and P402 are arranged side by side along the first direction D1 and share another gate.

[0026] In some embodiments, the first NMOS transistor and the second NMOS transistor are located between the zeroth NMOS transistor and the second NMOS transistor. Referring to Figure 3 the internal arrangement of the NMOS transistors of different word line drivers is the same. Taking the first word line driver as an example, the first NMOS transistor N11 in the first word line driver is composed of the first NMOS transistor N111 and the second NMOS transistor N112, and the zeroth NMOS transistor N10 is composed of the zeroth NMOS transistor N101 and the second NMOS transistor N102. N111 and N112 are located between N101 and N102.

[0027] In some embodiments, the arrangement direction of the first NMOS transistor and the second NMOS transistor is parallel to the arrangement direction of the zeroth NMOS transistor and the second NMOS transistor. Similarly, taking the first word line driver as an example, the arrangement direction of N111 and N112 is parallel to the arrangement direction of N101 and N102.

[0028] In some embodiments, the channel length directions of different transistors and their sub-transistors are the same. In this way, it is beneficial to achieve a unique preset spacing between PMOS transistors and NMOS transistors in the same word line driver, making the word line driver have more stable and balanced electrical performance. Specifically, taking the first word line driver as an example, in the first direction D1, the distance between P101 and N101 is equal to the distance between P102 and N102; wherein, in the first direction D1, the horizontal positions of the gates of P101 and N101 at least partially overlap, and the distance between P101 and N101 is the distance between the gates of P101 and N101. The same applies to P102 and N102, and details will not be elaborated here.

[0029] Correspondingly, in the first direction D1, the distance between P101 and N111 is equal to the distance between P102 and N112; wherein, in the first direction D1, the horizontal positions of the gates of P101 and N111 at least partially overlap, and the distance between P101 and N111 is the distance between the gates of P101 and N111. The same applies to P102 and N112, and details will not be elaborated here.

[0030] In some embodiments, the zero-first NMOS transistor and the first-first NMOS transistor share the same drain, the first-first NMOS transistor and the first-second NMOS transistor share the same source, and the first-second NMOS transistor and the zero-second NMOS transistor share the same drain. Different transistors sharing the same source or drain is beneficial to reducing the overall size of the word line driver, and further realizing the miniaturization and microminiaturization of the word line driver circuit and the memory. Taking the first word line driver as an example, N101 and N111 share the same active region, and this active region is connected to the zero-word line WL0 through a contact hole. N111 and N112 share the same active region, and this active region is grounded or connected to a low-level signal. N112 and N102 share the same active region, and this active region is also connected to the zero-word line WL0 through a contact hole.

[0031] Among them, the first-first NMOS transistor and the first-second NMOS transistor share the same gate. Different transistors sharing the same gate is beneficial to reducing the manufacturing difficulty of the gate and ensuring the conductive performance of the gate. Specifically, it is beneficial to reducing the complexity of the patterned opening of the mask, avoiding etching defects due to complex patterns, and ensuring that the gate can be effectively formed. Taking the first word line embodiment as an example, N111 and N112 share the same gate, or rather, the gates of N111 and N112 are different parts of the same conductive layer. Another part used to connect the gates of N111 and N112 is located on the isolation structure. The isolation structure is used to isolate adjacent active regions, and the word line can be made of doped polysilicon or metal materials, such as tungsten and molybdenum.

[0032] In some embodiments, the first NMOS transistor and the second NMOS transistor are located between the eleventh NMOS transistor and the twelfth NMOS transistor; wherein, the first NMOS transistor and the second NMOS transistor may share the same gate. Refer to Figure 4 , the internal arrangement of the NMOS transistors of different word line drivers is the same. Taking the first word line driver as an example, N101 and N102 are located between N111 and N112, and N101 and N102 share the same gate.

[0033] Similar to the previous embodiment, the arrangement directions of the first NMOS transistor and the second NMOS transistor located in the middle position are parallel to the arrangement directions of the eleventh NMOS transistor and the twelfth NMOS transistor located on both sides, corresponding to Figure 4 , the arrangement direction of N101 and N102 is parallel to the arrangement direction of N111 and N112.

[0034] Correspondingly, the eleventh NMOS transistor and the first NMOS transistor share the same drain, the first NMOS transistor and the second NMOS transistor share the same source, and the second NMOS transistor and the twelfth NMOS transistor share the same drain, corresponding to Figure 4 , N111 and N101 share the same active region, and this active region is connected to the zero-th word line WL0 through a contact hole. N101 and N102 share the same active region, and this active region is grounded or connected to a low-level signal. N102 and N112 share the same active region, and this active region is also connected to the zero-th word line WL0 through a contact hole.

[0035] In some embodiments, refer to Figure 4 , the word line driver includes a first word line driver and a second word line driver. The NMOS transistor N10 in the first word line driver and the NMOS transistor N20 in the second word line driver share the same source and the same gate. Among them, the NMOS transistor N10 is composed of N101 and N102, the NMOS transistor N20 is composed of N201 and N202, and N201, N202, N101, and N102 share the same continuous active region and the same continuous conductive layer. It can be understood that the gates of different transistors are different parts of the same conductive layer, and the other parts of the conductive layer connecting the gates of different transistors are located on the isolation structure.

[0036] Correspondingly, the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver share the source. Among them, the first NMOS transistor N11 included in the first word line driver is composed of N111 and N112, the first NMOS transistor N21 included in the second word line driver is composed of N211 and N212, N111 and N211 share the same source, and N112 and N212 share the same source.

[0037] It can be understood that there are multiple combinations between different word line drivers. In the embodiments of the present application, the adjacent arrangement of the first word line driver and the second word line driver is taken as an example, and based on this example, the connection relationship of the NMOS transistors of the adjacent word line drivers in the word line driver circuit is described. It can be understood that in Figure 4 In the illustrated embodiment, the connection relationship of the NMOS transistors of the first word line driver and the second word line driver can be equally applicable to the NMOS transistors of the third word line driver and the fourth word line driver; similarly, in other embodiments, if the first word line driver and the third word line driver are adjacent, the above description of the connection relationship is also applicable to the NMOS transistors of the first word line driver and the third word line driver. Subsequently, the first word line driver and the second word line driver are still taken as examples for description, and the applicable situations will not be elaborated any further.

[0038] In some embodiments, the word line driver further includes a third word line driver and a fourth word line driver. The NMOS transistor N10 of the first word line driver, the NMOS transistor N20 of the second word line driver, the NMOS transistor N30 of the third word line driver, and the NMOS transistor N40 of the fourth word line driver share the same gate.

[0039] In some embodiments, the distance between the PMOS transistor and the NMOS transistor in the word line driver is denoted as a preset distance, and the preset distances between different word line drivers are the same. Referring to Figure 4 , in the first direction D1, the PMOS transistors of the second word line driver, the first word line driver, the fourth word line driver, and the third word line driver are arranged in sequence. At the same time, the NMOS transistors of the second word line driver, the first word line driver, the fourth word line driver, and the third word line driver are arranged in sequence. The distance between P10 and N10 and N11 is equal, the distance between P20 and N20 and N21 is equal, the distance between P30 and N30 and N31 is equal, and the distance between P40 and N40 and N41 is equal; further, the first distance between P10 and N10 is equal to the second distance between P20 and N20, the third distance between P30 and N30, and the fourth distance between P40 and N40. Setting the different preset distances to be equal is beneficial to making different word line drivers have the same or similar performance, so that the moments when different word line drivers apply voltages to the corresponding word lines are close, ensuring the stability of the internal timing of the memory.

[0040] In some embodiments, the arrangement direction of the first NMOS transistor and the second NMOS transistor is parallel to the arrangement direction of the first NMOS transistor and the second NMOS transistor; wherein, the first NMOS transistor and the second NMOS transistor share the same gate, and / or the first NMOS transistor and the second NMOS transistor share the same gate.

[0041] Specifically, in some embodiments, referring to Figure 5 , the arrangement directions of N111 and N112 are parallel to the arrangement directions of N101 and N102; in addition, the first NMOS transistors included in the first word line driver and the first NMOS transistors included in the second word line driver are located between the zero NMOS transistors included in the first word line driver and the zero NMOS transistors included in the second word line driver, that is, N11 and N21 are located between N10 and N20.

[0042] In other embodiments, referring to Figure 6 , the arrangement directions of N111 and N112 are parallel to the arrangement directions of N101 and N102; in addition, the zero NMOS transistors included in the first word line driver and the zero NMOS transistors included in the second word line driver are located between the first NMOS transistors included in the first word line driver and the first NMOS transistors included in the second word line driver, that is, N10 and N20 are located between N11 and N21; in addition, N10, N20, N30, and N40 share the same gate.

[0043] In some embodiments, referring to Figures 3 to 6 , the channel length directions of the NMOS transistors in the word line driver are parallel to the channel length directions of the PMOS transistors, or rather, the channel length directions of the PMOS transistors are the same as the channel length directions of the NMOS transistors; in other embodiments, referring to Figures 7 to 9 , the channel length directions of the NMOS transistors in the word line driver are perpendicular to the channel length directions of the PMOS transistors. Among them, Figure 7 The difference between the embodiment shown in Figure 3 and the embodiment shown in Figure 8 lies in overall adjusting the channel length directions of the NMOS transistors in the word line driver circuit, and setting N301 and N101 to share the same source, and setting N401 and N201 to share the same source. Correspondingly, Figure 6 The main adjustment of the embodiment shown in Figure 9 and Figure 5 and the embodiment shown in

[0044] also lies in this. Since the extension direction of the word line connected to the word line driver is generally parallel to the extension direction of the gate of the PMOS transistor in the word line driver, setting the channel length direction of the NMOS transistor perpendicular to the channel length direction of the PMOS transistor is beneficial to avoiding arranging more NMOS transistors side by side in the second direction D2 perpendicular to the first direction D1, reserving a larger space for the extension of the drain of the NMOS transistor, enabling the drain of the NMOS transistor to have a larger width, which is beneficial to directly connecting the word line extending from the drain of the PMOS transistor to the drain of the corresponding NMOS transistor without bending, that is, making the word line straight, reducing the resistance of the word line and the RC delay caused by the resistance, and ensuring that the word line driver circuit has good electrical performance.

[0045] In this embodiment, in the arrangement direction of the PMOS transistors, multiple PMOS transistors are located on the same side of multiple NMOS transistors. In this way, it is beneficial to avoid arranging the PMOS transistors and NMOS transistors side by side in the direction perpendicular to the above arrangement direction, so that there is a larger space for the PMOS transistors and NMOS transistors in the vertical direction, which is conducive to extending the channel length or gate width of the PMOS transistors and NMOS transistors, and improving the electrical performance of the word line driver circuit. At the same time, controlling multiple PMOS transistors to be located on the same side of multiple NMOS transistors is beneficial to making the relative position relationship between the PMOS transistors and NMOS transistors in different word line drivers the same, and different word lines connected to different word line drivers extend in the same direction, thus simplifying the layout complexity of the word line driver circuit and reducing the manufacturing cost. In addition, multiple PMOS transistors are located on the same side of multiple NMOS transistors. In the layout design, it is only necessary to control the arrangement pitch of multiple PMOS transistors to be equal to that of multiple NMOS transistors, without considering the pitch between the side-by-side NMOS transistors and the side-by-side PMOS transistors, which is beneficial to making the pitch between the PMOS transistors and NMOS transistors in different word line drivers equal, so as to ensure that the driving capabilities of different word line drivers are the same or similar, and further make the word line driver circuit have good stability.

[0046] The embodiment of the present application further provides a memory, including the word line driver circuit described in any one of the above. In the case where the size of the integrated circuit is increasingly miniaturized, by using the word line driver circuit with the above structure, since its transistors and word lines can have good electrical performance, the word line driver circuit as a whole has good characteristics, thereby improving the overall performance of the memory.

[0047] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.< / n>

Claims

1. A word line driver circuit, characterized in that, it includes: a plurality of word line drivers, each of the word line drivers includes a corresponding PMOS transistor and an NMOS transistor, the plurality of PMOS transistors included in the plurality of word line drivers are arranged side by side, the plurality of NMOS transistors included in the plurality of word line drivers are arranged side by side, and in the arrangement direction of the PMOS transistors, the plurality of PMOS transistors are located on the same side of the plurality of NMOS transistors; the word line driver includes a zero-th PMOS transistor, a zero-th NMOS transistor and a first NMOS transistor, the gate of the zero-th PMOS transistor receives a first control signal, the source receives a second control signal, the drain is connected to the word line, the gate of the zero-th NMOS transistor receives the first control signal, the source is grounded, the drain is connected to the word line, the gate of the first NMOS transistor receives a second control complementary signal, the source is grounded, the drain is connected to the word line, the zero-th NMOS transistor is composed of a zero-one NMOS transistor and a zero-two NMOS transistor, and the first NMOS transistor is composed of a first-one NMOS transistor and a first-two NMOS transistor.

2. The word line driver circuit according to claim 1, characterized in that, each of the PMOS transistors is composed of at least two sub-PMOS transistors.

3. The word line driver circuit according to claim 2, characterized in that, the two sub-PMOS transistors share the same source.

4. The word line driver circuit according to claim 2, characterized in that, the arrangement direction of the two sub-PMOS transistors is parallel to the channel length direction of the PMOS transistor.

5. The word line driver circuit according to claim 2, characterized in that, each of the PMOS transistors includes a first sub-PMOS transistor and a second sub-PMOS transistor, the first sub-PMOS transistors corresponding to different PMOS transistors share the same gate, and the second sub-PMOS transistors corresponding to different PMOS transistors share the same gate.

6. The word line driver circuit according to claim 1, characterized in that, the arrangement direction of the plurality of PMOS transistors is perpendicular to the channel length direction of the PMOS transistor.

7. The word line driver circuit according to claim 1, characterized in that, the first-one NMOS transistor and the first-two NMOS transistor are located between the zero-one NMOS transistor and the zero-two NMOS transistor.

8. The word line driver circuit according to claim 1, characterized in that, the zero-one NMOS transistor and the zero-two NMOS transistor are located between the first-one NMOS transistor and the first-two NMOS transistor.

9. The word line driver circuit according to claim 8, characterized in that, the word line driver includes a first word line driver, a second word line driver, a third word line driver and a fourth word line driver, and the zero-th NMOS transistors of the first word line driver, the second word line driver, the third word line driver and the fourth word line driver share the same gate.

10. The word line driver circuit according to claim 1, characterized in that, The arrangement directions of the first NMOS transistor and the second NMOS transistor are parallel to the arrangement directions of the zero-first NMOS transistor and the zero-second NMOS transistor.

11. The word line driver circuit according to claim 10, wherein, the word line driver includes a first word line driver and a second word line driver, and the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver are located between the zero-NMOS transistor included in the first word line driver and the zero-NMOS transistor included in the second word line driver.

12. The word line driver circuit according to claim 10, wherein, the word line driver includes a first word line driver and a second word line driver, and the zero-NMOS transistor included in the first word line driver and the zero-NMOS transistor included in the second word line driver are located between the first NMOS transistor included in the first word line driver and the first NMOS transistor included in the second word line driver.

13. The word line driver circuit according to claim 12, wherein, the word line driver includes a third word line driver and a fourth word line driver, and the zero-NMOS transistors of the first word line driver, the second word line driver, the third word line driver, and the fourth word line driver share the same gate.

14. The word line driver circuit according to claim 1, wherein, the channel extension direction of the NMOS transistor is perpendicular to the channel extension direction of the PMOS transistor.

15. A memory, wherein, it includes the word line driver circuit according to any one of claims 1 to 14.

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