Word line driver circuit and memory

Abstract

Embodiments of the present application relate to the field of semiconductors, and provide a word line driver circuit and a memory. The word line driver circuit at least includes: a first type of word line driver and a second type of word line driver. Each word line driver includes a PMOS transistor and an NMOS transistor. The first type of PMOS transistor in the first type of word line driver and the second type of PMOS transistor in the second type of word line driver are used to receive different first control signals; the first type of PMOS transistor and the second type of PMOS transistor are arranged side by side, and the NMOS transistors included in the first type of word line driver and the NMOS transistors included in the second type of word line driver are located on the same side of the first type of PMOS transistor and the second type of PMOS transistor. Embodiments of the present application are beneficial to improving the electrical performance of the word line driver circuit.

Description

[0001] Cross-reference

[0002] This application claims the priority of a Chinese patent application titled "Word Line Driver Circuit and Memory", with the application number 202110866739.0, which was filed on July 29, 2020, and is hereby incorporated by reference in its entirety into this application. Technical Field

[0003] Embodiments of this application relate to the field of semiconductors, and particularly to a word line driver circuit and a memory. Background Art

[0004] Various circuits in a memory need to use various signals, and signal drivers for applying signals to signal lines are widely used. A word line driver is used to apply a voltage to word lines in a memory cell array. The word lines can extend from a sub-word line driver (SWD) and pass through the entire column of memory cells. The sub-word line driver can selectively activate corresponding word lines in response to the row address corresponding to the word lines received by the storage device, and each memory cell connected to the activated word line can output or input data. Summary of the Invention

[0005] Embodiments of this application provide a word line driver circuit and a memory, which are at least beneficial to improving the electrical performance of the word line driver circuit.

[0006] According to some embodiments of this application, on the one hand, an embodiment of this application provides a word line driver circuit, which at least includes: a first type of word line driver and a second type of word line driver. Each word line driver includes a PMOS transistor and an NMOS transistor. The first type of PMOS transistor in the first type of word line driver and the second type of PMOS transistor in the second type of word line driver are used to receive different first control signals; the first type of PMOS transistor and the second type of PMOS transistor are arranged side by side, and the NMOS transistors included in the first type of word line driver and the NMOS transistors included in the second type of word line driver are located on the same side of the first type of PMOS transistor and the second type of PMOS transistor.

[0007] According to some embodiments of this application, on the other hand, an embodiment of this application further provides a memory, including the above-mentioned word line driver circuit.

[0008] The technical solutions provided by the embodiments of this application have at least the following advantages:

[0009] In the embodiments of the present application, the NMOS transistors included in the first type of word line driver and the NMOS transistors included in the second type of word line driver are located on the same side of the first type of PMOS transistors and the second type of PMOS transistors. In this way, it is beneficial to make the relative positional relationship between the PMOS transistors and the NMOS transistors in different word line drivers the same, and to make the different word lines connected to different word line drivers extend in the same direction, thereby simplifying the layout complexity of the word line driver circuit and reducing the manufacturing cost. In addition, since multiple PMOS transistors are located on the same side of multiple NMOS transistors, in the layout design, it is only necessary to control the arrangement pitch of the multiple PMOS transistors to be equal to the arrangement pitch of the multiple NMOS transistors, without considering the pitch between the side-by-side NMOS transistors and the side-by-side PMOS transistors, which is beneficial to making the pitches of the PMOS transistors and the NMOS transistors in different word line drivers equal, thereby ensuring that the driving capabilities of different word line drivers are the same or similar, and further making the word line driver circuit have good stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments are illustrated by way of example in the accompanying drawings, which illustrations do not constitute a limitation on the embodiments, unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0011] Figure 1 Schematic structural diagram of a memory provided by an embodiment of the present application;

[0012] Figure 2 Schematic circuit diagram of a word line driver circuit provided by an embodiment of the present application;

[0013] Figures 3 to 10 Schematic layout diagram of a word line driver circuit provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are proposed for the convenience of readers to understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented.

[0015] Figure 1 Schematic structural diagram of a memory provided by an embodiment of the present application; Figure 2 Schematic circuit diagram of a word line driver circuit provided by an embodiment of the present application; Figures 3 to 10 Schematic layout diagram of a word line driver circuit provided by an embodiment of the present application.

[0016] The word line driver circuit includes: a first type of word line driver and a second type of word line driver. Each word line driver includes a PMOS transistor and an NMOS transistor. The first type of PMOS transistor in the first type of word line driver and the second type of PMOS transistor in the second type of word line driver are used to receive different first control signals; the first type of PMOS transistor and the second type of PMOS transistor are arranged side by side, and the NMOS transistors included in the first type of word line driver and the NMOS transistors included in the second type of word line driver are located on the same side of the first type of PMOS transistor and the second type of PMOS transistor.

[0017] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.

[0018] Referring to Figure 1 , according to the different word lines connected, the word line driver can be divided into an odd word line driver SWD_ODD and an even word line driver SWD_EVEN. The odd word line driver SWD_ODD is used to connect odd-numbered word lines (such as WL1, WL3, WL5, and WL7), and the even word line driver SWD_EVEN is used to connect even-numbered word lines (such as WL0, WL2, WL4, and WL6). In a storage device, the odd word line driver SWD_ODD and the even word line driver SWD_EVEN are usually arranged at intervals, and the odd-numbered word lines and the even-numbered word lines are usually arranged at intervals.

[0019] Referring to Figure 1 and Figure 2 , taking an example that each word line driver circuit includes four word line drivers, it can be seen from the figure that the types of different word line drivers in the same word line driver circuit are the same, that is, they are all odd word line drivers or even word line drivers; each word line driver can include a PMOS transistor and two NMOS transistors, denoted as the zero PMOS transistor, the zero NMOS transistor, and the first NMOS transistor. The gates of the zero PMOS transistor and the zero NMOS transistor are used to receive the first control signal MWLB (such as MWLB <n>Or MWLB<n+1>), the source electrodes of the zero-th PMOS transistor and the first NMOS transistor are used to receive the second control signal FX (such as FX0 or FX2), the drain electrodes of the zero-th PMOS transistor, the zero-th NMOS transistor, and the first NMOS transistor are used to connect to the corresponding word lines (such as WL0, WL2, WL4, and WL6), the source electrode of the zero-th NMOS transistor is grounded or connected to a low-level signal, and the gate electrode of the first NMOS transistor is used to receive the second control complementary signal FXB (such as FXB0 or FXB2).

[0020] Among them, the moment when the first control signal MWLB jumps to the low level is the same as the moment when the second control complementary signal FXB jumps to the low level, the moment when the second control signal FX starts to boost is later than the moment when the second control complementary signal FXB jumps to the low level, the moment when the first control signal MWLB jumps to the high level is the same as the moment when the second control complementary signal FXB jumps to the high level, the moment when the second control signal FX starts to drop is earlier than the moment when the second control complementary signal FXB jumps to the high level, and during the process of the second control signal FX dropping to the low level, it stays at an intermediate level for a preset duration, and the moment when the second control signal FX drops to the low level is the same as the moment when the second control complementary signal FXB jumps to the high level.

[0021] Exemplarily, the word line driver circuit includes a first word line driver SWD1, a second word line driver SWD2, a third word line driver SWD3, and a fourth word line driver SWD4. The first word line driver SWD1 includes a PMOS transistor P10 and NMOS transistors N10 and N11. The second word line driver SWD2 includes a PMOS transistor P20 and NMOS transistors N20 and N21. The third word line driver SWD3 includes a PMOS transistor P30 and NMOS transistors N30 and N31. The fourth word line driver SWD4 includes a PMOS transistor P40 and NMOS transistors N40 and N41. Among them, P10, P20, P30, and P40 belong to the zero-th PMOS transistor, N10, N20, N30, and N40 belong to the zero-th NMOS transistor, and N11, N21, N31, and N41 belong to the first NMOS transistor.

[0022] According to Figure 2 As can be seen from the content shown, the first word line driver SWD1 and the third word line driver SWD3 are used to receive the same first control signal MWLB and the same second control complementary signal FXB, that is, MWLB <n>And the first word line driver SWD1 and the third word line driver SWD3 are used to receive a first control signal MWLB and a second control complementary signal FXB0, and the second word line driver SWD2 and the fourth word line driver SWD4 are used to receive another first control signal MWLB and another second control complementary signal FXB, namely MWLB <n>and FXB2; the first word line driver SWD1 and the second word line driver SWD2 are used to receive the same second control signal FX, i.e., FX0, and the third word line driver SWD3 and the fourth word line driver SWD4 are used to receive another second control signal FX, i.e., FX2. The word lines connected by different word line drivers are different. Among them, the word line drivers can be divided into the first type of word line drivers and the second type of word line drivers according to whether the received first control signal MWLB is the same. The first type of word line drivers includes the first word line driver and the third word line driver, and the second type of word line drivers includes the second word line driver and the fourth word line driver.

[0023] In some embodiments, each PMOS transistor is composed of at least two sub-PMOS transistors; in some other embodiments, each NMOS transistor is composed of at least two sub-NMOS transistors; in yet another embodiment, each PMOS transistor is composed of at least two sub-PMOS transistors, and each NMOS transistor is composed of at least two sub-NMOS transistors. Exemplarily, the zero PMOS transistor is composed of the zero-one PMOS transistor and the zero-two PMOS transistor, the zero NMOS transistor is composed of the zero-one NMOS transistor and the zero-two NMOS transistor, and the first NMOS transistor is composed of the first-one NMOS transistor and the first-two NMOS transistor. It should be noted that in the embodiments of the present application, the zero-one PMOS transistor and the zero-two PMOS transistor are NMOS transistors with exactly the same physical characteristics, and the only differences are their own positions and the connection relationships with other components. Similarly, the first-one NMOS transistor and the first-two NMOS transistor, as well as the zero-one NMOS transistor and the zero-two NMOS transistor, are NMOS transistors with exactly the same physical characteristics, and the only differences are their own positions and the connection relationships with other components. Setting the PMOS transistor or NMOS transistor to be jointly composed of two sub-MOS transistors is beneficial to adjusting the layout of the layout.

[0024] In addition, for the sake of simplicity of illustration, Figures 3 to 9 each transistor or sub-transistor is not labeled in Figure 2 and those skilled in the art can determine Figures 3 to 9 which transistor or sub-transistor is represented by the transistors at different positions in

[0025] Referring to Figure 3 , the PMOS transistors P10 and P30 in the first type of word line drivers and the PMOS transistors P20 and P40 in the second type of word line drivers are arranged side by side, and the NMOS transistors N10, N11, N30, and N31 included in the first type of word line drivers and the NMOS transistors N20, N21, N40, and N41 included in the second type of word line drivers are located on the same side of the PMOS transistors.

[0026] In some embodiments, each PMOS transistor is composed of at least two sub-PMOS transistors. Refer to Figure 3 , PMOS transistor P10 is composed of P101 and P102, PMOS transistor P20 is composed of P201 and P202, PMOS transistor P30 is composed of P301 and P302, and PMOS transistor P40 is composed of P401 and P402. Since the positional relationship between the sub-PMOSs in different PMOS transistors is similar, and the positional relationship between P10 and P30 is similar to that between P20 and P40, hereinafter, P10 and P30 are used for exemplary illustration.

[0027] In some embodiments, the arrangement direction of the first type of PMOS transistors and the second type of PMOS transistors is perpendicular to the channel length direction of the PMOS transistors. According to Figure 3 the illustrated embodiment, the arrangement direction of the first type of PMOS transistors composed of P10 and P30 and the second type of PMOS transistors composed of P20 and P40 is the first direction D1, and the channel length direction of the PMOS transistors is the second direction D2, and the second direction D2 is perpendicular to the first direction D1. It should be noted that when discussing the arrangement direction of the first type of PMOS transistors and the second type of PMOS transistors, P10 and P30 should be regarded as a whole, and P20 and P40 should be regarded as a whole.

[0028] In some embodiments, the arrangement direction of the two sub-PMOS transistors is parallel to the channel length direction of the PMOS transistor. Taking the first word line driver as an example, the arrangement direction of P101 and P102 is the second direction D2. At the same time, since the channel length directions of both P101 and P102 are the second direction D2, it can be considered that the channel length direction of P10 composed of P101 and P102 is the second direction D2, that is, the arrangement direction of P101 and P102 is parallel to the channel length direction of P10.

[0029] In some embodiments, the two sub-PMOS transistors share the same source electrode. According to Figure 3 the illustrated content, P101 and P102 share the same source electrode, and this source electrode is an independent and continuous active region, and this active region is used to receive the second control signal FX, specifically FX0; similarly, P201 and P202, P301 and P302, and P401 and P402 all share independent active regions, and this active region serves as the source electrode and is used to receive the corresponding second control signal FX.

[0030] In some embodiments, the first type of word line driver includes a first word line driver and a third word line driver. The first word line driver includes a first PMOS transistor, and the third word line driver includes a third PMOS transistor. The arrangement directions of the first PMOS transistor and the third PMOS transistor are perpendicular to the channel length direction of the PMOS transistors. If each word line driver includes only one PMOS transistor, the first PMOS transistor is PMOS transistor P10, and the third PMOS transistor is PMOS transistor P30. The arrangement direction of P10 and P30 is the first direction D1. In addition, in this embodiment, the channel length directions of different PMOS transistors are the same, specifically the second direction D2. Therefore, the arrangement direction of P10 and P30 is perpendicular to the arrangement direction of the PMOS transistors.

[0031] Similarly, the second type of word line driver includes a second word line driver and a fourth word line driver. The second word line driver includes a second PMOS transistor, and the fourth word line driver includes a fourth PMOS transistor. The arrangement directions of the second PMOS transistor and the fourth PMOS transistor are perpendicular to the channel length direction of the PMOS transistors. Taking the example that each word line driver includes one PMOS transistor and the channel length direction of each PMOS transistor is the second direction D2, the second PMOS transistor is PMOS transistor P20, the fourth PMOS transistor is PMOS transistor P40, the arrangement direction of P20 and P40 is the first direction D1, and the arrangement direction of P20 and P40 is perpendicular to the channel length direction of the PMOS transistors.

[0032] In some embodiments, the first PMOS transistor and the third PMOS transistor share the same gate. According to the above content, the first PMOS transistor is P10, the third PMOS transistor is P30, P10 and P30 share the same gate, and P101 and P102 that form P10 and P301 and P302 that form P30 share the same gate. The gate can be a single-layer structure or a multi-layer structure, and the material of the gate can include at least one of doped polysilicon or metal material.

[0033] Similarly, the second PMOS transistor and the fourth PMOS transistor share the same gate. Refer to Figure 3 , P20 and P40 share the same gate, and P201 and P202 included in P20 and P401 and P402 included in P40 share the same gate.

[0034] Assume that the PMOS transistors in the word line driver circuit have the same channel length direction, and the NMOS transistors have the same channel length direction. In some embodiments, the channel length direction of the PMOS transistors is parallel to the channel length direction of the NMOS transistors. Refer to Figures 3 to 6 ; in other embodiments, the channel length direction of the PMOS transistors is perpendicular to the channel length direction of the NMOS transistors. Refer to Figures 7 to 9 It should be noted that after adjusting the channel length direction of the NMOS transistor, adjacent NMOS transistors belonging to different word line drivers can share the same source in the channel direction of the NMOS transistor. For example Figure 7 in [reference figure], N102 and N201 share the same source, and N302 and N401 share the same source. Figure 8 in [reference figure], N411 and N311 share the same source, and N111 and N211 share the same source.

[0035] Figure 7 The adjustment made to the embodiment shown relative to Figure 3 the embodiment shown is the same as the adjustment made to the embodiment shown relative to Figure 9 the embodiment shown relative to Figure 5 the embodiment shown, and specifically includes: rotating the NMOS transistor so that the channel length direction of the NMOS transistor is perpendicular to the channel length direction of the PMOS transistor; controlling the first NMOS transistors of different word line drivers in the same type of word line driver to share the same source and the second NMOS transistors to share the same source. Exemplarily, N101 and N301, N102 and N302, N201 and N401, and N202 and N402 share the same source; further, controlling the first NMOS transistor of the first type of word line driver and the first NMOS transistor of the second type of word line driver to share the same source. Specifically, N101 and N201, and N302 and N401 share the same source; using relatively independent different conductive layers as the gate of the first NMOS transistor and the gate of the second NMOS transistor respectively. Exemplarily, the gate of N111 and the gate of N112 are relatively independent, and the gate of N311 and the gate of N312 are relatively independent.

[0036] Figure 8 The adjustment made to the embodiment shown relative to Figure 4 the embodiment shown is the same as the adjustment made to the embodiment shown relative to Figure 7 the embodiment shown relative to Figure 3 the embodiment shown, and specifically includes: rotating the NMOS transistor so that the channel length direction of the NMOS transistor is perpendicular to the channel length direction of the PMOS transistor; controlling the first NMOS transistor of the first type of word line driver and the first NMOS transistor of the second type of word line driver to share the same source. Specifically, N111 and N211, and N312 and N411 share the same source; using relatively independent different conductive layers as the gate of the first NMOS transistor and the gate of the second NMOS transistor respectively. Exemplarily, the gate of N201 and the gate of N202 are relatively independent, and the gate of N401 and the gate of N402 are relatively independent.

[0037] In some embodiments, the first NMOS transistor and the second NMOS transistor are located between the first NMOS transistor and the second NMOS transistor. Refer to Figure 3 , the internal arrangement of the NMOS transistors in different word line drivers is the same. Taking the first word line driver as an example, the first NMOS transistor N11 of the first word line driver is composed of the first one NMOS transistor N111 and the first two NMOS transistor N12, and the zero NMOS transistor N10 is composed of the zero one NMOS transistor N101 and the zero two NMOS transistor N02, and N111 and N112 are located between N101 and N102.

[0038] Among them, the arrangement directions of the first one NMOS transistor and the first two NMOS transistors are parallel to the arrangement directions of the zero one NMOS transistor and the zero two NMOS transistors. Similarly, taking the first word line driver as an example, the arrangement direction of N111 and N112 is parallel to the arrangement direction of N101 and N102. When the channel length directions of the PMOS transistor and the NMOS transistor are the same, setting the arrangement directions of the two sub-PMOS transistors to be parallel to the arrangement directions of the two sub-NMOS transistors is beneficial to making the distances between the PMOS transistor and each sub-NMOS transistor in the same word line driver the same, so that the word line driver has relatively balanced performance.

[0039] In addition, the zero one NMOS transistor and the first one NMOS transistor share the same drain, the first one NMOS transistor and the first two NMOS transistors share the same source, and the first two NMOS transistors and the zero two NMOS transistors share the same drain, correspondingly Figure 3 , N101 and N111 share the same active region, and this active region is connected to the zero word line WL0 through a contact hole. N111 and N112 share the same active region, and this active region is used to receive the first control signal FX, specifically FX0. N112 and N102 share the same active region, and this active region is also connected to the zero word line WL0 through a contact hole.

[0040] In addition, the first one NMOS transistor and the first two NMOS transistors share the same gate. Different transistors sharing the same gate is beneficial to reducing the manufacturing difficulty of the gate and ensuring the conductivity of the gate. Specifically, it is beneficial to reducing the complexity of the patterned opening of the mask, avoiding etching defects due to the relatively complex pattern, and ensuring that the gate can be effectively formed. Continuing with the first word line embodiment as an example, N111 and N112 share the same gate, or rather, the gates of N111 and N112 are different parts of the same conductive layer, and the other part for connecting the gates of N111 and N112 is located on the isolation structure.

[0041] In some other embodiments, the zero one NMOS transistor and the zero two NMOS transistor are located between the first one NMOS transistor and the first two NMOS transistors; among them, the zero one NMOS transistor and the zero two NMOS transistor can share the same gate. Refer to Figure 4 , the internal arrangement of the NMOS transistors of different word line drivers is the same. Taking the first word line driver as an example, N101 and N102 are located between N111 and N112, and N101 and N102 share the same gate.

[0042] Similar to the previous embodiment, the arrangement directions of the zero-first NMOS transistor and the zero-second NMOS transistor located in the middle position are parallel to the arrangement directions of the first-first NMOS transistor and the first-second NMOS transistor located on both sides. Taking the first word line driver as an example, that is, the arrangement direction of N101 and N102 is parallel to the arrangement direction of N111 and N112.

[0043] Similarly, the first-first NMOS transistor and the zero-first NMOS transistor share the same drain, the zero-first NMOS transistor and the zero-second NMOS transistor share the same source, and the zero-second NMOS transistor and the first-second NMOS transistor share the same drain. Refer to Figure 4 , N111 and N101 share the same active region, and this active region is connected to the zero-th word line WL0 through a contact hole. N101 and N102 share the same active region, and this active region is grounded or connected to a low-level signal. N102 and N112 share the same active region, and this active region is also connected to the zero-th word line WL0 through a contact hole; in addition, the zero-first NMOS transistor and the zero-second NMOS transistor share the same gate.

[0044] In some embodiments, the first type of word line driver includes the first word line driver and the third word line driver. The zero-first NMOS transistors of the first word line driver and the third word line driver share the same gate, that is, N101 and N301 share the same gate; the first-first NMOS transistors of the first word line driver and the third word line driver share the same gate, that is, N111 and N311 share the same gate; the first-second NMOS transistors of the first word line driver and the third word line driver share the same gate, that is, N112 and N312 share the same gate; the zero-second NMOS transistors of the first word line driver and the third word line driver share the same gate, that is, N102 and N302 share the same gate.

[0045] In some embodiments, taking Figure 5 as an example, the zero-first NMOS transistors of the first word line driver and the third word line driver share the same source, and the zero-second NMOS transistors of the first word line driver and the third word line driver share the same source, that is, N101 and N301 share the same source, and N102 and N302 share the same source.

[0046] Among them, the first type of word line driver includes a first word line driver and a third word line driver, the second type of word line driver includes a second word line driver and a fourth word line driver. The first PMOS transistor included in the first word line driver and the second PMOS transistor included in the second word line driver share a source electrode, that is, P10 and P20 share a source electrode. The third PMOS transistor included in the third word line driver and the fourth PMOS transistor included in the fourth word line driver share a source electrode, that is, P30 and P40 share a source electrode.

[0047] Furthermore, the first PMOS transistor is composed of a first PMOS transistor and a second PMOS transistor, the third PMOS transistor is composed of a first third PMOS transistor and a second third PMOS transistor. The gates of the first PMOS transistor, the second PMOS transistor, the first third PMOS transistor, and the second third PMOS transistor are on the same straight line. Specifically, referring to Figure 5 , P10 is composed of P101 and P102, P30 is composed of P301 and P302. The gates of P101, P102, P301, and P302 are on the same straight line.

[0048] Correspondingly, the second PMOS transistor is composed of a first second PMOS transistor and a second second PMOS transistor, the fourth PMOS transistor is composed of a first fourth PMOS transistor and a second fourth PMOS transistor. The first second PMOS transistor and the first PMOS transistor share the same source electrode, the second second PMOS transistor and the second PMOS transistor share the same source electrode, the first fourth PMOS transistor and the first third PMOS transistor share the same source electrode, and the second fourth PMOS transistor and the second third PMOS transistor share the same source electrode. Specifically, referring to Figure 5 , P20 is composed of P201 and P202, P40 is composed of P401 and P402. P201 and P101 share the same source electrode, P202 and P102 share the same source electrode, P401 and P301 share the same source electrode, and P402 and P302 share the same source electrode.

[0049] Among them, in some embodiments, both the first third PMOS transistor and the second third PMOS transistor are located between the first PMOS transistor and the second PMOS transistor; correspondingly, both the first fourth PMOS transistor and the second fourth PMOS transistor are located between the first second PMOS transistor and the second second PMOS transistor. Referring to Figure 5 , that is, both P301 and P302 are located between P101 and P102, and both P401 and P402 are located between P201 and P202.

[0050] In other embodiments, both the first PMOS transistor and the second PMOS transistor are located between the first third PMOS transistor and the second third PMOS transistor; correspondingly, both the first second PMOS transistor and the second second PMOS transistor are located between the first fourth PMOS transistor and the second fourth PMOS transistor. Referring to Figure 6 That is, both P101 and P102 are located between P301 and P302, and both P201 and P202 are located between P401 and P402.

[0051] In some embodiments, the arrangement directions of the first NMOS transistor and the second NMOS transistor are parallel to the arrangement directions of the zero-th NMOS transistor and the zero-th second NMOS transistor; wherein, the zero-th NMOS transistor and the zero-th second NMOS transistor share the same gate, and / or the first NMOS transistor and the second NMOS transistor share the same gate.

[0052] Reference Figure 7 , taking the first word line driver as an example, the arrangement directions of N111 and N112 are parallel to those of N101 and N102; in addition, the zero-th NMOS transistors of different word line drivers in the same type of word line driver share the same gate and the first NMOS transistors share the same gate. Taking the first NMOS transistor of the first word line driver and the first NMOS transistor of the third word line driver as an example, the first NMOS transistor N111 in the first word line driver and the first NMOS transistor N3112 in the third word line driver share the same gate, and the second NMOS transistor N112 in the first word line driver and the second NMOS transistor N312 in the third word line driver share the same gate. Referring to the accompanying drawings, that is, N111 and N3112 share the same gate, and N112 and N312 share the same gate.

[0053] In addition, in some embodiments, the zero-th NMOS transistors of the first type of word line driver and the zero-th NMOS transistors of the second type of word line driver are located between the first NMOS transistors of the first type of word line driver and the first NMOS transistors of the second type of word line driver. Referring to Figure 7 , N101 and N201 are located between N111 and N211, and N301 and N301 are located between N311 and N411; in some other embodiments, the first NMOS transistors of the first type of word line driver and the first NMOS transistors of the second type of word line driver are located between the zero-th NMOS transistors of the first type of word line driver and the zero-th NMOS transistors of the second type of word line driver.

[0054] In some embodiments, the arrangement directions of the first type of PMOS transistor and the second type of PMOS transistor are parallel to the channel length direction of the PMOS transistor and the channel length direction of the NMOS transistor. Referring to Figure 10 , P10 and P30 belonging to the first type of PMOS tubes share a gate and are arranged side by side in the second direction D2, P20 and P40 belonging to the second type of PMOS tubes share a gate and are also arranged side by side in the second direction D2, and the first type of PMOS tubes and the second type of PMOS tubes are arranged side by side along the first direction D1; at the same time, since the channel length direction of each sub-transistor is the first direction D1, the channel length direction of the PMOS tube and the NMOS tube composed of the sub-transistors is also the first direction D1, that is, the arrangement direction of the first type of PMOS tube and the second type of PMOS tube is parallel to the channel length direction of the PMOS tube and the channel length direction of the NMOS tube.

[0055] Among them, the connection relationship of a sub-PMOS tube included in different PMOS tubes is as follows: P101 and P301 are arranged side by side along the second direction D2 and share the same gate, P201 and P401 are arranged side by side along the second direction D2 and share the same gate, P101 and P201 share the same source, and P301 and P401 share the same source; the connection relationship of another sub-PMOS tube included in different PMOS tubes is the same as above and will not be repeated here.

[0056] In the embodiment of the present application, the NMOS tube included in the first type of word line driver and the NMOS tube included in the second type of word line driver are located on the same side of the first type of PMOS tube and the second type of PMOS tube. This is conducive to making the relative position relationship of the PMOS tube and the NMOS tube in different word line drivers the same, and making different word lines connected to different word line drivers extend in the same direction, thereby simplifying the layout complexity of the word line driver circuit and reducing the manufacturing cost; in addition, multiple PMOS tubes are located on the same side of multiple NMOS tubes. In the layout design, it is only necessary to control the arrangement spacing of the multiple PMOS tubes to be equal to the arrangement spacing of the multiple NMOS tubes, without considering the spacing between the side-by-side NMOS tubes and the side-by-side PMOS tubes, which is conducive to achieving equal spacing between the PMOS tubes and the NMOS tubes in different word line drivers, thereby ensuring that the driving capabilities of different word line drivers are the same or similar, and thus making the word line driver circuit have good stability.

[0057] The embodiment of the present application also provides a memory, including any of the above-mentioned word line driver circuits. As the size of integrated circuits is increasingly miniaturized, the word line driver circuit with the above structure is conducive to improving the electrical performance of transistors and word lines, thereby improving the electrical performance of the word line driver circuit, and further improving the overall performance of the memory.

[0058] Those of ordinary skill in the art can understand that the above-described embodiments are specific examples for implementing the present application. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.< / n> < / n> < / n>

Claims

1. A word line driver circuit, characterized in that, it includes: A first type of word line driver and a second type of word line driver. Each word line driver includes a PMOS transistor and an NMOS transistor. The type of each word line driver is the same, and it is either an odd-numbered word line driver or an even-numbered word line driver. The first type of PMOS transistor in the first type of word line driver and the second type of PMOS transistor in the second type of word line driver are used to receive different first control signals; The first type of PMOS transistor and the second type of PMOS transistor are arranged side by side. The NMOS transistors included in the first type of word line driver and the NMOS transistors included in the second type of word line driver are located on the same side of the first type of PMOS transistor and the second type of PMOS transistor.

2. The word line driver circuit according to claim 1, characterized in that, each of the NMOS transistors is composed of at least two sub-NMOS transistors.

3. The word line driver circuit according to claim 1 or 2, characterized in that, the word line driver includes a zero PMOS transistor, a zero NMOS transistor and a first NMOS transistor. The gate of the zero PMOS transistor receives the first control signal, the source receives the second control signal, and the drain is connected to the word line. The gate of the zero NMOS transistor receives the first control signal, the source is grounded, and the drain is connected to the word line. The gate of the first NMOS transistor receives the second control complementary signal, the source receives the first control signal, and the drain is connected to the word line. The zero NMOS transistor is composed of a zero-one NMOS transistor and a zero-two NMOS transistor. The first NMOS transistor is composed of a first-one NMOS transistor and a first-two NMOS transistor.

4. The word line driver circuit according to claim 3, characterized in that, the first-one NMOS transistor and the first-two NMOS transistor are located between the zero-one NMOS transistor and the zero-two NMOS transistor.

5. The word line driver circuit according to claim 4, characterized in that, the arrangement direction of the first-one NMOS transistor and the first-two NMOS transistor is the same as the arrangement direction of the zero-one NMOS transistor and the zero-two NMOS transistor.

6. The word line driver circuit according to claim 4, characterized in that, the zero-one NMOS transistor and the first-one NMOS transistor share the same drain, the first-one NMOS transistor and the first-two NMOS transistor share the same source, and the first-two NMOS transistor and the zero-two NMOS transistor share the same drain.

7. The word line driver circuit according to claim 6, characterized in that, the first-one NMOS transistor and the first-two NMOS transistor share the same gate.

8. The word line driver circuit according to claim 7, characterized in that, the first type of word line driver includes a first word line driver and a third word line driver. The first-one NMOS transistor and the first-two NMOS transistor included in the first word line driver and the first-one NMOS transistor and the first-two NMOS transistor included in the third word line driver share the same gate.

9. The word line driver circuit according to claim 7, It is characterized in that the first type of word line driver includes a first word line driver and a third word line driver, the first NMOS transistor of the first word line driver and the third word line driver share the same source electrode, and the second NMOS transistor of the first word line driver and the third word line driver share the same source electrode.

10. The word line driver circuit according to claim 9, It is characterized in that the first NMOS transistor of the first type of word line driver and the second NMOS transistor of the second type of word line driver share the same source electrode.

11. The word line driver circuit according to claim 3, It is characterized in that the first NMOS transistor and the second NMOS transistor are located between the eleventh NMOS transistor and the twelfth NMOS transistor.

12. The word line driver circuit according to claim 11, It is characterized in that the first NMOS transistor and the second NMOS transistor share the same gate electrode.

13. The word line driver circuit according to claim 3, It is characterized in that the arrangement directions of the eleventh NMOS transistor and the twelfth NMOS transistor are parallel to the arrangement directions of the first NMOS transistor and the second NMOS transistor.

14. The word line driver circuit according to claim 13, It is characterized in that the first type of word line driver includes a first word line driver and a third word line driver, and the eleventh NMOS transistor and the twelfth NMOS transistor in the first word line driver and the eleventh NMOS transistor and the twelfth NMOS transistor in the third word line driver share the same gate electrode.

15. A memory, It is characterized in that it includes the word line driver circuit according to any one of claims 1 to 14.

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