Memory reliability test method and device, storage medium and electronic equipment

Abstract

The present disclosure relates to a memory reliability test method and device, a storage medium and an electronic device. The method comprises: sending a plurality of write command signals to a memory; obtaining a data strobe signal and a corresponding clock signal generated by the memory after receiving each write command signal; obtaining a data strobe superposition signal and a clock superposition signal under the plurality of write command signals according to the data strobe signal and the corresponding clock signal generated after each write command signal; determining a phase difference starting point according to a phase difference allowable range and a phase difference end point of the data strobe signal and the clock signal; determining a maximum phase difference and a minimum phase difference based on the clock superposition signal and the data strobe superposition signal, according to the phase difference end point and the phase difference starting point; and comparing the maximum phase difference and the minimum phase difference with the phase difference allowable range respectively to determine whether the memory meets the data write reliability requirement. A method for determining the timing parameter tDQSS is provided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a memory reliability test method, a memory reliability test device, a computer readable storage medium and an electronic device. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, and has been widely applied in the computer field and electronic industry due to its simple structure, high density, low power consumption, low price and other advantages.

[0003] In DRAM writing, the most important timing parameter that cannot be violated is tDQSS (time of data input to the first DQS transition edge). tDQSS must be within the range specified by the protocol. If tDQSS exceeds the specified range, then the data written may be incorrect.

[0004] Therefore, accurately determining tDQSS is of great significance to data writing reliability.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to provide a memory reliability test method, a memory reliability test device and an electronic device, and to provide a method for determining the timing parameter tDQSS.

[0007] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, a memory reliability test method is provided, the method comprising: sending a plurality of write command signals to a memory; obtaining a data strobe signal and a corresponding clock signal generated by the memory after receiving each write command signal; obtaining a data strobe superimposed signal and a clock superimposed signal under a plurality of write command signals according to the data strobe signal and the corresponding clock signal generated after each write command signal; determining a phase difference starting point according to a phase difference allowable range and a phase difference end point; determining a phase difference maximum value and a phase difference minimum value based on the clock superimposed signal and the data strobe superimposed signal, according to the phase difference end point and the phase difference starting point; and comparing the phase difference maximum value and the phase difference minimum value with the phase difference allowable range respectively to determine whether the memory meets the data write reliability requirement.

[0009] In an example embodiment of the present disclosure, the determining of the phase difference starting point according to the phase difference allowable range and the phase difference end point comprises: setting an initial rising edge of the clock superimposed signal where the phase difference starting point is located; determining a phase difference average value of a middle position of the initial rising edge from the phase difference end point; determining whether the phase difference average value is within the phase difference allowable range; if yes, determining the initial rising edge as a target rising edge where the phase difference starting point is located; and if no, moving the initial rising edge forward or backward and determining a corresponding phase difference average value from the phase difference end point until the target rising edge is determined.

[0010] In an example embodiment of the present disclosure, the determining of the phase difference average value of the middle position of the initial rising edge from the phase difference end point comprises: determining a difference value between a data strobe signal average value of a middle position of a rising edge where the phase difference end point is located and a clock signal average value of a middle position of the initial rising edge as the phase difference average value.

[0011] In an example embodiment of the present disclosure, the determining of the phase difference maximum value and the phase difference minimum value based on the clock superimposed signal and the data strobe superimposed signal according to the phase difference end point and the phase difference starting point comprises: determining a first maximum value and a first minimum value of a middle position of a rising edge where the phase difference end point is located based on the data strobe superimposed signal; determining a second maximum value and a second minimum value of a middle position of a rising edge where the phase difference starting point is located based on the clock superimposed signal; determining a difference value between the first maximum value and the second minimum value as the phase difference maximum value; and determining a difference value between the first minimum value and the second maximum value as the phase difference minimum value.

[0012] In an example embodiment of the present disclosure, the comparing the maximum phase difference and the minimum phase difference with the phase difference allowable range respectively, and determining whether the memory meets the data write reliability requirement, comprises: if the maximum phase difference and the minimum phase difference are both within the phase difference allowable range, determining that the memory meets the data write reliability requirement; if the maximum phase difference or the minimum phase difference is not within the phase difference allowable range, determining that the memory does not meet the data write reliability requirement.

[0013] In an example embodiment of the present disclosure, the method further comprises: the number of the write command signals sent to the memory is greater than a preset number.

[0014] In an example embodiment of the present disclosure, the obtaining the data strobe superimposed signal and the clock superimposed signal under the multiple write command signals according to the data strobe signal and the corresponding clock signal generated after each write command signal comprises: superimposing the data strobe signals under the multiple write command signals to obtain the data strobe superimposed signal; and superimposing the clock signals under the multiple write command signals to obtain the clock superimposed signal.

[0015] According to a second aspect of the present disclosure, a memory reliability testing device is provided, which comprises: a command sending module configured to send multiple write command signals to the memory; a signal obtaining module configured to obtain a data strobe signal and a corresponding clock signal generated by the memory after receiving each write command signal; a signal superimposing module configured to obtain a data strobe superimposed signal and a clock superimposed signal under the multiple write command signals according to the data strobe signal and the corresponding clock signal generated after each write command signal; a starting point determining module configured to determine a phase difference starting point on the clock superimposed signal according to a phase difference allowable range and a phase difference end point of the data strobe signal and the clock signal; a maximum and minimum value determining module configured to determine a maximum phase difference and a minimum phase difference according to the phase difference end point and the phase difference starting point based on the clock superimposed signal and the data strobe superimposed signal; and a determining module configured to compare the maximum phase difference and the minimum phase difference with the phase difference allowable range respectively, and determine whether the memory meets the data write reliability requirement.

[0016] In an example embodiment of the present disclosure, the start point determination module is configured to set an initial rising edge of the clock superimposed signal where the phase difference start point is located; determine a phase difference average value of a middle position of the initial rising edge from the phase difference end point; determine whether the phase difference average value is within the phase difference allowable range; if yes, determine the initial rising edge as a target rising edge where the phase difference start point is located; if no, move the initial rising edge forward or backward and determine a corresponding phase difference average value from the phase difference end point until the target rising edge is determined.

[0017] In an example embodiment of the present disclosure, the start point determination module is configured to determine a difference value between a data strobe signal average value of a middle position of a rising edge where the phase difference end point is located and a clock signal average value of a middle position of the initial rising edge as the phase difference average value.

[0018] In an example embodiment of the present disclosure, the extreme value determination module is configured to determine a first maximum value and a first minimum value of a middle position of a rising edge where the phase difference end point is located based on the data strobe superimposed signal; determine a second maximum value and a second minimum value of a middle position of a rising edge where the phase difference start point is located based on the clock superimposed signal; determine a difference value between the first maximum value and the second minimum value as the phase difference maximum value; and determine a difference value between the first minimum value and the second maximum value as the phase difference minimum value.

[0019] In an example embodiment of the present disclosure, the determination module is configured to determine that the memory satisfies the data write reliability requirement if both the phase difference maximum value and the phase difference minimum value are within the phase difference allowable range; and determine that the memory does not satisfy the data write reliability requirement if either the phase difference maximum value or the phase difference minimum value is not within the phase difference allowable range.

[0020] In an example embodiment of the present disclosure, the apparatus further includes that a number of the write command signals sent to the memory is greater than a preset number.

[0021] In an example embodiment of the present disclosure, the signal superimposition module is configured to superimpose the data strobe signals under a plurality of the write command signals to obtain the data strobe superimposed signal; and superimpose the clock signals under a plurality of the write command signals to obtain the clock superimposed signal.

[0022] According to a third aspect of the present disclosure, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the memory reliability test method described above.

[0023] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the memory reliability testing method described above by executing the executable instructions.

[0024] The technical solution provided in this disclosure may include the following beneficial effects:

[0025] The memory reliability testing method provided in this disclosure sends multiple write command signals to the memory and acquires the data strobe signal and corresponding clock signal generated under each write command signal. Based on the data strobe signal and corresponding clock signal generated under each write command signal, a superimposed data strobe signal and a superimposed clock signal under multiple write command signals are acquired. After determining the starting point of the phase difference based on the allowable phase difference range and the phase difference ending point, the maximum and minimum phase difference values ​​can be determined based on the superimposed clock signal and the superimposed data strobe signal, according to the phase difference ending point and the phase difference starting point. Finally, the maximum and minimum phase difference values ​​are compared with the allowable phase difference range to determine whether the memory meets the data write reliability requirements. This provides a relatively strict test method for memory write reliability and can also determine whether the signal jitter is too large, providing data support for the reliability of memory use.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0028] Figure 1 A partial timing diagram of a DRAM according to an exemplary embodiment of the present disclosure is schematically shown;

[0029] Figure 2 The flowchart illustrating the steps of a memory reliability testing method according to an exemplary embodiment of the present disclosure is shown in the schematic diagram.

[0030] Figure 3 The diagram schematically illustrates a data strobe signal and its corresponding clock signal waveform generated by a memory after receiving a write command signal, according to an exemplary embodiment of the present disclosure.

[0031] Figure 4 A waveform diagram of a post-stacked data strobe signal and a clock signal is schematically shown according to an example embodiment of the present disclosure;

[0032] Figure 5 A comparison diagram of two sets of data strobe signals and clock signals is schematically shown according to an example embodiment of the present disclosure;

[0033] Figure 6 A flowchart of steps for determining a phase difference starting point from a post-stacked data strobe signal and a clock signal is schematically shown according to an example embodiment of the present disclosure;

[0034] Figure 7 A block diagram of a memory reliability test apparatus is schematically shown according to an example embodiment of the present disclosure;

[0035] Figure 8 A module diagram of an electronic device is schematically shown according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0037] Moreover, described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0038] The block diagrams in the drawings show functions and functionality as they can be implemented in software or computer programs executed by one or more computers or processors. In other words, the block diagrams are meant to show functional blocks of various features as they can be implemented in software or computer programs executed by one or more computers or processors. The computer programs can be written in any of a number of high level programming languages such as C, C++, Java, Visual Basic, or other suitable programming languages, and can be executed in stationary or distributed computing environments. However, it will be apparent to those of ordinary skill in the art attached hereto that the functions can be implemented in software as well as in hardware or a combination thereof.

[0039] DRAM is a commonly used data storage device, and its data storage is achieved by charging and discharging the capacitor of each storage unit, thereby controlling the high or low level of the stored data, corresponding to data 1 or 0. DRAM usually stores data after receiving a data write command.

[0040] DQS (Data Strobe Signal) is used for signal synchronization between memory and memory controller. The DQS data strobe signal is sent by the DQ signal sending end, and the signal receiving end triggers the reception of data according to the rising and falling edges of the DQS data strobe signal. In simple terms, if it is to read signals from the memory, then the motherboard (memory controller) determines when to receive the read data according to the DQS data strobe signal sent by the memory. If it is writing, it is just the opposite, the memory triggers the reception of data according to the DQS sent by the north bridge.

[0041] Generally, write data is transmitted from the memory control end to the DRAM end. After receiving the write command, the DQS data strobe signal will toggle for a period of time to ensure that the DQS data strobe signal is in a stable state. The time mentioned above for toggling is called tWPRE, where tWPRE is the first negative pulse parameter (pre-synchronization parameter) of the write operation. Referring to Figure 1 , a partial timing diagram of DRAM is shown, which includes tWPRE and tDQSS.

[0042] After tWPRE, the DQ data signal starts to toggle, and at the same time, data transmission begins. However, before transmitting data, the DQS data strobe signal needs to be synchronized with the clock signal to ensure the correctness of data transmission. At this time, the phase difference between the DQS data strobe signal and the CK clock signal is called tDQSS. Where CK represents the clock signal clock, as shown in Figure 1 .

[0043] The most important timing parameter that cannot be violated when writing data into DRAM is tDQSS, where tDQSS is also called the time of data input to the first valid DQS transition edge, that is, the time difference between the rising edge of the DQS data strobe signal and the corresponding CK clock signal rising edge, indicating the relative position of the data valid signal DQS relative to the clock signal CK. tDQSS must be within the allowed range specified by the protocol. If tDQSS exceeds the specified allowed range, it may write incorrect data.

[0044] However, in actual situations, there is usually jitter in the transmission of signals. If the jitter of the signal is too large, it may affect the phase difference between the DQS data strobe signal and the CK clock signal, i.e., affect the tDQSS value. Specifically, it may cause the minimum or maximum value of tDQSS to exceed the allowed range specified by the standard, thereby causing the occurrence of data with write errors, and further causing the problem of poor write reliability of the memory.

[0045] Based on this, the exemplary embodiments of the present disclosure first provide a memory reliability test method for evaluating the write reliability of a memory.

[0046] Reference Figure 2 , a step flow chart of a memory reliability test method according to an embodiment of the present disclosure is shown. In a feasible embodiment, the memory reliability test method can include:

[0047] Step S210, sending a plurality of write command signals to the memory;

[0048] Step S220, obtaining the data strobe signal and its corresponding clock signal generated by the memory after receiving each write command signal;

[0049] Step S230, obtaining the data strobe superimposed signal and the clock superimposed signal under the plurality of write command signals according to the data strobe signal and its corresponding clock signal generated after each write command signal;

[0050] Step S240, determining the phase difference starting point according to the phase difference allowed range and the phase difference end point of the data strobe signal and the clock signal;

[0051] Step S250, determining the maximum phase difference and the minimum phase difference according to the phase difference end point and the phase difference starting point based on the clock superimposed signal and the data strobe superimposed signal;

[0052] Step S260, comparing the maximum phase difference and the minimum phase difference with the phase difference allowed range respectively, and judging whether the memory meets the data write reliability requirement.

[0053] The memory reliability test method provided by the embodiments of the present disclosure comprises the following steps: multiple write command signals are sent to a memory; data strobe signals generated under each write command signal and corresponding clock signals are obtained; data strobe superimposed signals and clock superimposed signals under the multiple write command signals are obtained according to the data strobe signals generated under each write command signal and the corresponding clock signals; after a phase difference starting point is determined according to a phase difference allowable range and a phase difference end point, the phase difference maximum value and the phase difference minimum value are determined according to the phase difference end point and the phase difference starting point based on the clock superimposed signals and the data strobe superimposed signals; and finally, the phase difference maximum value and the phase difference minimum value are compared with the phase difference allowable range respectively to determine whether the memory meets the data write reliability requirement, thereby providing a relatively strict test method for the write reliability of the memory, and further determining whether the signal jitter is too large, thereby providing data support for the use reliability of the memory.

[0054] The memory reliability test method will be described in detail below in combination with a specific embodiment:

[0055] In step S210, multiple write command signals are sent to the memory.

[0056] In actual application, the CPU (Central Processing Unit, central processor) usually sends the write command signal to the memory, specifically, the CPU writes the content in the data register into the memory. During the write operation, the address register of the CPU first puts the storage unit of the memory to be written into data on the address bus, and then selects the above-mentioned storage unit through the address decoder; then, the CPU puts the content in the data register on the data bus, and the CPU sends a "write" control signal to the memory, and under the control of the signal, the content in the data register is written into the addressed storage unit.

[0057] Usually, the memory does not transmit data immediately after receiving the write command signal, but first flips the DQS data strobe signal for a period of time to ensure that the DQS data strobe signal is in a stable state before the DQ signal starts to flip to transmit data. The period of time when the DQS data strobe signal flips is called the first negative pulse parameter tWPRE of the write operation. The length of the first negative pulse parameter tWPRE is about twice the clock unit, i.e. 2*tCK.

[0058] In the exemplary embodiments of the present disclosure, in order to detect the influence of signal jitter on the data strobe signal DQS and the clock signal CK, multiple write command signals need to be sent to the memory to obtain multiple pairs of data strobe signals DQS and clock signals CK under the multiple write command signals.

[0059] In actual application, the plurality of write command signals are sent to the memory in sequence, and after the previous write command signal is executed, the next write command signal is sent and executed. In addition, the time interval between the adjacent two write command signals can be set according to actual conditions, for example, one clock unit or two clock units, and the exemplary embodiments of the present disclosure do not make special limitation on the time interval between the adjacent two write command signals.

[0060] It should be noted that in actual operation, the plurality of write command signals can be to write the same data into the same storage unit, can be to write different data into the same storage unit, and can be to write different data into different storage units in the memory, and the exemplary embodiments of the present disclosure do not make special limitation thereon.

[0061] In actual application, the number of the plurality of write command signals sent to the memory can be determined according to actual conditions, for example, can be several hundred, can be several thousand, and the like, and the exemplary embodiments of the present disclosure do not make special limitation on the number of the plurality of write command signals sent to the memory.

[0062] In step S220, the data strobe signal generated by the memory after receiving each write command signal and the corresponding clock signal are acquired.

[0063] In actual application, in the process of acquiring the data strobe signal and the clock signal generated by the memory, the data point signal can be acquired, or the corresponding waveform signal can be acquired. In the exemplary embodiments of the present disclosure, the waveform signal of the data strobe signal and the clock signal is preferably acquired, so as to facilitate the phase difference determination of the data strobe signal and the clock signal.

[0064] In the process of actually acquiring the waveform signal of the data strobe signal and the clock signal, there can be a plurality of different capture modes, for example, can include a conventional capture mode, a maximum value capture mode, a mean value capture mode, and a high pixel capture mode, and the like.

[0065] The conventional capture mode is to sample the data signal at the same interval time to establish the waveform, and is suitable for the case that there is no special requirement for waveform capture.

[0066] The maximum value capture mode mainly collects the maximum value and the minimum value of the sampled interval data signal, and is suitable for capturing the narrow single pulse and the high frequency burr which are very likely to occur.

[0067] The mean value capture mode aligns the two ends of the collected N waveforms, then carries out mean value calculation on the N waveforms, and finally obtains a waveform after mean value calculation, and is suitable for the case of reducing random noise in the waveform and improving vertical screen resolution.

[0068] The high-pixel capture mode is to select a super sampling technology, and average adjacent points of a sampling waveform to reduce random noise on a data signal and cause smoother waveforms on a display screen. Specifically, an average value of every N points in a waveform is calculated, and the original N sampling points are replaced by an average point. Generally, the sampling frequency of the digital converter is higher than the storage speed of the collection storage.

[0069] In the process of acquiring the waveform signals of the data strobe signal and the clock signal in the example embodiment of the present disclosure, any of the above methods can be selected according to actual conditions. Referring to Figure 3 , a waveform diagram of a data strobe signal and a corresponding clock signal generated by a memory after receiving a write command signal in an example embodiment of the present disclosure is shown.

[0070] In step S230, a data strobe superimposed signal and a clock superimposed signal under multiple write command signals are acquired according to the data strobe signal and the corresponding clock signal generated after each write command signal.

[0071] In actual applications, superimposing the data strobe signals and the corresponding clock signals under multiple write command signals means superimposing multiple data strobe signals under multiple write command signals respectively, and superimposing multiple clock signals under multiple write command signals.

[0072] In the specific superimposition process, the superimposed data strobe signal and the clock signal need to be aligned. In the alignment process, the received write command signal can be selected as the starting point for alignment, or other points can be selected as the starting point for alignment. The example embodiment of the present disclosure does not make special limitations on this.

[0073] Referring to Figure 4 , a data strobe superimposed signal DQS' and a clock superimposed signal CK' obtained after superimposition in the example embodiment of the present disclosure according to the above method are shown, and Figure 3 Compared with the data strobe signal DQS and the clock signal CK in , the data strobe superimposed signal DQS' and the clock superimposed signal CK' are obviously thicker than the lines of the data strobe signal DQS and the clock signal CK, indicating that there may be a jitter condition in the transmission process of the signal.

[0074] In step S240, the phase difference starting point is determined according to the phase difference allowed range and the phase difference end point of the data strobe signal and the clock signal.

[0075] Generally, the end point of the phase difference tDQSS of the data strobe signal and the clock signal, i.e., the phase difference end point, is the middle position of the third rising edge of the data strobe superimposed signal.

[0076] However, in practical application, the starting point of the phase difference tDQSS between the data strobe signal and the clock signal, i.e. the phase difference starting point, can be unstable. For example, as shown in Figure 5 , according to the difference of signal frequency, the corresponding phase difference starting point is also different. For example, when the frequency of the clock signal CK is low, the phase difference starting point M1 is the 2nd rising edge of the clock signal CK within the same phase difference; when the frequency of the clock signal CK is high, the phase difference starting point M1 is the 3rd rising edge of the clock signal CK within the same phase difference.

[0077] Therefore, the phase difference starting point needs to be determined according to the phase difference ending point and the phase difference allowable range. Specifically, in the determination process, the phase difference starting point can be determined according to the superimposed data strobe superimposed signal and the clock superimposed signal, or can be determined according to any data strobe signal and clock signal before superposition.

[0078] When the phase difference starting point is determined according to any data strobe signal and clock signal before superposition, the phase difference ending point, i.e. the middle position of the 3rd rising edge of the data strobe signal, can be determined first, i.e. the 0 position; then the 1st rising edge of the clock signal adjacent to the 3rd rising edge of the data strobe signal is determined from the phase difference ending point, the 1st length from the middle position of the 3rd rising edge of the data strobe signal to the middle position of the 1st rising edge of the clock signal is calculated, and it is judged whether the 1st length is within the phase difference allowable range. If yes, the middle position of the 1st rising edge of the clock signal is determined as the phase difference starting point.

[0079] If no, the 2nd rising edge of the clock signal is determined by counting one clock pulse forward, the 2nd length from the middle position of the 3rd rising edge of the data strobe signal to the middle position of the 2nd rising edge of the clock signal is calculated, and it is judged whether the 2nd length is within the phase difference allowable range. If yes, the middle position of the 2nd rising edge of the clock signal is determined as the phase difference starting point. If no, one clock pulse is continuously counted forward, and the judgment is continuously made until the phase difference starting point is determined.

[0080] If no clock signal rising edge meeting the phase difference allowable range is found in the process of determining the phase difference starting point, it is directly determined that the memory has a data write reliability problem.

[0081] When the phase difference starting point is determined according to the superimposed data strobe superimposed signal and the clock superimposed signal, reference can be made to Figure 6 , which can include the following steps.

[0082] Firstly, in step S601, an initial rising edge of the clock superimposed signal where the phase difference starting point is located can be set, for example, the Nth rising edge is set as the phase difference starting point; secondly, in step S602, the average phase difference between the middle position of the initial rising edge and the phase difference ending point is determined, which is equivalent to determining the average phase difference between the Nth rising edge and the phase difference ending point; then, in step S603, a judgment condition is entered, and it is judged whether the average phase difference is within the allowed phase difference range; if yes, in step S604, the Nth rising edge is determined as the target rising edge where the phase difference starting point is located, that is, the Nth rising edge is determined as the target rising edge; if no, in step S605, the initial rising edge is moved forward or backward, that is, the N-1th or N+1th rising edge is determined as the Nth rising edge, that is, the phase difference starting point, and the step S601 is entered again, that is, the average phase difference between the rising edge and the phase difference ending point is determined until the target rising edge is determined.

[0083] Specifically, in the process of determining the average phase difference between the middle position of the initial rising edge and the phase difference ending point, the average value of the data strobe signal at the middle position of the rising edge where the phase difference ending point is located and the difference between the average value of the clock signal at the middle position of the initial rising edge on the clock superimposed signal are determined as the average phase difference on the data strobe superimposed signal.

[0084] That is, in the process of determining the average phase difference between the Nth rising edge and the phase difference ending point, the average value of the data strobe signal at the middle position of the rising edge where the phase difference ending point is located and the difference between the average value of the clock signal at the middle position of the Nth rising edge on the clock superimposed signal are determined as the average phase difference on the data strobe superimposed signal.

[0085] In step S250, based on the clock superimposed signal and the data strobe superimposed signal, the maximum phase difference and the minimum phase difference of the phase difference between the data strobe signal and the clock signal are determined according to the phase difference ending point and the phase difference starting point.

[0086] In the example embodiment of the present disclosure, after the phase difference starting point is determined, the maximum phase difference and the minimum phase difference of the phase difference between the data strobe signal and the clock signal can be determined according to the phase difference ending point on the data strobe superimposed signal and according to the phase difference starting point on the clock superimposed signal.

[0087] From Figure 4 It can be seen that due to the signal jitter, the width of the signal curve corresponding to the superimposed data strobe superimposed signal or the width of the signal curve corresponding to the superimposed clock superimposed signal is relatively large. Therefore, there is a certain error in judging the data write reliability of the memory only according to the average phase difference of the phase difference between the data strobe signal and the clock signal determined above, which further affects the final judgment result.

[0088] Therefore, in the example embodiment of the present disclosure, the maximum phase difference and the minimum phase difference of the phase difference between the data strobe signal and the clock signal are used to determine the data write reliability of the memory, so that the influence of signal jitter can be considered, and the accuracy of determining the data write reliability of the memory can be improved.

[0089] Specifically, in the process of determining the maximum phase difference and the minimum phase difference of the phase difference between the data strobe signal and the clock signal, there can be various determination rules. For example, the maximum phase difference of the phase difference between the data strobe signal and the clock signal can be determined according to the maximum value of the phase difference end point on the width of the data strobe superimposed signal and the maximum value of the phase difference start point on the width of the clock superimposed signal; and the minimum phase difference of the phase difference between the data strobe signal and the clock signal can be determined according to the minimum value of the phase difference end point on the width of the data strobe superimposed signal and the minimum value of the phase difference start point on the width of the clock superimposed signal.

[0090] In the example embodiment of the present disclosure, in order to further improve the accuracy of determining the data write reliability of the memory, more stringent determination conditions are set, that is, more stringent determination rules are set for determining the maximum phase difference and the minimum phase difference of the phase difference between the data strobe signal and the clock signal.

[0091] Specifically, first, the first maximum value and the first minimum value of the intermediate position of the rising edge where the phase difference end point is located are determined based on the superimposed data strobe superimposed signal, that is, the maximum value and the minimum value of the width of the curve at the intermediate position of the rising edge of the data strobe superimposed signal where the phase difference end point is located are determined as the first maximum value and the first minimum value; then, the second maximum value and the second minimum value of the intermediate position of the rising edge where the phase difference start point is located are determined based on the superimposed clock superimposed signal, that is, the maximum value and the minimum value of the width of the curve at the intermediate position of the rising edge of the clock superimposed signal where the phase difference start point is located are determined as the second maximum value and the second minimum value.

[0092] After the first maximum value and the first minimum value on the data strobe superimposed signal and the second maximum value and the second minimum value on the clock superimposed signal are determined, the difference between the first maximum value and the second minimum value can be determined as the maximum phase difference, that is, the maximum value of the phase difference end point on the data strobe superimposed signal and the minimum value of the phase difference start point on the clock superimposed signal are used to determine the maximum phase difference of the phase difference between the data strobe signal and the clock signal. For reference Figure 4As shown, M3 represents the first maximum value, M4 represents the second minimum value, and the difference between M3 and M4 is the maximum value of the phase difference between the data strobe signal and the clock signal, i.e., the maximum value of tDQSS.

[0093] Further, after determining the first maximum value and the first minimum value on the data strobe superimposed signal and the second maximum value and the second minimum value on the clock superimposed signal, the difference between the first minimum value and the second maximum value can be determined as the minimum value of the phase difference, that is, the minimum value of the phase difference between the data strobe signal and the clock signal is determined using the minimum value of the phase difference end point on the data strobe superimposed signal and the maximum value of the phase difference start point on the clock superimposed signal. Refer to Figure 4 As shown, M5 represents the second minimum value, M6 represents the second maximum value, and the difference between M5 and M6 is the minimum value of the phase difference between the data strobe signal and the clock signal, i.e., the minimum value of tDQSS.

[0094] In the exemplary embodiments of the present disclosure, in the process of determining the maximum value and the minimum value of the phase difference between the data strobe signal and the clock signal, the maximum value of the phase difference between the data strobe signal and the clock signal is determined using the maximum value of the phase difference end point on the data strobe superimposed signal and the minimum value of the phase difference start point on the clock superimposed signal, which can determine a wider range of the maximum value of the phase difference; the minimum value of the phase difference between the data strobe signal and the clock signal is determined using the minimum value of the phase difference end point on the data strobe superimposed signal and the maximum value of the phase difference start point on the clock superimposed signal, which can determine a narrower range of the minimum value of the phase difference, so that the determined range of the phase difference between the data strobe signal and the clock signal is larger, which can avoid omission of the value of the phase difference between the data strobe signal and the clock signal to the greatest extent, can include all values of the phase difference between the data strobe signal and the clock signal as much as possible, provide accuracy of determination of the phase difference between the data strobe signal and the clock signal, so that the coverage is as wide as possible, and further provide a basis for accuracy of subsequent judgment of data write reliability of the memory.

[0095] In step S260, the maximum value and the minimum value of the phase difference are compared with the allowed range of the phase difference, respectively, to determine whether the memory meets the data write reliability requirement.

[0096] In the exemplary embodiments of the present disclosure, after the maximum value and the minimum value of the phase difference between the data strobe signal and the clock signal are determined according to the method in step S250, the data write reliability can be determined according to the determined maximum value and minimum value of the phase difference. The determination is mainly compared with the allowed range of the phase difference between the data strobe signal and the clock signal specified in the standard.

[0097] Specifically, in the judgment process, if the phase difference maximum value and the phase difference minimum value are both within the phase difference allowable range, it is determined that the memory meets the data write reliability requirement; if one of the phase difference maximum value or the phase difference minimum value is not within the phase difference allowable range, it is determined that the memory does not meet the data write reliability requirement.

[0098] In actual application, the specific size of the phase difference allowable range can be determined according to actual situation, for example, the phase difference allowable range can be between 0.75*tCK~1.25*tCK, and the specific size of the phase difference allowable range is not specially limited in the exemplary embodiments of the present disclosure.

[0099] In actual application, if it is determined that the memory does not meet the data write reliability requirement, it is necessary to stop sending the write command signal to the memory, and the memory needs to be troubleshooted to determine the cause of the data write reliability problem of the memory. The specific cause is not described in the exemplary embodiments of the present disclosure.

[0100] In summary, the memory reliability test method provided by the embodiments of the present disclosure, on the one hand, by sending a plurality of write command signals to the memory, and obtaining the data strobe signal and the corresponding clock signal generated under each write command signal, according to the data strobe signal and the corresponding clock signal generated under each write command signal, the data strobe superposition signal and the clock superposition signal under the plurality of write command signals are obtained; after determining the phase difference starting point according to the phase difference allowable range and the phase difference ending point, the phase difference maximum value and the phase difference minimum value can be determined based on the clock superposition signal and the data strobe superposition signal, according to the phase difference ending point and the phase difference starting point; finally, the phase difference maximum value and the phase difference minimum value are compared with the phase difference allowable range respectively, to determine whether the memory meets the data write reliability requirement, thereby providing a relatively strict test method for the write reliability of the memory, and further it can be judged whether the jitter of the signal is too large, which provides data support for the use reliability of the memory.

[0101] In another aspect, in the process of determining the phase difference maximum value and the phase difference minimum value of the phase difference between the data strobe signal and the clock signal in the exemplary embodiment of the present disclosure, the maximum value of the phase difference end point on the data strobe superimposed signal and the minimum value of the phase difference start point on the clock superimposed signal are used to determine the phase difference maximum value of the phase difference between the data strobe signal and the clock signal, so that a wider range of phase difference maximum values can be determined; the minimum value of the phase difference end point on the data strobe superimposed signal and the maximum value of the phase difference start point on the clock superimposed signal are used to determine the phase difference minimum value of the phase difference between the data strobe signal and the clock signal, so that a narrower range of phase difference minimum values can be determined, so that the determined range of the phase difference between the data strobe signal and the clock signal is larger, the omission of the value of the phase difference between the data strobe signal and the clock signal can be avoided to the greatest extent, all values of the phase difference between the data strobe signal and the clock signal can be included as much as possible, the accuracy of the determination of the phase difference between the data strobe signal and the clock signal is provided, the coverage is as wide as possible, and the accuracy of the data write reliability of the memory is further improved.

[0102] It should be noted that although the steps of the method in the present application are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc.

[0103] In addition, in the present exemplary embodiment, a memory reliability test device is also provided. Referring to Figure 7 The memory reliability test device 700 can include a command sending module 710, a signal obtaining module 720, a signal superimposing module 730, a start point determining module 740, a maximum value determining module 750, and a determination module 760, wherein:

[0104] The command sending module 710 is configured to send a plurality of write command signals to the memory;

[0105] The signal obtaining module 720 is configured to obtain a data strobe signal and a corresponding clock signal generated by the memory after receiving each write command signal;

[0106] The signal superimposing module 730 is configured to obtain a data strobe superimposed signal and a clock superimposed signal under a plurality of write command signals according to the data strobe signal and the corresponding clock signal generated after each write command signal;

[0107] The start point determining module 740 is configured to determine a phase difference start point on the clock superimposed signal according to a phase difference allowed range and a phase difference end point between the data strobe signal and the clock signal;

[0108] The maximum value and minimum value of the phase difference are determined based on the clock superimposed signal and the data strobe superimposed signal according to the phase difference end point and the phase difference start point by the maximum value and minimum value determination module 750.

[0109] The maximum value and minimum value of the phase difference are compared with the phase difference allowable range respectively by the determination module 760 to determine whether the memory meets the data write reliability requirement.

[0110] In an exemplary embodiment of the present disclosure, the start point determination module 740 is configured to set an initial rising edge of the clock superimposed signal where the phase difference start point is located; determine a phase difference average value of a middle position of the initial rising edge from the phase difference end point; determine whether the phase difference average value is within the phase difference allowable range; if yes, determine the initial rising edge as a target rising edge where the phase difference start point is located; if no, move the initial rising edge forward or backward and determine a corresponding phase difference average value from the phase difference end point until the target rising edge is determined.

[0111] In an exemplary embodiment of the present disclosure, the start point determination module 740 is configured to determine the difference between the data strobe signal average value of the middle position of the rising edge where the phase difference end point is located and the clock signal average value of the middle position of the initial rising edge as the phase difference average value.

[0112] In an exemplary embodiment of the present disclosure, the maximum value and minimum value determination module 750 is configured to determine a first maximum value and a first minimum value of the middle position of the rising edge where the phase difference end point is located based on the data strobe superimposed signal; determine a second maximum value and a second minimum value of the middle position of the rising edge where the phase difference start point is located based on the clock superimposed signal; determine the difference between the first maximum value and the second minimum value as the phase difference maximum value; and determine the difference between the first minimum value and the second maximum value as the phase difference minimum value.

[0113] In an exemplary embodiment of the present disclosure, the determination module 760 is configured to determine that the memory meets the data write reliability requirement if both the phase difference maximum value and the phase difference minimum value are within the phase difference allowable range; and determine that the memory does not meet the data write reliability requirement if the phase difference maximum value or the phase difference minimum value is not within the phase difference allowable range.

[0114] In an exemplary embodiment of the present disclosure, the apparatus further comprises: the number of write command signals sent to the memory is greater than a preset number.

[0115] In an exemplary embodiment of the present disclosure, the signal superimposition module 730 is configured to superimpose the data strobe signals under the plurality of write command signals to obtain the data strobe superimposed signal; and superimpose the clock signals under the plurality of write command signals to obtain the clock superimposed signal.

[0116] The specific details of the virtual modules of the memory reliability testing apparatuses in the above embodiments have been described in detail in the corresponding memory reliability testing methods, and thus will not be described here again.

[0117] It should be noted that although several modules or units of the memory reliability testing apparatus are mentioned in the above detailed description, such division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into several modules or units for embodiment.

[0118] In the exemplary embodiments of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0119] Those skilled in the art can understand that various aspects of the present disclosure can be implemented as a system, a method or a program product. Therefore, various aspects of the present disclosure can be embodied as a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, which can be collectively referred to as "circuitry", "module" or "system" herein.

[0120] The electronic device 800 according to this embodiment of the present disclosure will be described below with reference to Figure 8 Figure 8 The electronic device 800 shown is merely an example and should not impose any limitation on the function and scope of use of the embodiments of the present disclosure.

[0121] As shown in Figure 8 The electronic device 800 is in the form of a general computing device. The components of the electronic device 800 can include, but are not limited to, the at least one processing unit 810 described above, the at least one storage unit 820 described above, a bus 830 connecting different system components (including the storage unit 820 and the processing unit 810), and a display unit 840.

[0122] The storage unit 820 stores program code that can be executed by the processing unit 810, so that the processing unit 810 performs the steps according to various exemplary embodiments of the present disclosure described in the "Exemplary Method" section of the present specification. For example, the processing unit 810 can execute the steps described in the "Exemplary Method" section of the present specification. Figure 2 ​The steps shown in the middle of S210, sending a plurality of write command signals to the memory; step S220, obtaining the data strobe signal and its corresponding clock signal generated by the memory after receiving each write command signal; step S230, obtaining the data strobe superposition signal and clock superposition signal under a plurality of write command signals according to the data strobe signal and its corresponding clock signal generated after each write command signal; step S240, determining the phase difference starting point according to the phase difference allowable range and the phase difference end point of the data strobe signal and the clock signal; step S250, determining the phase difference maximum value and the phase difference minimum value according to the phase difference end point and the phase difference starting point based on the clock superposition signal and the data strobe superposition signal; step S260, comparing the phase difference maximum value and the phase difference minimum value with the phase difference allowable range respectively, and judging whether the memory meets the data write reliability requirement.

[0123] The storage unit 820 can include a readable medium in the form of a volatile storage unit, such as a random access memory (RAM) 8201 and / or a cache memory unit 8202, and can further include a read-only memory (ROM) 8203.

[0124] The storage unit 820 can also include a program / utility 8204 having a set of program modules 8208, including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination thereof can include implementation of a network environment.

[0125] The bus 830 can represent one or more of several types of bus structures, including a storage unit bus or storage unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of a variety of bus structures.

[0126] The electronic device 800 can also communicate with one or more external devices 870 such as a keyboard or pointing device, a Bluetooth device, or a database via I / O interface 880. The communication can be facilitated via an output / interface 880. The electronic device 800 can communicate with one or more networks, such as a local area network (LAN), a wide area network (WAN), and / or the public network, such as the Internet, via network adapter 860. As depicted, network adapter 860 communicates with the other components of electronic device 800 via bus 830. It should be understood that although not shown, other hardware and / or software components could be used in conjunction with electronic device 800. These include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0127] From the above description of the embodiments, those skilled in the art will readily appreciate that the example embodiments described herein can be implemented by software and / or by hardware coupled with software. Accordingly, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash disk, a mobile hard disk, or the like) or a network, and includes a number of instructions for causing a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to perform the methods according to the embodiments of the present disclosure.

[0128] In the example embodiments of the present disclosure, a computer readable storage medium is also provided, which stores a program product capable of implementing the above-mentioned method of the present disclosure. In some possible embodiments, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program codes for causing a terminal device to perform the steps according to various example embodiments of the present disclosure described in the above-mentioned “example method” section of the present disclosure when the program product is run on the terminal device.

[0129] The program product for implementing the above-mentioned method according to the embodiments of the present disclosure can be in the form of a portable compact disc read-only memory (CD-ROM) and includes program codes, and can be run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited to this, and in the present document, the readable storage medium can be any tangible medium containing or storing a program, which can be used by or in conjunction with an instruction execution system, device, or apparatus.

[0130] The program product can employ any combination of one or more computer-readable media. The computer-readable media can be a computer-readable storage medium or a computer-readable signal medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0131] The computer-readable signal medium can include a computer-readable storage medium that is propagated as a carrier wave. The computer-readable signal medium can further be any computer-readable medium that is not a storage medium. The computer-readable signal medium can be a computer-readable storage medium that is a propagated signal on a computer-readable storage medium.

[0132] The program code embodied on the computer-readable media can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0133] The program code can be executed by one or more programmable processors, which can be implemented as one or more microprocessors, microcontrollers, microcomputers, digital signal processors, central processing units, state machines, logic circuitries, and / or any devices that manipulate form, codes, or propertied of data and / or other data.

[0134] Furthermore, the above-described diagrams are merely schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is readily understood that the processes shown in the above-described diagrams do not indicate or limit the time sequence of the processes. In addition, it is readily understood that the processes can be executed synchronously or asynchronously, for example, in a plurality of modules.

[0135] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

[0136] It should be understood that the present disclosure is not limited to the precise structures herein described and illustrated in the drawings, and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A method for testing the reliability of a memory, characterized in that, The method includes: Send multiple write command signals to the memory; Obtain the data strobe signal and its corresponding clock signal generated by the memory after receiving each write command signal; Based on the data strobe signal generated after each write command signal and its corresponding clock signal, obtain the superimposed data strobe signal and clock superimposed signal under multiple write command signals; The starting point of the phase difference is determined based on the allowable range of the phase difference between the data strobe signal and the clock signal, as well as the end point of the phase difference. Based on the clock superposition signal and the data gating superposition signal, the maximum and minimum phase difference values ​​are determined according to the phase difference end point and the phase difference start point; The maximum and minimum phase differences are compared with the allowable phase difference range to determine whether the memory meets the data write reliability requirements.

2. The method according to claim 1, characterized in that, The step of determining the phase difference start point based on the allowable range of the phase difference between the data strobe signal and the clock signal, and the phase difference end point, includes: Set the initial rising edge of the clock superposition signal where the phase difference starts; Determine the average phase difference between the midpoint of the initial rising edge and the end point of the phase difference; Determine whether the average phase difference is within the allowable range of the phase difference; If so, then the initial rising edge is determined to be the target rising edge where the phase difference start point is located; If not, the initial rising edge is shifted forward or backward, and the corresponding average phase difference from the end point of the phase difference is determined until the target rising edge is determined.

3. The method according to claim 2, characterized in that, Determining the average phase difference between the midpoint of the initial rising edge and the end point of the phase difference includes: The average value of the phase difference is determined by the difference between the average value of the data gating signal at the midpoint of the rising edge where the phase difference ends and the average value of the clock signal at the midpoint of the initial rising edge.

4. The method according to claim 1, characterized in that, The step of determining the maximum and minimum phase difference values ​​based on the clock superposition signal and the data gating superposition signal, according to the phase difference end point and the phase difference start point, includes: Based on the data gating superposition signal, determine the first maximum value and the first minimum value at the middle position of the rising edge where the phase difference end point is located; Based on the clock superposition signal, determine the second maximum value and the second minimum value at the middle position of the rising edge where the phase difference starts; The difference between the first maximum value and the second minimum value is determined as the maximum phase difference. The difference between the first minimum value and the second maximum value is determined as the minimum phase difference.

5. The method according to claim 1 or 4, characterized in that, The step of comparing the maximum and minimum phase difference values ​​with the allowable phase difference range to determine whether the memory meets the data write reliability requirements includes: If both the maximum and minimum phase difference values ​​are within the allowable phase difference range, then the memory is determined to meet the data write reliability requirements. If the maximum or minimum phase difference is not within the allowable range of the phase difference, then the memory is determined to not meet the data write reliability requirements.

6. The method according to claim 1, characterized in that, The method further includes: The number of write command signals sent to the memory is greater than a preset number.

7. The method according to claim 1, characterized in that, The step of obtaining a superimposed data strobe signal and a superimposed clock signal under multiple write command signals based on the data strobe signal generated after each write command signal and its corresponding clock signal includes: The data strobe signals under multiple write command signals are superimposed to obtain the superimposed data strobe signal; The clock signals under multiple write command signals are superimposed to obtain the superimposed clock signal.

8. A memory reliability testing device, characterized in that, The device includes: The command sending module is used to send multiple write command signals to the memory; The signal acquisition module is used to acquire the data strobe signal and its corresponding clock signal generated by the memory after receiving each write command signal; The signal superposition module is used to obtain a data strobe superposition signal and a clock superposition signal under multiple write command signals based on the data strobe signal generated after each write command signal and its corresponding clock signal. The starting point determination module is used to determine the starting point of the phase difference on the clock superimposed signal based on the allowable range of the phase difference between the data strobe signal and the clock signal and the end point of the phase difference; The maximum and minimum value determination module is used to determine the maximum and minimum values ​​of the phase difference based on the clock superposition signal and the data gating superposition signal, according to the phase difference end point and the phase difference start point; The determination module is used to compare the maximum phase difference and the minimum phase difference with the allowable phase difference range to determine whether the memory meets the data write reliability requirements.

9. The apparatus according to claim 8, characterized in that, The starting point determination module is used to set the initial rising edge of the clock superimposed signal where the phase difference starting point is located; determine the average phase difference value from the middle position of the initial rising edge to the phase difference ending point; and determine whether the average phase difference value is within the allowable range of the phase difference. If so, then the initial rising edge is determined to be the target rising edge where the phase difference start point is located; If not, the initial rising edge is shifted forward or backward, and the corresponding average phase difference from the end point of the phase difference is determined until the target rising edge is determined.

10. The apparatus according to claim 9, characterized in that, The starting point determination module is used to determine the average value of the phase difference as the difference between the average value of the data gating signal at the middle position of the rising edge where the phase difference ends and the average value of the clock signal at the middle position of the initial rising edge.

11. The apparatus according to claim 8, characterized in that, The extreme value determination module is used to determine the first maximum value and the first minimum value at the middle position of the rising edge where the phase difference end point is located, based on the data gating superposition signal. Based on the clock superposition signal, determine the second maximum value and the second minimum value at the middle position of the rising edge where the phase difference starts; The difference between the first maximum value and the second minimum value is determined as the maximum phase difference; the difference between the first minimum value and the second maximum value is determined as the minimum phase difference.

12. The apparatus according to claim 8 or 11, characterized in that, The determination module is used to determine that the memory meets the data write reliability requirements if both the maximum and minimum phase difference values ​​are within the allowable phase difference range; and to determine that the memory does not meet the data write reliability requirements if either the maximum or minimum phase difference value is not within the allowable phase difference range.

13. The apparatus according to claim 8, characterized in that, The device further includes: The number of write command signals sent to the memory is greater than a preset number.

14. The apparatus according to claim 8, characterized in that, The signal superposition module is used to superimpose the data strobe signals under multiple write command signals to obtain the data strobe superposition signal; and to superimpose the clock signals under multiple write command signals to obtain the clock superposition signal.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory reliability testing method according to any one of claims 1-7.

16. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the memory reliability testing method according to any one of claims 1-7 by executing the executable instructions.

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