An apparatus and method for displaying multiple PAL format images based on FPGA

Abstract

This invention discloses a multi-channel PAL image display device based on FPGA, comprising multiple parallel image display channels. Each image display channel includes an image selection module, a decompression module, a FIFO buffer module, a BT.656 protocol generation module, and an encoder output interface module connected in sequence. Each image selection module is connected to n ROM storage modules. Each image display channel stores n image data in the ROM storage modules according to application needs. The image selection module reads the image data from the memory, the decompression module performs reverse decompression processing, and the decompressed data is buffered in the FIFO buffer module. The BT.656 protocol generation module reads the data from the FIFO buffer module to generate a complete BT.656 data frame, which is then output in parallel via the encoder output interface module. This invention does not require CPU intervention, significantly reducing processor utilization and solving the problem of CPU inability to process multiple image displays in parallel.

Description

Technical Field

[0001] This invention belongs to the field of aviation testing technology and relates to a device and method for displaying multiple PAL format images based on FPGA, which is applied to aircraft simulation display systems in aviation. Background Technology

[0002] ITU-R BT.601 and ITU-R BT.656 are standards developed by the International Telecommunication Union (ITU-R) Radiocommunication Sector. Strictly speaking, ITU-R BT.656 should be considered a sub-protocol of ITU-R BT.601. ITU-R BT.601 is the studio digital television coding parameter standard, while ITU-R BT.656 is the digital interface standard in Annex A of ITU-R BT.601, used for digital transmission interfaces between major digital video devices (including chips) using 27MHz parallel or 243Mbps serial interfaces.

[0003] When only one output is being used, a DSP or other types of processors can be considered for output. However, when displaying multiple images, processor resources will be significantly consumed, and in certain cases, the timing requirements of the protocol may not be met, resulting in abnormal image display. Based on the above considerations, this patent uses a logic gate array to achieve multi-channel image display.

[0004] Chinese invention patent 201310682689.6 relates to an automatic conversion method for multiple video formats to BT.656 protocol NTSC video, including the following steps: 1. Creating an automatic conversion system; 2. Sending the input video signals to the protocol detection module; 3. Using a high-level enable signal CEn to drive the protocol N acquisition unit corresponding to the protocol N detection unit to acquire the effective pixels of the input video signal; 4. Using the high-level enable signal CEn as the control signal of the multiplexer controller; 5. Using a scaling processing module to scale the video to a resolution of 640*480 and simultaneously write it to the output storage unit; 6. Using a transmission control module to generate a control pixel stream for the NTSC video blanking area according to the BT.656 protocol, thus realizing the conversion of the input video to NTSC video. This patent solves the integration problem of converting videos of any protocol type to PAL format, and can automatically convert videos of any protocol type and resolution to BT.656 protocol NTSC format videos with low conversion time. The patented method for automatically converting multiple video formats to BT.656 protocol NTSC video is different from the implementation method and protocol of the invention described in this paper.

[0005] Chinese invention patent 201610468028.7 relates to an FPGA chip for converting BT656 video signals to DC video signals, including an interface data buffer module, a frequency multiplication module, a protocol parsing module, and a timing generation module. This patent improves the compatibility of the video processing chip with video input devices, enhances the flexibility of horizontal and vertical signal generation, and ensures the accuracy of the correspondence between horizontal and vertical signals and valid data. Using the conversion method of this patent, the converted video data can be used as the data input interface of the video processing chip, making it convenient and fast. While this patent uses an FPGA to convert BT656 video signals to DC video signals, it only implements a protocol conversion, and its protocol content and implementation method are different from those of this invention. Summary of the Invention

[0006] (I) Purpose of the Invention

[0007] The purpose of this invention is to provide a device and method for displaying multiple PAL format images based on FPGA, enabling parallel processing of multiple image displays.

[0008] (II) Technical Solution

[0009] To address the aforementioned technical problems, this invention provides a device for implementing multi-channel PAL image display based on FPGA. The device includes multiple parallel image display channels. Each image display channel comprises an image selection module, a decompression module, a FIFO buffer module, a BT.656 protocol generation module, and an encoder output interface module connected sequentially. Each image selection module is connected to n ROM storage modules. Each image display channel stores n image data points in the ROM storage modules according to application needs. The image selection module reads the image data from the memory, the decompression module performs reverse decompression, and the decompressed data is buffered in the FIFO buffer module. The BT.656 protocol generation module reads the data from the FIFO buffer module to generate a complete BT.656 data frame, and outputs the data in parallel via the encoder output interface module.

[0010] This invention also provides a method for displaying multiple PAL format images based on FPGA, which includes the following steps:

[0011] S1: Extract and process image data

[0012] First, the image data is extracted, and the extracted data is compressed using the RLE compression algorithm to generate a file that conforms to the FPGAROM format.

[0013] S2: Image Selection

[0014] Each channel stores n image data according to application needs. Based on the needs of the field application, the image to be used is selected through bus configuration. The FPGA provides decoding and selection functions to realize image selection.

[0015] S3: RLE decompression

[0016] The decompression module is responsible for coordinating the read data rate with the ROM storing the images to achieve RLE decompression and cache the decompressed data in the FIFO.

[0017] S4: FIFO Data Cache

[0018] When FIFO data is cached, the number of cached data in FIFO is counted to ensure that the data is dynamically and stably kept at half the size of FIFO, so that FIFO will not overflow or be read empty.

[0019] S5: Generate a complete BT.656 data frame

[0020] According to the BT.656 protocol requirements, a complete BT.656 data frame is generated, which also includes line and field synchronization data, blanking data, timing reference code, and output image data;

[0021] S6: Encoded Output

[0022] The FPGA output interface module is responsible for data encoding, which encodes the received 0 / 1 binary data into 8-bit codes and outputs the data in parallel.

[0023] (III) Beneficial Effects

[0024] The device and method for displaying multiple PAL format images based on FPGA provided by the above technical solution, compared with the prior art, adopts a logic gate array to implement multiple parallel BT.656 protocol and interface timing, and realizes the storage and playback of multiple image data through compression and decompression algorithms. It effectively utilizes the valuable ROM resources of FPGA, supports CPU to select the displayed image, and the underlying protocol and data processing rely entirely on FPGA operation without CPU intervention. This can greatly reduce the processor's occupancy rate and solve the problem that the CPU cannot process multiple image displays in parallel. Attached Figure Description

[0025] Figure 1 This is a block diagram of the compressed data extraction method described in this invention.

[0026] Figure 2 This is a block diagram illustrating the image display principle described in this invention. Detailed Implementation

[0027] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0028] The design concept of this invention is as follows: the BT.656 interface protocol is implemented using a logic gate array to strictly guarantee the protocol timing; MATLAB is used to compress video images, and the compression algorithm used is the RLE compression algorithm, but it is not limited to this compression algorithm; the FPGA internal read-only memory is generated using the internal IP core of the logic, but depending on the data capacity, an external ROM can also be used; the parallel output of multiple images is achieved by instantiating multiple circuit modules with the same function using the logic characteristics.

[0029] Reference Figure 1 and Figure 2 As shown, the device for multi-channel PAL image display based on FPGA in this embodiment includes multiple parallel image display channels. Each image display channel includes an image selection module, a decompression module, a FIFO buffer module, a BT.656 protocol generation module, and an encoder output interface module connected in sequence. Each image selection module is connected to n ROM storage modules. According to application needs, each image display channel stores n image data in the ROM storage module. The image selection module reads the image data from the memory, the decompression module performs reverse decompression processing, and the decompressed data is buffered in the FIFO buffer module. The BT.656 protocol generation module reads the data in the FIFO buffer module to generate a complete BT.656 data frame, and outputs the data in parallel through the encoder output interface module.

[0030] The method for implementing multi-channel PAL image display based on FPGA uses an FPGA to implement the BT.656 interface protocol and instantiates multiple BT.656 interfaces. These are then converted into PAL analog signals by a video encoding chip, enabling parallel display of multiple images. The specific steps of this method are as follows:

[0031] S1: Extract and process image data

[0032] A method for implementing multi-channel PAL image display based on FPGA. This method first extracts the image data, then compresses the extracted data using the RLE (Run Length Encoding) algorithm to generate a file conforming to the FPGA ROM (IP core) format. The specific method is as follows:

[0033] S11: Extracting image data using MATLAB

[0034] The image format used in this patent is .bmp. The original image data is read by MATLAB, and the read data is in RGB format. Then, MATLAB is used to convert the data into YCbCr format.

[0035] S12: Compress the image data.

[0036] After data extraction and conversion, MATLAB was used to compress the data. Since the displayed image contains 0 / 1 data, the Run-Length Encoding (RLE) compression algorithm was employed. Because bitmap data inherently contains a large amount of repetitive data, this compression algorithm achieves a high compression ratio, significantly saving ROM storage space. The RLE algorithm is a simple and efficient lossless data compression algorithm. Its basic idea is to treat the data as a linear sequence, and these data sequences are organized in two ways: continuous repeating data blocks and continuous non-repetitive data blocks. In actual implementation, the RLE compressed data format is as follows:

[0037]

[0038] S13: Generate a file conforming to the FPGA storage format

[0039] After obtaining the compressed data in step S12, it needs to be converted into a data format that the FPGA storage ROM can recognize. The format of the FPGA read-only memory data file includes file header information, compressed data, and data padding. Since the data storage contains 2^n data (n is a natural number), any data that does not meet the requirements is replaced with 0xffff. The above data format is implemented using MATLAB coding.

[0040] The principle of multi-image display is shown in the attached diagram. Figure 2 As shown. Based on actual needs, a multi-channel parallel image display module is generated using FPGA instantiation. The following description focuses on one of the channels; the functions of the other channels are similar.

[0041] S2: Image Selection Module

[0042] To increase the flexibility of image display, an image selection function was designed into the FPGA. The specific design is as follows: Each channel stores n image data points according to application needs. Based on the field application requirements, the software can select the image to use via the bus configuration. The FPGA provides decoding and selection functionality, thereby realizing the image selection function.

[0043] S3:RLE decompression

[0044] The RLE decompression module performs the following functions: It coordinates the data read rate with the ROM read module to achieve RLE decompression and buffers the decompressed data in a FIFO. Since the data output rate of the BT.656 interface protocol module is mismatched with that of the decompression module, the aforementioned FIFO is used for data buffering. A specific algorithm is employed to dynamically balance the data within the FIFO, preventing data overflow or emptying, thus ensuring data integrity.

[0045] S4: FIFO Data Cache

[0046] Because the BT.656 protocol data frames require the construction of frame headers, frame data, blanking signals, and horizontal and vertical synchronization signals to achieve interlaced scanning, the timing requirements are extremely stringent. Furthermore, decoding and compressing the stored data also requires several clock cycles. To address the clock asynchrony issue, this invention employs a FIFO (First-In, First-Out) for data buffering. By counting the number of buffered data items in the FIFO, the data is dynamically stabilized at half the capacity of the FIFO, ensuring that the FIFO neither overflows nor becomes empty.

[0047] S5:BT.656 interface protocol

[0048] The BT.656 interface protocol module mainly implements the following functions: generating complete BT.656 data frames according to BT.656 protocol requirements, including line and field synchronization data, blanking data, timing reference codes, and output image data. In addition to transmitting 4:2:2 YCbCr video data streams, the BT.656 parallel interface also provides control signals for line and column synchronization. One frame of image data consists of a 625-line, 1728-byte data block. Lines 23-311 are even-numbered field video data, lines 336-624 are odd-numbered field video data, and the remainder are vertical control signals.

[0049] S6: Encoded Output

[0050] The FPGA output interface module is responsible for data encoding, encoding the received 0 / 1 binary data into 8-bit values ​​and outputting the data in parallel. The format of the output 8-bit multiplexed data is shown below.

[0051]

[0052] PAL image encoding uses the SAA7121 to convert digital encoding into analog signals. This chip supports PAL and NTSC video standards, with a pixel frequency of 13.5MHz. The MP0-MP7 video data pins input data are digital video signals in ITU-R BT.656 format. After the data management module within the SAA7121 chip separates the Y, Cb, and Cr signals, they are then sent to the corresponding on-chip digital-to-analog converter module to convert the digital video signal into a composite video signal, which is finally output by CVBS.

[0053] Compared with the prior art, the method described in this invention uses a logic gate array to implement multiple parallel BT.656 protocols and interface timings, and uses compression and decompression algorithms to store and play back multiple image data. It effectively utilizes the valuable ROM resources of the FPGA, supports the CPU to select and display images, and the underlying protocol and data processing rely entirely on FPGA operation without CPU intervention. This can greatly reduce the processor's utilization rate and solve the problem that the CPU cannot process multiple image displays in parallel.

[0054] As can be seen from the above technical solution, the present invention has the following significant features: It uses an FPGA to implement the BT.656 interface protocol and instantiates multiple BT.656 interfaces, which are then converted into PAL analog signals by a video encoding chip to achieve parallel display of multiple images; the FPGA implements the BT.656 interface protocol, which realizes functions such as timing reference, video data output, and auxiliary signals; the instantiation of multiple interfaces for parallel output is achieved by using an FPGA to implement multiple BT.656 interface protocols, with each channel working in parallel; the video encoding chip converts the FPGA output digital signals into PAL analog signals and outputs them to the display terminal; the image data is extracted, processed, and compressed using MATLAB to generate files conforming to the FPGA reading format; the image data is stored in an IP ROM instantiated inside the FPGA; the BT.656 protocol data is read from the memory using the FPGA reading module, decompressed in reverse, and finally inserted into a specific position in the data frame according to the BT.656 protocol to achieve standard protocol interface timing; the multiple images can be selected through programming. This method can utilize gate arrays to implement the cumbersome BT.656 interface timing, enabling parallel output of multiple images, which can greatly reduce processor utilization. At the same time, it can compress and decompress image data, effectively utilizing the valuable ROM resources of the FPGA.

[0055] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An apparatus for implementing multi-path PAL system picture display based on FPGA, characterized in that, The application relates to a multi-channel parallel picture display channel, each picture display channel comprising a picture selection module, a decompression module, a FIFO cache module, a BT.656 protocol generation module and an encoder output interface module which are sequentially connected, and each picture selection module is connected with n ROM storage modules; each picture display channel stores n picture data in the ROM storage modules according to application requirements, the picture selection module reads the picture data in the ROM storage modules, the decompression module performs reverse decompression processing, the decompressed data is cached in the FIFO cache module, the BT.656 protocol generation module reads the data in the FIFO cache module to generate a BT.656 complete data frame, and the data is output in parallel through the encoder output interface module. The picture stored in the ROM storage module is original picture data read by MATLAB and compressed by an RLE compression algorithm, and a file in the FPGA ROM format is generated.

2. The device for implementing multi-PAL mode picture display based on FPGA according to claim 1, wherein, The format of the data compressed by the RLE compression algorithm is as follows: sampling data; repetition times; sampling data; repetition times;...; sampling data; repetition times. The decompression module is an RLE decompression.

3. The device for implementing multi-PAL mode picture display based on FPGA according to claim 2, wherein, The BT.656 complete data frame generated by the BT.656 protocol generation module further comprises line field synchronization data, blanking data, timing reference code and output image data.

4. The device for implementing multi-PAL mode picture display based on FPGA according to claim 3, wherein, The encoder output interface module encodes the received 0 / 1 binary data according to 8bit, converts the data into PAL system analog signals and outputs the data in parallel.

5. The apparatus for implementing multi-PAL mode picture display based on FPGA according to claim 4, wherein, The application further discloses a picture display method comprising the following steps:

6. A method for implementing multi-path PAL system picture display based on FPGA, characterized in that, S1: extracting and processing picture data First, picture data is extracted, and the extracted data is compressed by an RLE compression algorithm to generate a file in the FPGA ROM format; S2: picture selection Each channel stores n picture data according to application requirements, and the used picture is selected through bus configuration according to field application requirements; the FPGA provides decoding selection function to realize picture selection; S3: RLE decompression The decompression module is responsible for coordinating the readout data rate with the ROM reading out the stored picture to realize RLE decompression and cache the decompressed data in the FIFO; S4: FIFO data caching When the FIFO data is cached, the number of cached data in the FIFO is counted to ensure that the data is dynamically stabilized at half the data amount of the FIFO, and the FIFO will not overflow or be read empty; S5: generating a BT.656 complete data frame According to the requirements of the BT.656 protocol, a BT.656 complete data frame is generated, which further comprises line field synchronization data, blanking data, timing reference code and output image data; S6: encoding output The FPGA output interface module is responsible for data encoding, and the received 0 / 1 binary data is encoded according to 8bit and output in parallel. Step S1 comprises the following substeps:

7. The method for implementing multi-PAL mode picture display based on FPGA according to claim 6, wherein, S11: extracting picture data by MATLAB The original picture data is read by MATLAB, and the read data format is RGB; then the data is converted into YCbCr format data by MATLAB; S12: compressing the picture data ​ After the data extraction and conversion, the data is compressed by MATLAB using RLE compression algorithm; S13: generate a file in the storage format of FPGA After the compressed data is obtained according to step S12, it is converted into a data format recognizable by the read-only memory of FPGA, and the data file format of the read-only memory of FPGA includes file header information, compressed data and data padding.

8. The method for implementing multi-PAL mode picture display based on FPGA according to claim 7, wherein, In step S5, one frame of image data in the generated BT.656 complete data frame is composed of a data block of 625 rows and 1 728 bytes per row, wherein rows 23-311 are even field video data, rows 336-624 are odd field video data, and the rest are vertical control signals.

9. The method for implementing multi-PAL mode picture display based on FPGA according to claim 8, characterized in that, In step S6, PAL system picture encoding converts digital encoding into analog signals by using SAA7121; the SAA7121 chip supports PAL and NTSC video systems, and the pixel frequency is 13.5 MHz; the video data pins MP0- MP7 input data are digital video signals in the ITU-R BT.656 format, the Y, Cb and Cr signals are separated by the data management module in the SAA7121 chip, and then the digital video signals are converted into composite video signals by the digital-to-analog conversion module in the chip, and finally output by CVBS.

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