OLED display panel and display device

Abstract

The present application relates to the technical field of display, in particular to an OLED display panel and a display device, a virtual pixel unit, a switch tube opening voltage potential line and a constant voltage potential line are arranged in the non-display area of the display panel, the constant voltage potential line is connected with a constant voltage potential film layer; the virtual pixel unit and the constant voltage potential film layer are both multilayer film structures including a metal layer; a via is arranged on the multilayer film structure, the metal layer of the virtual pixel unit is connected to the metal layer or the anode layer of the constant voltage potential film layer through the via, so that the metal layer of the virtual pixel unit has a constant potential, and the metal layer of the virtual pixel unit is not connected with the switch tube opening voltage potential line. The present application can solve the technical problem that the display panel with a virtual pixel unit is in a large-area metal potential floating or a large-current white screen downtime due to the short circuit between VGH and ELVSS during use.

Description

Technical Field

[0001] This invention relates to the field of display technology, specifically to an OLED display panel and display device. Background Technology

[0002] In the OLED display industry, manufacturers typically place dummy pixels in the non-AA (display pixel area) areas at the edges of the screen. These dummy pixels do not participate in driving the display; their purpose is to improve the dimensional uniformity of the display area array pattern after dry etching. Specifically, because differences in pattern density at the screen edges lead to differences in the plasma gas etching rate, the added dummy pixels can improve the dimensional uniformity of the inner pixel unit array pattern.

[0003] In existing technologies, when setting up dummy pixels, to avoid large-area metal potential floating, the dummy pixel is typically connected to an external potential to reduce the risk of ESD (electro-static discharge). Specifically, a ring around the dummy pixel is shorted with a metal Ti / Al / Ti, and then connected to a constant VGH potential (e.g., +7V). This VGH potential trace also connects to the GIP circuit. Because there is a large area of ​​ITO / Ag / ITO film above the dummy pixel area, the film overlaps with the cathode at the outer ELVSS overlap area, resulting in a low ELVSS potential (e.g., -3V). Normally, the VGH and ELVSS potentials connected to the dummy pixel area do not affect each other. However, due to electrostatic breakdown or foreign objects, a short circuit may occur between the vertical VGH and ELVSS in the dummy pixel area. The VGH potential is pulled low by the ELVSS potential, and in actual measurements, the GIP EM circuit outputs a low level. When the AA area pixel circuit is working, due to the low EM level, the input voltage V... data Continuous writing to the operating voltage VDD generates a large current, eventually causing a white screen and system crash with no display. To address this issue, some manufacturers may adopt a dummy pixel floating solution (i.e., the dummy pixel is not connected to a constant potential externally) or eliminate the dummy pixel altogether. However, these solutions may lead to the risk of localized charge accumulation in the display area array manufacturing process or deterioration in the uniformity of the display area array's graphic size.

[0004] In summary, existing display panels cannot solve the technical problem of using dummy pixels to ensure the uniformity of array graphic size while avoiding large-area metal potential floating or high-current white screen crashes and no display caused by short circuits between VGH and ELVSS when using dummy pixels. Summary of the Invention

[0005] This invention provides an OLED display panel that solves the technical problems of existing display panels with dummy pixels, such as large-area metal potential floating due to the use of dummy pixels or high current white screen crash and no display caused by short circuit between VGH and ELVSS.

[0006] Based on the same inventive concept, embodiments of the present invention also provide a display device.

[0007] On one hand, embodiments of the present invention provide an OLED display panel, the display panel including a display pixel area and a non-display area located at the edge of the display pixel area; the non-display area is provided with a virtual pixel unit, a switching transistor turn-on voltage potential line and a constant voltage potential line, the constant voltage potential line being connected to a constant voltage potential film layer;

[0008] Both the virtual pixel unit and the constant voltage potential film layer are multilayer film structures including metal layers, wherein the constant voltage potential film layer also includes an anode layer; vias are provided on the multilayer film structure, and the metal layer of the virtual pixel unit is connected to the metal layer or the anode layer of the constant voltage potential film layer through the vias, so that the metal layer of the virtual pixel unit has a constant potential, and the metal layer of the virtual pixel unit is not connected to the switching voltage potential line of the switching transistor.

[0009] In a preferred embodiment, the display panel further includes a common metal layer; the virtual pixel unit further includes an insulating layer, and the metal layer, insulating layer and common metal layer of the virtual pixel unit are stacked; the constant voltage potential film layer further includes an insulating layer, and the metal layer, insulating layer and common metal layer of the constant voltage potential film layer are stacked.

[0010] Vias are provided on the insulating layer of the virtual pixel unit and the insulating layer of the constant voltage potential film layer. The metal layer of the virtual pixel unit is connected to the common metal layer through the vias via conductive traces. The metal layer of the constant voltage potential film layer is connected to the common metal layer through the vias via conductive traces.

[0011] More preferably, the conductive trace is a metal trace; the metal trace is disposed on a common metal layer. Even more preferably, the metal trace is a Mo trace, and the metal layer is a Ti / Al / Ti film.

[0012] In a preferred embodiment, the constant voltage potential film layer includes a cathode layer, an anode layer, a planarization layer, a fourth metal layer, a third metal layer, an insulating layer, a second metal layer, and a first metal layer stacked sequentially; the common metal layer is either the second metal layer or the first metal layer; the third metal layer of the constant voltage potential film layer is connected to the first metal layer or the second metal layer through a via.

[0013] In a preferred embodiment, the virtual pixel unit includes a third metal layer, an insulating layer, a second metal layer, and a first metal layer; the common metal layer is either the second metal layer or the first metal layer; the third metal layer of the virtual pixel unit is connected to the first metal layer or the second metal layer through a via.

[0014] In a preferred embodiment, the virtual pixel unit further includes a planarization layer stacked on the metal layer, with vias provided on the planarization layer and the vias filled with conductive connectors, so that the metal layer of the virtual pixel unit is connected to the anode layer of the constant voltage potential film layer.

[0015] More preferably, the connector is made of the same conductive metal material as the anode layer of the constant voltage potential film; even more preferably, the anode layer is an ITO / Ag / ITO film and the metal layer is a Ti / Al / Ti film.

[0016] In a preferred embodiment of the present invention, the switching transistor turn-on voltage potential line is the VGH potential line, and the constant voltage potential line is the ELVSS signal line.

[0017] On the other hand, based on the same inventive concept, embodiments of the present invention also provide a display device, the display device including the display panel provided in embodiments of the present invention.

[0018] Compared with existing technologies, the OLED display panel and display device provided in this invention, by connecting the ELVSS potential to the dummy pixel area, can maintain a constant dummy pixel potential and avoid static electricity accumulation caused by large-area metal potential floating. Furthermore, the traces of the dummy pixel and the VGH potential are not connected, preventing a high-current white screen crash and no display caused by a short circuit between VGH and ELVSS due to electrostatic breakdown or foreign objects occurring during the manufacturing process of the display area array. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of an OLED display panel in one embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the ELVSS potential film layer structure of an OLED display panel in one embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of a virtual pixel unit in an OLED display panel connected to the ELVSS potential film layer in one embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the virtual pixel unit film layer structure of an OLED display panel in another embodiment of the present invention;

[0024] Figure descriptions: 1. ELVSS signal line, 2. VGH potential line, 21. Cathode layer, 22. Anode layer, 23. PLN layer, 24. Fourth metal layer, 25. Third metal layer, 26. Inorganic film layer, 27. Via, 28. First or second metal layer, 3. Virtual pixel unit, 31. First or second metal layer, 32. Third metal layer, 33. First PLN layer, 34. Fourth metal layer, 35. Second PLN layer, 36. ITO / Ag / ITO film layer, 4. Display pixel unit, 5. GIP circuit. Detailed Implementation

[0025] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present invention and not to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present invention by illustrating examples of the invention.

[0026] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of this invention can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0028] Example 1

[0029] like Figure 1 As shown, the display panel provided in this embodiment includes a display pixel area and a non-display area located at the edge of the display pixel area. The display pixel area is arrayed with display pixel units 4, and the non-display area is provided with dummy pixel units 3, GIP circuits 5, a VGH potential line 2, and an ELVSS signal line 1. The VGH potential line provides the turn-on voltage for the switching transistors of the display pixel units, and is also connected to the GIP circuits related to driving the screen display. The ELVSS potential is lower than the VGH potential.

[0030] To ensure the uniformity of the array pattern size, this embodiment sets multiple vias on the inorganic film layer of the ELVSS potential and the virtual pixel unit, respectively. Traces are then run within these vias to connect the third metal layer (M3) of the ELVSS potential to the first metal layer (M1) or the second metal layer (M2). This connects the third metal layer (M3) of the virtual pixel unit to the first metal layer (M1) or the second metal layer (M2), allowing the third metal layer of the virtual pixel unit to directly connect to the area near the screen bezel with the ELVSS potential film layer. This ensures the virtual pixel unit is connected to the ELVSS potential and has a constant potential. Furthermore, the virtual pixel unit is not connected to the VGH, meaning it is also not connected to the GIP circuit, thus not affecting the display.

[0031] In this embodiment, the ELVSS signal line is connected to an ELVSS potential film layer with a multilayer film structure. The ELVSS potential film layer, located near the screen frame, has a multilayer film structure with a Ti / Al / Ti–ITO / Ag / ITO cathode. Figure 2 As shown, the ELVSS potential film layer includes a cathode layer 21, an anode layer 22, a planarization layer (PLN) 23, a fourth metal layer 24, a third metal layer 25, an insulating layer 26, a second metal layer, and a first metal layer, which are stacked sequentially. The ELVSS signal line is connected to the cathode layer. A via 27 is provided on the inorganic film layer, and the third metal layer 25 is connected to the first metal layer or the second metal layer 28 through the via. The third metal layer 25 is in contact with the fourth metal layer 24, and the fourth metal layer 24 is connected to the anode layer 22. The anode layer 22 is connected to the cathode layer 21 at an opening on the planarization layer (PLN) 23. For ease of description, the first metal layer and the second metal layer are both represented by the reference numeral 28 in the accompanying drawings, that is, 28 represents the second metal layer or the first metal layer of the virtual pixel unit. The insulating layer 26 can be an inorganic film layer such as an ILD.

[0032] Meanwhile, the virtual pixel unit also has a multilayer film structure, including a third metal layer, an insulating layer, a second metal layer, and a first metal layer; among which, the second metal layer and the first metal layer are shared with the ELVSS potential film layer, serving as common metal layers. Vias are also provided on the inorganic film layer of the virtual pixel unit, and the third metal layer of the virtual pixel unit is connected to the first metal layer or the second metal layer through these vias, thereby allowing the third metal layer of the virtual pixel unit to connect to the region containing the ELVSS potential film layer through the vias, such as... Figure 3 As shown. Similarly, the insulating layer of the virtual pixel unit can also be an inorganic film layer such as ILD.

[0033] In a preferred embodiment, the third metal layer of the virtual pixel unit can be a Ti / Al / Ti film layer surrounding the virtual pixel. Metal traces (which can be Mo metal traces) are provided on the first or second metal layer. One end of the metal traces is connected to the Ti / Al / Ti film layer surrounding the virtual pixel, and the other end of the metal traces is connected to the region of the film layer with ELVSS potential.

[0034] It should be noted that the metal used for wiring in the specific embodiments of the present invention is not limited to Mo, but can also be other conductive metal materials, such as copper, aluminum, and their conductive metal oxides and alloys. The planarization layer (PLN3) has insulating properties, which can separate adjacent film layers and ensure the effectiveness of electrical signal transmission between adjacent film layers.

[0035] In Example 1, even if there is process electrostatic breakdown or foreign matter causing a short circuit in the film layer in the Dummy Pixel area, the Ti / Al / Ti film layer of the Dummy Pixel already has an ELVSS potential and is not connected to the GIP circuit, so it will not affect the display.

[0036] Example 2

[0037] like Figure 1 As shown, the display panel provided in this embodiment includes a display pixel area and a non-display area located at the edge of the display pixel area. The display pixel area is arrayed with display pixel units 4, and the non-display area is provided with dummy pixel units 3, GIP circuits 5, a VGH potential line 2, and an ELVSS signal line 1. The VGH potential line provides the turn-on voltage for the switching transistors of the display pixel units, and is also connected to the GIP circuits related to driving the screen display. The ELVSS potential is lower than the VGH potential.

[0038] In this embodiment, the ELVSS signal line is connected to an ELVSS potential film layer with a multilayer film structure. The ELVSS potential film layer, located near the screen frame, has a multilayer film structure with a Ti / Al / Ti–ITO / Ag / ITO cathode. The ELVSS potential film layer includes a cathode layer, an anode layer, a planarization layer (PLN), a fourth metal layer, a third metal layer, an insulating layer, a second metal layer, and a first metal layer, which are stacked sequentially. The ELVSS signal line is connected to the cathode layer. The insulating layer can be an inorganic film layer such as an ILD (Inorganic Liquid Crystal Layer).

[0039] In this embodiment, to ensure the uniformity of array pattern size, the virtual pixel unit is connected to the ITO / Ag / ITO film layer by setting vias on the planarization layer. That is, the fourth metal layer is connected to the anode layer through vias, and the anode layer is connected to the cathode layer, so that the virtual pixel unit has a constant low ELVSS potential; and the virtual pixel unit is not connected to VGH, that is, the virtual pixel unit is not connected to the GIP circuit.

[0040] In this embodiment, the virtual pixel unit has a multilayer film structure, such as Figure 4As shown, the structure includes a second planarization layer (PLN) 35, a fourth metal layer 34, a first planarization layer (PLN) 33, a third metal layer 32, a second metal layer, and a first metal layer stacked sequentially. Vias are formed in the second planarization layer 35, with multiple vias filled with connectors, connecting the fourth metal layer to the upper ITO / Ag / ITO film layer with an ELVSS potential. This allows the fourth metal layer of the virtual pixel unit to possess an ELVSS potential, and the virtual pixel unit is not connected to the VGH. In this embodiment, both the third and fourth metal layers can be selected as Ti / Al / Ti film layers. For ease of description, the first and second metal layers are both denoted by the reference numeral 31 in the accompanying drawings, where 31 represents either the second or first metal layer of the virtual pixel unit.

[0041] More preferably, the connector filled in the via is an ITO / Ag / ITO film layer, that is, the ITO / Ag / ITO film layer 36 extends into the via provided on the second planarization layer, so that the multilayer film structure of the virtual pixel unit has an ELVSS potential, is easy to manufacture, and has a more stable structure.

[0042] It should be noted that, in specific embodiments of the present invention, the connector is not limited to a mixture of ITO / Ag / ITO films, but can also be other conductive metal materials, such as copper, aluminum, molybdenum and their conductive metal oxides and alloys.

[0043] In Example 2, the M4 film layer in the Dummy Pixel is directly connected to the upper ELVSS potential film layer and has the same ELVSS potential as the upper film layer. It is not connected to the GIP circuit and will not affect the display.

[0044] In this embodiment, the PLN layer (planarization layer) is insulating and can separate adjacent film layers, ensuring the effectiveness of electrical signal transmission between adjacent film layers. Exemplarily, the first planarization layer 33 and the second planarization layer 35 can be made of insulating Resin layers. The ITO layer is a film layer containing ITO (indium tin oxide) material, commonly used in various touch screens for current conduction, and has good conductivity.

[0045] Example 3

[0046] Based on the same inventive concept as Embodiments 1 and 2, this embodiment provides a display device. This display device is any electronic device with display function that includes the display panel of Embodiment 1 or 2, including but not limited to mobile phones, tablets, laptops, televisions, display walls, etc. The structure of the display panel has been described in detail in the above embodiments, and will not be repeated here for the sake of brevity.

[0047] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0048] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0049] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An OLED display panel, comprising a display pixel area and a non-display area located at the edge of the display pixel area; wherein the non-display area is provided with a virtual pixel unit, a switching transistor turn-on voltage potential line and a constant voltage potential line, the constant voltage potential line being connected to a constant voltage potential film layer, characterized in that: Both the virtual pixel unit and the constant voltage potential film layer are multilayer film structures including metal layers, wherein the constant voltage potential film layer also includes an anode layer; vias are provided on the multilayer film structure, and the metal layer of the virtual pixel unit is connected to the metal layer or the anode layer of the constant voltage potential film layer through the vias, so that the metal layer of the virtual pixel unit has a constant potential, and the metal layer of the virtual pixel unit is not connected to the switching voltage potential line of the switching transistor.

2. The OLED display panel according to claim 1, characterized in that, The display panel further includes a common metal layer; the virtual pixel unit further includes an insulating layer, and the metal layer, insulating layer and common metal layer of the virtual pixel unit are stacked; the constant voltage potential film layer further includes an insulating layer, and the metal layer, insulating layer and common metal layer of the constant voltage potential film layer are stacked. Vias are provided on the insulating layer of the virtual pixel unit and the insulating layer of the constant voltage potential film layer. The metal layer of the virtual pixel unit is connected to the common metal layer through the vias via conductive traces. The metal layer of the constant voltage potential film layer is connected to the common metal layer through the vias via conductive traces.

3. The OLED display panel according to claim 2, characterized in that, The conductive traces are metal traces; the metal traces are placed on a common metal layer.

4. The OLED display panel according to claim 3, characterized in that, The metal trace is a Mo metal trace, and the metal layer is a Ti / Al / Ti film.

5. The OLED display panel according to claim 2, characterized in that, The constant voltage potential film layer includes a cathode layer, an anode layer, a planarization layer, a fourth metal layer, a third metal layer, an insulating layer, a second metal layer, and a first metal layer stacked sequentially; the common metal layer is either the second metal layer or the first metal layer; the third metal layer of the constant voltage potential film layer is connected to the first metal layer or the second metal layer through a via.

6. The OLED display panel according to claim 2, characterized in that, The virtual pixel unit includes a third metal layer, an insulating layer, a second metal layer, and a first metal layer; the common metal layer is either the second metal layer or the first metal layer; the third metal layer of the virtual pixel unit is connected to the first metal layer or the second metal layer through a via.

7. The OLED display panel according to claim 1, characterized in that, The virtual pixel unit also includes a planarization layer stacked on the metal layer, with vias provided on the planarization layer and the vias filled with conductive connectors, so that the metal layer of the virtual pixel unit is connected to the anode layer of the constant voltage potential film.

8. The OLED display panel according to claim 7, characterized in that, The connector is made of the same conductive metal material as the anode layer of the constant voltage potential film.

9. The OLED display panel according to claim 8, characterized in that, The anode layer is an ITO / Ag / ITO film, and the metal layer is a Ti / Al / Ti film.

10. The OLED display panel according to any one of claims 1-9, characterized in that, The switching transistor turn-on voltage potential line is the VGH potential line, and the constant voltage potential line is the ELVSS signal line.

11. The OLED display panel according to any one of claims 1-9, characterized in that, The number of vias on the multilayer film structure of the virtual pixel unit and the number of vias on the multilayer film structure of the constant voltage potential film are both multiple.

12. A display device, characterized in that, The display device includes a display panel as claimed in any one of claims 1-11.

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