Display substrate, manufacturing method thereof and display device

Abstract

A display substrate, a manufacturing method thereof and a display device. The display substrate includes a display area, a non-display area and an extension. The display area includes display pixels, and the non-display area at least partially surrounds the display area. The display substrate includes a substrate, the extension, a first insulating layer and a conductive structure. The substrate is located in the display area, the non-display area and the extension, and includes a bendable portion located in the non-display area and away from an edge of the display area. The display substrate has a first side for display and a second side opposite to the first side. The extension is connected with the bendable portion and is bendable to the second side of the display substrate through the bendable portion. The first insulating layer is at least partially located on the extension and includes an opening. The conductive structure is located in the extension and includes a lower portion and an upper portion. The lower portion is located on a side of the upper portion close to the substrate, and the opening exposes at least part of the lower portion. The upper portion is located on a side of the lower portion away from the substrate, is at least partially located in the opening and is in direct contact with the lower portion.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] Active-matrix organic light-emitting diode (AMOLED) displays offer advantages over traditional liquid crystal displays (LCDs) such as self-illumination, wide color gamut, high contrast, and thinness, making them widely used in mobile phones, tablets, and flexible wearable devices like smartwatches. Typically, pixel circuits are located in the display area, while gate driving circuits, such as GOA driving circuits, are located in the non-display area to provide driving signals to the pixel circuits. Additionally, integrated circuit boards and flexible circuit boards are often located in the non-display area to provide detection signals for the display substrate and driving signals for the driving circuits. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate, the display substrate including a display area, a non-display area, and an extension; the display area includes display pixels, and the non-display area at least partially surrounds the display area; the display substrate includes a substrate, a first insulating layer, and a conductive structure. The substrate is located in the display area, the non-display area, and the extension, and includes a bendable portion located at an edge of the non-display area away from the display area; the display substrate has a first side for display and a second side opposite to the first side, the extension is connected to the bendable portion and is bendable to the second side of the display substrate through the bendable portion; the first insulating layer is at least partially located on the extension and includes an opening; the conductive structure is located in the extension and includes a lower portion and an upper portion; the opening exposes at least a portion of the lower portion; the upper portion is located on the side of the lower portion away from the substrate, at least partially located in the opening, and in direct contact with the lower portion.

[0004] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a pixel circuit, a driving circuit, and a detection lead. The pixel circuit is located in the display area and configured to control the display state of the display pixels; the driving circuit is at least partially located in the non-display area and includes a driving signal line at least partially located in the non-display area, the driving signal line being configured to provide a driving signal to the pixel circuit; the detection lead is electrically connected to the driving signal line and configured to provide a detection signal to the driving signal line, extending from the non-display area of ​​the display substrate through the bending area to an extension of the display substrate, and the detection lead includes a protective portion, the conductive structure includes the protective portion, the lower portion includes a first lower portion, the opening includes a first opening, and the first opening exposes at least a portion of the first lower portion; the upper portion includes a first upper portion, the first upper portion and the first lower portion are stacked in a direction perpendicular to the substrate and located on the side of the first lower portion away from the substrate, the first upper portion is at least partially located in the first opening and in direct contact with the first lower portion; and the protective portion includes the first lower portion and the first upper portion.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the first upper part on the substrate substantially coincides with the orthographic projection of the first opening on the substrate.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, the first upper portion includes an interior and an exterior. The interior is located within the first opening and is in direct contact with the first lower portion; the exterior is located outside the first opening, wherein the first insulating layer is located between the exterior and the first lower portion, and the lower surface of the exterior near the substrate is in direct contact with the first insulating layer.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the first upper portion covers the first lower portion, and the first upper portion and the first lower portion are located within the first opening.

[0008] For example, at least one embodiment of the present disclosure provides a display substrate that further includes an integrated circuit board and a first pin. The integrated circuit board is located in the extension and configured to provide the drive signal to the drive circuit, the extension having an edge extending in a first direction; the conductive structure includes the first pin, the lower portion includes a second lower portion, the opening includes a second opening, and the second opening exposes at least a portion of the second lower portion; the upper portion includes a second upper portion, the second upper portion and the second lower portion are stacked in a direction perpendicular to the substrate and located on the side of the second lower portion away from the substrate, the second upper portion is at least partially located in the second opening, the lower surface of the second upper portion near the substrate is in direct contact with the second lower portion, and the orthographic projection of the second upper portion on the substrate is located within the orthographic projection of the second opening on the substrate; the first pin includes a second lower portion and a second upper portion; an integrated circuit board pin is provided on the integrated circuit board, and the upper surface of the second upper portion of the first pin away from the substrate is in direct contact with the integrated circuit board pin.

[0009] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a flexible circuit board and a second pin. A flexible circuit board is located in the extension portion. At least a portion of the flexible circuit board is connected to the detection lead and configured to provide the detection signal to the detection lead, and is connected to the integrated circuit board and configured to provide the integrated circuit board with an electrical signal for generating the drive signal. A second pin is connected to the flexible circuit board and includes a first portion of the pin, which is connected to the detection lead. The lower portion includes a third lower portion, and the opening includes a third opening, which exposes at least a portion of the third lower portion. The upper portion includes a third upper portion, which is stacked with the third lower portion in a direction perpendicular to the substrate and located on the side of the third lower portion away from the substrate. The third upper portion is at least partially located in the third opening, and the lower surface of the third upper portion near the substrate is in direct contact with the third lower portion. The orthographic projection of the third upper portion on the substrate substantially coincides with the orthographic projection of the third opening on the substrate. The second pin includes the third lower portion and the third upper portion. A flexible circuit board pin is provided on the flexible circuit board, and the upper surface of the third upper portion of the second pin away from the substrate is in direct contact with the flexible circuit board pin.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the protective portion includes a first protective portion, the first lower portion includes a first sub-lower portion, the first opening includes a first sub-opening, and the first sub-opening exposes at least a portion of the first sub-lower portion; the first upper portion includes a first sub-upper portion, the first sub-upper portion and the first sub-lower portion are stacked in a direction perpendicular to the substrate and located on the side of the first sub-lower portion away from the substrate, the first sub-upper portion is at least partially located in the first sub-opening and is in direct contact with the first sub-lower portion; the first protective portion includes the first sub-lower portion and the second sub-upper portion, the detection lead has an end that is in direct contact with the corresponding second pin, and the end has the first protective portion.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the protective portion includes a second protective portion, the second lower portion includes a second sub-lower portion, the first opening includes a second sub-opening, and the second sub-opening exposes at least a portion of the second sub-lower portion; the second upper portion includes a second sub-upper portion, the second sub-upper portion and the second sub-lower portion are stacked in a direction perpendicular to the substrate and located on the side of the second sub-lower portion away from the substrate, the second sub-upper portion is at least partially located in the second sub-opening and in direct contact with the second sub-lower portion; the second protective portion includes the second sub-lower portion and the second sub-upper portion; the extension portion has an edge opposite to the bendable portion and extending along a first direction, in the first direction, the detection lead is located on at least one side of the integrated circuit board, the detection lead includes a first detection lead near the integrated circuit board, the first detection lead has a first protective portion and a second protective portion, the second protective portion of the first detection lead is connected to the first protective portion of the first detection lead and is located on the side of the first protective portion of the first detection lead away from the second pin.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the second direction is located in the same plane as the first direction and intersects with the first direction; the first detection lead has an overlapping portion that overlaps with the first pin in the second direction, the overlapping portion including the second lower sub-part and the second upper sub-part.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, for the first detection lead, the overlapping portion is located on the side of the end away from the second pin, and the overlapping portion is connected to the second pin via the end.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the first detection lead includes an inclined portion intersecting the first direction, and the inclined portion includes the overlapping portion.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the display substrate includes a plurality of second pins arranged along the first direction; the display substrate includes a plurality of detection leads, and the first portion of the pins of the plurality of second pins is connected to the plurality of detection leads in a one-to-one correspondence; the flexible circuit board is provided with a plurality of flexible circuit board pins arranged along the first direction, and the plurality of second pins are connected to the plurality of flexible circuit board pins in a one-to-one correspondence.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the third upper portion of at least one of the plurality of second pins and the first upper portion of the corresponding detection lead are integrally formed.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the first pin includes an input pin and an output pin, and both the input pin and the output pin include a second upper part and a second lower part; the second upper part of the input pin is electrically connected to the third upper part of the second pin.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the second direction is located on the same plane as the first direction and intersects with the first direction. In the second direction, the flexible circuit board is located on the side of the detection lead and the integrated circuit board near the edge of the extension. In the second direction, the plurality of input pins, the plurality of output pins, and the plurality of second pins are arranged at intervals from each other, and the plurality of input pins are located between the plurality of output pins and the plurality of second pins. The display substrate also includes a plurality of connection electrodes, which are disposed on the same layer as the second upper part and the third upper part. The plurality of connection electrodes electrically connect the second upper part of the plurality of input pins to the third upper part of the plurality of second pins one-to-one across the interval between the plurality of input pins and the plurality of second pins.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit includes a power line. The power line includes a portion located in the extension and is configured to provide a power supply voltage to the pixel circuit and is electrically connected to a portion of a plurality of second pins of the flexible circuit board configured to provide a power supply voltage to the pixel circuit. The conductive structure includes the portion of the power line located in the extension. The lower portion includes a fourth lower portion, and the opening includes a fourth opening that exposes at least a portion of the fourth lower portion. The upper portion includes a fourth upper portion, which is stacked with the fourth lower portion in a direction perpendicular to the substrate and located on the side of the fourth lower portion away from the substrate. The fourth upper portion is at least partially located in the fourth opening. The lower surface of the fourth upper portion near the substrate is in direct contact with the fourth lower portion. The orthographic projection of the fourth upper portion onto the substrate substantially coincides with the orthographic projection of the fourth opening onto the substrate. The portion of the power line located in the extension includes the fourth upper portion and the fourth lower portion.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the power line includes a first power line and a second power line. The first power line is configured to provide a first power supply voltage to the display pixel; the second power line is configured to provide a second power supply voltage to the display pixel, wherein the second power supply voltage has the opposite polarity to the first power supply voltage; the first power line and the second power line each include a first portion located in the extension, and at least one of the first portion of the first power line and the first portion of the second power line includes the fourth lower portion and the fourth upper portion.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the display substrate further includes an electrostatic discharge (ESD) shielding unit located on the extension and configured to shield the electrostatic interference of the detection lead. The conductive structure includes the ESD shielding unit, the lower portion includes a fifth lower portion, the opening includes a fifth opening, and the fifth opening exposes at least a portion of the fifth lower portion; the upper portion includes a fifth upper portion, the fifth upper portion and the fifth lower portion are stacked in a direction perpendicular to the substrate and located on the side of the fifth lower portion away from the substrate, the fifth upper portion is at least partially located in the fifth opening, the lower surface of the fifth upper portion near the substrate is in direct contact with the fifth lower portion, and the orthographic projection of the fifth upper portion on the substrate substantially coincides with the orthographic projection of the fifth opening on the substrate; and the ESD shielding unit includes the fifth lower portion and the fifth upper portion.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit further includes a light-emitting device and a driving transistor, a data writing transistor, a first gate line and a data line; the data writing transistor is configured to transmit a data signal transmitted on the data line to the driving transistor under the control of a first scan signal transmitted on the first gate line; the driving transistor is configured to control the magnitude of the driving current flowing through the driving transistor according to the data signal; the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the data line is disposed on the same layer as the upper part.

[0023] For example, in a display substrate provided in at least one embodiment of this disclosure, the first power supply voltage provided by the first power line is a low potential voltage, and the second power supply voltage provided by the second power line is a high potential voltage; the first power line also includes a second portion located in the display pixel of the display area, and the second portion of the first power line is disposed on the same layer as the upper part.

[0024] At least one embodiment of this disclosure also provides a display device, which includes any of the above-described display substrates.

[0025] At least one embodiment of this disclosure also provides a method for manufacturing a display substrate, the display substrate including a display area, a non-display area, and an extension, wherein the display area includes display pixels, and the non-display area at least partially surrounds the display area; the manufacturing method includes: providing a substrate, wherein the substrate is located on the display area, the non-display area, and the extension, and includes a bendable portion located at an edge of the non-display area away from the display area; the display substrate has a first side for display and a second side opposite to the first side, the extension is connected to the bendable portion and bendable to the second side of the display substrate through the bendable portion; forming a first insulating layer at least on the extension, and forming an opening in the first insulating layer; forming a conductive structure on the extension, the conductive structure including: forming a lower portion, wherein the opening exposes at least a portion of the lower portion; and forming an upper portion, wherein the upper portion and the lower portion are stacked in a direction perpendicular to the substrate and located on the side of the lower portion away from the substrate, at least partially located in the opening and in direct contact with the lower portion.

[0026] For example, in a method for fabricating a display substrate provided in at least one embodiment of this disclosure, forming the conductive structure includes: forming a first conductive material layer; performing a first patterning process on the first conductive material layer to form the lower portion; forming a first insulating material layer covering the lower portion, wherein the first insulating material layer is in direct contact with the lower portion; performing a second patterning process on the first insulating material layer to form an intermediate insulating layer, wherein the intermediate insulating layer includes an opening region that exposes at least a portion of the lower portion; forming a second metal material layer on the side of the intermediate insulating layer away from the substrate, wherein the second metal material layer includes a first portion located within the opening region and a second portion located outside the opening region, the first portion being in direct contact with the lower portion, and the lower surface of the second portion near the substrate being in direct contact with the upper surface of the first insulating material layer away from the substrate; and performing a third patterning process on the second metal material layer to form the upper portion, wherein the opening region is used to form an opening of the conductive structure.

[0027] For example, the method for manufacturing a display substrate provided in at least one embodiment of this disclosure further includes: forming a second insulating material layer covering the upper portion and the opening area, wherein the second insulating material layer is in direct contact with the lower portion; and performing a fourth patterning process on the second insulating material layer to form the opening and the first insulating layer.

[0028] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the method further includes: forming a pixel circuit, wherein the pixel circuit is configured to control the display state of the display pixels; forming a driving circuit, wherein the driving circuit is at least partially located in the non-display area and includes a driving signal line located in the non-display area, the driving signal line being configured to provide a driving signal to the pixel circuit; forming a detection lead, wherein the detection lead is electrically connected to the driving signal line and configured to provide a detection signal to the driving signal line, and extends from the non-display area of ​​the display substrate through the bending area to an extension portion of the display substrate; the detection lead includes a protective portion, the lower portion includes a first lower portion, the opening includes a first opening, and the first opening exposes at least a portion of the first lower portion; the upper portion includes a first upper portion, the first upper portion and the first lower portion are stacked in a direction perpendicular to the substrate and located on the side of the first lower portion away from the substrate, the first upper portion is at least partially located in the first opening and in direct contact with the first lower portion; and the protective portion includes The extension includes a first lower portion and a first upper portion; an integrated circuit board is provided on the extension, wherein the integrated circuit board is located on the extension and configured to provide the drive signal to the drive circuit, wherein the extension has an edge extending in a first direction; and a first pin is formed on the extension, wherein the conductive structure includes the first pin, the lower portion includes a second lower portion, the opening includes a second opening, and the second opening exposes at least a portion of the second lower portion; the upper portion includes a second upper portion, the second upper portion and the second lower portion are stacked in a direction perpendicular to the substrate and located on the side of the second lower portion away from the substrate, the second upper portion is at least partially located in the second opening, the lower surface of the second upper portion near the substrate is in direct contact with the second lower portion, and the orthographic projection of the second upper portion on the substrate is located within the orthographic projection of the second opening on the substrate; the first pin includes a second lower portion and a second upper portion; the opening region includes a first opening region, the first opening region exposing the second lower portions of the plurality of first pins and the first lower portion of the at least partial detection lead.

[0029] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the method further includes: providing a flexible circuit board in the extension portion, wherein the flexible circuit board is located connected to the detection lead and configured to provide the detection signal to the detection lead, and connected to the integrated circuit board and configured to provide the integrated circuit board with an electrical signal for generating the drive signal; and forming a second pin on the extension portion, wherein the second pin is connected to the flexible circuit board, the second pin includes a first portion pin, the first portion pin is connected to the detection lead, wherein the conductive structure includes the second pin, the second pin includes a third lower portion, the lower portion includes the third lower portion; the opening region further includes a second opening region, the first opening region is connected to and communicates with the second opening region, and the second opening region exposes the third lower portion.

[0030] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the protective portion includes a first protective portion, the first lower portion includes a first sub-lower portion, the first opening includes a first sub-opening, and the first sub-opening exposes at least a portion of the first sub-lower portion; the first upper portion includes a first sub-upper portion, the first sub-upper portion and the first sub-lower portion are stacked in a direction perpendicular to the substrate and located on the side of the first sub-lower portion away from the substrate, the first sub-upper portion is at least partially located in the first sub-opening and in direct contact with the first sub-lower portion; the first protective portion includes the first sub-lower portion and the second sub-upper portion; the detection lead has an end that is in direct contact with the second pin, the end having the first protective portion; the first opening area exposes the second lower portion of the plurality of first pins and the first sub-lower portion of the end.

[0031] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the protective portion includes a second protective portion, the second lower portion includes a second sub-lower portion, the first opening includes a second sub-opening, and the second sub-opening exposes at least a portion of the second sub-lower portion; the second upper portion includes a second sub-upper portion, the second sub-upper portion and the second sub-lower portion are stacked in a direction perpendicular to the substrate and located on the side of the second sub-lower portion away from the substrate, the second sub-upper portion is at least partially located in the second sub-opening and in direct contact with the second sub-lower portion; the second protective portion includes the second sub-lower portion and the second sub-upper portion; in the first direction, the detection lead is located on one side of the integrated circuit board, the plurality of detection leads include a first detection lead close to the integrated circuit board, the second direction is in the same plane as the first direction and intersects the first direction, the first detection lead has an overlapping portion that overlaps with the first pin in the second direction, the overlapping portion has a second sub-lower portion and a second sub-upper portion; the first opening area exposes the second lower portion of the plurality of first pins and the second sub-lower portion of the overlapping portion.

[0032] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, for the first detection lead, the overlapping portion is located on the side of the end away from the second pin, and the overlapping portion is connected to the second pin via the end.

[0033] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the first opening region includes a first edge and a second edge. The first edge extends generally along the first direction and is the boundary between the first opening region and the second opening region; the second edge intersects with the first edge and overlaps with the first lower portion in a direction perpendicular to the substrate; the angle between the first edge and the second edge is an angle region, and the second lower portion is located in the angle region.

[0034] For example, in the method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the planar shape of the first opening area is a first rectangle, the planar shape of the second opening area is a second rectangle, the length of the first rectangle along the first direction is less than the length of the second rectangle along the first direction, and the overall planar shape of the first opening area and the second opening area is T-shaped.

[0035] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the integrated circuit board is provided with integrated circuit board pins, and the flexible circuit board is provided with flexible circuit board pins; providing the integrated circuit board on the extension includes: binding the integrated circuit board to the substrate so that the first pin corresponds to the integrated circuit board pin, and the upper surface of the second upper part of the first pin away from the substrate is in direct contact with the corresponding integrated circuit board pin; providing the flexible circuit board on the extension includes: binding the flexible circuit board to the substrate so that the plurality of second pins correspond one-to-one with the plurality of flexible circuit board pins, and the upper surface of the third upper part of each of the plurality of second pins away from the substrate is in direct contact with the corresponding flexible circuit board pin.

[0036] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the method further includes forming a pixel circuit, the pixel circuit further including: a light-emitting device and a driving transistor, a data writing transistor, a first gate line and a data line; the data writing transistor is configured to transmit a data signal transmitted on the data line to the driving transistor under the control of a first scan signal transmitted on the first gate line, the driving transistor is configured to control the magnitude of a driving current flowing through the driving transistor according to the data signal, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light; the method for manufacturing the display substrate includes: forming the upper part and the data line by performing the third patterning process on the second conductive material layer.

[0037] For example, in a method for manufacturing a display substrate provided in at least one embodiment of this disclosure, the pixel circuit includes a first power line and a second power line. The first power line is configured to provide a first power supply voltage to the display pixel; the second power line is configured to provide a second power supply voltage to the display pixel, wherein the first power supply voltage is a low potential voltage and the second power supply voltage is a high potential voltage; the first power line includes a first portion located on the extension portion and a second portion located in the display pixel of the display area; the method for manufacturing the display substrate includes: further forming the second portion of the first power line by performing the third patterning process on the second conductive material layer. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0039] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0040] Figure 2 for Figure 1 A schematic cross-sectional view of the display area of ​​the display substrate along line I-I'.

[0041] Figure 3A for Figure 1 A schematic diagram of a portion D including the drive signal line;

[0042] Figure 3B This is a schematic diagram of clock signal lines and multiple shift registers;

[0043] Figure 4A An equivalent circuit diagram of a pixel circuit of a display substrate provided in an embodiment of this disclosure;

[0044] Figure 4B An equivalent circuit diagram of another pixel circuit of a display substrate provided in an embodiment of this disclosure;

[0045] Figure 5A for Figure 1 The enlarged planar schematic diagram of a portion E of the bending area and extension of the display substrate shown includes a first conductive layer, a first insulating layer and a second conductive layer.

[0046] Figure 5B During the manufacturing process of the display substrate, a process is formed Figure 5A A schematic diagram of the structure after performing a second patterning process on the first insulating material layer to form an opening region;

[0047] Figure 5C for Figure 5B A schematic diagram of the first and second opening regions in the opening area;

[0048] Figure 5D for Figure 5A A planar schematic diagram of the second conductive layer in the middle;

[0049] Figure 6A for Figure 5A An enlarged schematic diagram of a portion L in the diagram, which includes a first conductive layer, a first insulating layer, and a second conductive layer;

[0050] Figure 6B During the manufacturing process of the display substrate, a process is formed Figure 6A A schematic diagram of the structure after performing a second patterning process on the first insulating material layer to form an opening region;

[0051] Figure 6C for Figure 6A A planar schematic diagram of the second conductive layer in the middle;

[0052] Figure 7A This is a cross-sectional schematic diagram of a conductive structure provided in an embodiment of the present disclosure;

[0053] Figure 7B For along Figure 6A A schematic diagram of the cross-section of line A-A' in the diagram;

[0054] Figure 7C For along Figure 6A A schematic diagram of the cross-section of line B-B' in the diagram;

[0055] Figure 7D For along Figure 6A A cross-sectional diagram of line C-C' in the diagram;

[0056] Figure 7E For along Figure 6A A schematic diagram of the cross-section of line D-D' in the diagram;

[0057] Figure 7F For along Figure 5A A schematic diagram of the cross-section of line E-E' in the diagram;

[0058] Figure 7G For along Figure 6A Another cross-sectional diagram of line A-A' in the diagram;

[0059] Figure 7H For along Figure 6A Another cross-sectional diagram of line A-A' in the diagram;

[0060] Figures 8A-8H This is a schematic diagram illustrating a method for fabricating a conductive structure according to an embodiment of the present disclosure;

[0061] Figures 9A-9E A schematic diagram illustrating a method for fabricating another conductive structure according to an embodiment of this disclosure;

[0062] Figure 10 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The embodiments described below are some, but not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0065] At least one embodiment of this disclosure provides a display substrate, the display substrate including a display area, a non-display area, and an extension; the display area includes display pixels, and the non-display area at least partially surrounds the display area; the display substrate includes a substrate, a first insulating layer, and a conductive structure. The substrate is located in the display area, the non-display area, and the extension, and includes a bendable portion located at an edge of the non-display area away from the display area; the display substrate has a first side for display and a second side opposite to the first side, the extension is connected to the bendable portion and is bendable to the second side of the display substrate through the bendable portion; the first insulating layer is at least partially located on the extension and includes an opening; the conductive structure is located in the extension and includes a lower portion and an upper portion; the opening exposes at least a portion of the lower portion; the upper portion is located on the side of the lower portion away from the substrate, at least partially located in the opening, and in direct contact with the lower portion.

[0066] Figure 1 This is a schematic diagram of the structure of a display substrate provided in one embodiment of the present disclosure. Figure 7A This is a cross-sectional schematic diagram of a conductive structure provided in one embodiment of this disclosure. For example... Figure 1 and Figure 7AAs shown, at least one embodiment of this disclosure provides a display substrate 10 with a display area 11, a non-display area 12, and an extension 13. The display area 11 includes display pixels, and the non-display area 12 at least partially surrounds the display area 12. For example, the display area 11 includes a plurality of display pixels, such as a plurality of display pixels arranged in an array; the non-display area 12 surrounds the entire display area 11. Of course, in other embodiments, the non-display area 12 may also surround a portion of the display area 11. The substrate 1 is located in the display area 11, the non-display area 12, and the extension 13, and includes a bendable portion 12A located at the edge of the non-display area 12 away from the display area 11; the display substrate 10 has a first side (i.e., the display side) for display and a second side (i.e., the non-display side) opposite to the first side, and the extension 13 is connected to the bendable portion 12A and can be bent to the second side of the display substrate 10 through the bendable portion 12A. A conductive structure C is located in the extension 13. Figure 7A Taking a conductive structure C as an example, a first insulating layer 5 is at least partially located on the extension 13 and includes an opening V. The conductive structure C includes a lower portion 3 and an upper portion 4, with the opening V exposing the lower portion 3. The upper portion 4 is located on the side of the lower portion 3 away from the substrate 1, and is at least partially located in the opening V and in direct contact with the lower portion. For example, a display substrate 10 includes a first conductive layer and a second conductive layer, with the second conductive layer located on the side of the first conductive layer away from the substrate 1; for example, the lower portion 3 is located on the first conductive layer, and the upper portion 4 is located on the second conductive layer. On the one hand, in some embodiments, the direct overlap of the lower part 3 and the upper part 4 can reduce the resistance of the overall structure formed by the two. On the other hand, in some embodiments, after the lower part 3 and the first insulating layer 5 with the opening V exposing the lower part 3 are formed, if other layers are to be formed on the lower part 3 and patterned, it is often necessary to form a protective layer covering the lower part 3 to prevent the lower part 3 from being etched and damaged during the patterning process. In the display substrate 10 provided in the embodiments of this disclosure, the upper part 4 covers the lower part 3 and can serve as an etching protective layer. The upper part 4 can be formed with other conductive structures of the second conductive layer (e.g., conductive structures located in the display area 11 and non-display areas) through the same patterning process on the same film layer, without the need to form another protective layer, which simplifies the manufacturing process of the display substrate and saves costs.

[0067] For example, the substrate 1 can be rigid, such as a glass substrate or a quartz substrate, or it can be flexible, such as a polyimide (PI) substrate. The extension 13 is made of a flexible material, such as polyimide (PI) or rubber.

[0068] Figure 5A for Figure 1 The diagram shows a magnified planar view of a portion E of the bending area and extension of the display substrate. Figure 6A for Figure 5A A magnified diagram of a portion of L in the image. Figure 5A and Figure 6A The diagram shows a first conductive layer, a first insulating layer, and a second conductive layer. Other layers of the driving circuit and pixel circuit (e.g., the layer containing the gate, the transition layer connecting the detection signal line to other layers, etc.) are not shown. For example, the display substrate 10 also includes pixel circuitry and driving circuitry. (See reference...) Figure 5A and Figure 6A For example, the display substrate 10 also includes a detection lead C1. The pixel circuit is located in the display area 11 and configured to control the display state of the display pixels; the driving circuit is at least partially located in the non-display area 12 and includes a driving signal line located in the non-display area 12, the driving signal line being configured to provide a driving signal to the pixel circuit. The detection lead C1 is electrically connected to the driving signal line and configured to provide a detection signal to the driving signal line, extending from the non-display area 12 of the display substrate 10 through a bend to the extension 13 of the display substrate 10.

[0069] Figure 3A for Figure 1 The diagram includes a partial D of the drive signal line. Figure 3B This is a schematic diagram of clock signal lines and multiple shift registers. Figure 3A As shown, Figure 1 The drive signal line 20 includes multiple signal lines spaced apart from each other. Combined Figure 3A and Figure 3B The driving circuit includes a gate driving circuit, such as a GOA driving circuit; the gate driving circuit includes multiple cascaded shift registers and trigger signal lines. The multiple cascaded shift registers include a first shift register, a second shift register, ..., an Nth shift register, where N is a positive integer; each shift register includes a signal input terminal INT and a signal output terminal OUT. The display substrate includes multiple display pixels arranged in an array, including multiple display pixel rows, each corresponding one-to-one with the multiple cascaded shift registers. The trigger signal line is connected to the signal input terminal of the first shift register and configured to provide a trigger signal to the first shift register. The first shift register, in response to the trigger signal, outputs a corresponding driving signal from its signal output terminal OUT to scan the display pixel rows of the display area (AA) corresponding to the first shift register. The aforementioned driving signal line includes this trigger signal line. Figure 3B As shown, the drive signal output from the signal output terminal OUT of the previous stage shift register is fed into the signal input terminal INT of the next stage shift register as the trigger signal for the next stage shift register. The drive signal lines include the trigger signal lines.

[0070] For example, in some embodiments, such as Figure 3AAs shown, the driving signals include a scan driving signal; the trigger signal line includes a scan trigger signal line GSTV. The scan trigger signal line GSTV is configured to provide a scan trigger signal to the first shift register so that the first shift register outputs a scan driving signal, for example, by outputting a scan driving signal from the signal output terminal OUT of the first shift register, and the scan driving signal is provided to the pixel circuit.

[0071] Figure 4A This is an equivalent circuit diagram of a pixel circuit of a display substrate provided in one embodiment of the present disclosure. (In conjunction with...) Figure 4A and Figures 3A-3B For example, the gate drive circuit also includes gate scan lines, such as gate scan lines corresponding to each row of display pixels. For each gate scan line corresponding to a row of display pixels, the gate scan line is connected to the signal output terminals OUT of a plurality of shift registers and configured to provide scan drive signals output from the plurality of shift registers to the pixel circuit. For example, Figure 4A The pixel circuit shown is a 2T1C pixel circuit. This pixel circuit includes: a data line, a light-emitting device, and a first transistor T1, a second transistor T2, and a storage capacitor C located in each pixel. The data line is configured to provide a data signal to the display pixel, for example, a data voltage signal. The light-emitting device L includes a first electrode and a second electrode. A first power supply line 31 (VSS) is connected to the first electrode to receive a first power supply voltage. The gate of the first transistor T1 is connected to the gate scan line to receive a scan drive signal. The first electrode of the first transistor T1 is connected to the data line to receive the data signal. The second electrode of the first transistor T1 is connected to the gate of the second transistor T2. The first electrode of the second transistor T2 is connected to the second power supply line 32 (VDD) to receive a second power supply voltage. The second electrode of the second transistor T2 is connected to the second electrode of the light-emitting device L. The first electrode of the storage capacitor C is connected to the gate of the second transistor T2, and the second electrode of the storage capacitor C is connected to the second power supply line 32 (VDD). For example, both the first transistor T1 and the second transistor T2 are N-type transistors. For example, when using an N-type transistor, IGZO can be used as the active layer of the thin-film transistor to reduce the size of the driving transistor and prevent leakage current. For example, an N-type transistor turns on in response to a high-level signal.

[0072] For example, for Figure 4A In the embodiment shown, the scan trigger signal is input to the first-stage shift register via the scan trigger signal line, thereby outputting a scan drive signal through the first-stage shift register. The scan drive signal is provided to the pixel circuit through the gate scan line.

[0073] In other embodiments of this disclosure, the type of pixel circuit is not limited to a 2T1C circuit, but can also be any implementable type such as 4T2C, 7T1C, etc.

[0074] For example, in some embodiments, the driving signal further includes a light emission control driving signal; the trigger signal line further includes a light emission control trigger signal line ESTV, which is configured to provide a light emission control trigger signal to the first shift register so that the first shift register outputs a light emission control driving signal, which is then provided to the pixel circuit. This will be explained below using the case where the display substrate employs a 7T1C pixel circuit as an example.

[0075] For example, Figure 4B This is an equivalent circuit diagram of another pixel circuit of a display substrate provided in one embodiment of the present disclosure. Figure 4B The pixel circuit shown is a 7T1C pixel circuit. Combined with... Figure 4B and Figures 3A-3BThe scan drive signals include a first scan drive signal and a second scan drive signal, and the light control drive signals include a first light emission control drive signal, a second light emission control drive signal, and a reset drive signal. The gate drive circuit also includes a first scan line GATE1, a second scan line GATE2, a first light emission control line EM1, and a second light emission control line EM2. For each display pixel row, these four signal lines are correspondingly provided. For each display pixel row, the first scan line GATE1 and the second scan line GATE2 are connected to the signal output terminal OUT of the shift register and configured to provide the first scan drive signal and the second scan drive signal output from the shift register to the pixel circuit; the first light emission control line EM1 and the second light emission control line EM2 are connected to the signal output terminal OUT of the shift register and configured to provide the first light emission control drive signal and the second light emission control drive signal output from the shift register to the pixel circuit. For example, the pixel circuit includes: a data line, a light-emitting device L1, an initial signal line Vinit, and a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C located in each pixel. The data line is configured to provide a data signal Vdata to the display pixel, for example, the data signal Vdata is a data voltage; the light-emitting device L1 includes a first electrode and a second electrode, and a first power line (VSS) is connected to the first electrode to receive a first power supply voltage; the initial signal line Vinit is configured to provide an initial signal to the display pixel.The gate of the first transistor T1 is connected to the first node N1; the first terminal of the first transistor T1 is connected to the second node N2, and the second terminal of the first transistor T1 is connected to the third node N3; the gate of the second transistor T2 is connected to the first scan line GATE1 to receive the first scan drive signal, the first terminal of the second transistor T2 is connected to the data line to receive the data signal Vdata, and the second terminal of the second transistor T2 is connected to the second node N2; the gate of the third transistor T3 is connected to the second scan line GATE2 to receive the second scan drive signal, the first terminal of the third transistor T3 is connected to the first node N1 (i.e., the gate of the first transistor T1), and the second terminal of the third transistor T3 is connected to the third node N3; the first terminal of the storage capacitor C is connected to the first node N1 (i.e., the gate of the first transistor T1), and the second terminal of the storage capacitor C is connected to the second power supply line 32 (VDD) to receive the second power supply voltage; the gate of the fourth transistor T4 is connected to the first light-emitting control line EM1. The first terminal of the fourth transistor T4 is connected to the second power supply line 32 (VDD) to receive the second power supply voltage, and the second terminal of the fourth transistor T4 is connected to the second node N2; the gate of the fifth transistor T5 is connected to the second light-emitting control line EM2 to receive the second light-emitting control signal, the first terminal of the fifth transistor T5 is connected to the third node N3, and the second terminal of the fifth transistor T5 is connected to the second electrode of the light-emitting device L1; the gate of the sixth transistor T6 is connected to the reset control terminal to receive the reset drive signal, the first terminal of the sixth transistor T6 is connected to the initial signal line Vinit to receive the initial signal, and the second terminal of the sixth transistor T6 is connected to the second electrode of the light-emitting device L1; the gate of the seventh transistor T7 is connected to the reset control terminal to receive the reset drive signal, the first terminal of the seventh transistor T7 is connected to the initial signal line Vinit to receive the initial signal, and the second terminal of the seventh transistor T7 is connected to the first node N1.

[0076] For example, in Figure 4BIn the illustrated embodiment, the first to seventh transistors T1 to T7 are all N-type transistors. For example, when using N-type transistors, IGZO can be used as the active layer of the thin-film transistor to reduce the size of the driving transistor and prevent leakage current. N-type transistors turn on in response to a high-level signal. In other embodiments, for example, the pixel circuit can use a hybrid N-type and P-type transistor design. For instance, the third transistor T3 and the seventh transistor T7 are N-type transistors, while the remaining transistors are P-type transistors. Because N-type transistors have lower leakage current, they can overcome screen flicker when the pixel circuit is used for low-frequency driving. Furthermore, since the third transistor T3 in the compensation circuit of the pixel circuit uses an N-type transistor with lower leakage current and smaller size, the storage capacitor C of the compensation circuit can be a smaller capacitor, thereby increasing the resolution of the display panel. Simultaneously, because N-type transistors have lower leakage current, there is no need to consider the aging problem of N-type transistors. For example, combined with... Figure 1 , Figure 3A and Figure 4B The driving signal line also includes an initial signal line Vinit, which extends from the non-display area 12 to the display area 11. For example, the initial signal line Vinit extends through the area where the shift register is located to the display area 11 and is connected to the first terminal of the sixth transistor T6 and the first terminal of the seventh transistor T7 to provide them with an initial signal, that is, to reset the first node N1 and the fourth node N4 of the previous stage before proceeding to the next display stage.

[0077] For example, such as Figures 3A-3B As shown, the drive signal lines also include clock signal lines, which are configured to provide clock control drive signals to each shift register so that scan drive signals and light emission control drive signals are provided to the pixel circuit. For example, the clock signal lines include a first scan clock signal line GCLK1, a second scan clock signal line GCLK2, a first light emission control clock signal line ECLK1, and a second light emission control clock signal line ECLK2. These four provide the first scan clock signal line, the second scan clock signal, the first light emission control clock signal, and the second light emission control clock signal to the shift register, respectively. The shift register outputs the first scan drive signal, the second scan drive signal, the first light emission control drive signal, and the second light emission control drive signal. These signals are provided to the pixel circuit through the first scan line, the second scan line, the first light emission control line, and the second light emission control line, respectively. That is, the clock signal lines are configured to provide the first scan drive signal, the second scan drive signal, the first light emission control drive signal, and the second light emission control drive signal to the pixel circuit through the shift register, respectively.

[0078] For example, such as Figures 3A-3BAs shown, the drive signal lines also include a low-level signal line VGL and a high-level signal line VGH. The low-level signal line VGL is connected to each shift register and configured to provide a first voltage drive signal to each shift register; the high-level signal line VGH is connected to each shift register and configured to provide a second voltage drive signal to each shift register, the second voltage being greater than the first voltage, so as to provide a power supply voltage for the operation of each shift register.

[0079] for Figure 4B In the illustrated embodiment, the power supply circuit of the display substrate provides a scan trigger signal to the scan trigger signal line, a light emission control trigger signal to the light emission control trigger signal line, and clock control drive signals to the first scan clock signal line GCLK1, the second scan clock signal line GCLK2, the first light emission control clock signal line ECLK1, and the second light emission control clock signal line ECLK2, respectively. Furthermore, the second power supply circuit 6 provides a first voltage drive signal to the low-level signal line VGL and a second voltage drive signal to the high-level signal line VGH. The first and second voltage drive signals are provided to the shift register via the low-level signal line VGL and the high-level signal line VGH, respectively.

[0080] It should be noted that the drive signal lines are not limited to the types listed above, and may also include signal lines with other functions. The types of drive signal lines listed in the above embodiments are merely exemplary.

[0081] Figure 2 for Figure 1 A schematic cross-sectional view of the display area of ​​the display substrate along line I-I'. (See diagram below.) Figure 2 As shown, the pixel circuit of each sub-pixel of the display area 11 of the display substrate includes a thin-film transistor (TFT), a light-emitting element 180, and a storage capacitor Cst. The TFT includes an active layer 120, a gate 121, and source / drain electrodes 122 / 123; the storage capacitor Cst includes a first electrode CE1 and a second capacitor electrode CE2. The light-emitting element 180 includes a cathode 183, an anode 181, and a light-emitting layer 182 between the cathode 183 and the anode 181. The anode 181 is electrically connected to one of the source / drain electrodes 122 / 123 of the TFT, such as the drain 123. Of course, in other embodiments, the anode 181 and the drain 123 of the TFT can also be electrically connected via a transition electrode. For example, the light-emitting element can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and correspondingly, the light-emitting layer 182 is an organic light-emitting layer or a quantum dot light-emitting layer.

[0082] For example, the first power line is disposed on the same layer as the second electrode CE2 of the storage capacitor Cst. This same-layer structure can be formed in a single patterning process, thereby simplifying the fabrication process of the display substrate 20. Alternatively, each first power line includes a first portion disposed on the same layer as the gate 121 and the first electrode CE1 of the storage capacitor Cst, and a second portion disposed on the same layer as the second electrode CE2 of the storage capacitor Cst. The first portion and the second portion, which are disposed on different layers, are electrically connected through vias, thereby connecting the first portion and the second portion in parallel to reduce the resistance of each first power line.

[0083] For example, the second electrode CE2 of the storage capacitor Cst is located in the first conductive layer, that is, the second electrode CE2 is in the same layer as the lower part of the conductive structure provided in the embodiments of this disclosure, and both can be formed by performing the same patterning process on the same conductive material layer; the source / drain electrodes 122 / 123 and the data lines of the thin-film transistor TFT are located in the second conductive layer, that is, the source / drain electrodes 122 / 123 and the data lines are in the same layer as the upper part of the above-mentioned conductive structure, and both can be formed by performing the same patterning process on the same conductive material layer. As another example, in some embodiments, the lower part of the conductive structure provided in the embodiments of this disclosure is connected to the second power line VDD of the pixel circuit (e.g., ...). Figure 4B The second power line (VDD) connected to the second voltage terminal and the source / drain electrodes 122 / 123 are on the same layer. The upper part of the conductive structure provided in this embodiment is on the same layer as the data line; or, the lower part of the conductive structure provided in this embodiment is on the same layer as the data line and the source / drain electrodes 122 / 123, and the upper part of the conductive structure provided in this embodiment is on the same layer as the second power line VDD.

[0084] For example, such as Figure 2 As shown, the display area 11 also includes a first gate insulating layer 151 located between the active layer 120 and the gate 121, a second gate insulating layer 152 located above the gate 121, and an interlayer insulating layer 160. The second gate insulating layer 152 is located between the first electrode CE1 and the second capacitor electrode CE2, such that the first electrode CE1, the second gate insulating layer 152, and the second capacitor electrode CE2 constitute a storage capacitor Cst. The interlayer insulating layer 160 covers the second capacitor electrode CE2.

[0085] For example, such as Figure 2 As shown, display area 11 also includes an insulating layer 113 (e.g., a passivation layer) and a first planarization layer 112 covering pixel circuitry. Display area 201 also includes a pixel defining layer 170 for defining a plurality of sub-pixels and spacers (not shown) on the pixel defining layer 170, etc. Figure 2As shown, in some embodiments, an insulating layer 113 is located above the source / drain electrodes 122 / 123 (e.g., a passivation layer formed of materials such as silicon oxide, silicon nitride, or silicon oxynitride), a first planarization layer 112 is disposed above the insulating layer 113, and the anode 181 is electrically connected to the drain electrode 123 through a via penetrating the first planarization layer 112 and the insulating layer 113.

[0086] For example, such as Figure 2 As shown, the display substrate also includes an encapsulation layer 190, which includes multiple encapsulation sub-layers 191 / 192 / 193. For example, a first encapsulation layer 291 is disposed on the same layer as the first encapsulation sub-layer 191 in the encapsulation layer 190, a second encapsulation layer 292 is disposed on the same layer as the second encapsulation sub-layer 192 in the encapsulation layer 190, and a third encapsulation layer 293 is disposed on the same layer as the third encapsulation sub-layer 193 in the encapsulation layer 190. For example, the first encapsulation layer 291 and the third encapsulation layer 293 may both include inorganic encapsulation materials, such as silicon oxide, silicon nitride, or silicon oxynitride, while the second encapsulation layer 292 may include organic materials, such as resin materials. The multi-layer encapsulation structure of the display substrate can achieve better encapsulation effect to prevent impurities such as moisture or oxygen from penetrating into the interior of the display substrate.

[0087] In some embodiments, such as Figure 2 As shown, the display substrate also includes a buffer layer 111 located on the substrate 210. The buffer layer 111 serves as a transition layer, preventing harmful substances in the substrate 1 from penetrating the interior of the display substrate, such as into the display area 11, and also increasing the adhesion of the film layers in the display substrate to the substrate 1. For example, the material of the buffer layer 111 may include a single layer or multiple layers formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0088] For example, the detection lead C1 includes a protective part C10 (such as...). Figure 6A The conductive structure C described above includes the protective part C10, and the protective part C10 is an example of the conductive structure C described above. Figure 6B During the manufacturing process of the display substrate, a process is formed Figure 6A A schematic diagram of the structure after performing a second patterning process on the first insulating material layer to form an opening region; Figure 6C for Figure 6A A planar schematic diagram of the second conductive layer. (Combined with...) Figures 6A-6CThe lower part of the aforementioned conductive structure includes a first lower part 31, and the opening of the conductive structure includes a first opening that exposes the first lower part 31; the upper part includes a first upper part 41, which is stacked with the first lower part 31 in a direction perpendicular to the substrate 1 and located on the side of the first lower part 31 away from the substrate 1; the first upper part 41 is at least partially located in the first opening and is in direct contact with the first lower part 31; and the protective part C10 includes the first lower part 31 and the first upper part 41. Figure 6A As shown, the protection portion C10 includes a first protection portion C10A and a second protection portion C10B. The first protection portion C10A and the second protection portion C10B are two examples of the aforementioned conductive structure C, which will be described in detail below. It should be noted that in the display substrate 10, not only detection leads may include conductive structures C, but other traces may also include conductive structures C; here, detection leads are used as an example. Furthermore, here... Figure 6A The wires electrically connected to the flexible printed circuit board (FPC) are used as test leads as an example. The wires electrically connected to the flexible printed circuit board (FPC) can also be traces for other functions.

[0089] For example, refer to Figure 1 , Figure 5A , Figure 6A The display substrate 10 also includes an integrated circuit board IC and a first pin C2. The integrated circuit board IC is located in the extension 13 and configured to provide a drive signal to the drive circuit. The extension 13 has an edge E1 extending along a first direction D1. The conductive structure C includes the first pin C2, which is another example of the conductive structure C. Figure 7D For along Figure 6A A cross-sectional diagram of line C-C' in the diagram. Figure 7D Taking the first pin C2 with two intervals as an example. Then, combined with... Figure 7D The lower part of the conductive structure includes a second lower part 32, and the opening of the conductive structure includes a second opening V2, which exposes the second lower part 32. The upper part of the conductive structure includes a second upper part 42, which is stacked with the second lower part 32 in a direction perpendicular to the substrate 1 and located on the side of the second lower part 32 away from the substrate 1. The second upper part 42 is at least partially located in the second opening V2, and the lower surface of the second upper part 42 near the substrate 1 is in direct contact with the second lower part 32. The orthographic projection of the second upper part 42 on the substrate 1 is located within the orthographic projection of the second opening V2 on the substrate 1. The first pin C2 includes a second lower part 32 and a second upper part 42. An integrated circuit board IC is provided with integrated circuit board pins (not shown in the figure), and the upper surface of the second upper part 42 of the first pin C2 away from the substrate 1 is in direct contact with the integrated circuit board pin. That is, the integrated circuit board IC is bonded to the area where the first pin C2 is located, so that the upper surface of the second upper part 42 of the first pin C2 away from the substrate 1 is in direct contact with the integrated circuit board pin. Figure 7D The upper surface of the second upper portion 42, away from the substrate 1, is in direct contact with the pins of the integrated circuit board. Thus, due to the stacking of the second upper portion 42 and the second lower portion 32, the step difference between the second lower portion 32 and the pins of the integrated circuit board IC is reduced, thereby enabling the entire assembly of the second upper portion 42 and the second lower portion 32 to achieve better direct contact and connection with the pins of the integrated circuit board.

[0090] For example, combining Figure 5A and Figure 7D The second opening V2 exposes the entire area used to house the integrated circuit board IC, that is, it exposes the entire area where the multiple first pins C2, arranged at intervals between each other, are located. Therefore, as Figure 7D There is no first insulating layer between adjacent first pins C2.

[0091] For example, refer to Figure 1 , Figure 5A , Figure 6A The display substrate 10 also includes a flexible circuit board (FPC) and a second pin C3. The conductive structure C described above includes the second pin C3, which is another example of the conductive structure C. The flexible circuit board (FPC) is located in the extension 13, connected to the detection lead C1 and configured to provide a detection signal to the detection lead C1, and connected to the integrated circuit board (IC) and configured to provide an electrical signal to the IC for generating a drive signal. The second pin C3 is connected to the flexible circuit board (FPC) and includes a first portion of the pin, which is connected to the detection lead. For example, the flexible circuit board (FPC) also provides a data signal, which is provided to the pixel circuit via the IC. Of course, the flexible circuit board (FPC) can also provide other signals; those skilled in the art can design according to specific needs, and this disclosure does not limit this.

[0092] For example, the display substrate 10 includes a plurality of second pins C3, which are arranged along a first direction D1; the display substrate 10 includes a plurality of detection leads C1, and a portion of the second pins C3 are first part pins (e.g. Figure 5A and Figure 6A The portion of the second pin C3 located near the first pin C2 in the first direction D1 is connected one-to-one with the multiple detection leads C1 of the first portion of the pin. For example, a flexible circuit board (FPC) has multiple flexible circuit board pins arranged along the first direction D1, and multiple second pins C3 are connected one-to-one with the multiple flexible circuit board pins.

[0093] Figure 7E For along Figure 6A A cross-sectional diagram of line D-D' in the diagram. Figure 7E Taking the second pin C3 with two intervals as an example. Then, combined with... Figure 7EThe lower part of the aforementioned conductive structure includes a third lower part 33, and the opening of the conductive structure includes a third opening V3, which exposes the third lower part 33. The upper part of the conductive structure includes a third upper part 43, which is stacked with the third lower part 33 in a direction perpendicular to the substrate 1 and located on the side of the third lower part 33 away from the substrate 1. The third upper part 43 is at least partially located in the third opening V3, and the lower surface of the third upper part 43 near the substrate 1 is in direct contact with the third lower part 33. The orthographic projection of the third upper part 33 on the substrate 1 substantially coincides with the orthographic projection of the third opening V3 on the substrate 1. The second pin C3 includes the third lower part 33 and the third upper part 43. Flexible circuit board pins (not shown in the figure) are provided on the flexible circuit board FPC, such as... Figure 7E As shown, the upper surface of the third upper portion 43 of the second pin C3, away from the substrate 1, is in direct contact with the flexible circuit board pin. That is, the flexible circuit board (FPC) is bonded to the area where the second pin C3 is located, so that the upper surface of the third upper portion 43 of the second pin C3, away from the substrate 1, is in direct contact with the flexible circuit board pin. Thus, due to the stacking of the third upper portion 43 and the third lower portion 33, the step difference between the third lower portion 33 and the flexible circuit board pin on the flexible circuit board (FPC) is reduced, thereby enabling the entire structure formed by the second upper portion 42 and the second lower portion 32 to achieve better direct contact and connection with the flexible circuit board pin.

[0094] It should be noted that the cases in this disclosure where the orthographic projection of the upper part substantially coincides with the orthographic projection of the opening include: the cases where the orthographic projection of the upper part completely coincides with the orthographic projection of the opening, and the cases where the orthographic projection of the upper part does not completely coincide with the orthographic projection of the opening, such as the case where the orthographic projection of the upper part is located within the orthographic projection of the opening. When the orthographic projection of the upper part does not completely coincide with the orthographic projection of the opening, for example, the area of ​​the non-overlapping part accounts for less than 10% of the overlapping area of ​​the two.

[0095] Figure 7B For along Figure 6A A cross-sectional diagram of line A-A' in the diagram. Figure 7B Take, for example, the first protection section of two spaced-apart detection leads. For instance, as shown... Figure 6A and Figure 7BThe protective portion C10 includes a first protective portion C10A. The first lower portion 31 includes a first sub-lower portion 311, and the first opening includes a first sub-opening V11, which exposes the first sub-lower portion 311. The first upper portion 41 includes a first sub-upper portion 411, which is stacked with the first sub-lower portion in a direction perpendicular to the substrate 1 and located on the side of the first sub-lower portion 311 away from the substrate 1. The first sub-upper portion 411 is at least partially located in the first sub-opening V11 and is in direct contact with the first sub-lower portion 311. The first protective portion C10A includes the first sub-lower portion 311 and the second sub-upper portion 411. The detection lead C1 has an end that is in direct contact with the corresponding second pin C3, and the end has the first protective portion C10A.

[0096] Figure 7C For along Figure 6A A cross-sectional diagram of line B-B' in the diagram. Figure 7C Take, for example, the second protection section with two spaced-apart detection leads. For instance, as shown... Figure 6A and Figure 7C The protection portion C10 further includes a second protection portion C10B. The first lower portion 31 includes a second sub-lower portion 312, and the first opening includes a second sub-opening V12, with the second sub-opening V12 exposing the second sub-lower portion 312. The first upper portion 41 includes a second sub-upper portion 412, which is stacked with the second sub-lower portion 312 in a direction perpendicular to the substrate 1 and located on the side of the second sub-lower portion 312 away from the substrate 1. The second sub-upper portion 412 is at least partially located in the second sub-opening V12 and in direct contact with the second sub-lower portion 312. The second protection portion C10B includes the second sub-lower portion 312 and the second sub-upper portion 412. In the first direction D1, multiple detection leads C1 are located on at least one side of the integrated circuit board IC. For example, in the first direction D1, multiple detection leads C1 are located on both sides of the integrated circuit board IC. Figure 5A Only showed Figure 1 The structure on the left side of the extension, for example, the right side of the extension, can be configured with... Figure 5A The structure shown is symmetrical. Detection lead C1 includes a first detection lead close to the integrated circuit board IC, for example... Figure 6A The detection lead within the dashed triangle is the first detection lead. The first detection lead has a second protection part C10B. For a single first detection lead, the second protection part C10B is connected to the first protection part C10A and located on the side of the first protection part C10A away from the second pin C3. That is, the second protection part C10B is electrically connected to the corresponding second pin C3 through the first protection part C10A.

[0097] For example, the second direction D2 lies in the same plane as the first direction D1 and intersects (e.g., is perpendicular to) the first direction D1. (Combined) Figure 5B and Figure 6A The first detection lead has an overlapping portion OR that overlaps with the first pin C2 of the integrated circuit board IC in the second direction D2. The overlapping portion OR is... Figure 6A The portion within the dashed triangle is designed to reduce the spacing between the detection lead C1 and the IC in the first direction D1, saving space. For a first detection lead, its overlapping portion OR includes a second lower sub-part 312 and a second upper sub-part 412.

[0098] For example, for the first detection lead, the overlapping portion OR is located on the side of the end (i.e., the first protection portion C10A) away from the second pin C3, and the overlapping portion OR is connected to the corresponding second pin C3 via the end.

[0099] For example, combining Figure 5A and Figure 6A The first detection lead includes an inclined portion intersecting the first direction D1, and the inclined portion includes an overlapping portion OR. For example, at least a portion of the first detection lead is configured to reduce the spacing between the detection lead C1 and the IC in the first direction D1.

[0100] For example, the third upper part 43 of each of the plurality of second pins C3 is integral with the first upper part 41 of the corresponding detection lead C1 (e.g., the first detection lead), thereby the third upper part 43 and the first upper part 41 can be integrally formed to simplify the structure and manufacturing process of the display substrate.

[0101] For example, such as Figure 5A As shown, the first pin C2 includes an input pin C21 and an output pin C22. Both the input pin C21 and the output pin C22 include a second upper part 42 and a second lower part 32; combined with Figure 6A At least a portion of the second upper part 32 of the input pin C21 is electrically connected to at least a portion of the third upper part 43 of the second pin C3, thereby the flexible circuit board FPC can be electrically connected to the input pin C21 of the integrated circuit board IC to provide a detection signal to the detection lead C1.

[0102] For example, refer to Figure 5A and Figure 6A In the second direction D2, the flexible circuit board FPC is located on the side of the detection lead C1 and the integrated circuit board IC near the extension away from the edge of the non-display area 12; in the second direction D2, multiple input pins C21, multiple output pins C22 and multiple second pins C3 are arranged at intervals, with multiple input pins C21 located between multiple output pins C22 and multiple second pins C3.

[0103] For example, Figure 6C for Figure 6A A planar schematic diagram of the second conductive layer in the diagram, combined with... Figure 5A , Figure 6A and Figure 6C The display substrate 10 also includes a plurality of connection electrodes 6. The plurality of connection electrodes 6 are disposed in the same layer as the second upper portion 42 and the third upper portion 43, for example, all located in the second conductive layer. The plurality of connection electrodes 6 electrically connect the second upper portion 42 of the plurality of input pins C21 and the third upper portion 43 of the plurality of second pins C3 in a one-to-one correspondence across the gap between the plurality of input pins C21 and the plurality of second pins C3.

[0104] For example, in some embodiments, such as Figure 7B and Figure 7C As shown, the orthographic projection of the first upper part 41 on the substrate 1 is substantially coincident with the orthographic projection of the first opening on the substrate 1. That is, for a first detection lead, the orthographic projection of the first sub-upper part 411 on the substrate 1 is substantially coincident with the orthographic projection of the first sub-opening V11 on the substrate 1, and the orthographic projection of the second sub-upper part 412 on the substrate 1 is substantially coincident with the orthographic projection of the second sub-opening V12 on the substrate 1.

[0105] Figure 7G For along Figure 6A Another cross-sectional view of line A-A' in the diagram. For example, in some other embodiments, Figure 7G As shown, for a first detection lead, the first upper part 41 includes an inner part and an outer part. Taking the first protective part C10A of the first detection lead as an example, the first sub-upper part 411 of the first protective part C10A includes an inner part 411A and an outer part 411B. The inner part 411A is located inside the first sub-opening V11 and is in direct contact with the first sub-lower part 311; the outer part 411B is located outside the first sub-opening V11, and the first insulating layer 5 is located between the outer part 411B and the first sub-lower part 311. Furthermore, the lower surface of the outer part 411B near the substrate 1 is in direct contact with the first insulating layer 5, that is, there is no other layer between the first insulating layer 5 and the outer part 411B. Here, the first sub-opening V11 is taken as an example of the first opening, the first sub-lower part 311 is taken as an example of the first lower part, and the first sub-upper part 411 is taken as an example of the first upper part.

[0106] Figure 7H For along Figure 6A Another cross-sectional view of line A-A' in the diagram. For example, in some other embodiments, such as... Figure 7H As shown, for a first detection lead, the first upper sub-part 411 covers the first lower sub-part 311, and the first upper sub-part 411 and the first lower sub-part 311 are located within the first sub-opening V11. Here, the first sub-opening V11 is taken as an example of the first opening, the first lower sub-part 311 is taken as an example of the first lower part, and the first upper sub-part 411 is taken as an example of the first upper part.

[0107] For example, combining Figure 1 and Figure 5AThe pixel circuit includes a power line C4, at least a portion of which is located in extension 13 and configured to provide a power supply voltage to the pixel circuit. This power line is electrically connected to a portion of a plurality of second pins C3 of a flexible printed circuit board (FPC) configured to provide a power supply voltage to the pixel circuit. In a first direction, the power line is located on both sides of the IC, for example, symmetrically. The aforementioned conductive structure C includes the portion of the power line C4 located in extension 13, which is yet another example of the conductive structure C.

[0108] It should be noted that this is not limited to the first testing line. Figure 7G , Figure 7H The structure shown can be applied to other traces with conductive structure C, and other examples of conductive structure C such as first pin C2, second pin C3, power line C4, electrostatic discharge (ESD) shielding unit C5, etc. Figure 7G , Figure 7H The structure shown.

[0109] Figure 7F For along Figure 6A The cross-sectional diagram of line E-E' in the diagram, combined with... Figure 7F The lower part of the conductive structure includes a fourth lower part 34, and the opening of the conductive structure includes a fourth opening. The fourth lower part 34 is located on the side of the first insulating layer 5 near the substrate 1, and the fourth opening exposes the fourth lower part 34. The upper part of the conductive structure includes a fourth upper part 44, which is stacked with the fourth lower part 34 in a direction perpendicular to the substrate 1 and is located on the side of the fourth lower part 34 away from the substrate 1. The fourth upper part 44 is at least partially located in the fourth opening, and the lower surface of the fourth upper part 44 near the substrate 1 is in direct contact with the fourth lower part 34. The orthographic projection of the fourth upper part 44 on the substrate 1 is substantially coincident with the orthographic projection of the fourth opening on the substrate 1. The portion of the power line C4 located in the extension 13 includes the fourth upper part 44 and the fourth lower part 43. This increases the thickness of the power line in the direction perpendicular to the substrate 1 to reduce the resistance of the power line. That is, the power line C4 includes a third protection part (i.e., the portion corresponding to the E-E' line), which is located at the end of the power line C4 connected to the second pin C3 of the flexible circuit board FPC.

[0110] For example, power line C4 includes a first power line C4A and a second power line C4B. The first power line C4A is configured to provide a first power supply voltage to the display pixels; the second power line C4B is configured to provide a second power supply voltage to the display pixels, the second power supply voltage having the opposite polarity to the first power supply voltage; for example, the first power supply voltage is a low-level voltage VSS, and the second power supply voltage is a high-level voltage VDD. The first power line C4A and the second power line C4B each include a first portion located in the extension 13, and at least one of the first portions of the first power line C4A and the second power line C4B includes a fourth lower portion and a fourth upper portion, for example, as... Figure 7F The first power line C4A includes a fourth lower portion 341, and the opening of the conductive structure includes a fourth lower opening V41. The fourth lower portion 341 is located on the side of the first insulating layer 5 near the substrate 1, and the fourth lower opening V41 exposes the fourth lower portion 341. The second power line C4B includes a fourth lower portion 342, and the opening of the conductive structure includes a fourth lower opening V42. The fourth lower portion 342 is located on the side of the first insulating layer 5 near the substrate 1, and the fourth lower opening V42 exposes the fourth lower portion 342. Increasing the thickness of the first power line C4A and the second power line C4B reduces the resistance of the first power line C4A and the second power line C4B.

[0111] For example, the second power line C4B also includes a second part located in the display pixels of the display area 11. The second part of the second power line C4B can be disposed on the same layer as the upper part, both located in the second conductive layer.

[0112] For example, such as Figure 5A As shown, the display substrate 10 also includes an electrostatic discharge (ESD) shielding unit C5, located on the extension 13 and configured to shield the electrostatic interference of the detection leads. This is another example of the conductive structure C including the ESD shielding unit C5. The lower part of the conductive structure includes a fifth lower part, and the opening of the conductive structure includes a fifth opening. The fifth lower part is located on the side of the first insulating layer 5 near the substrate 1, and the fifth opening exposes the fifth lower part. The upper part of the conductive structure includes a fifth upper part, which is stacked with the fifth lower part in a direction perpendicular to the substrate 1 and located on the side of the fifth lower part away from the substrate 1. The fifth upper part is at least partially located in the fifth opening, and the lower surface of the fifth upper part near the substrate 1 is in direct contact with the fifth lower part. The orthographic projection of the fifth upper part onto the substrate 1 substantially coincides with the orthographic projection of the fifth opening onto the substrate 1. The ESD shielding unit includes a fifth lower part and a fifth upper part. This increases the thickness of the ESD line to reduce its resistance.

[0113] For example, such as Figure 5A and 5BAs shown, in the second direction D2, the electrostatic discharge (ESD) shielding unit C5 is located on the side of the plurality of first pins C2 away from the second pins C3, that is, on the side of the integrated circuit board IC away from the second pins C3. For example, the ESD shielding unit C5 includes multiple ESD lines, for example, at least a portion of the multiple ESD lines extend along the first direction D1, and the multiple ESD lines are arranged along the second direction D2. For example, the multiple ESD lines extend beyond the plurality of first pins C2 in the first direction D1, that is, the length of the multiple ESD lines in the first direction D1 is greater than the length of the integrated circuit board IC.

[0114] like Figure 10 As shown, at least one embodiment of this disclosure also provides a display device 100, which includes any of the display substrates 10 provided in the embodiments of this disclosure.

[0115] The display device can be, for example, a display panel, or any product or component with a display function such as a monitor, OLED panel, OLED TV, electronic paper, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, etc.

[0116] At least one embodiment of this disclosure also provides a method for manufacturing a display substrate 10, the display substrate 10 having a display area 11, a non-display area 12, and an extension 13. The display area 11 includes display pixels, and the non-display area 12 at least partially surrounds the display area 12.

[0117] The production method includes steps 1-3, and steps 1-3 are not limited to the order of 1-3.

[0118] Step 1: Provide a substrate 1, which is located in the display area 11, the non-display area 12, and the extension 13, and includes a bendable portion 12A located at the edge of the non-display area 12 away from the display area 11; the display substrate 10 has a first side (i.e., the display side) for display and a second side (i.e., the non-display side) opposite to the first side, and the extension 13 is connected to the bendable portion 12A and can be bent to the second side of the display substrate 10 through the bendable portion 12A. For example, the substrate 1 can be rigid, such as a glass substrate, a quartz substrate, etc., or it can be flexible, such as a polyimide (PI) substrate, etc. The extension 13 is made of a flexible material, such as polyimide (PI), rubber, etc.

[0119] Step 2: A first insulating layer 5 is formed at least on the extension 13, and an opening is formed in the first insulating layer 5. For example, a portion of the first insulating layer 5 is located on the extension 13, and another portion of the first insulating layer 5 is located on the display area 11 and the non-display area 12 on the display side.

[0120] Step 3: Form a conductive structure on the extension 13. Forming the conductive structure includes: forming a lower part, wherein the lower part is located on the side of the first insulating layer 5 near the substrate 1, and an opening exposes the lower part; and forming an upper part, wherein the upper part and the lower part are stacked in a direction perpendicular to the substrate 1 and the upper part is located on the side of the lower part away from the substrate 1, at least partially located in the opening and in direct contact with the lower part.

[0121] For example, Figures 8A-8H This is a schematic diagram illustrating a method for fabricating a conductive structure according to an embodiment of the present disclosure. This embodiment uses the fabrication of the second lower portion 32 and the second upper portion 42 of the first pin C2 as an example. Step 3, forming the conductive structure, includes steps 31A-38A.

[0122] Step 31A: As Figure 8A A first conductive material layer 320 is formed.

[0123] Step 32A: As Figure 8B A first patterning process is performed on the first conductive material layer 320 to form a first conductive layer, the first conductive layer including a lower part of a conductive structure, the lower part including a second lower part 32.

[0124] Step 33A: As Figure 8C A first insulating material layer 500 is formed covering the lower part, such as the second lower part 32, wherein the first insulating material layer 500 is in direct contact with the lower part, such as the second lower part 32.

[0125] Step 34A: As Figure 8D A second patterning process is performed on the first insulating material layer to form an intermediate insulating layer, the intermediate insulating layer including an opening region that exposes at least a portion of the lower portion, such as a second lower portion 32. Figure 5B During the manufacturing process of the display substrate, a process is formed Figure 5A A schematic diagram of the structure after the first conductive layer and the first insulating material layer 500 are subjected to a second patterning process to form the opening region; Figure 6B During the manufacturing process of the display substrate, a process is formed Figure 6A A schematic diagram of the structure after the first conductive layer and the first insulating material layer 500 have undergone a second patterning process to form an opening region. (Reference) Figure 5B and Figure 6B The opening region formed in step 34 includes Figure 5B The first opening region V10 and the second opening region V20 are shown in the diagram. Since the first opening region V10 exposes the entire area used to mount the integrated circuit board IC, that is, the entire area where the multiple first pins C2 arranged at intervals are located, therefore, as... Figure 7D There is no intermediate insulating layer between the second lower part 32 of the adjacent first pin C2, therefore Figure 8E The intermediate insulating layer is not shown in the diagram. Figure 5BIt includes an insulating layer comprising a first opening region V10 and a second opening region V20.

[0126] Step 35A: As Figure 8E A second metal material layer 400 is formed on the side of the intermediate insulating layer away from the substrate 1. The second metal material layer 400 includes a first part located within the opening area and a second part located outside the opening area. The first part is in direct contact with the lower part, and the lower surface of the second part near the substrate 1 is in direct contact with the upper surface of the first insulating material layer away from the substrate 1. Thus, there are no other layers between the second conductive layer formed by the subsequent patterning process of the second metal material layer and the first conductive layer. By thickening the lower part to reduce the resistance of the first pin C2, the structure is simplified.

[0127] Step 36A: As Figure 8F A third patterning process is performed on the second metal material layer 400 to form the upper part of the conductive structure, such as the second upper part 42.

[0128] Step 37A: As Figure 8G A second insulating material layer 600 is formed covering the upper part and the opening area (here the opening area includes the interval between two adjacent second lower parts 32). The second insulating material layer 600 is in direct contact with the lower part, such as the second lower part 32, that is, there is no other layer between the lower part and the insulating layer finally formed by the second insulating material layer 600.

[0129] Step 38A: As Figure 8H A fourth patterning process is performed on the second insulating material layer 600 to form an opening in the conductive structure C, for example, exposing an opening V2 in the second upper portion 42, and to form the first insulating layer 5. Since the first opening region V10 exposes the entire area used to house the integrated circuit board IC, that is, the entire area where the plurality of first pins C2 arranged at intervals are located, therefore, as... Figure 7D There is no intermediate insulating layer between the second lower part 32 of the adjacent first pin C2, therefore Figure 8E The first insulating layer 5 is not shown.

[0130] For example, the manufacturing method of the display substrate 10 also includes steps 4-8, where steps 4-8 do not represent a specific order.

[0131] Step 4: Form a pixel circuit, wherein the pixel circuit is configured to control the display state of the display pixels;

[0132] Step 5: Form a driving circuit, wherein the driving circuit is at least partially located in the non-display area 12 and includes driving signal lines at least partially located in the non-display area 12, the driving signal lines being configured to provide driving signals to the pixel circuit; the specific type of the driving signal lines can be referred to the description in the previous embodiments.

[0133] Step 6: Form a detection lead C1, wherein the detection lead C1 is electrically connected to the drive signal line and configured to provide a detection signal to the drive signal line, and extends from the non-display area 12 of the display substrate 10 through the bending area 12A to the extension portion 13 of the display substrate 10, as shown in the reference. Figure 1 The detection lead C1 includes a protective portion C10, which is an example of the conductive structure C described above. The lower part of the protective portion C10 includes a first lower portion 31, and the opening of the conductive structure includes a first opening. The first lower portion 31 is located on the side of the first insulating layer 5 near the substrate 1, and the first opening exposes the first lower portion 31. The upper part includes a first upper portion 41, which is stacked with the first lower portion 31 in a direction perpendicular to the substrate 1 and is located on the side of the first lower portion 31 away from the substrate 1. The first upper portion 41 is at least partially located in the first opening and is in direct contact with the first lower portion 31. The protective portion C10 includes the first lower portion 31 and the first upper portion 41.

[0134] Step 7: Provide an integrated circuit board IC on the extension 13, wherein the integrated circuit board IC is located on the extension 13 and configured to provide a drive signal to the drive circuit, and the extension 13 has an edge E1 extending along the first direction D1; and

[0135] Step 8: A first pin C2 is formed on the extension 13, wherein the conductive structure includes the first pin C2, the lower part includes a second lower part 32, the opening includes a second opening, the second lower part 32 is located on the side of the first insulating layer 5 near the substrate 1, and the second opening exposes the second lower part 32; the upper part includes a second upper part 42, the second upper part 42 and the second lower part 32 are stacked in a direction perpendicular to the substrate 1 and are located on the side of the second lower part 32 away from the substrate 1, the second upper part 42 is at least partially located in the second opening, the lower surface of the second upper part 42 near the substrate 1 is in direct contact with the second lower part 32, and the orthographic projection of the second upper part 42 on the substrate 1 is substantially coincident with the orthographic projection of the second opening on the substrate 1; the first pin C2 includes the second lower part 32 and the second upper part 42; the first opening region V10 exposes the second lower parts 32 of the plurality of first pins C2 and the first lower part 31 of the detection lead C1 at least partially.

[0136] For example, the manufacturing method of the display substrate 10 also includes steps 9-10, where steps 9-10 do not represent a specific order.

[0137] Step 9: A flexible circuit board (FPC) is provided in the extension 13, wherein the FPC is located connected to the detection lead C1 and configured to provide a detection signal to the detection lead C1, and connected to the integrated circuit board IC and configured to provide an electrical signal to the integrated circuit board IC for generating a drive signal; and

[0138] Step 10: Form a second pin C3 on the extension 13, wherein the second pin C3 is connected to the flexible circuit board FPC, the second pin C3 includes a first part pin, the first part pin is connected to the detection lead C1, wherein the conductive structure includes the second pin C3, the second pin C3 is another example of the conductive structure C; the second pin C3 includes a third lower part 33, the lower part includes the third lower part 33.

[0139] refer to Figure 5B For example, the first opening region V10 in the interlayer insulation layer formed above is connected to and communicates with the second opening region V20, and the second opening region V20 exposes the third lower part 33.

[0140] For example, the protective portion C10 includes a first protective portion C10A; the first lower portion 31 includes a first sub-lower portion 311; the first opening includes a first sub-opening V11; the first sub-lower portion 311 is located on the side of the first insulating layer 5 near the substrate 1, and the first sub-opening V11 exposes the first sub-lower portion 311; the first upper portion 41 includes a first sub-upper portion 411; the first sub-upper portion 411 and the first sub-lower portion 311 are stacked in a direction perpendicular to the substrate 1 and located on the side of the first sub-lower portion 311 away from the substrate 1; the first sub-upper portion 411 is at least partially located in the first sub-opening V11 and in direct contact with the first sub-lower portion 311; the first protective portion C10A includes the first sub-lower portion 311 and the first sub-upper portion 411; the detection lead C1 has an end that is in direct contact with the second pin C3, and the end has the first protective portion C10A. (Reference) Figure 5B The first opening region V10 exposes the second lower part 32 of multiple first pins C2 and the first sub-lower part 311 at the end.

[0141] For example, the protective portion includes a second protective portion C10B, the second lower portion 32 includes a second sub-lower portion 312, the first opening includes a second sub-opening V12, the second sub-lower portion 312 is located on the side of the first insulating layer 5 near the substrate 1, and the second sub-opening V12 exposes the second sub-lower portion 312; the second upper portion 42 includes a second sub-upper portion 412, the second sub-upper portion 412 and the second sub-lower portion 312 are stacked in a direction perpendicular to the substrate 1 and located on the side of the second sub-lower portion 312 away from the substrate 1, the second sub-upper portion 412 is at least partially located in the second sub-opening V12 and is connected to the first insulating layer 5. The lower part 312 of the second pin is in direct contact; the second protection part C10B includes a lower part 312 and an upper part 412; in the first direction D1, the detection lead C1 is located at least on one side of the integrated circuit board IC, and multiple detection leads C1 include a first detection lead C1 close to the integrated circuit board IC; the second direction D2 is on the same plane as the first direction D1 and intersects with the first direction D1; the first detection lead C1 has an overlapping portion OR that overlaps with the first pin C2 in the second direction D2, and the overlapping portion OR has a lower part 312 and an upper part 412. (Reference) Figure 5BThe first opening region V10 also exposes the second lower part 32 of multiple first pins C2 and the second sub-lower part 312 of the overlapping part OR.

[0142] For example, the first opening region V10 exposes the entire area used to mount the integrated circuit board IC, that is, the entire area where multiple first pins C2 are located. Subsequent formation of other insulating layers above the first insulating layer 5 still exposes the entire area used to mount the integrated circuit board IC, ensuring that the entire area used to mount the integrated circuit board IC is exposed before IC bonding. Furthermore, the first pins C2 are not limited to a two-layer stacked structure consisting of a first lower part 31 and a first upper part 41. For example, when forming other insulating layers above the first insulating layer 5 increases the step difference between the integrated circuit board pins on the integrated circuit board IC and the first pins C2, a supplementary upper part can be formed on the side of the first upper part 41 away from the substrate 1, stacked and in contact with the first upper part 41. For example, the orthographic projection of this supplementary upper part on the substrate 1 substantially overlaps with the orthographic projection of the first upper part 41 on the substrate 1. Similarly, the same applies to the second pin C2.

[0143] For example, for the first detection lead C1, the overlapping portion OR is located on the side of the end away from the second pin C3, and the overlapping portion OR is connected to the second pin C3 via the end.

[0144] Figure 5C for Figure 5B A schematic diagram of the first and second opening regions in the opening area. For example, combined with... Figure 5B and Figure 5C The first opening region V10 includes a first edge L1 and a second edge L2. The first edge L1 extends generally along the first direction D1 and is the boundary between the first opening region V10 and the second opening region V20; the second edge L2 intersects the first edge L1, for example, the second edge L2 extends along the second direction D2; and the second edge L2 overlaps with the first lower portion 31 in a direction perpendicular to the substrate 1, and the included angle between the first edge L1 and the second edge L2 is the included angle region (corresponding to...). Figure 5D The overlapping part (OR) within the dashed triangle in the middle, and the lower part 312 of the second sub-section is located in the included angle area.

[0145] For example, such as Figure 5C As shown, the planar shape of the first opening area V10 is a first rectangle, and the planar shape of the second opening area V20 is a second rectangle. The length of the first rectangle along the first direction D1 is less than the length of the second rectangle along the first direction D1. The overall planar shape of the first opening area V10 and the second opening area V20 is T-shaped. It should be noted that... Figure 5A Only showed Figure 1 The structure on the left side of the extension, for example, the right side of the extension, can be configured with... Figure 5A The structure shown is symmetrical, while Figure 5C The entire first opening region V10 and the entire second opening region V20 are shown.

[0146] For example, an integrated circuit board (IC) has IC pins, and a flexible circuit board (FPC) has FPC pins. In step 7 above, providing the IC on the extension 13 includes: binding the IC to the substrate 1 so that a first pin C2 corresponds to an IC pin, and the upper surface of the second upper portion 42 of the first pin C2, away from the substrate 1, directly contacts the corresponding IC pin. In step 9 above, providing the FPC on the extension 13 includes: binding the FPC to the substrate 1 so that multiple second pins C3 correspond one-to-one with multiple FPC pins, and the upper surface of the third upper portion of each of the multiple second pins C3, away from the substrate 1, directly contacts the corresponding FPC pin.

[0147] For example, the method of fabricating the display substrate 10 further includes forming a pixel circuit, which includes: a light-emitting device and a driving transistor, a data writing transistor, a first gate line and a data line; the data writing transistor is configured to transmit a data signal transmitted on the data line to the driving transistor under the control of a first scan signal transmitted on the first gate line; the driving transistor is configured to control the magnitude of the driving current flowing through the driving transistor according to the data signal; and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. The method of fabricating the display substrate 10 includes: forming the upper part and the data line by performing a third patterning process on the second conductive material layer, that is, the upper part and the data line are formed in the same way by performing the same patterning on the same film layer.

[0148] For example, the pixel circuit also includes a first power line C4A and a second power line C4B. The first power line C4A is configured to provide a first power supply voltage to the display pixel; the second power line C4B is configured to provide a second power supply voltage to the display pixel, wherein the first power supply voltage is a low potential voltage and the second power supply voltage is a high potential voltage, although these two can be interchanged. The second power line C4B includes a first portion located on the extension 13 and a second portion located in the display pixel of the display area 11. For example, the second portion of the second power line C4B in the display pixel of the display area 11 is also formed by performing a third patterning process on the second conductive material layer. Specific features of the pixel circuit can be referred to the previous description in the embodiments of the display substrate, and will not be repeated here; specific features and corresponding technical effects of several examples of conductive structures can also be referred to the previous description in the embodiments of the display substrate, and will not be repeated here. For example, the first opening region V10 in the above-mentioned interlayer insulating layer also exposes Figure 7F The fourth lower part 34 of the first power line C4A and the second power line C4B shown.

[0149] For example, Figures 9A-9E This is a schematic diagram of another method for fabricating a conductive structure according to an embodiment of the present disclosure. This embodiment takes the fabrication of the second lower part 312 and the second upper part 412 of the detection lead C1 as an example. The formation of the conductive structure in step 3 includes the above-described steps 31A-31C, and steps 31B-3B performed after completing steps 31A-31C.

[0150] Step 31B: As Figure 9A As shown, a second patterning process is performed on the first insulating material layer to form an intermediate insulating layer 501, the intermediate insulating layer 501 including an opening region that exposes at least a portion of the lower portion, such as the second sub-lower portion 312.

[0151] Step 32B: As Figure 9B As shown, a second metal material layer 400 is formed on the side of the intermediate insulating layer 501 away from the substrate 1. The second metal material layer 400 includes a first part located within the opening area and a second part located outside the opening area. The first part is in direct contact with the lower part, and the lower surface of the second part near the substrate 1 is in direct contact with the upper surface of the first insulating material layer away from the substrate 1. Thus, there are no other layers between the second conductive layer formed by the subsequent patterning process of the second metal material layer and the first conductive layer. By thickening the lower part to reduce the resistance of the first pin C2, the structure is simplified.

[0152] Step 33B: As Figure 9C As shown, a third patterning process is performed on the second metal material layer 400 to form the upper part of the conductive structure, such as the second sub-upper part 412.

[0153] Step 34B: As Figure 9D As shown, a second insulating material layer 600 is formed covering the upper part, such as the second sub-upper part 412, and the opening area (here the opening area includes the interval between two adjacent second sub-lower parts 312). The second insulating material layer 600 is in direct contact with the lower part, such as the second sub-lower part 312, that is, there is no other layer between the lower part and the insulating layer finally formed by the second insulating material layer 600.

[0154] Step 35B: As Figure 9E As shown, a fourth patterning process is performed on the second insulating material layer 600 to form an opening of the conductive structure C, such as an opening V2 exposing the second upper portion 42, and to form the first insulating layer 5. In this embodiment, the first insulating layer 5 is composed of a portion of the first insulating material layer retained after the patterning process of the first insulating material layer and a portion of the second insulating material layer retained after the patterning process of the second insulating layer. In some embodiments, it is also possible to... Figure 9EBased on the structure shown, a conductive portion is formed above and in contact with the second sub-upper part 412. That is, in the conductive structure of this embodiment, the number of stacked conductive portions similar to the upper and lower parts is not limited. Correspondingly, after patterning the second insulating material layer, another insulating layer can be formed on the side of the formed insulating layer away from the substrate 1. For example, a third insulating material layer is formed and a patterning process is performed on the third insulating material layer. The first insulating layer 5 of the final conductive structure is composed of the portion of the first insulating material layer, the second insulating material layer and the third insulating material layer that is retained after patterning. As long as the upper surface of the first pin C2 away from the substrate and the upper surface of the second pin C3 away from the substrate are exposed, the upper surface of the first pin C2 away from the substrate and the upper surface of the second pin C3 away from the substrate can directly contact the pins of the flexible circuit board and the pins of the integrated circuit board, respectively, during the bonding of the flexible circuit board FPC and the integrated circuit board IC.

[0155] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. The scope of protection of this disclosure is determined by the scope defined in the claims.

Claims

1. A display substrate, comprising a display area, a non-display area, and an extension, wherein, The display area includes display pixels, and the non-display area at least partially surrounds the display area; the display substrate includes: A substrate is located in the display area, the non-display area, and the extension, and includes a bendable portion located at the edge of the non-display area away from the display area; the display substrate has a first side for display and a second side opposite to the first side, the extension is connected to the bendable portion and can be bent to the second side of the display substrate through the bendable portion; A first insulating layer, at least partially located on the extension and including an opening; and A conductive structure, located in the extension, includes: The lower portion, wherein the opening exposes at least a portion of the lower portion; and The upper part, located on the side of the lower part away from the substrate, is at least partially located in the opening and in direct contact with the lower part; The display substrate further includes: A pixel circuit, located in the display area and configured to control the display state of the display pixels; A driving circuit, at least partially located in the non-display area, and including driving signal lines at least partially located in the non-display area, wherein the driving signal lines are configured to provide a driving signal to the pixel circuit; and A detection lead is electrically connected to the drive signal line and configured to provide a detection signal to the drive signal line, wherein the detection lead extends from the non-display area of ​​the display substrate through the bendable portion to the extension portion of the display substrate; The lower portion includes a first lower portion, the opening includes a first opening, and the first opening exposes at least a portion of the first lower portion; The upper part includes a first upper part, which is stacked with the first lower part in a direction perpendicular to the substrate and located on the side of the first lower part away from the substrate. The first upper part is at least partially located in the first opening and is in direct contact with the first lower part. The first lower portion includes a second lower portion, the first opening includes a second lower opening, and the second lower opening exposes at least a portion of the second lower portion; The first upper part includes the second sub-upper part, the second sub-upper part and the second sub-lower part are stacked in a direction perpendicular to the substrate and located on the side of the second sub-lower part away from the substrate, the second sub-upper part is at least partially located in the second sub-opening and is in direct contact with the second sub-lower part; The display substrate further includes: An integrated circuit board, located in the extension and configured to provide the drive signal to the drive circuit; and The first pin is connected to the integrated circuit board pins provided on the integrated circuit board. The extension has an edge opposite to the bendable portion and extending along a first direction, in which the detection lead is located on at least one side of the integrated circuit board, and the detection lead includes a first detection lead close to the integrated circuit board; The second direction is located in the same plane as the first direction and intersects with the first direction; The first detection lead has an overlapping portion that overlaps with the first pin in the second direction, the overlapping portion including a second lower sub-part and a second upper sub-part.

2. The display substrate according to claim 1, wherein, The detection lead includes a protective portion, and the conductive structure includes the protective portion, which includes a first lower portion and a first upper portion.

3. The display substrate according to claim 2, wherein, The orthographic projection of the first upper part on the substrate substantially coincides with the orthographic projection of the first opening on the substrate.

4. The display substrate according to claim 2, wherein, The first upper part includes: Inside, located within the first opening and in direct contact with the first lower part; and The outer portion is located outside the first opening, wherein the first insulating layer is located between the outer portion and the first lower portion, and the lower surface of the outer portion near the substrate is in direct contact with the first insulating layer.

5. The display substrate according to claim 2, wherein, The first upper part covers the first lower part, and the first upper part and the first lower part are located within the first opening.

6. The display substrate according to any one of claims 2-5, wherein, The conductive structure includes the first pin, the lower portion includes a second lower portion, the opening includes a second opening, and the second opening exposes at least a portion of the second lower portion; the upper portion includes a second upper portion, the second upper portion and the second lower portion are stacked in a direction perpendicular to the substrate and located on the side of the second lower portion away from the substrate, the second upper portion is at least partially located in the second opening, the lower surface of the second upper portion near the substrate is in direct contact with the second lower portion, and the orthographic projection of the second upper portion on the substrate is located within the orthographic projection of the second opening on the substrate; The first pin includes a second lower part and a second upper part; The upper surface of the second upper part of the first pin, away from the substrate, is in direct contact with the pin of the integrated circuit board.

7. The display substrate according to claim 6, further comprising: A flexible circuit board, located in the extension, at least a portion of which is connected to the detection lead and configured to provide the detection signal to the detection lead, and connected to the integrated circuit board and configured to provide the integrated circuit board with an electrical signal for generating the drive signal; as well as The second pin, connected to the flexible circuit board, includes a first portion of pins, which is connected to the detection lead. The lower portion includes a third lower portion, the opening includes a third opening, and the third opening exposes at least a portion of the third lower portion; The upper part includes a third upper part, which is stacked with the third lower part in a direction perpendicular to the substrate and located on the side of the third lower part away from the substrate. The third upper part is at least partially located in the third opening. The lower surface of the third upper part near the substrate is in direct contact with the third lower part. The orthographic projection of the third upper part on the substrate is substantially coincident with the orthographic projection of the third opening on the substrate. The second pin includes the third lower portion and the third upper portion; The flexible circuit board is provided with flexible circuit board pins, and the upper surface of the third upper part of the second pin, away from the substrate, is in direct contact with the flexible circuit board pin.

8. The display substrate according to claim 7, wherein, The protection unit includes a first protection unit. The first lower portion includes a first sub-lower portion, the first opening includes a first sub-opening, and the first sub-opening exposes at least a portion of the first sub-lower portion; The first upper part includes a first sub-upper part, the first sub-upper part and the first sub-lower part are stacked in a direction perpendicular to the substrate and located on the side of the first sub-lower part away from the substrate, the first sub-upper part is at least partially located in the first sub-opening and is in direct contact with the first sub-lower part; The first protective part includes a first lower sub-part and a first upper sub-part. The detection lead has an end that directly contacts the corresponding second pin, and the end has the first protective portion.

9. The display substrate according to claim 8, wherein, The protective part includes a second protective part, which includes a second lower sub-part and a second upper sub-part; The first detection lead has a first protection portion and a second protection portion. The second protection portion of the first detection lead is connected to the first protection portion of the first detection lead and is located on the side of the first protection portion of the first detection lead away from the second pin.

10. The display substrate according to claim 9, wherein, For the first detection lead, the overlapping portion is located on the side of the end away from the second pin, and the overlapping portion is connected to the second pin via the end.

11. The display substrate according to claim 10, wherein, The first detection lead includes an inclined portion intersecting the first direction, and the inclined portion includes the overlapping portion.

12. The display substrate according to claim 7, wherein, The display substrate includes a plurality of second pins, which are arranged along the first direction; the display substrate includes a plurality of detection leads, and the first portion of the pins of the plurality of second pins are connected to the plurality of detection leads one-to-one; The flexible circuit board has a plurality of flexible circuit board pins arranged along the first direction, and a plurality of second pins are connected to the plurality of flexible circuit board pins one by one.

13. The display substrate according to claim 12, wherein, At least one third upper portion of the plurality of second pins is integrally formed with the first upper portion of the corresponding detection lead.

14. The display substrate according to claim 12, wherein, The first pin includes an input pin and an output pin, and both the input pin and the output pin include a second upper part and a second lower part; The second upper part of the input pin is electrically connected to the third upper part of the second pin.

15. The display substrate according to claim 14, wherein, The second direction is located in the same plane as the first direction and intersects with the first direction. In the second direction, the flexible circuit board is located on the side of the detection lead and the integrated circuit board near the edge of the extension. In the second direction, the plurality of input pins, the plurality of output pins, and the plurality of second pins are arranged at intervals from each other, with the plurality of input pins located between the plurality of output pins and the plurality of second pins; The display substrate further includes: Multiple connection electrodes are disposed on the same layer as the second upper part and the third upper part, wherein the multiple connection electrodes electrically connect the second upper part of the multiple input pins and the third upper part of the multiple second pins in a one-to-one correspondence across the gap between the multiple input pins and the multiple second pins.

16. The display substrate according to claim 7, wherein, The pixel circuit includes: A power line, including a portion located in the extension, is configured to provide a power supply voltage to the pixel circuit and is electrically connected to a portion of the second pins of a plurality of second pins of the flexible circuit board configured to provide a power supply voltage to the pixel circuit, wherein the conductive structure includes the portion of the power line located in the extension. The lower portion includes a fourth lower portion, the opening includes a fourth opening, and the fourth opening exposes at least a portion of the fourth lower portion; The upper portion includes a fourth upper portion, which is stacked with the fourth lower portion in a direction perpendicular to the substrate and located on the side of the fourth lower portion away from the substrate. The fourth upper portion is at least partially located in the fourth opening, and the lower surface of the fourth upper portion near the substrate is in direct contact with the fourth lower portion. The orthographic projection of the fourth upper portion onto the substrate substantially coincides with the orthographic projection of the fourth opening onto the substrate. The portion of the power cord located in the extension includes the fourth upper portion and the fourth lower portion.

17. The display substrate according to claim 16, wherein, The power cord includes: A first power line is configured to provide a first power voltage to the display pixels; and A second power line is configured to provide a second power supply voltage to the display pixel, wherein the second power supply voltage has the opposite polarity to the first power supply voltage; The first power line and the second power line each include a first portion located in the extension, and at least one of the first portion of the first power line and the first portion of the second power line includes the fourth lower portion and the fourth upper portion.

18. The display substrate according to any one of claims 2-5, wherein, The display substrate further includes: An electrostatic discharge (ESD) shielding unit is located on the extension and configured to shield the detection lead from electrostatic interference, wherein the conductive structure includes the ESD shielding unit. The lower portion includes a fifth lower portion, the opening includes a fifth opening, and the fifth opening exposes at least a portion of the fifth lower portion; The upper portion includes a fifth upper portion, which is stacked with the fifth lower portion in a direction perpendicular to the substrate and located on the side of the fifth lower portion away from the substrate. The fifth upper portion is at least partially located in the fifth opening, and the lower surface of the fifth upper portion near the substrate is in direct contact with the fifth lower portion. The orthographic projection of the fifth upper portion onto the substrate substantially coincides with the orthographic projection of the fifth opening onto the substrate. The electrostatic shielding unit includes the fifth lower part and the fifth upper part.

19. The display substrate according to any one of claims 1-5, wherein, The pixel circuit also includes: The light-emitting device and driving transistor, the data writing transistor, the first gate line and the data line, wherein, The data writing transistor is configured to transmit the data signal transmitted on the data line to the driving transistor under the control of the first scan signal transmitted on the first gate line. The driving transistor is configured to control the magnitude of the driving current flowing through the driving transistor according to the data signal. The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. The data cable is located on the same layer as the upper part.

20. The display substrate according to claim 19, wherein, The pixel circuit includes: A first power line is configured to provide a first power voltage to the display pixels; and The second power line is configured to provide a second power supply voltage to the display pixels. Wherein, the first power supply voltage provided by the first power supply line is a low potential voltage, and the second power supply voltage provided by the second power supply line is a high potential voltage; The first power line also includes a second portion located in the display pixels of the display area, and the second portion of the first power line is disposed on the same layer as the upper part.

21. A display device comprising the display substrate according to any one of claims 1-20.

22. A method for manufacturing a display substrate, wherein, The display substrate includes a display area, a non-display area, and an extension, wherein the display area includes display pixels, and the non-display area at least partially surrounds the display area; the manufacturing method includes: A substrate is provided, wherein the substrate is located in the display area, the non-display area and the extension, and includes a bendable portion located at an edge of the non-display area away from the display area; the display substrate has a first side for display and a second side opposite to the first side, the extension is connected to the bendable portion and bendable to the second side of the display substrate through the bendable portion; A first insulating layer is formed at least on the extension, and an opening is formed in the first insulating layer; A conductive structure is formed on the extension, wherein forming the conductive structure includes: A lower portion is formed, wherein the opening exposes at least a portion of the lower portion; and An upper portion is formed, wherein the upper portion and the lower portion are stacked in a direction perpendicular to the substrate and the upper portion is located on the side of the lower portion away from the substrate, at least partially located in the opening and in direct contact with the lower portion; The method for manufacturing the display substrate further includes: A pixel circuit is formed, wherein the pixel circuit is configured to control the display state of the display pixel; A driving circuit is formed, wherein the driving circuit is at least partially located in the non-display area and includes driving signal lines located in the non-display area, the driving signal lines being configured to provide driving signals to the pixel circuit; and A detection lead is formed, wherein the detection lead is electrically connected to the drive signal line and configured to provide a detection signal to the drive signal line, and extends from the non-display area of ​​the display substrate through the bendable portion to the extension portion of the display substrate; The lower portion includes a first lower portion, the opening includes a first opening, and the first opening exposes at least a portion of the first lower portion; The upper part includes a first upper part, which is stacked with the first lower part in a direction perpendicular to the substrate and located on the side of the first lower part away from the substrate. The first upper part is at least partially located in the first opening and is in direct contact with the first lower part. The first lower portion includes a second lower portion, the first opening includes a second lower opening, and the second lower opening exposes at least a portion of the second lower portion; The first upper part includes the second sub-upper part, the second sub-upper part and the second sub-lower part are stacked in a direction perpendicular to the substrate and located on the side of the second sub-lower part away from the substrate, the second sub-upper part is at least partially located in the second sub-opening and is in direct contact with the second sub-lower part; The method for manufacturing the display substrate further includes: An integrated circuit board is provided on the extension, wherein the integrated circuit board is located on the extension and configured to provide the drive signal to the drive circuit; and A first pin is formed on the extension, wherein the first pin is connected to an integrated circuit board pin disposed on the integrated circuit board; The extension has an edge opposite to the bendable portion and extending along a first direction, in which the detection lead is located on at least one side of the integrated circuit board, and the detection lead includes a first detection lead close to the integrated circuit board; The second direction is located in the same plane as the first direction and intersects with the first direction; The first detection lead has an overlapping portion that overlaps with the first pin in the second direction, the overlapping portion including a second lower sub-part and a second upper sub-part.

23. The method for manufacturing a display substrate according to claim 22, wherein, Forming the conductive structure includes: Forming the first conductive material layer; A first patterning process is performed on the first conductive material layer to form the lower part; A first insulating material layer is formed to cover the lower part, wherein the first insulating material layer is in direct contact with the lower part; A second patterning process is performed on the first insulating material layer to form an intermediate insulating layer, wherein the intermediate insulating layer includes an opening region that exposes at least a portion of the lower portion; A second metallic material layer is formed on the side of the intermediate insulating layer away from the substrate, wherein the second metallic material layer includes a first portion located within the opening region and a second portion located outside the opening region, the first portion being in direct contact with the lower portion, and the lower surface of the second portion near the substrate being in direct contact with the upper surface of the first insulating material layer away from the substrate; and A third patterning process is performed on the second metal material layer to form the upper part, and the opening area is used to form the opening of the conductive structure.

24. The method for manufacturing a display substrate according to claim 23, further comprising: A second insulating material layer is formed to cover the upper part and the opening area, wherein the second insulating material layer is in direct contact with the lower part; A fourth patterning process is performed on the second insulating material layer to form the opening and the first insulating layer.

25. The method for manufacturing a display substrate according to claim 24, wherein, The detection lead includes a protective portion, the conductive structure includes the protective portion, and the protective portion includes a first lower portion and a first upper portion; The conductive structure includes the first pin, the lower portion includes a second lower portion, the opening includes a second opening, and the second opening exposes at least a portion of the second lower portion; The upper part includes a second upper part, which is stacked with the second lower part in a direction perpendicular to the substrate and located on the side of the second lower part away from the substrate. The second upper part is at least partially located in the second opening. The lower surface of the second upper part near the substrate is in direct contact with the second lower part. The orthographic projection of the second upper part on the substrate is located within the orthographic projection of the second opening on the substrate. The first pin includes a second lower part and a second upper part; The opening region includes a first opening region that exposes a second lower portion of a plurality of the first pins and at least a first lower portion of the detection lead.

26. The method for manufacturing a display substrate according to claim 25, wherein, The method for manufacturing the display substrate further includes: A flexible circuit board is provided in the extension, wherein the flexible circuit board is located connected to the detection lead and configured to provide the detection signal to the detection lead, and connected to the integrated circuit board and configured to provide the integrated circuit board with an electrical signal for generating the drive signal; and A second pin is formed on the extension, wherein the second pin is connected to the flexible circuit board, and the second pin includes a first portion of pins, which is connected to the detection lead. The conductive structure includes a second pin, the second pin includes a third lower portion, and the lower portion includes the third lower portion; The opening area further includes a second opening area, the first opening area being connected to and communicating with the second opening area, and the second opening area exposing the third lower part.

27. The method for manufacturing a display substrate according to claim 26, wherein, The protective portion includes a first protective portion, the first lower portion includes a first sub-lower portion, the first opening includes a first sub-opening, and the first sub-opening exposes at least a portion of the first sub-lower portion; The first upper part includes a first sub-upper part, the first sub-upper part and the first sub-lower part are stacked in a direction perpendicular to the substrate and located on the side of the first sub-lower part away from the substrate, the first sub-upper part is at least partially located in the first sub-opening and in direct contact with the first sub-lower part; the first protective part includes the first sub-lower part and the first sub-upper part; The detection lead has an end that directly contacts the second pin, and the end has the first protective portion; The first opening exposes the second lower portion of a plurality of the first pins and the first sub-lower portion of the end.

28. The method for manufacturing a display substrate according to claim 27, wherein, The protective part includes a second protective part, which includes a second lower sub-part and a second upper sub-part; The first opening exposes the second lower portion of a plurality of the first pins and the second sub-lower portion of the overlapping portion.

29. The method for manufacturing a display substrate according to claim 28, wherein, For the first detection lead, the overlapping portion is located on the side of the end away from the second pin, and the overlapping portion is connected to the second pin via the end.

30. The method for manufacturing a display substrate according to claim 28, wherein, The first opening region includes: The first edge extends generally along the first direction and is the boundary between the first opening area and the second opening area; and The second edge intersects the first edge and overlaps the first lower portion in a direction perpendicular to the substrate, wherein, The angle between the first edge and the second edge is called the included angle region, and the second lower part is located in the included angle region.

31. The method for manufacturing a display substrate according to claim 28, wherein, The first opening area has a planar shape of a first rectangle, the second opening area has a planar shape of a second rectangle, the length of the first rectangle along the first direction is less than the length of the second rectangle along the first direction, and the overall planar shape of the first opening area and the second opening area is T-shaped.

32. The method for manufacturing a display substrate according to claim 26, wherein, The flexible circuit board is provided with flexible circuit board pins; Providing an integrated circuit board on the extension includes: binding the integrated circuit board to the substrate such that the first pin corresponds to the pin of the integrated circuit board, and the upper surface of the second upper part of the first pin away from the substrate is in direct contact with the corresponding pin of the integrated circuit board; Providing a flexible circuit board in the extension includes: binding the flexible circuit board to the substrate such that a plurality of second pins correspond one-to-one with a plurality of flexible circuit board pins, and the upper surface of the third upper portion of each of the plurality of second pins, away from the substrate, is in direct contact with the corresponding flexible circuit board pin.

33. The method for manufacturing a display substrate according to any one of claims 24-32, wherein, The pixel circuit also includes: The light-emitting device and driving transistor, the data writing transistor, the first gate line and the data line, wherein, The data writing transistor is configured to transmit the data signal transmitted on the data line to the driving transistor under the control of the first scan signal transmitted on the first gate line. The driving transistor is configured to control the magnitude of the driving current flowing through the driving transistor according to the data signal. The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light. The method for manufacturing the display substrate includes: The upper part and the data line are formed by performing the third patterning process on the second conductive material layer.

34. The method for manufacturing a display substrate according to claim 33, wherein, The pixel circuit includes: A first power line is configured to provide a first power voltage to the display pixels; and The second power line is configured to provide a second power supply voltage to the display pixel, wherein the first power supply voltage is a low potential voltage and the second power supply voltage is a high potential voltage; The first power line includes a first portion located on the extension and a second portion located in the display pixels of the display area; The method for manufacturing the display substrate includes: The second portion of the first power line is also formed by performing the third patterning process on the second conductive material layer.

Images