Internal ripple compensation circuit for COT mode converter and converter

Abstract

The application discloses an internal ripple compensation circuit suitable for a COT mode converter and the converter, and the internal ripple compensation circuit comprises an inductor current sampling circuit, which is used for sampling an inductor current signal, obtaining a sampling current in a certain proportional relationship with the inductor current, and inputting the sampling current into an inductor current ripple sampling and holding circuit; the inductor current ripple sampling and holding circuit is used for converting the received sampling current signal into a voltage signal, obtaining sampling inductor current information and inductor current valley information in a sampling period, and holding the inductor current valley information and inputting the inductor current valley information into a ripple superposition circuit; the ripple superposition circuit is used for superimposing a reference voltage, the sampling inductor current information and the inductor current valley information to obtain a superimposed ripple compensation reference voltage. Through the embodiment of the application, the internal ripple compensation circuit is ensured to realize ripple compensation to meet loop stability, and meanwhile, the precision of an output voltage is ensured.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an internal ripple compensation circuit and converter suitable for COT mode converters. Background Technology

[0002] In electronic circuit design, compared to traditional voltage control and peak current mode control, COT (Constant-on-Time) control mode has significant advantages. COT control mode does not require a traditional error amplifier, allowing for faster response while maintaining accuracy. COT control mode offers significantly improved efficiency under light loads, aligning with future trends in electronic products. Furthermore, COT control mode maintains a constant frequency across the entire input range, which is crucial for combating electromagnetic interference. Additionally, the COT control loop is relatively simple. COT control architecture is highly favored in power management chips.

[0003] Traditional ripple compensation circuits require output capacitors with high ESR (Equivalent Series Resistance) to generate significant output ripple. However, with the increasing demand for integration, low-ESR, small-size surface-mount tantalum or ceramic capacitors have become mainstream. Therefore, a phase lag exists between the output voltage and inductor current in traditional COT-controlled buck converters, causing subharmonic oscillations in the converter. For example... Figure 1 As shown.

[0004] To address the subharmonic oscillations caused by the phase lag of the output ripple, on-chip ripple compensation is introduced, such as... Figure 2 As shown, this ripple compensation method requires the use of more external components, which undoubtedly increases the complexity and cost of the system.

[0005] Chinese patent (publication number CN106253671A) discloses a method for ripple compensation based on sampled inductor current, including the following steps: first, sampling the inductor current; second, pre-amplifying the inductor current ripple information; third, maintaining the amplified signal; and fourth, a ripple superposition circuit. This patent's internal ripple compensation circuit eliminates the need for an additional sampling circuit, reducing external components, simplifying system design complexity, and ensuring system stability. However, in the disclosed technical solution, the sampled inductor current signal is affected by the on-resistance of the power device. The on-resistance of the power transistor is affected by temperature, manufacturing process, and power supply voltage. Therefore, the final ripple compensation is significantly affected by temperature, manufacturing process, and power supply voltage. Furthermore, the input common-mode range of the ripple amplification circuit and the ripple superposition circuit is relatively small. For applications with high current and high power transistor on-resistance, the sampled voltage signal exceeds the input common-mode range, making on-chip ripple compensation impossible. Summary of the Invention

[0006] The present invention aims to provide an internal ripple compensation circuit and converter suitable for COT mode converters. The internal ripple compensation circuit generates a reference voltage with superimposed ripple compensation in a linear relationship with the inductor current ripple, and is unaffected by process, temperature and internal voltage. This ensures that the internal ripple compensation circuit achieves ripple compensation to meet loop stability, while also ensuring the accuracy of the output voltage.

[0007] To solve the above-mentioned technical problems, embodiments of the present invention provide the following technical solution: an internal ripple compensation circuit suitable for COT mode converters, the internal ripple compensation circuit comprising: an inductor current sampling circuit, an inductor current ripple sample-and-hold circuit, and a ripple superposition circuit; wherein:

[0008] The inductor current sampling circuit is used to sample the inductor current signal to obtain a sampling current that is proportional to the inductor current, and input the sampling current into the inductor current ripple sample-and-hold circuit.

[0009] The inductor current ripple sample-and-hold circuit is used to convert the received sampled current signal into a voltage signal, and to acquire the sampled inductor current information and inductor current valley information within the sampling period, and to hold the inductor current valley information and input it into the ripple superposition circuit.

[0010] The ripple superposition circuit is used to superimpose the reference voltage, the sampled inductor current information, and the inductor current valley information to obtain a reference voltage with superimposed ripple compensation.

[0011] Optionally, the inductor current sampling circuit includes: a voltage sampling circuit and a current sampling circuit; wherein:

[0012] The voltage sampling circuit is used to sample the lower power transistor turn-on voltage generated by the inductor current across the lower power transistor's on-resistance.

[0013] The current sampling circuit is used to convert the conduction voltage of the lower power transistor into a sampling current.

[0014] Optionally, the voltage sampling includes: a first NMOS transistor, a second NMOS transistor, and an inverter;

[0015] The input terminal of the inverter is connected to the sampling control signal terminal and then to the gate of the second NMOS transistor, and the output terminal is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is grounded, and the drain is connected to the source of the second NMOS transistor. The drain of the second NMOS transistor is connected to the switch SW terminal. The sampling voltage is output at the connection between the drain of the first NMOS transistor and the source of the second NMOS transistor.

[0016] Optionally, when the lower power transistor is turned on, the sampling control signal is high, the first NMOS transistor is turned off, the second NMOS transistor is turned on, and the sampling voltage is equal to the voltage of switch SW; when the lower power transistor is turned off, the sampling control signal is low, the first NMOS transistor is turned on, the second NMOS transistor is turned on, and the sampling voltage is equal to the ground voltage.

[0017] Optionally, the current sampling circuit includes: a first amplifier circuit, a current mirror, and a voltage-controlled resistor;

[0018] The first amplifier circuit is used to ensure that the voltages at the two input terminals of the amplifier circuit are equal; the voltage-controlled resistor is used to convert the voltage difference between SW voltage and GND into current; the current mirror is used to mirror the sampled current.

[0019] Optionally, the first amplifier circuit includes two or more current sources, three or more NMOS transistors, and two or more PMOS transistors; the current mirror includes two or more PMOS transistors.

[0020] Optionally, the inductor current ripple sample-and-hold circuit includes: a first switch, a second switch, a first resistor, a first capacitor, and a second capacitor; wherein,

[0021] The first resistor converts the sampled current into a voltage; the first switch and the first capacitor sample the converted voltage; the second switch and the second capacitor hold the voltage of the first capacitor and transmit the sampled voltage and the held voltage to the ripple superposition circuit.

[0022] Optionally, the ripple superposition circuit includes a transconductance amplifier and an operational amplifier; the input terminal of the transconductance amplifier is connected to the inductor current ripple sampling and holding circuit; the positive terminal of the operational amplifier is connected to the reference voltage terminal, the negative terminal is connected to the output terminal, and the output terminal is connected to the reference voltage output terminal of the transconductance amplifier for superposition ripple compensation through a fourth resistor.

[0023] Optionally, the transconductance amplifier converts the difference between the sampled voltage and the holding voltage into a current signal; the operational amplifier serves as a buffer for the reference voltage; the fourth resistor converts the current signal into a voltage signal; and the transconductance amplifier, the operational amplifier, and the fourth resistor superimpose the difference between the sampled voltage and the holding voltage onto the reference voltage.

[0024] To solve the above-mentioned technical problems, the embodiments of the present invention also provide the following technical solution: a converter, the converter including an internal ripple compensation circuit as described in any embodiment of the present invention.

[0025] Compared with existing technologies, the present invention provides an internal ripple compensation circuit and converter suitable for COT mode converters. It samples the inductor current signal through an inductor current sampling circuit to obtain a sampling current proportional to the inductor current, ensuring that the sampling current and the inductor current have the same phase information. Simultaneously, the ratio of the sampling current to the inductor current is a fixed constant, independent of the power transistor's on-resistance, thus eliminating the influence of process, temperature, and internal voltage. Finally, the sampled current is input to an inductor current ripple sample-and-hold circuit. This circuit converts the received sampling current signal into a voltage signal and acquires the sampled inductor current information and inductor current valley information within the sampling period, inputting these to a ripple superposition circuit. This ensures that the final superimposed ripple is the inductor current ripple information, eliminating the DC information of the inductor current. The ripple superposition circuit superimposes the reference voltage, the sampled inductor current information, and the inductor current valley information to obtain a reference voltage for superimposed ripple compensation. This ensures that the ripple magnitude of the reference voltage Vsigma generated by the internal ripple compensation circuit is linearly related to the inductor current ripple, and is unaffected by process, temperature, or internal voltage. This guarantees that the internal ripple compensation circuit achieves ripple compensation to meet loop stability requirements, while also preventing DC offset of the output voltage. Furthermore, all circuits in the entire ripple compensation circuit have a large linear input range, ensuring that ripple compensation remains unaffected in applications with high current and high power transistor on-resistance. By superimposing the AC quantity of the sampled current onto the reference voltage, the phase lag between the output ripple voltage and the inductor current caused by the small ESR (Equivalent Series Resistance) of the output capacitor is eliminated, thereby solving the subharmonic oscillation problem of the converter. The internal ripple compensation circuit for a COT-mode converter provided in this invention overcomes the subharmonic oscillation of COT control, maintains good stability, improves the DC error of traditional COT, and enhances circuit accuracy. Compared to traditional COT control systems, this invention eliminates the dependence on the ESR of the output capacitor, broadening the range of selectable output capacitor components. Compared to off-chip ripple compensation circuits, it reduces external components, lowering costs and system complexity. Compared to other on-chip ripple compensation circuits, it ensures a linear relationship between the ripple compensation amount and the inductor current ripple, and is almost unaffected by process, power supply voltage, and temperature. This makes the circuit stability design independent of power supply voltage, process, and temperature drift. Furthermore, the solution of this invention does not impose any particular limitations on the inductor current magnitude or the power transistor on-resistance. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0027] Figure 1 This is a block diagram of a traditional COT mode controlled buck converter.

[0028] Figure 2 This is a schematic diagram of a traditional COT mode controlled off-chip ripple compensation circuit.

[0029] Figure 3 This is a block diagram of a converter with an internal ripple compensation circuit based on COT mode control provided by the present invention.

[0030] Figure 4 This is a block diagram of an internal ripple compensation circuit based on a COT mode converter provided by the present invention.

[0031] Figure 5 This is a schematic diagram of the inductor current sampling circuit in the internal ripple compensation circuit of a COT mode converter provided by the present invention.

[0032] Figure 6 This is a schematic diagram of an inductor current ripple sample-and-hold circuit in an internal ripple compensation circuit of a COT mode converter provided by the present invention.

[0033] Figure 7 This is a schematic diagram of the ripple superposition circuit in the internal ripple compensation circuit of a COT mode converter provided by the present invention.

[0034] Figure 8 This is a simulation diagram of the internal signal waveform for ripple compensation in an internal ripple compensation circuit based on a COT mode converter provided by the present invention.

[0035] Figure 9 This is a simulation diagram of the waveform of the reference voltage signal after ripple compensation under different process angles in the internal ripple compensation circuit of the COT mode converter provided by the present invention.

[0036] Figure 10 This is a simulation diagram of the waveform of the reference voltage signal after ripple compensation at different temperatures in the internal ripple compensation circuit of a COT mode converter provided by the present invention. Detailed Implementation

[0037] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0039] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] In one embodiment, such as Figure 4 As shown, the present invention provides an internal ripple compensation circuit suitable for COT mode converters. The internal ripple compensation circuit 100 includes: an inductor current sampling circuit 10, an inductor current ripple sample-and-hold circuit 20, and a ripple superposition circuit 30; wherein:

[0041] The inductor current sampling circuit 10 is used to sample the inductor current signal to obtain a sampling current that is proportional to the inductor current, and input the sampling current into the inductor current ripple sample-and-hold circuit 20.

[0042] The inductor current ripple sample-and-hold circuit 20 is used to convert the received sampled current signal into a voltage signal, and to acquire the sampled inductor current information and inductor current valley information within the sampling period, hold the inductor current valley information, and input the sampled inductor current information and inductor current valley information into the ripple superposition circuit 30.

[0043] The ripple superposition circuit 30 is used to superimpose the reference voltage, the sampled inductor current information, and the inductor current valley information to obtain a reference voltage with superimposed ripple compensation.

[0044] In this embodiment, the inductor current signal is sampled by an inductor current sampling circuit to obtain a sampling current that is proportional to the inductor current, ensuring that the sampling current and the inductor current have the same phase information. Simultaneously, the ratio of the sampling current to the inductor current is a fixed constant, independent of the power transistor's on-resistance, thus eliminating the influence of process, temperature, and internal voltage. Finally, the sampled current is input to an inductor current ripple sample-and-hold circuit. This circuit converts the received sampling current signal into a voltage signal and acquires the sampled inductor current information and inductor current valley information within the sampling period, inputting these to a ripple superposition circuit. This ensures that the final superimposed ripple is the inductor current ripple information, eliminating the DC information of the inductor current. The ripple superposition circuit then superimposes the reference voltage, the sampled inductor current information, and the inductor current valley information to obtain a reference voltage for superimposed ripple compensation. This ensures that the ripple magnitude of the reference voltage Vsigma generated by the internal ripple compensation circuit is linearly related to the inductor current ripple, and is unaffected by process technology, temperature, or internal voltage. This guarantees that the internal ripple compensation circuit achieves ripple compensation to meet loop stability requirements, while also preventing DC offset of the output voltage. Furthermore, all circuits in the entire ripple compensation circuit have a large linear input range, ensuring that ripple compensation remains unaffected in applications with high current and high power transistor on-resistance. By superimposing the AC quantity of the sampled current onto the reference voltage, the phase lag between the output ripple voltage and the inductor current caused by the small ESR (Equivalent Series Resistance) of the output capacitor is eliminated, thereby resolving the subharmonic oscillation problem of the converter.

[0045] In one embodiment, the inductor current sampling circuit 10 is used to sample the inductor current signal, obtain a sampling current that is proportional to the inductor current, and input the sampling current into the inductor current ripple sample-and-hold circuit 20.

[0046] like Figure 3 The diagram shown is a block diagram of a converter with an internal ripple compensation circuit based on COT mode control provided by the present invention.

[0047] like Figure 5 The diagram shown is a schematic of the inductor current sampling circuit in the internal ripple compensation circuit of a COT mode converter provided by the present invention.

[0048] The inductor current sampling circuit 10 includes a voltage sampling circuit 11 and a current sampling circuit 12.

[0049] in:

[0050] The current sampling circuit 12 is used to sample the inductor current I. L ;

[0051] The voltage sampling circuit 11 is used to sample the inductor current I. L The on-resistance R of the lower power transistor MPL dson_p1 The generated sampling voltage V SW_R ;

[0052] The current sampling circuit 12 is used to sample the voltage V. SW_R Converted to sampling current I SENSE .

[0053] The voltage sampling circuit 11 includes: a first NMOS transistor MN1, a second NMOS transistor MN2, and an inverter INV; the input terminal of the inverter INV is connected to the sampling control signal G1 and then to the gate of the second NMOS transistor MN2, and the output terminal is connected to the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is grounded, and its drain is connected to the source of the second NMOS transistor MN2; the drain of the second NMOS transistor MN2 is connected to the switch SW terminal; the sampling voltage V is output at the connection between the drain of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2. SW_R .

[0054] When the current power transistor MPL is turned on, the sampling control signal G1 is high, the first NMOS transistor MN1 is turned off, the second NMOS transistor MN2 is turned on, and the sampling voltage V... SW_R Equal to the voltage V of switch SW sw When the current power transistor MPL is turned off, the sampling control signal G1 is low, the first NMOS transistor MN1 is turned on, the second NMOS transistor MN2 is turned on, and the sampling voltage V... SW_R It equals the voltage of ground (GND).

[0055] The current sampling circuit 12 includes: a first amplifier circuit, a current mirror, and a voltage-controlled resistor; the first amplifier circuit is used to ensure that the voltages at the two input terminals of the first amplifier circuit are equal; the voltage-controlled resistor is used to convert the voltage difference between SW voltage and GND into current; the current mirror is used to mirror the sampled current.

[0056] The first amplifier circuit includes two or more current sources, three or more NMOS transistors, and two or more PMOS transistors; the current mirror includes two or more PMOS transistors.

[0057] Specifically, the first amplifier circuit includes at least a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a first PMOS transistor MP1, a third PMOS transistor MP3, and a first current source I. b1 Second current source I b2 The current mirror structure includes at least a second PMOS transistor MP2 and a fourth PMOS transistor MP4. At the same time, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 can together constitute the current mirror structure.

[0058] in:

[0059] First current source I b1 Second current source I b2 Each is connected to the internal power supply AVCC terminal; the gate of the third NMOS transistor MN3 is connected to the internal power supply AVCC terminal, and then connected to the gate of the fourth NMOS transistor MN4, with its source connected to the sampling voltage V. SW_R The drain of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5; the gate of the fourth NMOS transistor MN4 is connected to the internal power supply AVCC terminal, its source is grounded, and its drain is connected to the source of the sixth PMOS transistor MN6; the gate and drain of the fifth NMOS transistor MN5 are connected, and its drain is connected to the first current source I. b1 Connections: The gate of the sixth NMOS transistor MN6 is connected to the gate of the fifth NMOS transistor MN5, and the drain is connected to the second current source I. b2 Connections: The gate of the seventh NMOS transistor MN7 is connected to the gates of the sixth NMOS transistor MN6 and the fifth NMOS transistor MN5, respectively. Its source is connected to the junction of the drain of the third NMOS transistor MN3 and the source of the fifth NMOS transistor MN5. Its drain is connected to the drain of the third PMOS transistor MP3. The gate and drain of the first PMOS transistor MP1 are connected, its source is connected to the internal power supply AVCC terminal, and its drain is connected to the source of the third PMOS transistor MP3. The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, its source is connected to the internal power supply AVCC terminal, and its drain is connected to the source of the fourth PMOS transistor MP4. The gate and drain of the third PMOS transistor MP3 are connected, its source is connected to the drain of the first PMOS transistor MP1, and its drain is connected to the drain of the seventh NMOS transistor MN7. The gate of the fourth PMOS transistor MP4 is connected to the gate of the third PMOS transistor MP3, and its source is connected to the drain of the second PMOS transistor MP2. The drain outputs a sampling current I. SENSE The sampling current I SENSE The input is fed into the inductor current ripple sampling and holding circuit 20.

[0060] When the current power transistor MPL is turned on, the inductor current I is sampled according to the inductor current sampling circuit.L and the on-resistance R of the lower power transistor MPL dson_p1 The sampled voltage V was calculated. SW_R The sampling voltage V SW_R It can be represented as:

[0061] V SW_R =0-I L R dson_p1 =-I L R dson_p1 (1)

[0062] Wherein, the sampling voltage V SW_R Includes inductor current I L Information.

[0063] At the same time, the voltage-controlled resistor will convert the sampling voltage V SW_R The voltage difference with GND is converted into a sampling current I. SENSE The voltage-controlled resistor includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4, with an on-resistance of R for MN3 and MN4. dson_n3 According to the voltage-controlled resistor R dson_n3 The sampling current I can be calculated. SENSE :

[0064]

[0065] From the above (2), it can be concluded that the sampling current I sampled by the inductor current sampling circuit 10 is... SENSE With inductor current I L A certain proportional relationship is maintained to ensure the sampling current I SENSE With inductor current I L Having the same phase information, and simultaneously sampling current I SENSE With inductor current I L The ratio is a fixed constant.

[0066] In one embodiment, the inductor current ripple sample-and-hold circuit 20 is used to convert the received sampled current signal into a voltage signal, and to acquire the sampled inductor current information and the inductor current valley value I within the sampling period. L_MIN Information, and maintain the inductor current valley value information, and combine the sampled inductor current information and the inductor current valley value I L_MIN The information is input into the ripple superposition circuit 30.

[0067] The inductor current ripple sample-and-hold circuit 20 includes: a first switch S1, a second switch S2, a first resistor R1, a first capacitor C1, and a second capacitor C2; wherein...

[0068] The first resistor R1 converts the sampled current into a voltage; the first switch S1 and the first capacitor C1 sample the converted voltage; the second switch S2 and the second capacitor C2 hold the voltage of the first capacitor C1 and transmit the sampled voltage and the held voltage to the ripple superposition circuit.

[0069] like Figure 6 The diagram shown is a schematic of an inductor current ripple sample-and-hold circuit in an internal ripple compensation circuit of a COT mode converter provided by the present invention.

[0070] The inductor current ripple sample-and-hold circuit 20 includes: a first switch S1, a second switch S2, a first resistor R1, a first capacitor C1, and a second capacitor C2; wherein, one end of the first switch S1 is connected in series with one end of the second switch S2, one end of the first capacitor C1 is connected to the connection point of the first switch S1 and the second switch S2, the other end of the first resistor R1 is connected to the other end of the first switch S1, the other end of the second capacitor C2 is connected to the other end of the second switch S2, and the other ends of the first resistor R1, the first capacitor C1, and the second capacitor C2 are respectively connected together; the connection point of the first resistor R1 and the first switch S1 is connected to the sampling current I of the inductor current ripple sample-and-hold circuit 20. SENSE Connect the output terminal.

[0071] exist Figure 6 In the process, the inductor current ripple sample-and-hold circuit 20 samples the current I. SENSE Converted to sampling voltage V SENSE .

[0072] When the lower power transistor MPL is turned on, the first switch S1 is turned on and the second switch S2 is turned off. At this time, the sampled voltage V SENSE The voltage V across the first capacitor C1 SENSEP Same; that is:

[0073]

[0074] When the lower power transistor MPL is turned off, the first switch S1 is off and the second switch S2 is on. At this time, the first capacitor C1 and the second capacitor C2 remain connected in parallel. The voltage V across the first capacitor C1 at this time is... SENSEP_MIN The valley value of the inductor current I L_MIN Based on the sampling voltage corresponding to the time, and according to the formula for the potential energy of a capacitor, the voltage V of the second capacitor C2 can be calculated. SENSEN for:

[0075]

[0076] Wherein, voltage V SENSEN_N-1This is the voltage across the second capacitor C2 in the previous switching cycle.

[0077] After the circuit stabilizes, the voltage V SENSEP_MIN Given a fixed value, the following can be derived using the iterative method:

[0078]

[0079] In this embodiment, the inductor current ripple sample-and-hold circuit 20 first samples the current I... SENSE Converted to sampling voltage V SENSE Obtain the sampled inductor current information and the inductor current valley value I within the sampling period. L_MIN Information, and maintain the inductor current valley value information, and combine the sampled inductor current information and the inductor current valley value I L_MIN The information is input into the ripple superposition circuit 30, thereby ensuring that the final superimposed ripple is the ripple information of the inductor current and eliminating the DC information of the inductor current.

[0080] In one embodiment, the ripple superposition circuit 30 is used to superimpose the reference voltage, the sampled inductor current information, and the inductor current valley information to obtain a reference voltage with superimposed ripple compensation.

[0081] The ripple superposition circuit 30 includes a transconductance amplifier 31 and an operational amplifier 32; the input terminal of the transconductance amplifier 31 is connected to the inductor current ripple sampling and holding circuit 20; the positive terminal of the operational amplifier 31 is connected to the reference voltage terminal, the negative terminal is connected to the output terminal, and the output terminal is connected to the reference voltage output terminal of the transconductance amplifier 31 for superposition ripple compensation through a fourth resistor R4.

[0082] The transconductance amplifier 31 converts the difference between the sampled voltage and the holding voltage into a current signal; the operational amplifier 32 serves as a buffer for the reference voltage; the fourth resistor R4 converts the current signal into a voltage signal; the transconductance amplifier 31, the operational amplifier 32, and the fourth resistor R4 superimpose the difference information between the sampled voltage and the holding voltage onto the reference voltage, such as by multiplying the voltage difference by a corresponding coefficient or by performing corresponding calculations on the voltage difference and then superimposing it onto the reference voltage.

[0083] like Figure 7 The diagram shown is a schematic of the ripple superposition circuit in the internal ripple compensation circuit of a COT mode converter provided by the present invention.

[0084] The ripple superposition circuit 30 includes a transconductance amplifier 31 and an operational amplifier 32.

[0085] The transconductance amplifier 31 includes: a third current source I b3The transistors are: 8th NMOS transistor MN8, 9th NMOS transistor MN9, 10th NMOS transistor MN10, 11th NMOS transistor MN11, 5th PMOS transistor MP5, 6th PMOS transistor MP6, 7th PMOS transistor MP7, 8th PMOS transistor MP8, 9th PMOS transistor MP9, 10th PMOS transistor MP10, 2nd resistor R2, 3rd resistor R3, and 4th resistor R4. Where:

[0086] The third current source Ib3 is connected to the internal power supply AVCC terminal.

[0087] The voltage V at the gate of the fifth PMOS transistor MP5 connected to the first capacitor C1 SENSEP The source of the transistor is connected to the second resistor R2 and then to the third current source Ib3. The drain of the transistor is connected to the drain of the ninth NMOS transistor MN9. The gate of the sixth PMOS transistor MP6 is connected to the voltage V of the second capacitor C2. SENSEN The source of the NMOS transistor MN10 is connected to the third current source Ib3 after being connected to the third resistor R3. The drain of the NMOS transistor MN9 is connected to the drain of the tenth NMOS transistor MN10. The gate and drain of the ninth NMOS transistor MN9 are connected, the source is grounded, and the drain of the ninth PMOS transistor MP5 is connected. The gate and drain of the tenth PMOS transistor MN10 are connected, the source is grounded, and the drain of the sixth PMOS transistor MP6 is connected. The gate of the eighth NMOS transistor MN8 is connected to the gate of the ninth NMOS transistor MN9, the source is grounded, and the drain of the seventh PMOS transistor MP7 is connected. The gate of the eleventh NMOS transistor MN11 is connected to the gate of the tenth NMOS transistor MN10, the source is grounded, and the drain of the sixth PMOS transistor MP6 is connected. The gate and drain of the seventh PMOS transistor MP7 are connected, and the source of the eighth NMOS transistor MP6 is connected. The drain of PMOS transistor MP8 is connected to the drain of the eighth NMOS transistor MN8; the gate of the tenth PMOS transistor MP10 is connected to the gate of the seventh PMOS transistor MP7, and its source is connected to the drain of the ninth PMOS transistor MP9, and its drain is connected to the drain of the eleventh NMOS transistor MN11; the gate and drain of the eighth PMOS transistor MP8 are connected, its source is connected to the internal power supply AVCC terminal, and its drain is connected to the source of the seventh PMOS transistor MP7; the gate of the ninth PMOS transistor MP9 is connected to the gate of the eighth PMOS transistor MP8, its source is connected to the internal power supply AVCC terminal, and its drain is connected to the source of the tenth PMOS transistor MP10; the connection between the drain of the tenth PMOS transistor MP10 and the drain of the eleventh NMOS transistor MN11 outputs a reference voltage V with superimposed ripple compensation. sigma .

[0088] The positive terminal of the operational amplifier 32 is connected to the reference voltage VREF, and the negative terminal is connected to the output terminal VREBUF. The output terminal VRBUF is connected to the reference voltage V of the transconductance amplifier 31 through a fourth resistor R4, which is used for superimposed ripple compensation.sigma Connect the output terminal.

[0089] exist Figure 7 In the circuit, the ripple superposition circuit 30 includes a transconductance amplifier 31 and an operational amplifier 32; the input terminal of the transconductance amplifier 31 is connected to the voltage V of the second capacitor C2. SENSEN The voltage V of the first capacitor C1 SENSEP The output terminal V of the transconductance amplifier 31 sigma A fourth resistor R4 is connected to the output terminal VRBUF of operational amplifier 32. The positive terminal of operational amplifier 32 is connected to the reference voltage VREF terminal, and the negative terminal is connected to the output terminal VREBUF.

[0090] Based on the virtual short characteristic of the input of operational amplifier 32, the output voltage VRBUF of operational amplifier 32 can be derived as follows:

[0091] VRBUF = VREF (6)

[0092] The second resistor R2 and the third resistor R3 in the transconductance amplifier 31 are set to have the same size, and the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are set to have the same size. The transconductance g of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 is set to be... m5，6 The product of g and the resistance of the second resistor R2 m5，6 With R2 >> 1, the transconductance Gm of transconductance amplifier 31 can be calculated as follows:

[0093]

[0094] The current flowing into transconductance amplifier 31 can then be calculated as follows:

[0095]

[0096] The reference voltage V for superimposed ripple compensation can then be calculated. sigma for:

[0097] V sigma =VRBUF-I ripple R4 (9)

[0098] Based on the above formulas, the reference voltage V for superimposed ripple compensation can be obtained. sigma :

[0099]

[0100] The structure of the transconductance amplifier 31 in the ripple superposition circuit 30 determines that the ripple superposition circuit 30 has a large input differential mode range, which can well handle applications with large inductor current ripple.

[0101] Among them, the lower power transistor MPL and the third NMOS transistor and the fourth NMOS transistor MN4 in the inductor current sampling circuit 10 both operate in the linear region. According to the expression of the on-resistance when operating in the linear region:

[0102]

[0103] In equation (11) above, u n，p V is the carrier mobility, Cox is the gate oxide capacitance per unit area, W and L are the width and length of the MOSFET, respectively, and V is the voltage. GS This is the gate-source voltage of the MOSFET.

[0104] To ensure that the power transistor MPL and the third and fourth NMOS transistors MN4 in the inductor current sampling circuit 10 are of the same type, and that the gate voltage is connected to the internal power supply AVCC, the reference voltage V for ripple compensation is superimposed. sigma It can be represented as:

[0105]

[0106] In equation (12) above, (W / L) PL The aspect ratio (W / L) of the lower power transistor MPL. 3，4 This refers to the width-to-length ratio of the third and fourth NMOS transistors MN4 in the inductor current sampling circuit 10. The first resistor R1 and the second resistor R2 are set to be of the same type. Choosing a resistor with zero temperature coefficient for the third resistor R3 ensures that ripple compensation is unaffected by temperature, voltage, or the manufacturing process of the power transistors.

[0107] At the same time, in the inductor current I L Reaching the inductor current valley value I L_MIN When the upper power transistor MPH is turned on and the lower power transistor MPL is turned off, that is, V FB (Feedback voltage) = V sigma =V REF When the upper power transistor MPH is turned on and the lower power transistor MPL is turned off, the internal ripple compensation circuit can achieve ripple compensation to meet loop stability, while also preventing DC offset of the output voltage.

[0108] like Figure 8 The diagram shown is a simulation schematic of the internal ripple compensation signal waveform in an internal ripple compensation circuit based on a COT mode converter provided by this invention. Figure 9 The image shown is a simulation diagram illustrating the waveform of the reference voltage signal after ripple compensation in the internal ripple compensation circuit of a COT mode converter provided by this invention, under different process corners (SS, FF, TT). Figure 10The figure shown is a simulation diagram of the waveform of the reference voltage signal after ripple compensation in the internal ripple compensation circuit of the COT mode converter provided by the present invention at different temperatures of -40°, 25° and 125°. Figures 8 to 10 In this context, Io represents the load current, i.e. Figure 3 Load resistance R L Current on; I L It is the inductor current, i.e. Figure 3 Current in inductor L; V SW_R V is the sampling voltage; SENSEN V is the voltage across the second capacitor C2. SENSEP I is the voltage across the first capacitor C1; ripple V is the current flowing into the transconductance amplifier; REF V is the reference voltage. FB For feedback voltage; V sigma The reference voltage for superimposed ripple compensation.

[0109] from Figures 8 to 10 As can be seen from the simulation diagram, this invention provides an internal ripple compensation circuit suitable for COT mode converters, generating a reference voltage V for superimposed ripple compensation. sigma The ripple magnitude is linearly related to the inductor current and is unaffected by process technology, temperature, or internal voltage. Furthermore, when the inductor current reaches its trough, the ripple compensation is zero. FB =V sigma =V REF Therefore, the ripple compensation circuit ensures both system stability and accuracy, guaranteeing that the internal ripple compensation circuit achieves ripple compensation to meet loop stability requirements, while also preventing DC offset of the output voltage. Furthermore, all circuits in the entire ripple compensation circuit have a large linear input range, ensuring that ripple compensation remains unaffected in applications with high current and high power transistor on-resistance. By superimposing the AC quantity of the sampling current onto the reference voltage, the phase lag between the output ripple voltage and the inductor current caused by the small ESR (Equivalent Series Resistance) of the output capacitor is eliminated, thereby solving the subharmonic oscillation problem of the converter.

[0110] Based on the same concept, in one embodiment, such as Figure 3 As shown, the present invention provides a converter, the converter including an internal ripple compensation circuit 100 of a COT mode converter as described in any of the above embodiments.

[0111] In this embodiment, the internal ripple compensation circuit 100 of the COT mode converter is the same as the internal ripple compensation circuit 100 of the COT mode converter described in any of the above embodiments. The specific structure and function can be referred to the internal ripple compensation circuit 100 of the COT mode converter described in any of the above embodiments, and will not be repeated here.

[0112] In this embodiment, the converter includes an internal ripple compensation circuit based on a COT mode converter, and the internal ripple compensation circuit generates a reference voltage V with superimposed ripple compensation. sigma The ripple magnitude is linearly related to the inductor current and is unaffected by process technology, temperature, or internal voltage. Furthermore, when the inductor current reaches its trough, the ripple compensation is zero. FB =V sigma =V REF Therefore, the ripple compensation circuit ensures both system stability and accuracy, guaranteeing that the internal ripple compensation circuit achieves ripple compensation to meet loop stability requirements, while also preventing DC offset of the output voltage. Furthermore, all circuits in the entire ripple compensation circuit have a large linear input range, ensuring that ripple compensation remains unaffected in applications with high current and high power transistor on-resistance. By superimposing the AC quantity of the sampling current onto the reference voltage, the phase lag between the output ripple voltage and the inductor current caused by the small ESR (Equivalent Series Resistance) of the output capacitor is eliminated, thereby solving the subharmonic oscillation problem of the converter.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An internal ripple compensation circuit suitable for COT mode converters, characterized in that, The internal ripple compensation circuit includes: an inductor current sampling circuit, an inductor current ripple sample-and-hold circuit, and a ripple superposition circuit; wherein: The inductor current sampling circuit is used to sample the inductor current signal to obtain a sampling current that is proportional to the inductor current, and input the sampling current into the inductor current ripple sample-and-hold circuit. The inductor current ripple sample-and-hold circuit is used to convert the received sampled current signal into a voltage signal, and to acquire the sampled inductor current information and inductor current valley information within the sampling period, and to hold the inductor current valley information and input it into the ripple superposition circuit. The ripple superposition circuit is used to superimpose the reference voltage, the sampled inductor current information, and the inductor current valley value information to obtain a reference voltage for superimposed ripple compensation. The inductor current sampling circuit includes: A voltage sampling circuit is used to sample the lower power transistor's on-state voltage generated by the inductor current across the lower power transistor's on-resistance. A current sampling circuit is used to convert the conduction voltage of the lower power transistor into the sampling current, wherein the ratio coefficient between the sampling current and the inductor current is a constant determined by the voltage-controlled resistor inside the current sampling circuit and the conduction resistance of the lower power transistor.

2. The internal ripple compensation circuit according to claim 1, characterized in that, The voltage sampling circuit includes: a first NMOS transistor, a second NMOS transistor, and an inverter; The input terminal of the inverter is connected to the sampling control signal terminal and then to the gate of the second NMOS transistor, and the output terminal is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is grounded, and the drain is connected to the source of the second NMOS transistor. The drain of the second NMOS transistor is connected to the switch SW terminal. The sampling voltage is output at the connection between the drain of the first NMOS transistor and the source of the second NMOS transistor.

3. The internal ripple compensation circuit according to claim 2, characterized in that, When the lower power transistor is turned on, the sampling control signal is high, the first NMOS transistor is off, the second NMOS transistor is on, and the sampling voltage is equal to the voltage of switch SW; when the lower power transistor is turned off, the sampling control signal is low, the first NMOS transistor is on, the second NMOS transistor is on, and the sampling voltage is equal to the ground voltage.

4. The internal ripple compensation circuit according to any one of claims 1-3, characterized in that, The current sampling circuit includes: a first amplifier circuit, a current mirror, and a voltage-controlled resistor; The first amplifier circuit is used to ensure that the voltages at the two input terminals of the first amplifier circuit are equal; the voltage-controlled resistor is used to convert the voltage difference between SW voltage and GND into current; the current mirror is used to mirror the sampled current.

5. The internal ripple compensation circuit according to claim 4, characterized in that, The first amplifier circuit includes at least two current sources, at least three NMOS transistors, and at least two PMOS transistors; the current mirror includes at least two PMOS transistors.

6. The internal ripple compensation circuit according to claim 1, characterized in that, The inductor current ripple sample-and-hold circuit includes: a first switch, a second switch, a first resistor, a first capacitor, and a second capacitor; wherein, The first resistor converts the sampled current into a voltage; the first switch and the first capacitor sample the converted voltage; the second switch and the second capacitor hold the voltage of the first capacitor and transmit the sampled voltage and the held voltage to the ripple superposition circuit.

7. The internal ripple compensation circuit according to claim 1, characterized in that, The ripple superposition circuit includes a transconductance amplifier and an operational amplifier; the input terminal of the transconductance amplifier is connected to the inductor current ripple sampling and holding circuit; the positive terminal of the operational amplifier is connected to the reference voltage terminal, the negative terminal is connected to the output terminal, and the output terminal is connected to the reference voltage output terminal of the transconductance amplifier for superposition ripple compensation through a fourth resistor.

8. The internal ripple compensation circuit according to claim 7, characterized in that, The transconductance amplifier converts the difference between the sampled voltage and the holding voltage into a current signal; the operational amplifier serves as a buffer for the reference voltage; the fourth resistor converts the current signal into a voltage signal; the transconductance amplifier, the operational amplifier, and the fourth resistor superimpose the difference information between the sampled voltage and the holding voltage onto the reference voltage.

9. A converter, characterized in that, The converter includes an internal ripple compensation circuit as described in any one of claims 1 to 8.

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