A quantum computer operating system and quantum computer

Abstract

The application belongs to the field of quantum computing, and discloses a quantum computer operating system and a quantum computer. In the quantum computer operating system, for a quantum chip in a quantum chip cluster of the system, if the number of idle quantum bits on the quantum chip is not less than the number of quantum bits of a quantum computing task, first quantum bits with a readout fidelity within a preset range are selected from the idle quantum bits of the quantum chip, and quantum bits near the first quantum bits that meet the requirements of a reward function obtained based on a community discovery algorithm and a greedy algorithm are combined to form a quantum bit topology structure, until the number of quantum bits of the obtained quantum bit topology structure is equal to the number of quantum bits of the quantum computing task, and the combining is stopped. Finally, the to-be-processed quantum computing task is mapped into the quantum bit topology structure to execute the to-be-processed quantum computing task. The execution timeliness of the quantum computing task in the program waiting queue is effectively improved.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and in particular to a quantum computer operating system and a quantum computer. Background Technology

[0002] Quantum computers use qubits as their basic unit and leverage properties such as quantum superposition and quantum entanglement to achieve revolutionary computing methods. They offer the potential to surpass all classical computing techniques in terms of information carrying capacity and ultra-powerful parallel computing capabilities. Quantum computing is expected to outperform classical computing in problems such as machine learning, chemical simulation, and solving linear equations.

[0003] The importance of the operating system to a computer is self-evident, especially for classical computers and even more so for the still-developing quantum computing technology. The quantum computer's operating system determines its functionality, computational efficiency, and stability, thus determining its practicality. The quantum computer's operating system is the tool connecting the terminal and the core component of the quantum computer—the quantum chip. On one hand, it receives quantum computing tasks sent by the user; on the other hand, it maps these tasks to the specific qubit topology within the quantum chip to execute them. In the implementation of quantum computing tasks, developers primarily focus on the task implementation itself, which often involves the connection of two quantum logic gates between any two qubits. However, for practical quantum chips, due to limitations in physical structure, such as… Figure 1 As shown, qubits are arranged in a grid on the quantum chip. Q1, Q2, Q3, and Q4 represent qubits. Generally, only qubits that are directly connected are allowed to perform two-qubit quantum logic gate operations.

[0004] In existing technologies, quantum computer operating systems typically first divide all qubits on a quantum chip into several executable quantum circuit blocks (i.e., qubit topologies) using a multi-layered partitioning method. Then, based on the number of qubits in the quantum computing task to be run, available executable quantum circuit blocks are selected for mapping. The number of qubits available for execution in these blocks is the same as the number of qubits in the task. However, as the demands of quantum computing in quantum computer operating systems continue to increase, the number of quantum computing tasks to be processed will also increase, and the number of qubits required for each task will vary significantly. Using these executable quantum circuit blocks for mapping to the task can lead to problems such as unreasonable partitioning of executable quantum circuit blocks, long processing time in finding executable quantum circuit blocks that match the task, low utilization of quantum chip qubit resources, long waiting times for quantum computing tasks, and low program efficiency, resulting in a poor user experience. Summary of the Invention

[0005] The purpose of this application is to provide a quantum computer operating system and a quantum computer. The quantum computer operating system can quickly find the optimal partition region on the idle qubits of the quantum chip in the system for each quantum computing task in the program waiting queue to perform the mapping, which effectively improves the utilization rate of quantum chip qubit resources and the runtime efficiency of quantum computing tasks.

[0006] In a first aspect, embodiments of this application provide a quantum computer operating system, comprising:

[0007] A quantum computing task allocation service module, configured to determine quantum computing tasks to be processed from currently unprocessed quantum computing tasks;

[0008] A quantum chip resource allocation service module is configured to obtain the topology of qubits in the idle qubits of a quantum chip based on a community discovery algorithm and a greedy algorithm, wherein the value of the reward function and the number of qubits satisfy a preset threshold, wherein the reward function is obtained through the community discovery algorithm and the greedy algorithm, and the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks;

[0009] A quantum computing task mapping service module is configured to map the quantum computing task to be processed into the qubit topology to execute the quantum computing task.

[0010] Secondly, embodiments of this application provide a method for executing a quantum computing task in a quantum computer, comprising:

[0011] Identify unfinished quantum computing tasks to be processed;

[0012] Based on the community detection algorithm and the greedy algorithm, the reward function value and the number of qubits in the idle qubits of the quantum chip are obtained and the qubit topology structure is such that the number of qubits meets the preset threshold. The reward function is obtained by the community detection algorithm and the greedy algorithm. The idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks.

[0013] The quantum computing task to be processed is mapped into the qubit topology to execute the quantum computing task.

[0014] Thirdly, embodiments of this application provide a quantum computer including a quantum computer operating system as described in any of the above features.

[0015] Fourthly, embodiments of this application provide a readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the execution method described in any of the above features.

[0016] Fifthly, embodiments of this application provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the execution method described in any one of the above features.

[0017] Compared with existing technologies, the quantum chip resource allocation service module in this application provides a quantum computing operating system that uses a community discovery algorithm and a greedy algorithm to acquire a suitable qubit topology from the idle qubits of a quantum chip. For a quantum chip in the system's quantum chip cluster, if the number of idle qubits on it is not less than the number of qubits for the quantum computing task, a suitable qubit topology is selected from the idle qubits of that quantum chip. Merging stops when the number of qubits in the obtained qubit topology equals the number of qubits for the quantum computing task. Finally, the quantum computing task to be processed is mapped to the qubit topology to execute the task. Therefore, the quantum computer operating system of this application... The system utilizes a "bottom-up" approach to perform high-quality, real-time dynamic partitioning of the idle qubits of a quantum chip in the system's quantum chip cluster that meets the required number of idle qubits, according to the actual needs of the quantum computing task to be processed. The resulting qubit topology can uniquely match the quantum computing task to be processed, with no matching waiting time and a high matching degree, greatly improving the resource utilization of the quantum chips and effectively improving the execution timeliness of quantum computing tasks in the program waiting queue. Using the quantum computer operating system of this application, each quantum computing task in the program waiting queue can quickly find its optimal partition region on the idle qubits of a quantum chip in the system's quantum chip cluster that meets the requirements for execution mapping.

[0018] This application also proposes a method for executing quantum computing tasks in a quantum computer, a quantum computer, a readable storage medium, and an electronic device, which belong to the same inventive concept as the quantum computer operating system and therefore have the same beneficial effects, and will not be described in detail here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 Based on the quantum chip model diagram in related technologies;

[0021] Figure 2 This is a reference figure illustrating a quantum circuit diagram according to an embodiment of this application;

[0022] Figure 3 This is a block diagram of a quantum computer operating system according to an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the topology of a quantum chip according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the feeder allocation of the quantum chip according to an embodiment of this application;

[0025] Figure 6 This is a block diagram of another quantum computer operating system structure according to an embodiment of this application;

[0026] Figure 7 This is a schematic diagram illustrating the workflow of a method for executing a quantum computing task in a quantum computer according to an embodiment of this application.

[0027] Figure 8 This is a schematic diagram illustrating the workflow of another method for executing quantum computing tasks in a quantum computer according to an embodiment of this application. Detailed Implementation

[0028] The specific embodiments of this application will be described in more detail below with reference to the schematic diagrams. The advantages and features of this application will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0030] This application provides a quantum computer operating system. The quantum computer will be described first below.

[0031] As those skilled in the art will understand, a true quantum computer has a hybrid structure, comprising two main parts: a classical computer responsible for performing classical computations and control, and a quantum device responsible for running quantum computing tasks to achieve quantum computing. A quantum computing task (or quantum program) is a sequence of instructions written in a quantum language such as QRunes that can run on a quantum computer, supporting quantum logic gate operations and ultimately realizing quantum computing. Specifically, a quantum computing task is a sequence of instructions that operates on quantum logic gates according to a specific timing order.

[0032] Quantum circuits, also known as quantum logic circuits, serve as a representation of quantum computing tasks. They are the most commonly used general-purpose quantum computing model, representing a circuit that operates on qubits under an abstract concept. Their components include qubits, circuitry (timelines), and various quantum logic gates. Finally, quantum measurement operations are often used to retrieve the results. See also... Figure 2 , Figure 2 The following is a quantum circuit diagram illustration provided for an embodiment of this application, wherein q[0], q[1], q[2], and q[3] refer to qubits from 0 to 3, and are usually also denoted as q0, q1, q2, and q3.

[0033] Unlike traditional circuits that use metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be seen as being connected by time. That is, the state of a quantum bit evolves naturally over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated on.

[0034] A quantum computing task corresponds to a single quantum circuit. The quantum computing task described in this application refers to this single quantum circuit, where the total number of qubits in the single quantum circuit is the same as the total number of qubits in the quantum computing task. This can be understood as follows: a quantum computing task can consist of a quantum circuit, measurement operations on the qubits within the quantum circuit, registers for storing measurement results, and control flow nodes (jump instructions). A single quantum circuit can contain tens, hundreds, or even tens of millions of quantum logic gate operations. The execution process of a quantum computing task is the process of executing all the quantum logic gates in a certain timing order. It should be noted that the timing order refers to the chronological sequence in which individual quantum logic gates are executed.

[0035] It's important to note that in classical computing, the most basic unit is the bit, and the most fundamental control mode is the logic gate. Circuit control can be achieved through combinations of logic gates. Similarly, the way to process qubits is through quantum logic gates. Quantum logic gates enable the evolution of quantum states and are the foundation of quantum circuits. Quantum logic gates include single-qubit quantum logic gates (or simply "single gate"), such as the Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, etc.; two-qubit quantum logic gates (or simply "dual gate"), such as the CNOT gate, CR gate, SWAP gate, iSWAP gate, etc.; and multi-qubit quantum logic gates (or simply "multi-gate"), such as the Toffoli gate, etc. Quantum logic gates are generally represented using unitary matrices, which are not only matrix forms but also operations and transformations. The general quantum logic gate's effect on a quantum state is calculated by left-multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.

[0036] For example, the vector corresponding to the right vector of the quantum state |0> is The vector corresponding to the right vector of the quantum state |1> is

[0037]

[0038] A quantum state is the logical state of a qubit. In quantum computing tasks, the quantum states of a group of qubits in a quantum circuit are represented in binary. For example, a group of qubits q0, q1, and q2, representing the 0th, 1st, and 2nd qubits, are represented in binary from most significant bit to least significant bit as q2q1q0. This group of qubits corresponds to a total of 2^(1 / 2) qubits, or 8 eigenstates (determined states): |000>, |001>, |010>, |011>, |100>, |101>, |110>, and |111>. Each bit in a quantum state corresponds to a qubit. For example, in the |001> state, 001 corresponds to q2q1q0 from most significant bit to least significant bit. |> represents the Dirac notation. For a quantum circuit containing N qubits q0, q1, ..., q... n , ..., q N-1 In quantum circuits, the binary representation of quantum states is ordered as q. N-1 q N-2 …、q1q0.

[0039] Taking a single qubit as an example, the logical state ψ of a single qubit may be in a superposition of the states |0>, |1>, and |0> and |1> (an uncertain state), specifically expressed as ψ = a|0> + b|1>, where a and b are complex numbers representing the amplitude (probability amplitude) of the quantum state, and the square of the magnitude of the amplitude represents the probability. 2 b 2 Let |a| represent the probabilities that the logical state is |0> and |1>, respectively. 2 +|b| 2 =1. In short, a quantum state is a superposition of eigenstates. When the probability of other states is 0, it is in a uniquely determined eigenstate.

[0040] With the continuous development of quantum computing technology, the number of quantum computing tasks that need to be processed will increase dramatically. However, due to the limitations of the development of quantum device hardware, the physical qubit resources on quantum chips are limited. In order to ensure that all quantum computing tasks can run smoothly, it is urgent to make reasonable arrangements for the limited quantum chips and the physical qubit resources on them.

[0041] See Figure 3 , Figure 3 A quantum computer operating system provided in this application includes a quantum computing task allocation service module 11, a quantum chip resource configuration service module 14, and a quantum computing task mapping service module 15.

[0042] The quantum computing task allocation service module 11 is configured to determine quantum computing tasks to be processed from currently unprocessed quantum computing tasks.

[0043] It should be noted that with the continuous development of quantum computing technology, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc. The quantum computing tasks submitted by users to the quantum cloud platform are processed through a quantum computer operating system. With the development of quantum computing technology, the backend of the quantum cloud platform has a multi-quantum chip cluster containing N quantum chips Ci, i∈{1,N}, each containing |Ci| qubits, and the number of qubits on each chip can support the execution of multiple quantum computing tasks.

[0044] Furthermore, as users' interest in quantum computing grows, more and more quantum applications will be submitted to quantum cloud platforms. However, because the qubits of the NISQ (Noisy Intermediate-Scale Quantum) devices currently used in quantum chip clusters have finite coherence times and error-prone quantum logic gates, a quantum computing task queue will emerge as more quantum applications are submitted by users during the use of quantum cloud platforms.

[0045] It should be noted that in practical applications, the quantum applications submitted by users to the quantum cloud platform include multiple quantum circuits. Each quantum circuit can be regarded as an independent entity when sending data, and one quantum circuit corresponds to one quantum computing task. Thus, the quantum computing task queue stores the quantum computing tasks that have not yet been processed.

[0046] A quantum computing task requires mapping to be performed on a quantum chip with a sufficient number of qubits. Generally, the number of qubits required by a quantum chip cluster exceeds its processing power. Therefore, how to schedule quantum computing tasks to ensure full utilization of the quantum chip cluster is a key research area. This application employs a unique quantum computing task scheduling priority determination method to ensure this effect. Specifically:

[0047] The priority values ​​for all the currently unprocessed quantum computing tasks can be calculated based on the following ranking index formula:

[0048]

[0049] Where R is the priority value, W is the queuing time in the quantum computing task queue after the quantum computing task is submitted, and S is the size of the quantum computing task, which can be expressed as S = n*d, where n is the number of qubits in the quantum computing task, and d is the depth of the quantum computing task. The depth represents the depth of the quantum circuit corresponding to the quantum computing task, which is also the length of the quantum circuit. A layer is the unit of quantum circuit depth. A layer refers to a time sequence. A layer of quantum logic gates consists of quantum logic gates located in one time sequence that can be executed simultaneously. Quantum logic gates in the same layer are quantum logic gates in the same time sequence that can be executed simultaneously.

[0050] Furthermore, the priority ranking formula reveals the following rule: the larger R is, the higher the priority of the corresponding quantum computing task. Therefore, W ensures that the quantum computing tasks are assigned on a first-come, first-served basis; and when queuing times are similar, the quantum computing task with a smaller S has a higher priority, thus maximizing quantum resource utilization. For quantum computing tasks with similar S values, the quantum computing task with a smaller number of qubits has a higher priority.

[0051] Therefore, in the quantum computing task queue, the quantum computing task with the highest R value is the quantum computing task with the highest priority.

[0052] The quantum chip resource allocation service module 14 is configured to obtain a compliant quantum bit topology from the idle qubits of the quantum chip based on a community discovery algorithm and a greedy algorithm, wherein the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks.

[0053] It should be noted that the number of high-quality qubits and links on a specific quantum chip is limited, and some qubits have more interaction with their surroundings. If a single-program mapping method is used in the quantum chip resource configuration service module 14 to map each quantum computing task to a quantum chip, the mapping method will tend to select the highest-quality quantum chips and physical qubits. This will lead to insufficient utilization of quantum resources in the system, thereby prolonging the queuing time of quantum computing tasks in the quantum computing task queue. In fact, provided that the fidelity of the quantum computing task is greater than a certain threshold, it is possible to choose to execute the quantum computing task on physical qubits or quantum chips that are not of the highest quality. Therefore, it is necessary to find an optimal balance between improving the utilization rate of physical qubits on quantum chips, reducing program waiting time, and ensuring sufficient fidelity of quantum computing tasks.

[0054] In the implementation of quantum computing tasks, developers primarily focus on the task's execution. This often results in quantum circuits containing quantum logic gates that are not supported by quantum chips. Specifically, in a quantum circuit, any two logical qubits can execute a two-qubit quantum logic gate. However, in actual quantum chips, only adjacent physical qubits are fully connected, thus coupling is only permitted between adjacent qubits. Therefore, in practical operation, it is necessary to convert quantum logic gates that are not supported by the quantum chip into those that are, thereby processing the quantum circuits corresponding to the quantum computing task to obtain executable quantum circuits. Executable quantum circuits are composed of quantum logic gates that can be directly executed on a quantum chip.

[0055] Furthermore, any qubit on a quantum chip has two opposing states: one is that it is currently being used to perform quantum computing tasks or has been partitioned and mapped; the other is that it is idle and available. The topology of a quantum chip reflects the spatial characteristics of its qubits, including the number and location of the qubits, as well as the connections between them, which determines the chip's availability.

[0056] See Figure 4 , Figure 4 This is a schematic diagram of the topology of a quantum chip according to an embodiment of this application. Figure 4Each white and black dot represents a qubit. White dots represent qubits not currently used by quantum computing tasks, while black dots represent qubits being used by tasks. The position of each dot indicates the location of the qubit. Lines connecting two dots represent connections between qubits, forming links between them. A two-qubit quantum logic gate can be executed between two connected qubits; however, links with high error rates for two-qubit quantum logic gates may exist, such as... Figure 4 The link between two qubits is represented by both solid and dashed lines. If a quantum computing task requiring 6 qubits is to be mapped to a partitioned region with tightly and reliably interconnected areas within this quantum chip, then... Figure 4 The area enclosed by the dashed box is a suitable choice.

[0057] The qubit topology described in this application embodiment is a mappable partitioned region on the quantum chip for the quantum computing task to be processed, such as... Figure 4 The area enclosed by the dashed box.

[0058] The quantum computing task mapping service module 15 is used to map the quantum computing task to be processed to the qubit topology to execute the quantum computing task.

[0059] It should be noted that mapping the quantum computing task to be processed onto the qubit topology involves establishing a mapping between the logical qubits of the quantum computing task and the physical qubits of the quantum chip, and adaptively converting the quantum logic gates before and after the mapping. This process generates an executable quantum circuit by processing the quantum circuit corresponding to the quantum computing task. The executable quantum circuit then performs the execution of the quantum computing task.

[0060] Furthermore, the quantum chip resource allocation service module 14 includes:

[0061] The first qubit acquisition unit is configured to acquire a first qubit that meets a preset requirement, wherein the read fidelity of the first qubit is within a preset range.

[0062] It should be noted that the readout fidelity of the qubit is the same as its readout accuracy. The quantum state of the evolved qubit can only be known after measurement and readout operations. The readout accuracy of the qubit is 1 minus the measurement error of the qubit. The readout fidelity of a qubit in a quantum chip can be obtained during the early testing phase of the quantum chip. The readout fidelity of the first qubit is within a preset range, which ensures good quality of the first qubit. The preset range can be set according to the accuracy requirements of the quantum computing task to be processed. For quantum computing tasks with high accuracy requirements, qubits with higher readout fidelity are selected, and the preset range needs to limit the readout fidelity to a higher range. For quantum computing tasks with low accuracy requirements, qubits with lower readout fidelity can be selected, and the preset range can limit the readout fidelity to a lower lower limit.

[0063] A qubit topology acquisition unit is configured to acquire a qubit topology that meets the requirements based on the first qubit, the community detection algorithm, and the greedy algorithm.

[0064] It should be noted that the reward function of the qubit is obtained by using the community detection algorithm and the greedy algorithm, and other idle qubits with the required reward function value are merged with the first qubit to form the qubit topology.

[0065] Furthermore, the quantum bit topology acquisition unit includes:

[0066] The parameter acquisition subunit is configured to acquire the readout fidelity of qubits near the first qubit, the reliability parameters for performing a two-bit quantum logic gate operation between any two qubits with a direct connection relationship in the vicinity of the first qubit, and the number of feed lines, wherein the feed lines are coupled to several qubits and used to measure the quantum state information of the qubits.

[0067] The topology is divided into sub-units, which are configured to divide qubits whose reward function values ​​meet the requirements into the qubit topology. The reward function is obtained by the community detection algorithm and the greedy algorithm. The value of the reward function is determined by the read fidelity of the qubits near the first qubit, the reliability parameter of performing a two-bit quantum logic gate operation between any two qubits with a direct connection relationship in the vicinity of the first qubit, and the number of feeders.

[0068] It should be noted that the qubits on the quantum chip required to execute a single quantum computing task should be tightly allocated. The qubits near the first qubit refer to idle qubits that have a direct or indirect connection to the first qubit. Specifically, the reliability parameter for executing a two-qubit quantum logic gate operation between any two directly connected qubits refers to the reliability of the two-qubit quantum logic gate itself, i.e., the reliability of the link between the two directly connected qubits. The reliability of the two-qubit quantum logic gate is calculated as 1 minus the operation error rate of the two qubits implementing the two-qubit quantum logic gate. The operation error rate of the qubits is a known parameter, and similar to read fidelity, the reliability of the two-qubit quantum logic gate is obtained in advance during the early testing phase of the quantum chip. Furthermore, since the probability of error in a single-qubit quantum logic gate is very low in practical applications, the reliability of a single-qubit quantum logic gate is generally set to 1. When calculating the value of the reward function, only the reliability of the two-qubit quantum logic gate is considered.

[0069] See Figure 5 , Figure 5 This is a schematic diagram of the feed line allocation for a quantum chip in an embodiment of this application. All qubits within the same dashed rectangle are coupled to the same feed line. Since qubit measurement requires several sequential steps, measurement of a qubit cannot begin while another qubit coupled to the same feed line is being measured. However, any combination of qubits coupled to the same feed line can be measured simultaneously at a given time. Therefore, if two quantum computing tasks share the same feed line and they have different depths, their measurements must be synchronized or not overlap in time. This results in a delay in the start of the shorter quantum computing task when measurements overlap. In practical applications, allowing a quantum computing task to fill a feed line as much as possible reduces the possibility of too many quantum computing tasks sharing the same feed line, effectively avoiding the problem of low execution efficiency in quantum computing tasks.

[0070] The reward function is obtained through the community detection algorithm and the greedy algorithm. Since the value of the reward function is determined by the read fidelity of the qubits near the first qubit, the reliability parameter for performing a two-bit quantum logic gate operation between any two directly connected qubits near the first qubit, and the number of feed lines, the qubit topology can be defined as a set of qubits whose read fidelity, reliability parameter, and number of feed lines are all within the preset range. Those skilled in the art will understand that whether the value of the reward function meets the requirements can be determined based on the quality requirements of the qubit topology, and no limitation is imposed here.

[0071] Furthermore, the quantum chip resource allocation service module 14 also includes:

[0072] A quantity determination unit is configured to determine whether the number of qubits in the qubit topology is greater than or equal to the number of qubits required for the quantum computing task to be processed.

[0073] The processing unit is configured to, when the determination result is yes, output a first instruction to the quantum computing task mapping service module so that the current quantum bit topology is used to execute the quantum computing task to be processed; and when the determination result is no, output a second instruction to the topology partitioning subunit so that the topology partitioning subunit continues to partition other qualified quantum bits into the quantum bit topology.

[0074] It should be noted that when mapping the quantum computing task to be processed onto the qubit topology, it is essential to ensure that the number of qubits in the qubit topology is not less than the number of qubits in the quantum computing task. Therefore, when partitioning the qubit topology among the idle qubits of the quantum chip, it is necessary to use the number of qubits in the quantum computing task as a benchmark and continuously determine whether the number of qubits merged into the qubit topology has reached the logical number of qubits in the quantum computing task. Furthermore, the other eligible qubits refer to those whose reward function meets the requirements.

[0075] Furthermore, the reward function is:

[0076]

[0077] Where F is the value of the reward function, Q mQ represents the compactness of the topology of the qubit after adding another qubit. o The density of the qubit topology before adding another qubit is given. E represents the average fidelity of performing a two-bit quantum logic gate operation between any two directly connected qubits in the qubit topology after adding another qubit. This fidelity represents the reliability of the link between the two directly connected qubits. V represents the average read fidelity of all qubits in the qubit topology after adding another qubit. ω and β are pre-configured weighting coefficients, which are empirical constants. L represents the total number of feeders in the qubit topology after adding another qubit. Those skilled in the art will understand that for a specific quantum chip cluster, appropriate ω and β can be used to adjust the physical topology of the qubit topology, the error rate of the two-bit quantum logic gate operation, and the weights of the feeder structure in a quantum chip, thereby maximizing the value of the reward function. For example, if the third term in the calculation formula of the reward function is large, it indicates that the resulting community structure will cover some feeders, and these feeders need to be filled as much as possible.

[0078] It should be noted that the reward function is obtained using the community detection algorithm and the greedy algorithm. The community detection algorithm is used to discover community structures within the network structure; it is a clustering algorithm. These partitioned community structures are subgraphs, including vertices and edges. Vertices within the same community are tightly connected, while connections between communities are relatively sparse. Modularity is chosen as the metric for evaluating the quality of a community structure partition. Modularity is the degree of the edges within a community structure minus the total degree of the vertices within that community structure. Its calculation formula is:

[0079]

[0080] Where Q is the modularity of a community structure C. The higher the modularity Q, the more appropriate the partitioning of the community structure C is. m is the total number of edges in the community structure C. Ic is the number of all internal edges in the community structure C. Dc is the sum of the degrees of all vertices in the community structure C.

[0081] Quantum computing tasks create entanglement using two-qubit quantum logic gates, and these gates can only execute between two physically coupled qubits on a quantum chip. Therefore, the qubits on the quantum chip required to execute a single quantum computing task should be tightly allocated, and crosstalk and other interference should be avoided between different quantum computing tasks. The qubit topology is essentially a community structure of idle physical qubits on the quantum chip; therefore, the tightness Q of the qubit topology is crucial. m and Q o The modularity Q can be obtained using the community detection algorithm's modularity Q calculation formula, where each qubit in the lattice structure of the quantum chip is equivalent to a vertex of the community structure, and the link between two qubits is equivalent to an edge of the community structure.

[0082] The greedy algorithm treats the first qubit of the quantum chip as a community structure, continuously merging nearby idle qubits with this community structure to form a new community structure, thereby maximizing the reward function, until a final community structure is obtained that contains the number of qubits required for the quantum computing task. This final community structure is the qubit topology.

[0083] Furthermore, since the coherence time of each qubit in a quantum chip is finite and different, qubits with longer coherence times have better reliability. If a quantum computing task contains qubits with short coherence times in its qubit topology, the fidelity of the task will be significantly affected. The decoherence error of a qubit increases exponentially with respect to the length of the quantum computing task. Therefore, quantum computing tasks should be executed on qubits with coherence times longer than their own execution time. Before acquiring the qubit topology, qubits with coherence times too short relative to the execution time of the quantum computing task need to be excluded from the allocation of usable qubits.

[0084] Therefore, please see Figure 6 Another quantum computer operating system according to an embodiment of this application, which, based on the structure of the previous embodiment, further includes:

[0085] The coherence time acquisition and judgment module 12 is configured to acquire the coherence time of the idle qubits in the quantum chip and determine whether the coherence time of each idle qubit is greater than a first threshold, wherein the first threshold is determined based on the execution time of the quantum computing task to be processed.

[0086] When the quantum chip resource discrimination module 13 determines the result to be negative, it sets the corresponding quantum bit as an unusable quantum bit. The quantum chip resource configuration service module 14 will not allocate the unusable quantum bit to the quantum bit topology.

[0087] The quantum computer operating system is a tool that connects the user terminal and the quantum chip, a core component of the quantum computer. The operating system receives quantum computing tasks from the user terminal and maps these tasks to specific qubit topologies within the quantum chip to execute them. However, existing NISQ devices used in quantum chip clusters cannot achieve complete connectivity between any two qubits, while quantum computing tasks typically require executing a two-qubit quantum logic gate between any two qubits. Therefore, finding an optimized mapping region (i.e., the qubit topology) for the quantum computing task within a suitable quantum chip cluster is crucial. The quantum chip resource configuration service module 14 in the quantum computer operating system provided in this application can find a mapping region with tightly connected qubits and a low connection error rate for each quantum computing task. It utilizes a scheme based on the community detection algorithm and the greedy algorithm, which comprehensively considers meeting the fidelity requirements of program execution, avoiding crosstalk, and rationally using the feeder, to find the optimal qubit topology as the mapping region for the quantum computing task. This provides a reliable solution for the efficient and rapid execution of quantum computing tasks.

[0088] Based on the same inventive concept, this application proposes a method for executing quantum computing tasks in a quantum computer. Please refer to [link to relevant documentation]. Figure 7 The method includes the following steps:

[0089] Step S22: Identify the quantum computing tasks to be processed from the currently unprocessed quantum computing tasks;

[0090] Step S24: Obtain a qubit topology that meets the requirements from the idle qubits of the quantum chip based on the community detection algorithm and the greedy algorithm, wherein the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks;

[0091] Step S26: Map the quantum computing task to be processed into the qubit topology to execute the quantum computing task to be processed.

[0092] Please refer to the description of the above embodiments for details, which will not be repeated here.

[0093] It should be noted that step S24, which describes obtaining the required qubit topology from the idle qubits of the quantum chip based on the community detection algorithm and the greedy algorithm, includes:

[0094] Obtain a first quantum bit that meets a preset requirement, wherein the read fidelity of the first quantum bit is within a preset range;

[0095] The topology of the qubit that meets the requirements is obtained based on the first qubit, the community detection algorithm, and the greedy algorithm.

[0096] It should be specifically noted that obtaining the required qubit topology based on the first qubit, the community detection algorithm, and the greedy algorithm specifically includes:

[0097] Obtain the read fidelity of qubits near the first qubit, the reliability parameters of performing a two-bit quantum logic gate operation between any two qubits with a direct connection relationship in the vicinity of the first qubit, and the number of feeders;

[0098] The qubits whose reward function values ​​meet the requirements are assigned to the qubit topology. The reward function is obtained through the community detection algorithm and the greedy algorithm. The value of the reward function is determined by the read fidelity of the qubits near the first qubit, the reliability parameter of performing a two-bit quantum logic gate operation between any two qubits with a direct connection relationship in the vicinity of the first qubit, and the number of feeders.

[0099] Please refer to the description of the above embodiments for details, which will not be repeated here.

[0100] The reward function is as follows:

[0101]

[0102] Where F is the value of the reward function, Q m Q represents the compactness of the topology of the qubit after adding another qubit. o E represents the compactness of the qubit topology before adding another qubit, E represents the average fidelity of performing a two-bit quantum logic gate operation between any two directly connected qubits in the qubit topology after adding another qubit, V represents the average read fidelity of all qubits in the qubit topology after adding another qubit, ω and β are pre-configured weighting coefficients, and L represents the total number of feeders in the qubit topology after adding another qubit.

[0103] It should be noted that in step S24, the process of obtaining the required qubit topology from the idle qubits of the quantum chip based on the community detection algorithm and the greedy algorithm further includes:

[0104] If the number of qubits in the qubit topology is greater than or equal to the number of qubits required for the quantum computing task to be processed, a first instruction is output to the quantum computing task mapping service module 12 to enable the current qubit topology to be used to execute the quantum computing task to be processed. Otherwise, a second instruction is output to the topology partitioning subunit to enable the topology partitioning subunit to continue partitioning other qualified qubits into the qubit topology.

[0105] Please refer to the description of the above embodiments for details, which will not be repeated here.

[0106] Furthermore, each quantum computing task needs to be completed within the coherence time of the qubit; otherwise, significant errors will occur in the execution results. Therefore, before configuring quantum chip resources for a specific quantum computing task, it is necessary to identify unavailable qubits for that task and exclude them from the required qubit topology.

[0107] Therefore, please see Figure 8 This application proposes another method for executing quantum computing tasks in a quantum computer. This execution method, in addition to the previous embodiment, further includes:

[0108] Step S23: Obtain the coherence time of the idle qubits in the quantum chip;

[0109] Determine whether the coherence time of each of the idle qubits is greater than a first threshold, wherein the first threshold is determined based on the execution time of the quantum computing task to be processed;

[0110] If not, the corresponding qubit will be set as an unavailable qubit, and the quantum chip resource configuration service module 14 will not allocate the unavailable qubit to the qubit topology.

[0111] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0112] Based on the same inventive concept, embodiments of this application also propose a quantum computer, including the quantum computer operating system described in any of the above features.

[0113] Based on the same inventive concept, embodiments of this application also propose a readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the execution method described in any of the above features.

[0114] The readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage on a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this application can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions to implement various aspects of this application.

[0115] Various aspects of this application are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program includes an article of manufacture comprising instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0116] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0117] Based on the same inventive concept, embodiments of this application also propose an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the execution method described in any of the above features.

[0118] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0119] The above are merely preferred embodiments of this application and do not constitute any limitation on this application. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in this application without departing from the scope of the technical solutions of this application shall still fall within the protection scope of this application.

Claims

1. A quantum computer operating system, characterized in that, include: A quantum computing task allocation service module is configured to dynamically determine the highest priority quantum computing task to be processed from the currently unprocessed quantum computing tasks. The quantum computing task allocation service module calculates the priority of quantum computing tasks according to the following ranking index formula: Where R is the priority value, W is the queuing time in the quantum computing task queue after the quantum computing task is submitted, and S is the size of the quantum computing task. Where n is the number of qubits in the quantum computing task, and d is the depth of the quantum circuit corresponding to the quantum computing task; the larger the priority value R, the higher the priority of the corresponding quantum computing task. A quantum chip resource allocation service module is configured to obtain a qubit topology that meets the requirements from the idle qubits of the quantum chip based on a community discovery algorithm and a greedy algorithm, wherein the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks; A quantum computing task mapping service module is configured to map the quantum computing task to be processed to the qubit topology to execute the quantum computing task to be processed; The coherence time acquisition and judgment module is configured to acquire the coherence time of the idle qubits in the quantum chip and determine whether the coherence time of each idle qubit is greater than a first threshold, wherein the first threshold is determined based on the execution time of the quantum computing task to be processed. When the quantum chip resource discrimination module determines the result to be negative, it sets the corresponding quantum bit as an unusable quantum bit. The quantum chip resource configuration service module will not allocate the unusable quantum bit to the quantum bit topology.

2. The quantum computer operating system as described in claim 1, characterized in that, The quantum chip resource allocation service module includes: The first quantum bit acquisition unit is configured to acquire a first quantum bit that meets a preset requirement, wherein the preset requirement is that the read fidelity of the first quantum bit is within a preset range; A qubit topology acquisition unit is configured to acquire a qubit topology that meets the requirements based on the first qubit, the community detection algorithm, and the greedy algorithm.

3. The quantum computer operating system as described in claim 2, characterized in that, The quantum bit topology acquisition unit includes: The parameter acquisition subunit is configured to acquire the readout fidelity of the qubits near the first qubit, the reliability parameters for performing a two-bit quantum logic gate operation between any two qubits that are directly connected to each other in the vicinity of the first qubit, and the number of feed lines, wherein the feed lines are coupled to several qubits and used to measure the quantum state information of the qubits. The topology is divided into sub-units, which are configured to divide qubits whose reward function values ​​meet the requirements into the qubit topology. The reward function is obtained by the community detection algorithm and the greedy algorithm. The value of the reward function is determined by the read fidelity of the qubits near the first qubit, the reliability parameter of performing a two-bit quantum logic gate operation between any two qubits with a direct connection relationship in the vicinity of the first qubit, and the number of feeders.

4. The quantum computer operating system as described in claim 3, characterized in that, The quantum chip resource allocation service module also includes: A quantity determination unit is configured to determine whether the number of qubits in the qubit topology is greater than or equal to the number of qubits required for the quantum computing task to be processed. The processing unit is configured to, when the determination result is yes, output a first instruction to the quantum computing task mapping service module so that the current quantum bit topology is used to execute the quantum computing task to be processed; and when the determination result is no, output a second instruction to the topology partitioning subunit so that the topology partitioning subunit continues to partition other qualified quantum bits into the quantum bit topology.

5. The quantum computer operating system as described in claim 3, characterized in that, The reward function is: Where F is the value of the reward function, Q m Q represents the compactness of the topology of the qubit after adding another qubit. o E represents the compactness of the qubit topology before adding another qubit, E represents the average fidelity of performing a two-bit quantum logic gate operation between any two directly connected qubits in the qubit topology after adding another qubit, V represents the average read fidelity of all qubits in the qubit topology after adding another qubit, ω and β are pre-configured weighting coefficients, and L represents the total number of feeders in the qubit topology after adding another qubit.

6. A method for executing a quantum computing task in a quantum computer, characterized in that, include: Dynamically determine the highest priority quantum computing task to be processed from the currently unprocessed quantum computing tasks; The priority of quantum computing tasks is calculated using the following ranking index formula: Where R is the priority value, W is the queuing time in the quantum computing task queue after the quantum computing task is submitted, and S is the size of the quantum computing task. Where n is the number of qubits in the quantum computing task, and d is the depth of the quantum circuit corresponding to the quantum computing task; the larger the priority value R, the higher the priority of the corresponding quantum computing task. Based on community discovery and greedy algorithms, a qubit topology that meets the requirements is obtained from the idle qubits of a quantum chip, wherein the idle qubits are the qubits in the quantum chip that have not been assigned quantum computing tasks; The quantum computing task to be processed is mapped to the topology of the qubit to execute the quantum computing task; The coherence time of the idle qubits in the quantum chip is obtained, and it is determined whether the coherence time of each idle qubit is greater than a first threshold, wherein the first threshold is determined based on the execution time of the quantum computing task to be processed; If the judgment result is negative, the corresponding qubit is set as an unavailable qubit, and the quantum chip resource configuration service module will not allocate the unavailable qubit to the qubit topology.

7. The method for executing a quantum computing task in a quantum computer as described in claim 6, characterized in that, The method of obtaining a suitable qubit topology from the idle qubits of a quantum chip based on community detection and greedy algorithms includes: Obtain a first quantum bit that meets a preset requirement, wherein the read fidelity of the first quantum bit is within a preset range; The topology of the qubit that meets the requirements is obtained based on the first qubit, the community detection algorithm, and the greedy algorithm.

8. The method for executing a quantum computing task in a quantum computer as described in claim 7, characterized in that, The process of obtaining the required topological structure of the qubit based on the first qubit, the community detection algorithm, and the greedy algorithm includes: Obtain the read fidelity of qubits near the first qubit, the reliability parameters of performing a two-bit quantum logic gate operation between any two qubits with a direct connection relationship in the vicinity of the first qubit, and the number of feeders; The qubits whose reward function values ​​meet the requirements are assigned to the qubit topology. The reward function is obtained through the community detection algorithm and the greedy algorithm. The value of the reward function is determined by the read fidelity of the qubits near the first qubit, the reliability parameter of performing a two-bit quantum logic gate operation between any two qubits with a direct connection relationship in the vicinity of the first qubit, and the number of feeders.

9. The method for executing a quantum computing task in a quantum computer as described in claim 8, characterized in that, The method of obtaining a suitable qubit topology from the idle qubits of a quantum chip based on community detection and greedy algorithms also includes: Determine whether the number of qubits in the qubit topology is greater than or equal to the number of qubits required for the quantum computing task to be processed; If so, the first instruction is output to the quantum computing task mapping service module so that the current qubit topology is used to execute the quantum computing task to be processed; If not, a second instruction is output to the topology partitioning subunit so that the topology partitioning subunit can continue to partition other qualified qubits into the qubit topology.

10. The method for executing a quantum computing task in a quantum computer as described in claim 8, characterized in that, The reward function is: Where F is the value of the reward function, Q m Q represents the compactness of the topology of the qubit after adding another qubit. o E represents the compactness of the qubit topology before adding another qubit, E represents the average fidelity of performing a two-bit quantum logic gate operation between any two directly connected qubits in the qubit topology after adding another qubit, V represents the average read fidelity of all qubits in the qubit topology after adding another qubit, ω and β are pre-configured weighting coefficients, and L represents the total number of feeders in the qubit topology after adding another qubit.

11. The method for executing a quantum computing task in a quantum computer as described in claim 6, characterized in that, The execution method further includes: Obtain the coherence time of the idle qubits in the quantum chip; Determine whether the coherence time of each of the idle qubits is greater than a first threshold, wherein the first threshold is determined based on the execution time of the quantum computing task to be processed; If not, the corresponding qubit will be set as an unavailable qubit, and the quantum chip resource configuration service module will not allocate the unavailable qubit to the qubit topology.

12. A quantum computer, characterized in that, Including the quantum computer operating system as described in any one of claims 1-5.

13. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it can implement the execution method according to any one of claims 6 to 11.

14. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the execution method according to any one of claims 6 to 11.

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