Bottom-source trench MOSFET with shielding electrode

Abstract

An improved reverse field-effect transistor semiconductor device and its fabrication method may include a source layer at the bottom and a drain at the top of a semiconductor substrate, and a vertical conduction channel between the source layer and the drain region, the trench being controlled by a trench gate electrode disposed in a gate trench lined with insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding the upper portion of the shielding trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding the lower portion of the shielding trench. A shielding electrode extends upward from the source layer in the shielding trench for electrically short-circuiting the source layer and the body region, wherein the shielding structure extends upward to the heavily doped drain region and is insulated from the heavily doped drain region to serve as a shielding electrode.

Description

Technical Field

[0001] Various aspects of this invention relate primarily to semiconductor power devices. More specifically, various aspects of this invention relate to reverse trench grounded field-effect transistors (FETs). Background Technology

[0002] The package size of semiconductor power devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), continues to shrink. Recent developments in FETs have led to the emergence of three-dimensional stacked power devices with voltage regulators (so-called "buck converters"). These three-dimensional stacked devices employ bottom-source laterally diffused MOSFETs (LD MOSFETs). While LD MOSFET designs allow for stacking, they have lower channel density, require expensive complementary MOSFET (CMOS)-based processes, and necessitate numerous masking steps for creation.

[0003] Therefore, it would be beneficial to develop three-dimensional stacked power devices using cheaper transistor device designs, such as trench MOSFET designs. One possible trench MOSFET design is the reverse trench grounded field-effect transistor (iT-FET). These designs have a bottom source and a top drain, making the devices easy to stack. Compared to LD MOSFETs, these iT-FETs have a higher channel density. One problem with current iT-FET designs is that they have a high gate-to-drain capacitance, resulting in high capacitance in the on-state (R0). ds-on The switching speed is relatively slow, and the drain-to-source resistance is relatively high. In addition, the current manufacturing process is complex and costly.

[0004] Therefore, in this skill, a reduced R is required. ds-on iT-FETs offer faster switching speeds and better manufacturing processes. Summary of the Invention

[0005] This invention discloses a reverse field-effect transistor (iT-FET) semiconductor device, comprising a source layer located at the bottom and a heavily doped drain region disposed on top of a semiconductor substrate; a vertical current conduction channel between the source layer and the drain region, controlled by a trench gate disposed in a gate trench lined with insulating material; a shielding trench disposed between adjacent gate trenches, the heavily doped drain region being disposed near the top of the substrate surrounding the upper portion of the shielding trench and the gate trench; a doped body region disposed in the substrate and surrounding the lower portion of the shielding trench; and a shielding electrode in the shielding trench extending upward from the source layer to electrically short-circuit the source layer and the body region, wherein the shielding electrode extends upward in the shielding trench to the heavily doped drain region and is insulated from the heavily doped drain region to serve as a shielding electrode.

[0006] The shielding structure also includes a conductive plug in a shielding trench that extends upward from the source layer, through the body region, and reaches at least a portion of the drift region.

[0007] The shielding electrode also includes a tungsten plug in a shielding trench that extends upwards from the source layer.

[0008] The shielding electrode also includes a titanium silicide plug in a shielding trench that extends upwards from the source layer.

[0009] The semiconductor substrate has a source layer heavily doped with impurities of a first conductivity type, and the semiconductor substrate also includes an epitaxial layer formed above the source layer, which is doped with impurities of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type.

[0010] The bulk region is formed in the epitaxial layer and is heavily doped with impurities of the second conductivity type.

[0011] In this process, a heavily doped drain region is formed in the epitaxial layer and is heavily doped with ions of the first conductivity type.

[0012] In this configuration, an insulating layer between the shielding electrode and the heavily doped drain region and drift region is thicker than the insulating material portion between the gate electrode and the source layer and body region.

[0013] This also includes a drift region between the bulk region and the heavily doped drain region formed in the epitaxial layer, wherein the drift region is lightly doped with impurities of the first conductivity type than the heavily doped drain region.

[0014] The drift region has an impurity concentration gradient, with the highest impurity concentration near the heavily doped drain region and the impurity concentration decreasing in the deeper epitaxial layer below the heavily doped drain region.

[0015] It also includes a conductive drain contact plug that contacts the heavily doped drain region and the drain metal phase.

[0016] This invention also discloses a method for fabricating an iT-FET semiconductor device, comprising: forming an epitaxial layer doped with a second conductivity type impurity on a substrate heavily doped with a first conductivity type impurity, wherein the first conductivity type is opposite to the second conductivity type, wherein the substrate serves as a source layer; forming a gate trench penetrating the epitaxial layer into the source layer; lining a shielding trench with an insulating material and forming a gate electrode in the gate trench; forming a drift region doped with a first conductivity type impurity and a heavily doped drain region in the epitaxial layer; forming a shielding trench in the epitaxial layer through the heavily doped drain region and the drift region; forming a body contact region at the bottom of the shielding trench by heavily doping with a second conductivity type impurity; lining the shielding trench with an insulating material; deepening the shielding trench to the source layer through the body contact region and forming a shielding structure in the shielding trench, wherein the shielding structure extends upward from the source layer, short-circuiting the source layer and the body region, wherein the shielding structure extends upward to the heavily doped drain region and is insulated from the drain region; and forming a drain above the epitaxial layer.

[0017] The shielding structure includes a shielding electrode that extends downward from the bottom of the drain region, through the shielding trench and the body region, to the source.

[0018] The preparation of the shielding electrode also includes the preparation of a conductive plug that extends upward from the source electrode through the body region and reaches at least a portion of the drain region in the shielding trench.

[0019] The conductive plug can be a tungsten plug that extends upwards from the source in the shielding trench.

[0020] The conductive plug is lined with titanium silicide, which extends upward from the source electrode in the shielding trench.

[0021] The formation of the drift region also includes the formation of an impurity concentration gradient in the drift region, wherein the impurity concentration is highest near the drain region and the ion concentration decreases in the epitaxial layer deeper below the heavily doped drain region.

[0022] h) further includes lining the sidewalls of the shielding trench with a shielding insulation that is thicker than the insulating material in the gate trench.

[0023] The process of fabricating a drain above the epitaxial layer also includes fabricating a conductive drain contact plug that contacts the heavily doped drain region and the drain metal above the drain contact plug. Attached Figure Description

[0024] Other features and advantages of the invention will become apparent after reading the following detailed description and referring to the following figures, wherein:

[0025] Figure 1 The image shows a side cross-sectional view of an improved iT-FET device according to various aspects of the present invention, the device having a combination of source short circuit and shield electrode.

[0026] Figure 2A This is a cross-sectional view of the source layer and epitaxial layer of a semiconductor substrate during the fabrication of an improved iT-FET, according to various aspects of the present invention.

[0027] Figure 2B This is a side cross-sectional view showing the fabrication of a gate trench in an improved iT-FET device according to various aspects of the present invention.

[0028] Figure 2C This is a side cross-sectional view showing the fabrication of a gate insulator in an improved iT-FET device according to various aspects of the present invention.

[0029] Figure 2D This is a side cross-sectional view showing the fabrication of a gate electrode in an improved iT-FET device according to various aspects of the present invention.

[0030] Figure 2E This is a side cross-sectional view showing the fabrication of a gate electrode in an improved iT-FET device according to various aspects of the present invention.

[0031] Figure 2F This is a side cross-sectional view showing the fabrication of a gate electrode and a gate strip in an improved iT-FET device according to various aspects of the present invention.

[0032] Figure 2G This is a side cross-sectional view showing the fabrication of a gate electrode and a gate strip in an improved iT-FET device according to various aspects of the present invention.

[0033] Figure 2H This is a side cross-sectional view showing the fabrication of a gate electrode and a gate strip in an improved iT-FET device according to various aspects of the present invention.

[0034] Figure 2I This is a side cross-sectional view showing the fabrication of the drain region and drift region in an improved iT-FET device according to various aspects of the present invention.

[0035] Figure 2J This is a side cross-sectional view showing the planarization process prior to the fabrication of the shielding structure in an improved iT-FET device, according to various aspects of the present invention.

[0036] Figure 2K This is a side cross-sectional view showing the fabrication of a source-body short-circuit and shielding structure in an improved iT-FET device according to various aspects of the present invention.

[0037] Figure 2L This is a side cross-sectional view showing the fabrication of a source-body short-circuit and shielding structure in an improved iT-FET device according to various aspects of the present invention.

[0038] Figure 2M This is a side cross-sectional view showing the fabrication of a source-body short-circuit and shielding structure in an improved iT-FET device according to various aspects of the present invention.

[0039] Figure 2N This is a side cross-sectional view showing the fabrication of a source-body short-circuit and shielding structure in an improved iT-FET device according to various aspects of the present invention.

[0040] Figure 2O This is a side cross-sectional view showing the fabrication of a source-body short-circuit and shielding structure in an improved iT-FET device according to various aspects of the present invention.

[0041] Figure 2P This is a side cross-sectional view showing the fabrication of a source-body short-circuit and shielding structure in an improved iT-FET device according to various aspects of the present invention.

[0042] Figure 2Q This is a side cross-sectional view of a modified iT-FET device, taken during the planarization process prior to the fabrication of the connector, according to various aspects of the present invention.

[0043] Figure 2R This is a side cross-sectional view showing the fabrication of a drain contact opening and a gate contact opening in an improved iT-FET device according to various aspects of the present invention.

[0044] Figure 2S This is a side cross-sectional view showing the fabrication of a drain contact plug and a gate contact plug in an improved iT-FET device according to various aspects of the present invention.

[0045] Figure 2T This is a side cross-sectional view showing the fabrication of drain metal and gate metal strips in an improved iT-FET device according to various aspects of the present invention. Detailed Implementation

[0046] Although the following detailed description contains many specific details for illustrative purposes, those skilled in the art will understand that many variations and modifications to these details are within the scope of the invention. Therefore, the exemplary embodiments of the invention described below do not impose any general limitation or restriction on the claimed invention.

[0047] In the following detailed description, reference is made to the accompanying drawings, which form part of this invention, illustrating by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “leading,” “tail,” etc., are used with reference to the orientation of the described figures. Since components of embodiments of the invention can be positioned in multiple different orientations, directional terms are used for illustration and not for limitation in any way. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description should not be considered a limiting description, and the scope of the invention is defined by the appended claims.

[0048] For clarity, not all conventional features of the implementations described herein are represented and described. Those skilled in the art will understand that in any such implementation, numerous implementation-specific decisions must be made to achieve specific goals of the developer, such as complying with application and business-related constraints, and these specific goals will vary from implementation to implementation and from developer to developer. Furthermore, it should be understood that such development work can be complex and time-consuming, but will be a routine engineering task for those skilled in the art who benefit from this invention.

[0049] According to various aspects of the present invention, components, process steps, and / or data structures can be implemented using various types of operating systems; computing platforms; user interfaces / displays, including personal or laptop computers, video game consoles, PDAs, and other handheld devices such as mobile phones, tablets, portable gaming devices; and / or general-purpose machines. Furthermore, those skilled in the art will recognize that less general-purpose devices, such as hardwired devices, field-programmable gate arrays (FPGs), application-specific integrated circuits (ASICs), etc., can also be used without departing from the scope and spirit of the inventive concepts disclosed herein.

[0050] This invention relates to silicon doped with ions of a first conductivity type or a second conductivity type. The ions of the first conductivity type can be the opposite of the second conductivity type. For example, the ions of the first conductivity type can be n-type, which generate charge carriers when doped into silicon. Ions of the first conductivity type include phosphorus, antimony, bismuth, lithium, and arsenic. The ions of the second conductivity type can be p-type, which create holes for charge carriers when doped into silicon, and are thus referred to as the opposite of n-type. p-type ions include boron, aluminum, gallium, and indium. Although the above description refers to n-type as the first conductivity type and p-type as the second conductivity type, the invention is not limited thereto; p-type can be the first conductivity type, and n-type can be the second conductivity type.

[0051] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention and illustrate specific embodiments in which the invention may be practiced. For convenience, the use of + or – after specifying conductivity or net impurity carrier type (p or n) generally refers to the relative concentration of the specified type of net impurity carriers within the semiconductor material. Generally, n+ materials have a higher concentration of N-type net dopant (e.g., electrons) than n materials, and n materials have a higher carrier concentration than n- materials. Similarly, p+ materials have a higher concentration of p-type net dopant (e.g., holes) than p materials, and p materials have a higher concentration than p- materials. It should be noted that what is relevant is the net carrier concentration, not necessarily the dopant. For example, a material can be heavily doped with n-type dopant, but if the material is also sufficiently dedoped with p-type dopant, the material will still have a relatively low net carrier concentration. As used herein, less than about 10 16 / cm 3 The doping concentration of 10 can be considered "lightly doped," while a concentration greater than approximately 10 is considered "lightly doped." 17 / cm 3 The dopant concentration can be considered "heavily doped".

[0052] A key characteristic of current iT-FET designs is the lack of an effective shielding electrode, which could reduce R in the circuit. ds-on The shielding electrode reduces the coupling between the drain and the gate, thereby reducing the Miller effect driving the gate (Q). gd This improves switching speed through a "shielding effect." A typical iT-FET structure includes a short circuit from the source layer of the substrate to the body region. In prior art embodiments, this short-circuit region is included in a gate trench or in a separate trench formed at a spacing larger than the gate spacing in the device. A detail of this invention is that the source-body junction and shielding electrode can be combined to improve Q. gd and switching speed and R ds-on .

[0053] An improved inverting field-effect transistor (iT-FET) semiconductor device may include a source layer at the bottom and a drain region disposed on top of a semiconductor substrate, and a vertical conduction channel between the source layer and the drain region controlled by a trench gate disposed in a gate trench lined with insulating material. The drain region is disposed near the top of the substrate surrounding the upper portion of the shielding trench and the gate trench. A doped body region is disposed in the substrate and surrounds the lower portion of the shielding trench. A shielding structure extends upward from the source layer to electrically short-circuit the source layer and the body region, wherein the shielding structure extends upward in the shielding trench to the drain region and is insulated from the drain region to act as a shielding electrode. The shielding structure may extend from the bottom of the drain region through the shielding trench and the body region to the source layer. The shielding structure may also include a conductive plug extending upward from the source layer through the body region to at least a portion of the drain region in the shielding trench. The shielding structure may also include a titanium silicide plug extending upward from the source layer in the shielding trench. Alternatively, the shielding structure may also include a cobalt silicide plug extending upward from the source in the shielding trench.

[0054] The source layer of a semiconductor substrate can be heavily doped with impurities of a first conductivity type. The semiconductor substrate may also include an epitaxial layer formed on top of the source layer, doped with impurities of a second conductivity type. A doped bulk region can also be formed in the epitaxial layer by implanting impurities of the second conductivity type. The drain region consists of a heavily doped region and a lightly doped region of the first conductivity type. The lightly doped region is also called a drift region. The heavily doped region can be formed in the epitaxial layer implanted with impurities of the first conductivity type. A drift region can be created between the bulk region and the heavily doped region in the epitaxial layer. The drift region can be doped with impurities of the first conductivity type less than the heavily doped region. The drift region can have an impurity concentration gradient, where the impurity concentration is highest near the heavily doped drain region and decreases in the deeper epitaxial layer below the heavily doped drain region. A conductive drain contact can contact the heavily doped drain region and the drain.

[0055] Devices

[0056] Figure 1This diagram shows a side cross-sectional view of an improved iT-FET device having a combined source-body short circuit and a shielding electrode, according to various aspects of the present invention. The device includes a bottom source layer 101 formed in a semiconductor substrate. The source layer may be heavily doped with impurities of a first conductivity type. An epitaxial layer 102 may be disposed on top of the source layer 101. The epitaxial layer 102 may be lightly doped with impurities of a second conductivity type, which also form the body of the device. A heavily doped drain region 104 may be formed in the upper region of the epitaxial layer 102 in the semiconductor substrate. The heavily doped drain region 104 may be heavily doped with impurities of the first conductivity type. A drift region 105 may be formed between the heavily doped drain region 104 and the epitaxial layer / body region 102. The drift region may be doped with impurities of the first conductivity type at a lower concentration relative to the heavily doped drain region 104. In some embodiments, the drift region 105 may be doped into the epitaxial layer with the highest dopant concentration located near the heavily doped drain region 104 in a gradient manner with decreasing concentration. The ion concentration decreases near the epitaxial layer 102. A drain contact plug 113 may be disposed on top of the heavily doped drain region 104. The drain contact plug 113 may include a silicide and a diffusion barrier layer 114 to improve contact resistance with the drain region 104 and device reliability. For example, but not limited to, the diffusion barrier layer 114 may be a metallic silicide of titanium or cobalt and titanium nitride, and the drain contact plug 113 may be a metal such as tungsten. A drain metal (also referred to herein as the "drain") 112 is disposed on top of the drain contact plug 113 and contacts and connects to the drain contact plug 113 for use as a drain terminal. The drain metal may be a metal such as copper or aluminum.

[0057] A vertical channel can be formed in the body region 102 between the drain 112 and the source layer 101, controlled by the gate electrode 107. The gate electrode 107 is disposed on an insulating layer 106 in a gate trench 120. The gate trench 120 is lined with an insulating material 106, and the insulating material 106 insulates the gate electrode 107 from the semiconductor substrate in the active region of the device. A gate strip electrode 108 in a gate strip region of the semiconductor substrate in the device termination region can control the gate electrode 107. The gate strip 108 can be disposed on the insulating material 106 lining the gate strip trench 121. The gate strip 108 can be electrically coupled to the gate electrode 107. As shown, the gate strip 108 can be electrically coupled to the gate metal 115 through a gate strip contact plug 116. The gate strip contact plug 116 may have a complementary material coating 117 similar to that of the drain contact plug. The gate strip contact plug 116 may include a metal silicide with a complementary diffusion barrier 114 to improve contact resistance with the gate strip 108 and device reliability. For example, but not limited to, the gate strip contact plug 116 may be a metal such as tungsten, and the diffusion barrier 114 may be a metal silicide of titanium or cobalt and titanium nitride. The gate strip 108 and the gate electrode 107 may be made of a conductive material, such as metal or polysilicon. The insulating material 106 may be a silicon oxide layer.

[0058] A shielding electrode 110 may be disposed in a shielding trench 122 between adjacent gate trenches 120 in the active region of the device. As shown, the shielding trench 122 may be disposed between adjacent drain contact plugs 113, and the drain plugs 113 may be disposed in the space between the gate trench 120 and the shielding trench 122. The shielding electrode 110 also acts as a conductive short circuit between the source layer and the body region. Therefore, the shielding electrode 110 is in conductive contact with the source layer 101 and the body region 102. The body region 102 surrounds the lower portion of the shielding trench 122. The drain region 104 surrounds the upper portion of the shielding trench 122, and the drift region 105 surrounds the shielding trench 122 below the heavily doped drain region 104. The bottom of the shielding trench 122 is located in the source layer 101. The shielding electrode 110 extends upward from the source layer 101 through the body region 102. A shielding insulator 109 isolates the shielding electrode 110 from the heavily doped drain region 104 and drift region 105, and aligns the sidewalls of the shielding trench 122 above the body region 102. A body contact region 103, having the same conductivity type as the body region 102 but with a higher doping concentration, may be formed near the bottom of the shielding trench to provide an ohmic contact between the body region 102 and the shielding electrode 110. The shielding electrode 110 may extend upward through the drift region 105 and into the heavily doped drain region 104. The insulating layer 109 between the shielding electrode 110 and the heavily doped drain region 104 and drift region 105 may be thicker than the insulating layer 106 between the gate 107 and the source 120, and between the body region 102 and the drift region 105.

[0059] During operation, when the device is in the off state, the shielding electrode 110 can induce a shielding effect, thereby allowing for a more heavily doped drift region, resulting in a lower R0. ds-on Similar to the gate and drain terminals, the shielding electrode 110 may include a complementary material coating 111, such as, but not limited to, tungsten. The shielding electrode 110 may be a metal, such as a titanium or cobalt silicide or a suitable alloy thereof. The shielding insulator 109 may be any suitable insulating material, such as silicon dioxide. According to various aspects of the invention, the improved trench gate design of the iT-FET allows for greater device density, as well as improved switching time characteristics and reduced Ro. ds-on The spacing of device cells 130 can be from 0.7 to 1.2 micrometers. The gate 107 is recessed to reduce overlap with the heavily doped drain region 104 and drift region 105, thereby reducing the gate-drain capacitance (C). gd ).

[0060] Preparation method

[0061] Figure 2A-2T A cross-sectional view showing a method for manufacturing an improved iT-FET device according to various aspects of the present invention. Figure 2A This diagram illustrates a cross-sectional view of the source layer and epitaxial layer of a semiconductor substrate during the formation of an improved iT-FET according to various aspects of the present invention. Initially, the semiconductor substrate includes a source layer 201 heavily doped with ions of a first conductivity type. An epitaxial layer 202 may be formed on the main surface of the source layer 201. The epitaxial layer 202 may be lightly doped with ions of a second conductivity type and may be grown on the surface of the source layer using atmospheric or depressurized epitaxial processes. A gate trench mask 203 may be applied to the main surface of the epitaxial layer 202 to prepare for gate trench formation. The gate trench mask 203 may be formed by any known method, such as, but not limited to, photolithography, or a patterned oxide layer formed by photolithography and oxide etching.

[0062] Figure 2B This diagram shows a side view cross-section of a gate trench formation in a modified iT-FET device according to various aspects of the present invention. A gate trench 204 can be formed in a semiconductor substrate through an epitaxial layer 202, extending into the source layer 201. The gate trench 204 can be formed using any known etching method. For example, dry reactive ion etching (DRIE) can be used to create the gate trench 204 without limitation. During etching, a gate trench mask 203 prevents the etching of portions of the epitaxial layer covered by the mask. The semiconductor substrate is etched in the areas not covered by the mask. After the gate trench is formed, the mask 203 is removed. The mask 203 can be removed using any suitable mask removal method, such as chemical etching or plasma ashing.

[0063] Figure 2CThis is a side cross-sectional view showing the gate formation step in an improved iT-FET device according to various aspects of the present invention. As shown, an insulating layer 205 is deposited over the surface of the epitaxial layer 202. The insulating layer 205 is arranged inside the gate trench 204. The insulating layer 205 can be a non-conductive material, such as, but not limited to, silicon dioxide. Silicon dioxide can be formed by chemical vapor deposition (CVD) or thermal oxidation.

[0064] Figure 2E This is a side view section illustrating the steps of forming a gate electrode in an improved iT-FET device according to various aspects of the present invention. The top surface of the semiconductor 15 substrate is polished to remove conductive material from the insulating layer 205 region not in the gate trench 204. Therefore, the gate electrode layer 206 is confined within the gate trench 204. The conductive material can be removed by polishing methods, such as, but not limited to, chemical mechanical polishing or plasma etching processes. Additionally, the gate electrode layer 206 can be etched to further reduce the height between the gate and source layers 201 in the gate trench. The gate electrode layer 206 can be etched using any known suitable plasma etching process.

[0065] Figure 2F This is a side cross-sectional view illustrating the steps of forming a gate electrode and gate stripe in an improved iT-FET device according to various aspects of the present invention. A gate stripe mask 207 is formed on top of a full-height gate electrode 208 in the gate stripe region. For example, the gate stripe mask 207 can be formed by any known masking method suitable for silicon etching, and is not limited thereto; the gate stripe mask 207 can be a photolithographic mask. After masking the gate stripe 208, the full-height gate electrode is etched to create a gate electrode 209 at an appropriate depth in the gate trench 204. The conductive material in the gate stripe trench 230 is not etched because it is covered by the gate stripe mask 207 that forms the gate stripe electrode 208. In this second etching step, the gate electrode 209 can be etched using any known suitable polysilicon or metal etching method, depending on the material of the gate electrode precursor.

[0066] Figure 2G This is a side view section illustrating the steps of forming the gate electrode and gate stripe in an improved iT-FET device according to various aspects of the present invention. The gate stripe mask 207 can be removed by any known mask removal method, depending on the type of mask used, such as, but not limited to, chemical etching or plasma ashing. An insulating layer 205 is deposited to cover the gate electrode 209 and the gate stripe electrode 208. The gate insulating layer 205 can be deposited by any known deposition method, such as, but not limited to, CVD.

[0067] Figure 2HThis is a side view section illustrating the steps of forming the gate electrode and gate strip in an improved iT-FET device according to various aspects of the present invention. The upper surface of the semiconductor substrate is polished to expose the surface of the epitaxial layer 202, and the height of the insulating layer 205 near the gate electrode 209 and the gate wheel insulation 210 near the gate wheel electrode 208 is reduced. The semiconductor substrate can be polished by any suitable method, such as CMP.

[0068] Figure 2I This is a side view cross-section illustrating the steps of forming a heavily doped drain region and a drift region in an improved iT-FET device according to various aspects of the present invention. A drain region mask 211 is formed on an active transistor region including, for example, a gate stripe 208. The drain region mask 211 extends from the edge of the semiconductor substrate onto the gate stripe insulator 210 and terminates at the gate insulator 209 closest to the gate stripe trench 230. The epitaxial layer 202 is doped with ions of a first conductivity type. The heavily doped drain region 212 is implanted with a high concentration of impurities of the first conductivity type after masking the gate-strip region. The drift region 213 is formed by implanting impurities of a lower concentration of the first conductivity type at an implantation energy of 150 keV to 500 keV. The doping of the drift region can occur along a gradient with the maximum impurity concentration near the heavily doped drain region 212, and the gradient decreases with distance from the heavily doped drain region 212 to the epitaxial layer 202. By protecting the gate-strip region from doping through a drain region mask, a portion of the epitaxial layer 202 remains undoped in the non-active transistor region. Doping of the drift region 213 and the heavily doped drain region 212 can be performed by any suitable method, such as, but not limited to, ion implantation. A drift doping concentration counter dops the bulk dopant in the epitaxial layer.

[0069] Figure 2J This is a side view section illustrating the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. The heavily doped drain region 212 and drift region 213 can be annealed by heating, for example, but not limited to, the semiconductor substrate can be heated in a furnace at about 1000°C for 30-60 minutes to anneal the drift region 213 and the heavily doped drain region 212. An insulating layer 214 is formed on top of the semiconductor substrate covering the gate trench and the gate strip trench. The insulating layer can be formed by any oxide layer formation method, for example, but not limited to CVD or thermal oxidation during the annealing of the heavily doped drain region and drift region.

[0070] Figure 2KThis is a side view cross-section illustrating the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. As shown, a shielding trench mask 215 is formed on a semiconductor substrate above an insulating layer 214. The mask is patterned to have gaps in the region between gate electrodes 209. After forming the shielding trench mask 215, the semiconductor substrate is etched through openings in the shielding trench mask. The etching process forms a shielding trench precursor that passes through the heavily doped drain region 212, the drift region 213, and into the epitaxial layer 202. The etching process can be any suitable silicon dioxide and silicon depth etching method, such as, but not limited to, DRIE. Then, the top of the epitaxial layer 202 at the shielding trench precursor is implanted with ions of a second conductivity type to form a body contact region 216 at the bottom of each shielding trench. The body contact region 216 can be implanted, for example, with boron at 20 keV-60 keV.

[0071] Figure 2L This is a side cross-sectional view illustrating the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. The shielding trench mask 215 is then removed after implantation of the epitaxial layer and the body contact region 216. The shielding trench mask 215 can be removed by any mask removal method, such as chemical etching or plasma ashing. An insulating layer 214 is further grown on the surface of the semiconductor substrate and in the shielding trench 217. The insulating layer 214 is arranged along the sides and bottom of the shielding trench precursor 217 covering the body contact region 216, as well as the sides of the heavily doped drain region 212, drift region 213, and epitaxial layer 202.

[0072] Figure 2M This is a side cross-sectional view showing the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. The insulating layer 214 located at the bottom of the shielding trench precursor 217 is etched away, exposing the upper surface of the body region 216. DRIE can be used to etch the insulating layer 214 at the bottom of the shielding trench precursor 217 without requiring a masking step.

[0073] Figure 2N This is a side view cross-section illustrating the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. The body contact region 216 and the epitaxial layer 202 are then etched in the shielding trench precursor 217 to complete the shielding trench. High-selectivity RIE etching is selected, preferentially etching, for example, the silicon at the bottom of the silicon substrate trench precursor without removing excessive silicon dioxide. The insulating layer 214 also acts as a mask, preventing etching in the area covered by the insulating layer and allowing etching at the bottom of the shielding trench precursor 217.

[0074] Figure 2OThis is a side cross-sectional view illustrating the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. After forming the shielding trench, a shielding trench electrode layer 219 can be formed on the exposed top surface of the semiconductor substrate and in the shielding trench. The shielding trench electrode layer 219 can be a silicide of a metal, such as tungsten. The shielding trench metal layer 219 can be coated with a supplementary material 218 to act as a diffusion barrier. The supplementary material coating 218 can be titanium, cobalt, or titanium nitride.

[0075] Figure 2P This is a side cross-sectional view illustrating the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. Etching is applied to the shielding trench electrode layer, etching metal from the main surface of the gate insulating layer precursor 214. The upper surface of the shielding trench electrode layer is etched away in the shielding trench, creating a shielding trench electrode 220 coated with a complementary metal coating 221. The etchant can be any etchant selective for the metal used as the shielding electrode. The shielding trench electrode 220 and coating 221 extend from the source layer 201, through the epitaxial layer 202 and the body contact region 216. The shielding trench extends over the body contact region 216 to the drift region 213 and the heavily doped drain region 212. The thickness of the insulating layer 214 is optimized to reduce the Ro between the shielding trench electrode 220 and the heavily doped drain region 212 and drift region 213. ds-on And reliable undervoltage potential. The shielding electrode 220 and coating 221 also act as a short circuit connecting the source layer 201 and the epitaxial layer 202 through the body contact area 216.

[0076] Figure 2Q This is a side view section illustrating the steps of forming a shielding structure in an improved iT-FET device according to various aspects of the present invention. An insulating layer 222 is deposited on the prior insulation 214 on the shielding electrode 220 and coating 221. The insulating layer 222 can be, for example, but not limited to, silicon dioxide and borosilicate glass (BPSG) applied via CVD. After applying the insulating layer 222, the top surface of the semiconductor substrate may be non-uniform. The insulating layer 222 can then be planarized to form a uniform top surface of the semiconductor substrate.

[0077] Figure 2RThis is a side view section illustrating the steps of forming drain and gate contacts in an improved iT-FET device according to various aspects of the present invention. After planarization, a drain mask 235 is applied to the surface of the insulating layer. The drain mask 235 can be applied by any suitable method, such as, but not limited to, photolithography. Etching is then performed on the upper surface of the semiconductor substrate. An etchant removes portions of the insulating layer not covered by the drain mask 235. The heavily doped drain region 226 is exposed after the etching process. Furthermore, the mask can expose the gate strip electrode 225 after etching. This prepares the top of the semiconductor substrate for forming the drain and gate-strip contacts. After this etching and the final shaping of the gate insulation 224 and the shielding insulation 223, the insulating layer defining the gate strip region 227 is finally defined. The drain contact mask 235 can be removed after etching by any suitable mask removal method, such as chemical cleaning, plasma ashing, or planarization.

[0078] Figure 2S This is a side view section illustrating the steps of forming drain and gate contacts in an improved iT-FET device according to various aspects of the present invention. After removing the mask, a metal layer 228 may be applied to the top surface of the semiconductor substrate. The metal layer may cover the exposed gate strip electrode 225 forming the gate strip contact plug 229. The gate strip contact may include a complementary metal coating 236. Furthermore, the metal layer 228 may cover the drain contact region 226 forming the drain contact plug 231. The drain contact plug 231 may include a complementary metal coating 232. The metal coating may be a silicide of a metal, such as, but not limited to, silicides of titanium or cobalt. The complementary metal plugs for the drain and gate strip contacts may be, for example, but not limited to, tungsten.

[0079] Figure 2T This is a side view cross-section illustrating the steps of forming the drain and gate strips in an improved iT-FET device according to various aspects of the present invention. A metal layer mask is applied to the surface of the metal layer above the gate strip metal 233 and drain metal 234. The metal layer mask can be applied by any suitable method, such as photolithography. An etching process is applied to the mask metal layer to form the final gate strip metal 233 and drain metal layer 234. The mask can be removed by any suitable process, such as, but not limited to, chemical etching and plasma ashing. Thus, the improved iT-FET device has an internal combination of source body contact and shielding electrode. The combination of source body contact and shielding electrode reduces the Ro of the device through the shielding effect. ds-on The recessed gate electrode reduces the gate-to-drain capacitance. Furthermore, the improved iT-FET device can be fabricated using existing trench FET fabrication equipment through an additional masking step, which reduces the overall manufacturing cost of the improved iT-FET device relative to bottom-source LDMOS.

[0080] In various aspects of the present invention, the integrated source body short-circuit and shielding electrode allow for improved iT-FET devices with relatively low gate-to-drain capacitance and low on-state (R0) ds-on The resistance from the drain to the source is reduced. This device configuration allows for faster switching speeds. Furthermore, the process for manufacturing this device can be implemented using a relatively simple and inexpensive process flow.

[0081] While the foregoing is a complete description of preferred embodiments of the present invention, various alternatives, modifications, and equivalents may be used. Therefore, the scope of the invention should not be determined by reference to the foregoing description, but rather by reference to the appended claims and their full equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not.

Claims

1. A reverse field-effect transistor (iT-FET) semiconductor device, comprising a source layer located at the bottom and a heavily doped drain region disposed on top of a semiconductor substrate: A vertical current conduction path between the source layer and the drain region is controlled by a trench gate disposed in a gate trench lined with insulating material. A shielding trench is disposed between adjacent gate trenches, and the heavily doped drain region is disposed near the top of the substrate surrounding the upper portion of the shielding trench and the gate trench. A doped body region is disposed in the substrate and surrounds the lower portion of the shielding trench; A shielding electrode in a shielding trench extends upward from the source layer, short-circuiting the source layer and the body region. The shielding electrode extends upward in the shielding trench to the heavily doped drain region and is insulated from the heavily doped drain region to serve as a shielding electrode.

2. The iT-FET semiconductor device of claim 1, wherein the shielding structure further includes a conductive plug in a shielding trench extending upward from the source layer through the body region to at least a portion of the drift region.

3. The iT-FET semiconductor device of claim 1, wherein the shielding electrode further includes a tungsten plug in a shielding trench extending upward from the source layer.

4. The iT-FET semiconductor device of claim 1, wherein the shielding electrode further includes a titanium silicide plug in a shielding trench extending upward from the source layer.

5. The iT-FET semiconductor device of claim 1, wherein the source layer of the semiconductor substrate is heavily doped with impurities of a first conductivity type, and the semiconductor substrate further includes an epitaxial layer formed above the source layer, doped with impurities of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type.

6. The iT-FET semiconductor device of claim 5, wherein the body region is formed in the epitaxial layer and heavily doped with impurities of a second conductivity type.

7. The iT-FET semiconductor device of claim 5, wherein a heavily doped drain region is formed in the epitaxial layer and is heavily doped with ions of a first conductivity type.

8. The iT-FET semiconductor device of claim 7, wherein an insulating layer between the shielding electrode and the heavily doped drain region and drift region is thicker than the insulating material portion between the gate electrode and the source layer and body region.

9. The iT-FET semiconductor device of claim 7, further comprising a drift region between the body region and the heavily doped drain region formed in the epitaxial layer, wherein the drift region is lightly doped with impurities of a first conductivity type than the heavily doped drain region.

10. The iT-FET semiconductor device of claim 9, wherein the drift region has an impurity concentration gradient, wherein the impurity concentration is highest near the heavily doped drain region and decreases in the deeper epitaxial layer below the heavily doped drain region.

11. The iT-FET semiconductor device of claim 1 further includes a conductive drain contact plug in contact with the heavily doped drain region and the drain metal.

12. A method for fabricating an iT-FET semiconductor device, comprising: a) An epitaxial layer doped with a second conductivity type impurity is formed on a substrate heavily doped with a first conductivity type impurity, wherein the first conductivity type is opposite to the second conductivity type, and wherein the substrate is used as a source layer; b) Forming a gate trench that penetrates the epitaxial layer and enters the source layer; c) Line the shielding trench with insulating material and form the gate electrode in the gate trench; d) Forming a drift region and a heavily doped drain region in the epitaxial layer, both doped with impurities of the first conductivity type; e) Shielding trenches are formed in the epitaxial layer by heavily doped drain and drift regions; f) A bulk contact region is formed at the bottom of the shielding trench by heavy doping with impurities of the second conductivity type; g) Line the shielding trench with insulating material; h) The shielding trench is deepened to the source layer through the body contact area, and a shielding structure is formed in the shielding trench, wherein the shielding structure extends upward from the source layer, making the source layer and the body region electrically short-circuited, wherein the shielding structure extends upward to the heavily doped drain region and is insulated from the drain region. i) A drain is formed above the epitaxial layer.

13. The method for fabricating an iT-FET semiconductor device as described in claim 12, wherein the shielding structure includes a shielding electrode that extends downward from the bottom of the drain region through the shielding trench and the body region to the source.

14. The method for fabricating an iT-FET semiconductor device as described in claim 13, wherein fabricating the shielding electrode further includes fabricating a conductive plug that extends upward from the source through the body region in the shielding trench to at least a portion of the drain region.

15. The method for fabricating an iT-FET semiconductor device as described in claim 14, wherein the conductive plug may be a tungsten plug extending upward from the source in the shielding trench.

16. The method for fabricating an iT-FET semiconductor device as claimed in claim 14, wherein the conductive plug is lined with titanium silicide and extends upward from the source in a shielding trench.

17. The method for fabricating an iT-FET semiconductor device as claimed in claim 12, wherein forming the drift region further includes forming an impurity concentration gradient in the drift region, wherein the impurity concentration is highest near the drain region and the ion concentration decreases in the epitaxial layer deeper below the heavily doped drain region.

18. The method for fabricating an iT-FET semiconductor device as claimed in claim 12, wherein h) further comprises lining the sidewalls of the shielding trench with a shielding insulating material that is thicker than the insulating material in the gate trench.

19. The method for fabricating an iT-FET semiconductor device as described in claim 12, wherein fabricating a drain above the epitaxial layer further includes fabricating a conductive drain contact plug that contacts the heavily doped drain region and the drain metal above the drain contact plug.

Images