Digital image data conversion

Abstract

The present disclosure relates to a processing device (3) for converting digital image data. Conventional methods are affected by speed or non-ideal compression schemes. These disadvantages are overcome by the processing device (3), which determines a digital output value (OUT) from a digital input value (IN) based on a linear function (1) and a square root function (2). The processing device (3) includes a first calculation block (6) and a second calculation block (7), the first calculation block being configured to determine a first output value (y1) of the linear function (1) and the second calculation block being configured to determine a second output value (y2) of the square root function (2). A selector (14) is configured to select whether the digital output value (OUT) is determined by the first calculation block (6) or the second calculation block (7) based on a comparison between the digital input value (IN) and a threshold value (XLIN).

Description

Technical Field

[0001] The present invention relates to a processing device, an image sensor and a calculation method. Background Art

[0002] In some applications, particularly sensor applications, continuous processing of sensor signals is essential. Some applications or standards require that sensor values ​​read from sensor circuits be processed using a given formula. For example, the amount of data in a digital image from an image sensor can be reduced by using a compression scheme. This compression scheme can be implemented according to a predefined function.

[0003] Such calculations are typically performed using a conventional microprocessor that has implemented a specific standard calculation algorithm or has implemented a lookup table with pre-calculated values ​​for each possible input value.

[0004] Although the latter approach requires a large amount of memory and / or area on the semiconductor chip, the speed at which the microprocessor calculates the algorithm may be insufficient and / or arbitrary.

[0005] For the above compression schemes, an appropriate transfer curve must be found. For example, compressing digital data according to a square root function might be a solution. However, for the small pixel values ​​of image sensors, compressing data according to a square root function might not be ideal.

[0006] One object of the present invention is to provide a processing device for converting digital image data in an efficient manner according to an optimized transfer curve. Another object is to provide a computational method for converting digital image data according to an optimized transfer curve.

[0007] This object is achieved by a processing device and a computing method according to the independent claims. Embodiments follow from the dependent claims. Summary of the Invention

[0008] In one embodiment, a processing device for converting digital image data is provided to determine a digital output value from a digital input value. The determination is based on a linear function and a square root function. The processing device includes a first calculation block configured to determine a first output value of the linear function and a second calculation block configured to determine a second output value of the square root function. The processing device also includes a selector configured to select whether the digital output value is determined by the first calculation block or the second calculation block based on a comparison between the digital input value and a threshold value.

[0009] In a preferred embodiment, the processing device can be implemented as an integrated circuit, wherein the first calculation block, the second calculation block, and the selector form different parts of the integrated circuit. This means that the processing device as a whole is implemented in hardware. However, in another embodiment, the processing device forms a processing unit, wherein at least the first calculation block, the second calculation block, or the selector is implemented in software on the processing unit.

[0010] Converting image data by determining a digital output value from a digital input value can mean that the image data is compressed. This means that the magnitude of the digital input value is greater than the magnitude of the digital output value. For example, the number of bits of the digital input value is 12, while the number of bits of the digital output value is 10. Thus, the image data is compressed from a 12-bit representation to a 10-bit representation. However, other compression levels are also possible, such as from 12 bits to 8 bits or from 10 bits to 8 bits.

[0011] A linear function converts digital input values ​​according to a transfer curve exhibiting a constant gradient. The gradient of the transfer curve can be set to 1. In this case, the image data, i.e., the digital input values, are transmitted uncompressed. However, the gradient of the transfer curve can also differ from 1.

[0012] The square root function converts a digital input value according to a transfer curve, where the digital output value depends on the square root of the digital input value. However, the digital output value can also depend on other variables. For example, the digital output value can depend on at least the maximum representable digital output value of the processing device.

[0013] The selector can be placed before or after the first and second calculation blocks. If the selector is placed before the first and second calculation blocks, the selection is made before the calculation blocks perform any calculations. Therefore, the first and second output values ​​do not need to be determined simultaneously. Instead, based on the selection, only one of these output values ​​is determined. If the selector is placed after the first and second calculation blocks, both the first and second output values ​​are determined.

[0014] A threshold is a digital value. A threshold can be represented as a fixed hardware value or a programmable hardware value.

[0015] Advantageously, converting digital image data according to a linear function and a square root function provides an effective compression scheme. By using this compression scheme, the amount of digital image data can be reduced.

[0016] In practice, a linear function is used to convert very small digital input values, particularly those below a threshold. Furthermore, the gradient of the linear function can be chosen to be 1. Consequently, small illumination values ​​of the image sensor's pixels are transmitted unchanged, reducing the complexity of the processing device. Furthermore, compression of low illumination values ​​is unnecessary, as the number of effective bits is already small.

[0017] The square root function is used to convert digital input values ​​above a threshold. The shot noise of an image sensor pixel, a quantum noise effect related to the discrete nature of photons and electrons, is also the square root of its value. Therefore, the error introduced by compression using the square root function is equidistant from the error that always exists.

[0018] For example, the processing device may be used as a circuit capable of calculating the photoelectric transfer characteristics of image pixels, or the processing device may be used in such a circuit. When using the proposed processing device, existing recommended methods can be adopted. These recommendations include, for example, ITU-R BT.709-6, ITU-R BT.2020-2, and ITU-R BT.2100-0. While the calculated results may not conform to these recommendations, the error is likely to be within the noise tolerance of the image sensor pixels.

[0019] Furthermore, when this compression scheme is used, the amount of image data will be reduced, but the compressed image can still be used without having to reconstruct it again. The compressed image still adheres to the visual content.

[0020] In one embodiment of the processing device, the linear function is defined by y1=A·IN, where y1 is the first output value, A is the first factor, and IN is the digital input value. The square root function is defined by Definition, where y2 is the second output value, C is the second factor, B is the first subtrahend, and D is the second subtrahend.

[0021] Advantageously, the linear function and the square root function can be adjusted by adjusting the first factor, the second factor, the first subtrahend, and the second subtrahend.

[0022] In one embodiment of the processing device, the combined function is formed by applying a linear function to digital input values ​​less than a threshold value and by applying a square root function to digital input values ​​greater than the threshold value. Furthermore, the combined function is continuous at the threshold value. The first subtrahend is formed by Determine, where XLIN is the threshold value. The second subtrahend is given by is determined, and the second factor is given by In the last formula, YMAX is the maximum digital output value of the processing device, and XMAX is the maximum digital input value of the processing device.

[0023] By choosing variables B, C, and D as described above, the combined function is continuously differentiable at the threshold, which means that the derivative of the linear function at that point is equal to the derivative of the square root function.

[0024] In practice, the first factor can be selected as A=1. All variables A, B, C, D, and XLIN can be represented as fixed hardware values ​​or programmable hardware values. The maximum digital output value YMAX and the maximum digital input value XMAX can be given values ​​of the processing device. For example, the digital input values ​​come from an analog-to-digital converter (ADC) connected to an image sensor. If these digital input values ​​are represented by 12 bits, the maximum digital input value is 2 12 If the processing device converts these 12-bit representations to 10-bit representations, the maximum digital output value is 2 10 .

[0025] Advantageously, the combined function comprises two distinct components: a linear function and a square root function, which together form a single curve without exhibiting any discontinuities. When the processing device is implemented in digital computing circuitry, the inverse calculations required to recover the original image can be extracted directly from the formula, without the uncertainties introduced by silicon technology variations. Due to the properties of the combined function, the transformed image still adheres to the visual context.

[0026] According to the selection of the maximum digital input value, the maximum digital output value and the threshold value, the first factor, the second factor, the first subtrahend and the second subtrahend can be adjusted accordingly. This allows the proposed compression scheme to be used by processing devices with different input ranges or output ranges.

[0027] In one embodiment of the processing device, the second computation block further includes at least one left shift operator. The left shift operator is configured to shift the digital input value and the second subtrahend two bits (two-bit-wise) toward the most significant bit (MSB) based on the magnitude of the digital input value. In this embodiment, the second computation block further includes at least one right shift operator, which is configured to shift the digital intermediate value bit-wise toward the least significant bit (LSB) side.

[0028] The digital input value and the second subtrahend, specifically their difference, form the digital input word for the square root calculation. The left shift operator shifts the digital input word by two bits toward the MSB side, based on the magnitude of the digital input value. The newly created bits on the LSB side are replaced with zeros. This is done before calculating the square root. A left shift by two bits corresponds to multiplying the digital input word by a factor of 2. 2n , where n is a natural number corresponding to the number of two-bit left shift operations. For example, if n is 1, the digital input word is multiplied by 4 by adding 2 zeros to the LSB side of the digital input word. If n is 2, the digital input word is multiplied by 16 by adding 4 zeros to the LSB side of the digital input word.

[0029] Since the digital input word is artificially increased by the left shift operator, the digital output word of the square root calculation must be reduced by the right shift operator in order to obtain the correct result.The digital output word can be the digital intermediate value mentioned above.

[0030] However, since the two-bit shift of the digital input word is performed before the square root calculation, the right shift operation after the square root calculation is only a bitwise shift, which corresponds to division by the factor 2. n The introduction of left shift and right shift operations can be seen in the following formula:

[0031]

[0032] When the term under the square root is multiplied by the factor 2 2n When the square root calculation result is divided by the factor 2 n This means that the digital output word is right-shifted by half the number of bits by which the digital input word is left-shifted. This also means that n corresponds to the number of shift operations, where in the case of a left shift operation the shift is by two bits, and in the case of a right shift operation the shift is by one bit.

[0033] However, if the size of the digital input value already uses the full capacity of the data path of the processing device, then the shift operations performed by the left and right shift operators are not required.

[0034] Advantageously, for situations where the data size of the input data (i.e., the digital input value) is smaller than the data path of the processing device, a shift mechanism is provided by shifting the data upwards via the left shift operator. By doing so, the full computational power of the processing device is utilized for the bit calculations following the digital point, thereby enhancing the final result.

[0035] In one embodiment of the processing device, the second factor in the second calculation block includes a mantissa term and an exponent term, and the multiplication of the digital value and the exponent term corresponds to a shift operation of the digital value.

[0036] This means that the second factor C can be expressed as follows: C = C val C_exp=C_val·2 -m , where C_val is the mantissa, C_exp is the exponent, and m is a natural number. Because the exponent is given by a base-2 exponent, multiplying a digital value by the exponent can be implemented as a bitwise shift of the digital value, where m determines the number of bits to shift. The negative sign in the exponent specifies that the shift is a right shift.

[0037] Advantageously, by representing the second factor as a mantissa term and an exponent term, the multiplication of the second factor by the square root calculation result can be optimized. Typically, this multiplication is performed by a multiplier circuit, which is typically large in an ASIC. The mantissa term contains the efficient path for the second factor and is optimized for this multiplication. This allows for a more efficient design of the multiplier circuit. Meanwhile, the exponent term corresponds to a shift operation, which is typically easily implemented in circuits.

[0038] In one embodiment of the processing device, the second calculation block further comprises a noise injection operator. The noise injection operator is configured to add a random value to the LSB side of the further digital intermediate value.

[0039] This can mean that the random value is added to the further digital intermediate value after its digital point.The further digital intermediate value can be a temporary result after the square root calculation.

[0040] Advantageously, in the case where certain artifacts are visible in an image, noise can be injected. By injecting noise, these artifacts can be randomized so that they are no longer visible in the entire image or image sequence.

[0041] In an embodiment of the processing device, the second calculation block further comprises a rounding operator configured to round the second further digital intermediate value to a predetermined precision.

[0042] The second further digital intermediate value can be a temporary result after adding a random value by the noise injection operator.For example, the first digit after the digital point can be used for rounding purposes.

[0043] Advantageously, the size of the digital output value can be further reduced with the aid of a rounding operator. For example, the first bit after the digital point can be used for rounding purposes, while the remaining bits to the right of that bit (the LSB side) can be truncated. By doing so, the desired accuracy of the digital output value can still be maintained.

[0044] In an embodiment of the processing device, the second calculation block further comprises a clipping operator. The clipping operator is configured to clip the third further digital intermediate value if it exceeds the maximum digital output value.

[0045] In case the third further digital intermediate value should exceed a maximum digital output value having a certain number of output bits, clipping may be performed.The third further digital intermediate value may be a value determined by a rounding operator.

[0046] Advantageously, by providing a clipping operator, overflow of the conversion is prevented. Such overflow may be caused by noise injection operators and rounding operators inappropriately increasing calculated values.

[0047] In one embodiment, the processing device further includes a bypass operator configured to control, independently of the comparison between the digital input value and the threshold value, whether the digital output value is determined by one of the first calculation block and the second calculation block or by the unchanged digital input value. In the latter case, the digital input value can be transmitted unchanged.

[0048] Advantageously, a bypass operator can be provided for modes of the processing device in which no compression of the image data is required. For example, the first factor can be set to A=1 so that the digital input value is transmitted unchanged.

[0049] In one embodiment of the processing device, the second calculation block further comprises a cascade of circuits configured to determine a digital output word that forms the square root of a digital input word. Each circuit within the cascade of circuits comprises a first input for receiving a portion of a digital input word of up to two bits. Each circuit within the cascade of circuits further comprises a logic block configured to determine an output bit and a temporary calculation rest of a digital output word based on the portion of the digital input word. Furthermore, each circuit within the cascade of circuits further comprises a first output for forwarding at least a portion of the digital output word as a temporary calculation result.

[0050] In a preferred embodiment, each circuit in the circuit cascade receives exactly two bits of the digital input word via its first input. In the event that the digital input word contains an odd number of bits, a logic "0" bit can be connected to the MSB side of the digital input word to make the number of bits even.

[0051] The first two bits on the MSB side of the digital input word are assigned to the first circuit in the circuit cascade. The next two bits are assigned to the next circuit, and so on, until the last two bits on the LSB side of the digital input word are assigned to the last circuit. Since the number of bits of the digital input word is always the same according to the data path of the processing device, the number of circuits is also constant.

[0052] Each circuit in the cascade forwards at least a portion of the digital output word via its first output as a provisional calculation result. The provisional calculation result of the first circuit includes the most significant bit of the digital output word. The provisional calculation result of the next circuit includes the two most significant bits of the digital output word, and so on, until the provisional calculation result of the last circuit includes the entire digital output word. Thus, the number of bits in the provisional calculation result increases by one from one circuit to the next.

[0053] In one embodiment of the processing device, each circuit in the cascade circuit, except for the first and last circuits, further includes a second input for receiving a temporary calculation margin of a preceding circuit. Each of these circuits further includes a third input for receiving a temporary calculation result from a first output of the preceding circuit. Furthermore, each of these circuits further includes a second output for forwarding the temporary calculation margin of the circuit to a second input of a subsequent circuit.

[0054] This means that the third input of each of these circuits is connected to the first output of the previous circuit via a data path. Furthermore, the second input of each of these circuits is connected to the second output of the previous circuit via another data path. As a result of the temporary calculation, the temporary calculation margin also increases by one bit from one circuit to the next.

[0055] In one embodiment of the processing device, the first circuit in the circuit cascade further includes a second input for receiving a logic "0" as a temporary calculation remainder and a second output for forwarding the temporary calculation remainder of the first circuit to the second input of the subsequent circuit. In this embodiment, the last circuit in the circuit cascade further includes a second input for receiving the temporary calculation remainder from the second output of the previous circuit and a third input for receiving the temporary calculation result from the first output of the previous circuit. The first output of the last circuit forwards the output word.

[0056] Advantageously, by determining the square root of a digital input word using a circuit cascade, a complex microprocessor with associated memory and software is not required, either on-chip or off-chip. Implementations utilizing different circuit instances within the circuit cascade ensure that the computation time for each digital input word or digital output word remains constant, particularly regardless of the typically changing digital input values. This can be particularly useful when processing sequences of digital input values ​​at a fixed data rate.

[0057] Because circuits are arranged in cascade, with the output of one circuit connected to the input of the next, the architecture of the processing device can be pipelined. Consequently, high data throughput can be achieved. Thanks to the pipelined architecture, image data can be converted much faster than a microprocessor can. Furthermore, each circuit within the cascade has a similar structure, enabling efficient circuit design.

[0058] In one embodiment, the processing device is implemented as an integrated circuit, in particular as an application specific integrated circuit ASIC.

[0059] An ASIC may not have a microprocessor. Therefore, all of the above calculations are implemented using specific hardware representations. For example, no microprocessor programming or software is required to perform the above calculations. However, an ASIC can include a microprocessor for other functions besides the above calculations.

[0060] As embodiments are implemented as integrated circuits, it is assumed that all variables (i.e., the first factor, the second factor, the first subtrahend, the second subtrahend, and the threshold) are selected to be fixed. Furthermore, the maximum digital input value and the maximum digital output value of the processing device may also be selected to be fixed for a given desired application. However, the aforementioned variables may still be programmable, for example, via a lookup table.

[0061] Advantageously, the processing means do not require a microprocessor on chip. This has the positive effect of reducing the power consumption of the circuit. Furthermore, the integrated circuit can be very small because dedicated memory for the microprocessor is not required.

[0062] In one embodiment, the processing device is formed by an image sensor that provides sensor values ​​from a plurality of image pixels, and the processing device converts the sensor values, in particular in a serial manner.

[0063] In various embodiments, the processing device can be implemented directly, for example, on an image sensor that provides thousands or millions of sensor values ​​within a limited time frame (i.e., the frame rate of the image sensor). Generally, such a processing device can be implemented in the digital data path of an image sensor that can be used in a film camera or an image camera (e.g., 4K-HD, etc.).

[0064] Advantageously, the processing means is implemented as a pipelined integrated circuit. This allows for high throughput, enabling its implementation in image sensors that require a specific frame rate, which is difficult to achieve using conventional architectures using microprocessors.

[0065] The processing device can also be embodied or described as a computational method that converts digital image data by determining a digital output value from a digital input value based on a linear function and a square root function. The computational method includes selecting whether the digital output value is determined by a first output value or a second output value based on a comparison between the digital input value and a threshold value. The method also includes determining the first output value of the linear function and / or determining the second output value of the square root function by performing a square root computation process.

[0066] As described above, it is possible to select whether the digital output value is determined by the first output value or the second output value before or after determining the first and second output values. If the selection is made beforehand, the first and second output values ​​do not need to be determined simultaneously. Instead, depending on the selection, only one of these output values ​​is determined. However, the selection can also be made after determining the first and second output values, so that both the first and second output values ​​are calculated. Then, depending on the selection, one of the output values ​​is discarded.

[0067] Advantageously, converting digital image data according to a linear function and / or a square root function provides an effective compression scheme. By using a linear function, small illumination values ​​of the image sensor's pixels can be transmitted unchanged. By using a square root function, the errors introduced by compression are equidistant from the pixel's shot noise. Furthermore, when using this compression scheme, since the compressed image still adheres to the visual content, it can still be used without having to reconstruct it.

[0068] In one embodiment of the calculation method, the linear function is defined by y1=A·IN, where y1 is the first output value, A is the first factor, and IN is the digital input value. The square root function is defined by Definition, where y2 is the second output value, C is the second factor, B is the first subtrahend, and D is the second subtrahend.

[0069] Advantageously, the linear function and the square root function can be adjusted by adjusting the first factor, the second factor, the first subtrahend, and the second subtrahend.

[0070] In one embodiment of the calculation method, determining the second output value may further include shifting the digital input value and the second subtrahend by two bits toward the most significant bit (MSB) based on the magnitude of the digital input value. In this embodiment, the digital input word is determined by applying the formula INW=IN′-D′, where In′ is the shifted digital input value and D′ is the shifted second subtrahend.

[0071] Determining the second output value further includes determining the digital output word by performing a square root calculation process.

[0072] In one embodiment, determining the second output value may further include providing the second factor as a mantissa term and an exponent term. In this embodiment, the digital intermediate value is determined by applying the formula IMD1=C_VAL·OUTW, where IMD1 is the digital intermediate value and C_VAL is the mantissa term of the second factor.

[0073] The digital intermediate value is then shifted bit by bit toward the least significant bit (LSB) based on the magnitude of the digital input value and the exponent of the second factor. Another digital intermediate value IMD2 is then determined by applying the formula IMD2=IMD1′-B, where IMD1′ is the shifted digital intermediate value.

[0074] Advantageously, by shifting the digital input values ​​and the digital intermediate values ​​left and right, the performance of the calculation method can be enhanced. This means that the calculation of square roots and multiplications can be performed more efficiently.

[0075] In one embodiment of the calculation method, a square root calculation process includes determining a digital output word from a digital input word, wherein the digital output word forms the square root of the digital input word. The method further includes dividing the digital input word into portions of at most two digits. Each portion of the digital input word is assigned to a subsequent calculation step, starting with the portion on the MSB side of the digital input word and proceeding toward the LSB side.

[0076] Each calculation step includes forming a temporary calculation margin by connecting the corresponding portion of the calculation step to the temporary calculation margin of the previous calculation step, if the previous calculation step exists. The calculation step also includes determining an internal calculation error Y=4·R+1, where R is the temporary result of the previous calculation step, if the previous calculation step exists. The calculation step also includes comparing the temporary calculation margin with the internal calculation error.

[0077] If the internal calculation error is less than or equal to the temporary calculation margin, a logic "1" bit is connected to the temporary result. Additionally, if the internal calculation error is less than or equal to the temporary calculation margin, the temporary calculation margin is adjusted by subtracting the internal calculation error. If the internal calculation error is greater than the temporary calculation margin, a logic "0" bit is connected to the temporary result.

[0078] Advantageously, by dividing the square root calculation into subsequent calculation steps, each of which provides one bit of the digital output word, the square root of a digital input word is calculated in an efficient and reliable manner. Consequently, the calculation method is fast and provides high data throughput. Furthermore, no memory is required to perform the square root calculation process, as the provisional calculation results are directly forwarded to subsequent calculation steps. Since each two bits of the digital input word are assigned to a dedicated calculation step, the calculation time remains constant, particularly regardless of the typically varying digital input values. This can be particularly useful when processing sequences of digital input values ​​at a fixed data rate.

[0079] From the various descriptions of the embodiments of the processing device, other implementations of the computing method will be apparent to those skilled in the art.

[0080] The improved conversion concept will be described in more detail below with the aid of the accompanying drawings. Elements with the same or similar functions are given the same reference numerals throughout the accompanying drawings. Therefore, their description will not be repeated in the subsequent drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 A transfer curve comprising two different parts according to a linear function and a square root function is shown.

[0082] Figure 2 One embodiment of a processing device is shown.

[0083] Figure 3 Another embodiment of a processing device is shown.

[0084] Figure 4 An embodiment of a circuit cascade for calculating the square root of a digital input word is shown.

[0085] Figure 5 An embodiment of an exemplary circuit within a circuit cascade is shown.

[0086] Figure 6 An example is shown for calculating the square root of an exemplary digital input word.

[0087] Figure 7 An image sensor including a processing device is shown. DETAILED DESCRIPTION

[0088] exist Figure 1 , a transfer curve is shown, according to which a conversion of a digital input value IN into a digital output value OUT can be performed. The digital input value is shown on the x-axis, which can reach a maximum digital input value XMAX. The digital output value is shown on the y-axis, which can reach a maximum digital output value YMAX.

[0089] The transfer curve forms a combined function that includes two different parts. The first part is formed by a linear function 1 that describes the equation OUT=A·IN using a first factor A. The first part of the linear function 1 is only valid for digital input values ​​from zero (IN=0) to a threshold value XLIN (IN=XLIN). The second part of the combined function is formed by a square root function 2 that describes the equation using a first subtrahend B, a second factor C, and a second subtrahend D. The second part of the combined function, which forms the square root function 2, is only valid for digital input values ​​from a threshold value XLIN (IN=XLIN) to a maximum digital input value XMAX (IN=XMAX).

[0090] The combined function is continuously differentiable at the threshold XLIN. Therefore, the function values ​​and derivatives of the linear function 1 and the square root function 2 are equal at the threshold XLIN. This can be written as:

[0091]

[0092]

[0093] Substituting the square root in equation (1) for the square root in equation (2) results in

[0094]

[0095] At the maximum digital input value XMAX, the square root function 2 should obtain the result YMAX. This means where the second subtrahend D can be replaced by the expression from equation (1) and the first subtrahend B can be replaced by the expression from equation (2). This results in the second factor C being:

[0096]

[0097] Inserting the expression for the second factor C into equations (1) and (2) results in the second subtrahend D being:

[0098]

[0099] In application Figure 1 In practical applications of the transfer curve shown, the first factor A can be chosen to be 1. This further simplifies equations (3) to (5). However, the first factor A can also be chosen to be different from 1.

[0100] Figure 1 The transfer curves shown can be used to transform digital image data. Thus, the transformation corresponds to a compression of the data. The following figures illustrate how compression based on the transfer curves can be implemented in a calculation method for transforming digital image data and / or in a processing device 3.

[0101] Figure 2 Shown according to Figure 1 The transfer curve shown is one embodiment of a processing device 3 for converting digital image data. However, Figure 2 It can also be interpreted as based on Figure 1 1 is a block diagram of a calculation method for determining a digital input value IN from a digital output value OUT of a transfer curve shown. The processing device 3 comprises an input 4 for receiving the digital input value IN. The processing device further comprises a first calculation block 6 configured to determine a first output value y1. The first calculation block 6 is connected to the input 4 of the processing device 3 so that the first calculation block 6 receives the digital input value IN. Figure 2In the embodiment shown, the first calculation block 6 delivers the digital input value IN unchanged. This means that the first factor A is selected to be 1, so that the first output value y1 is equal to the digital input value IN.

[0102] The processing device 3 further comprises a second calculation block 7 configured to determine a second output value y2. The second calculation block 7 is connected to the input 4 of the processing device 3 so that the second calculation block 7 receives a digital input value IN. The digital input value IN is forwarded to a first summation operator 8, which is configured to subtract a second subtrahend D from the digital input value IN and forward the result of this subtraction as a digital input word INW.

[0103] The second calculation block 7 further comprises a first tester 9 which is connected at its input to the first summation operator 8. The first tester 9 checks whether the digital input word INW is positive. If the digital input word INW is positive, the digital input word INW is transmitted unchanged. If the digital input word INW is not positive, the digital input word INW is set to zero.

[0104] The second calculation block 7 further comprises a square root operator 10 which is connected at its input side to the first tester 9. The square root operator 10 is configured to determine a digital output word OUTW from the digital input word INW by calculating the square root of the digital input word INW.

[0105] The digital output word OUTW is forwarded to the multiplier 11 of the second calculation block 7 , which is configured to multiply the second factor C by the digital output word OUTW and to forward the result of this multiplication as a digital intermediate value IMD1 .

[0106] The digital intermediate value IMD1 is forwarded to a second summation operator 12 which is configured to subtract the first subtrahend B from the digital intermediate value IMD1 and to forward the result of this subtraction as a second output value y2 .

[0107] The second calculation block 7 further comprises a second tester 13 which is connected at its input to the second summation operator 12. The tester 13 checks whether the second output value y2 is positive. If the second output value y2 is positive, the second output value y2 is transmitted unchanged. If the second output value y2 is not positive, the second output value y2 is set to zero.

[0108] The second calculation block 7 further comprises a selector 14 configured to select whether the digital output value OUT is determined by the first calculation block 6 or by the second calculation block 7 based on a comparison between the digital input value IN and the threshold value XLIN.

[0109] The result of this selection is forwarded to the output 5 of the processing device 3, wherein a first output value y1 and a second output value y2 are provided. Depending on the selection of the selector 14, the output 5 forwards either the first output value y1 or the second output value y2 as a digital output value OUT.

[0110] Figure 3 Another embodiment of the processing device 3 is shown. However, Figure 3 It can also be interpreted as based on Figure 1 FIG. 1 is a block diagram of another embodiment of a calculation method for determining a digital input value IN from a digital output value OUT of a transfer curve.

[0111] Figure 3 The processing device 3 and Figure 2 The processing device 3 shown in differs in particular in that the first calculation block 6 comprises a multiplier which is configured to multiply the first factor A with the digital input value IN and to forward the result of this multiplication as a first output value y1 .

[0112] Furthermore, the second computation block 7 includes a first left shift operator 16 configured to shift the digital input value IN by two bits toward the most significant bit (MSB) based on the size IN_SIZE of the digital input value IN. The second computation block 7 also includes a second left shift operator 17 configured to shift the second subtrahend D by two bits toward the MSB based on the size IN_SIZE of the digital input value IN. This means that the number of two-bit left shift operations depends on the size IN_SIZE of the digital input value IN.

[0113] In the case where the digital input value IN and the second subtrahend D are shifted, the summation operator 8 is configured to subtract the shifted second subtrahend D from the shifted digital input value IN and forward the result of this subtraction as the digital input word INW. Therefore, the summation operator 8 is connected on its input side to the first left shift operator 16 and the second left shift operator 17.

[0114] exist Figure 3 In the embodiment shown, the second factor C is provided as a mantissa term C_val and an exponent term C_exp. The multiplier 11 of the second calculation block 7 is configured to multiply the mantissa term C_val with the digital output word OUTW, which is determined from the digital input word INW by the square root operator 10. Furthermore, the result of this multiplication is forwarded as a digital intermediate value IMD1.

[0115] The second calculation block 7 further includes a back shifting operator 18 that determines, based on the size IN_SIZE of the digital input value IN, how many bitwise right shift operations are required for the digital output word OUTW to compensate for the two-bit left shift operation of the digital input word INW. The number of bitwise right shift operations may be equal to the number of two-bit left shift operations to compensate for the left shift operation.

[0116] In the third summation operator 19, the result determined by the backshift operator 18 is added to the exponent of the exponential term C_exp. The second computation block 7 also includes a right shift operator 20 configured to shift the digital intermediate value IMD1 by a certain number of bits toward the least significant bit (LSB). The number of bitwise right shift operations is based on the summation result performed by the third summation operator 19. The right shift operator 20 forwards the shifted digital intermediate value IMD1′.

[0117] The shifted digital intermediate value IMD1 ′ is forwarded to a second summation operator 12 , which is configured to subtract the first subtrahend B from the shifted digital intermediate value IMD1 ′ and to forward the result of this subtraction as a further digital intermediate value IMD2 .

[0118] Figure 3 The embodiment shown further comprises a noise injection operator 21 which is connected at its input to the second summation operator 12. The noise injection operator 21 is configured to add a random value NC to the LSB side of the further digital intermediate value IMD2. The noise injection operator forwards the second further intermediate value IMD3 as a result of this operation.

[0119] Figure 3 The embodiment further comprises a rounding operator 22 connected at its input to the noise injection operator 21. The rounding operator 22 is configured to round the second further digital intermediate value IMD3 to a predetermined precision. As a result of this operation, the rounding operator 22 forwards a third further intermediate value IMD4.

[0120] Figure 3 The embodiment further comprises a clipping operator 23 connected at its input to the rounding operator 22. The clipping operator 23 is configured to clip the third further digital intermediate value IMD4 if it exceeds the maximum digital output value YMAX. To this end, the clipping operator 23 compares the magnitude of the third further digital intermediate value IMD4 with the maximum digital output value YMAX. The clipping operator 23 forwards the second output value y2, as a result of this operation, to the output 5 of the processing device 3.

[0121] exist Figure 3In the embodiment of FIG. 1 , the processing device 3 further includes a bypass operator 24 configured to control whether the digital output value OUT is determined by one of the first output value y1 and the second output value y2 based on the selection made by the selector 14, or by the unchanged digital input value IN. If the bypass control variable BP is activated, the bypass operator 24 assigns the digital input value IN to the digital output value OUT regardless of the selection made by the selector 14. Otherwise, the selection made by the selector 14 (i.e., the first output value y1 or the second output value y2) is assigned to the digital output value OUT.

[0122] Figure 4 An embodiment of a square root operator 10 is shown. The square root operator 10 includes a cascade of circuits 25, 26, and 27. The cascade of circuits 25, 26, and 27 includes a first circuit 25, an additional circuit 26, and a final circuit 27. The cascade of circuits 25, 26, and 27 is configured to determine a digital output word OUTW that forms the square root of a digital input word INW. Each circuit 25, 26, and 27 in the circuit cascade includes a first input 28 for receiving a portion of a two-bit digital input word INW. The digital input word INW includes 2n bits, where n is a natural number. Therefore, the digital input word INW includes an even number of bits. The first circuit 25 receives the first two bits INW (2n-1:2n-2) on the MSB side of the digital input word INW. The next additional circuit 26 receives the next two bits INW (2n-3:2n-4) on the MSB side of the digital input word INW. This process continues until the final circuit 27 receives the last two bits INW (1:0) on the LSB side of the digital input word INW. The cascade of circuits 25 , 26 , 27 therefore comprises n circuits.

[0123] Another circuit 26 is in Figure 4 denoted by ellipsis and an exemplary k-th circuit 26, where k is another natural number.

[0124] Each circuit 25, 26, 27 of the circuit cascade further comprises a first output 29 for forwarding at least a part of the digital output word OUTW as a provisional calculation result R. The first output 29 of the last circuit 27 forwards the output word OUTW.

[0125] Each circuit 26,27,28 further comprises a second input 30 for receiving a temporary calculation margin T. Each circuit 26,27 except the first circuit 25 receives the temporary calculation margin T from the previous circuit 25,26. The first circuit 25 receives at the second input 30 a logic "0".

[0126] Each circuit 26 , 27 , except the first circuit 25 , comprises a third input 31 for receiving the provisional calculation result R from the first output 29 of the preceding circuit 25 , 26 .

[0127] Each circuit 25 , 26 , except the last circuit 27 , comprises a second output 32 for forwarding the temporary calculation margin T to a second input 30 of the following circuit 26 , 27 .

[0128] Therefore, the second output 32 of the circuit 25, 26 is connected to the second input 30 of the subsequent circuit 26, 27 via the data path. The first output 29 of the circuit 25, 26 is connected to the third input 31 of the subsequent circuit 26, 27 via another data path. The number of bits of the temporary calculation margin T transmitted by the data path increases by one after passing through each circuit 25, 26. For example, the temporary calculation margin T includes two bits after passing through the first circuit 25, and includes three bits after passing through the next additional circuit 26. The number of bits of the temporary calculation result R transmitted by the other data path also increases by one after passing through each circuit 25, 26, 27. For example, the temporary calculation result R includes one bit after passing through the first circuit 25, includes two bits after passing through the next additional circuit 26, and includes n bits after passing through the last circuit 27, as shown in FIG. Figure 4 shown.

[0129] exist Figure 5 The k-th circuit 26 of the cascade is shown in detail in . The circuit 26 further comprises a logic block 33 configured to determine an output bit O of the digital output word OUTW and a temporary calculation margin T.

[0130] The logic block 33 includes a first connector 34 connected to the first input 28 and the second input 30. The first connector 34 connects the corresponding two bits INW (2*(n-k+1)-1:2*(n-k+1)-2) of the digital input word INW to the temporary calculation margin T of the previous circuit 26. This means that the temporary calculation margin T is updated by shifting the temporary calculation margin T to the MSB side by two bits and replacing the newly added bits on the LSB side with the two bits INW (2*(n-k+1)-1:2*(n-k+2)-2).

[0131] Logic block 33 further includes a multiplier 35 connected to third input 31 and a first summation operator 36 connected to multiplier 35 for calculating an internal calculation error Y. The internal calculation error Y is defined by Y=4·R+1. The multiplication by the factor 4 can be performed by two bitwise left shift operations.

[0132] The logic block 33 further includes a comparator 37 that receives the updated temporary calculation margin T and the internal calculation error Y. The comparator 37 compares the updated temporary calculation margin T with the internal calculation error Y. If the internal calculation error Y is greater than the updated temporary calculation margin T, the comparator 37 outputs a logic "0" as an output bit 0. Otherwise, the comparator 37 outputs a logic "1" as an output bit 0.

[0133] The logic block 33 further includes a second connector 38 connected to the output of the comparator 37 and the third input 31. The second connector 38 connects the output bit O to the temporary calculation result R of the previous circuit 26. This means that the temporary calculation result R is updated by shifting the temporary calculation result R by one bit to the MSB side and replacing the newly added bit on the LSB side with the output bit O. The result of this operation is forwarded to the first output 29 of the circuit 26 as the updated temporary result R.

[0134] The logic block 33 also includes a multiplexer 39 that receives the output bit O and the internal calculation error Y. Only when the output bit O is "1" is the internal calculation error Y forwarded to the second summation operator 40, where the internal calculation error Y is subtracted from the temporary calculation margin T to form an updated temporary calculation margin T. Otherwise, when the output bit O is "0", the output bit O is forwarded to the second summation operator 40, which means that the temporary calculation margin T remains unchanged. The result of this operation is forwarded to the second output 32 of the circuit 26 as the updated temporary margin T.

[0135] Figure 6 The functional principle of the square root operator 10 or an example of the above-mentioned calculation method is shown. In the example, the square root of the digital input word "01010001" corresponding to the number 81 in decimal is calculated. Since the digital input word comprises 8=4×2 bits, the calculation can be performed by four calculation steps (or by a cascade of four circuits 25, 26, 27, respectively). The four calculation steps are Figure 6 The intermediate results of the temporary calculation margin T, internal calculation error Y, output bit O and temporary calculation result R of these calculation steps are also shown in FIG. Figure 6 Shown in.

[0136] At the start of calculation, the temporary calculation margin T and the temporary calculation result R are set to zero, T="0", R="0".

[0137] Calculation begins, assigning the first two bits "01" of the digital input word INW to the first calculation step 41. These first two bits "01" are then connected to the current temporary calculation margin T. Thus, the temporary calculation margin T becomes T = "001." The internal calculation error Y can be determined as Y = 4·R + 1, resulting in Y = "1." Since the internal calculation error Y is less than or equal to the temporary calculation margin T, Y ≤ T, an output bit O = "1" is generated and connected to the temporary calculation result R, which becomes "1." The temporary calculation margin T is updated by subtracting the internal calculation error Y, resulting in T = "00."

[0138] In the second calculation step 42, the next two bits "01" of the digital input word INW are connected to the current temporary calculation margin T. Thus, the temporary calculation margin T becomes T = "0001." The internal calculation error Y can be determined as Y = "0101," which is greater than the temporary calculation margin T. Therefore, the output bit O = "0" is generated and connected to the temporary calculation result R, which becomes "10." The temporary calculation margin T is updated by subtracting the output bit O, so that it becomes T = "001."

[0139] In the third calculation step 43, the next two bits "00" of the digital input word INW are connected to the current temporary calculation margin T. Thus, the temporary calculation margin T becomes T = "00100." The internal calculation error Y can be determined as Y = "01001," which is greater than the temporary calculation margin T. Therefore, the output bit O = "0" is generated and connected to the temporary calculation result R, which becomes "100." The temporary calculation margin T is updated by subtracting the output bit O, so that it becomes T = "0100."

[0140] In the fourth calculation step 44, the next two bits "01" of the digital input word INW are connected to the current temporary calculation margin T. Thus, the temporary calculation margin T becomes T = "010001". The internal calculation error Y can be determined as Y = "010001", which is equal to the temporary calculation margin T. Therefore, the output bit O = "1" is generated and connected to the temporary calculation result R, which becomes "1001". The temporary calculation margin T is updated by subtracting the internal calculation error Y, so that T = "0". This means that there is no margin left. The temporary calculation result R is the digital output word OUTW = "1001", which corresponds to the number 9 in decimal.

[0141] Figure 7 An image sensor 45 is shown that includes a processing device 3. The image sensor further includes a plurality of pixels 46. The pixels are configured to receive electromagnetic radiation and generate analog signals 47 in response to the electromagnetic radiation. The analog signals 47 can be converted into digital input values ​​IN by an analog-to-digital converter 48, in particular in a serial manner. The processing device 3 receives the digital input values ​​IN. Furthermore, the processing device 3 converts each digital input value IN into a digital output value OUT in the manner described. The image sensor 45 may include further components, such as an image processor ( Figure 7 (not shown in FIG). The digital output value OUT can be further processed by an image processor.

[0142] In order to familiarize the reader with the novel aspects of the concept, the embodiments of the processing device 3 and the computing method disclosed herein have been discussed. Although preferred embodiments have been shown and described, those skilled in the art may make many changes, modifications, equivalents and substitutions to the disclosed concepts without departing from the scope of the claims.

[0143] It should be understood that the present disclosure is not limited to the disclosed embodiments and what has been particularly shown and described above. Rather, features described in separate dependent claims or in the specification may be advantageously combined. Furthermore, the scope of the present disclosure includes those changes and modifications that are obvious to a person skilled in the art and fall within the scope of the appended claims.

[0144] The term "comprising" used in the claims or the description does not exclude the presence of other elements or steps of the corresponding feature or procedure. If the terms "a" or "an" are used in conjunction with a feature, this does not exclude a plurality of such features. Furthermore, any reference signs in the claims should not be construed as limiting the scope.

[0145] This patent application claims priority from European patent application 20182937.1, the disclosure of which is incorporated herein by reference.

[0146] Description of Reference Numerals

[0147] 1 Linear function

[0148] 2 Square root function

[0149] 3 Processing device

[0150] 4 Processing device input

[0151] 5. Output of processing device

[0152] 6 First calculation block

[0153] 7 Second calculation block

[0154] 8 First summation operator

[0155] 9 First Tester

[0156] 10 Square root operator

[0157] 11 Multiplier of the second computation block

[0158] 12 Second summation operator

[0159] 13 Second Tester

[0160] 14 Selector

[0161] 15 Multiplier of the first computation block

[0162] 16 First left shift operator

[0163] 17 Second left shift operator

[0164] 18 Backshift operator

[0165] 19 The third summation operator

[0166] 20 Right shift operator

[0167] 21 Noise Injection Operator

[0168] 22 Rounding operators

[0169] 23 Clipping Operator

[0170] 24 Bypass Operator

[0171] 25 Circuit cascade first circuit

[0172] 26 Additional circuits in the circuit cascade

[0173] 27 The final circuit in the circuit cascade

[0174] 28 First input of the circuit

[0175] 29 First output of circuit

[0176] 30 Second input of circuit

[0177] 31 The third input of the circuit

[0178] 32 Second output of circuit

[0179] 33 logic blocks

[0180] 34 First Connector

[0181] 35 logic block multipliers

[0182] 36 The first summation operator of the logic block

[0183] 37 Comparator

[0184] 38 Second connector

[0185] 39 Multiplexer

[0186] 40 Second summation operator of logic block

[0187] 41 First calculation step

[0188] 42 Second calculation step

[0189] 43 Third calculation step

[0190] 44 Fourth calculation step

[0191] 45 Image Sensor

[0192] 46 pixels

[0193] 47 Analog Signal

[0194] 48 Analog-to-digital converters

[0195] A first factor

[0196] B First subtrahend

[0197] BP bypass control variable

[0198] C second factor

[0199] D Second subtrahend

[0200] IMD1 Digital Median Value

[0201] IMD1' intermediate value of the shifted number

[0202] IMD2 Additional digital intermediate value

[0203] IMD3 Second additional digital median value

[0204] IMD4 Third additional digital median value

[0205] IN digital input value

[0206] INW digital input word

[0207] IN_SIZE The size of the digital input value

[0208] NC Random Value

[0209] n, k natural numbers

[0210] O Output bit

[0211] OUT Digital output value

[0212] OUTW digital output word

[0213] XLIN Threshold

[0214] XMAX Maximum digital input value

[0215] y1 first output value

[0216] y2 second output value

[0217] YMAX Maximum digital output value

Claims

1. A processing device (3) for converting digital image data by determining a digital output value OUT from a digital input value IN based on a linear function (1) and a square root function (2), the processing device (3) comprising: a first calculation block (6) configured to determine a first output value y1 of said linear function (1), - a second calculation block (7) configured to determine a second output value y2 of said square root function (2), and - a selector (14) configured to select whether the digital output value OUT is determined by the first calculation block (6) or by the second calculation block (7) based on a comparison between the digital input value IN and a threshold value XLIN, wherein - the linear function (1) is defined by y1=A·IN, A being the first factor, and wherein the square root function (2) is defined by Definition: C is the second factor, B is the first subtrahend, and D is the second subtrahend.

2. The processing device (3) according to claim 1, wherein a combined function is formed by applying the linear function (1) to digital input values ​​IN less than the threshold value XLIN and by applying the square root function (2) to digital input values ​​IN greater than the threshold value XLIN, the combined function being continuous at the threshold value XLIN such that: - The first subtrahend B is given by Sure, - The second subtrahend D is given by OK, and The second factor C is given by Determine, where YMAX is the maximum digital output value of the processing device (3) and XMAX is the maximum digital input value of the processing device (3).

3. The processing device (3) according to claim 1, wherein the second calculation block (7) further comprises: - at least one left shift operator (16, 17) configured to shift the digital input value IN and the second subtrahend D by two bits toward the most significant bit (MSB) side based on the size IN_SIZE of the digital input value IN, and - at least one right shift operator (20) configured to shift the digital intermediate value IMD1 bitwise toward the least significant bit (LSB).

4. The processing device (3) according to claim 1, wherein in the second calculation block (7), the second factor C includes a mantissa term C_VAL and an exponent term C_EXP, and wherein the multiplication of the digital value by the exponent term C_EXP corresponds to a shift operation of the digital value.

5. The processing device (3) according to claim 2, wherein the second calculation block (7) further comprises: a noise injection operator (21) configured to add a random value NC to the LSB side of the further digital intermediate value IMD2, and / or - a rounding operator (22) configured to round the second further digital intermediate value IMD3 to a predetermined precision, and / or - a clipping operator (23) configured to clip the third further digital intermediate value IMD4 if the third further digital intermediate value exceeds the maximum digital output value YMAX.

6. The processing device (3) according to claim 1, wherein the second calculation block (7) further comprises a cascade of circuits (25, 26, 27), the cascade being configured to determine a digital output word OUTW forming the square root of a digital input word INW, and wherein each circuit (25, 26, 27) within the cascade comprises a first input (28) for receiving a portion of a digital input word INW of up to two bits, - a logic block (33) configured to determine an output bit O and a temporary calculation margin T of the digital output word OUTW based on a portion of the digital input word INW, and - a first output (29) for forwarding at least a portion of the digital output word OUTW as a temporary calculation result R.

7. The processing device (3) according to claim 6, wherein each circuit (26) in the cascade except the first circuit (25) and the last circuit (27) further comprises: - a second input (30) for receiving the temporary calculation margin T of the previous circuit (25, 26), - a third input (31) for receiving the temporary calculation result R from the first output (29) of the previous circuit (25, 26), and - a second output (32) for forwarding the temporary calculation remainder T of this circuit (26) to a second input (30) of a subsequent circuit (26, 27).

8. The processing device (3) according to claim 7, wherein the first circuit (25) in the cascade further comprises: - a second input (30) for receiving a logic "0" as a temporary calculation margin T, and a second output (32) for forwarding the temporary calculation margin T of said first circuit (25) to a second input (30) of a subsequent circuit (26), And wherein the last circuit (27) in the cascade further comprises a second input (30) for receiving the temporary calculation margin T from the second output (32) of the preceding circuit (26), - a third input (31) for receiving a temporary calculation result R from the first output (29) of the previous circuit (26), and wherein - The first output (29) of the last circuit (27) forwards the output word OUTW.

9. The processing device (3) according to claim 1, being implemented as an integrated circuit.

10. The processing device (3) according to claim 9, being implemented as an application specific integrated circuit (ASIC).

11. An image sensor (45) comprising a processing device (3) according to claim 1, the image sensor providing sensor values ​​from a plurality of image pixels (46), wherein the processing device (3) converts the sensor values.

12. The image sensor (45) according to claim 11, the processing device (3) converting the sensor values ​​in a serial manner.

13. A calculation method for converting digital image data by determining a digital output value OUT from a digital input value IN based on a linear function (1) and a square root function (2), the calculation method comprising: - selecting, based on a comparison between the digital input value IN and a threshold value XLIN, whether the digital output value OUT is determined by the first output value y1 or by the second output value y2, - determining a first output value y1 of said linear function (1), and / or - determining a second output value y2 of said square root function (2) by performing a square root calculation process, wherein - the linear function (1) is defined by y1=A·IN, A being the first factor, and wherein the square root function (2) is defined by Definition: C is the second factor, B is the first subtrahend, and D is the second subtrahend.

14. The method according to claim 13, wherein determining the second output value y2 further comprises: - shifting the digital input value IN and the second subtrahend D by two bits toward the most significant bit (MSB) based on the size IN_SIZE of the digital input value IN, and - determining the digital input word INW=IN′−D′, where IN′ is the shifted digital input value IN and D′ is the shifted second subtrahend D, -Determine the digital output word by performing a square root calculation process - providing said second factor C as a mantissa term C_VAL and an exponent term C_EXP, - Determine the digital intermediate value IMD1 via IMD1=C_VAL·OUTW, - shifting the digital intermediate value IMD1 bitwise toward the least significant bit (LSB) based on the size IN_SIZE of the digital input value IN and the exponential term C_EXP, and - Determining a further digital intermediate value IMD2 via IMD1 = IMD1 ′-B, where IMD1 ′ is the shifted digital intermediate value IMD1 .

15. The method of claim 13 , wherein the square root calculation process for determining the digital output word OUTW from the digital input word INW further comprises: - splitting the digital input word INW into parts of at most two digits, - assigning each portion of the digital input word INW to a subsequent calculation step (41, 42, 43, 44), starting with the portion on the MSB side of the digital input word INW and continuing with the subsequent portions towards the LSB side, wherein each calculation step (41, 42, 43, 44) comprises - forming a temporary calculation remainder T by connecting the corresponding parts of the calculation steps (41, 42, 43, 44) to the temporary calculation remainder T of the previous calculation step, in the presence of a previous calculation step, - in the presence of a previous calculation step, the internal calculation error Y is determined by Y=4·R+1, where R is the temporary calculation result of the previous calculation step, - comparing the temporary calculation margin T with the internal calculation error Y, - if the internal calculation error Y is less than or equal to the temporary calculation margin T, connecting a logic "1" bit to the temporary calculation result R and adjusting the temporary calculation margin T by subtracting the internal calculation error Y, - If the internal calculation error Y is greater than the temporary calculation margin T, a logic "0" bit is connected to the temporary calculation result R.

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