Memory channel controller operations

Abstract

The present disclosure includes systems, devices, and methods related to memory channel controller operations. For example, a data type associated with an access request can be determined. The access request can be performed utilizing a first memory channel controller coupled to a first memory device to access a first memory address range associated with a first data type allocated to the first memory device in response to determining that the access request is associated with the first data type. The access request can be performed by utilizing the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range associated with a second data type allocated among the first memory device and the second memory device in response to determining that the access request is associated with the second data type.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to methods, systems, and apparatus for operating memory channel controllers. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM) and three-dimensional crosspoint memory (e.g., 3D XPoint). TM Resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), and programmable conductive memory, as well as other types of memory. Summary of the Invention

[0003] In one aspect, this disclosure relates to a method comprising: determining a data type associated with an access request; executing the access request by accessing a first portion of a first memory address range allocated to the first memory device and associated with the first data type using a first memory channel controller coupled to a first memory device in response to determining that the access request is associated with a first data type; and executing the access request by accessing a second memory address range allocated in the first memory device and associated with the second data type using the first memory channel controller and a second memory channel controller coupled to a second memory device in response to determining that the access request is associated with a second data type.

[0004] In another aspect, this disclosure relates to an apparatus comprising: a first memory controller coupled to a first memory device, wherein a first memory address range reserved for a portion of a first data type is allocated to the first memory device; a second memory controller coupled to a second memory device, wherein a second memory address range reserved for a portion of a second data type is allocated in both the first and second memory devices; and a memory manager configured to: determine a data type associated with an access request; execute the access request using the first memory controller in response to the determination that the access request is associated with the first data type and in response to the determination that another access request to be executed concurrently with the access request is not for the first memory address range; and execute the access request using both the first and second memory controllers in response to the determination that the access request is associated with the second data type.

[0005] In another aspect, this disclosure relates to a system comprising: a first memory controller coupled to a first memory device, wherein a first memory address range reserved for a first portion of a first data type is allocated to the first memory device; a second memory controller coupled to a second memory device, wherein: a second memory address range reserved for the first portion of the second data type is allocated in both the first and second memory devices, and a third memory address range reserved for a second portion of the first data type is allocated to the second memory device; and a memory manager configured to: determine a memory address range associated with a first access request; determine a memory address range associated with a second access request; execute the first access request using the first and second memory controllers in response to the determination that the first access request is associated with the second memory address range; execute the first access request using the first memory controller in response to the determination that the first access request is associated with the first memory address range; and execute the second access request using the second memory controller in parallel with the execution of the first access request using the first memory controller in response to the determination that the first access request is associated with the first memory address range and the determination that the second access request is associated with the third memory address range. Attached Figure Description

[0006] Figure 1 This is a block diagram of a device in the form of a computing system including a memory system, according to embodiments of the present disclosure.

[0007] Figure 2 This is a block diagram of a memory channel within a memory system according to an embodiment of the present disclosure.

[0008] Figure 3 This is a block diagram illustrating the execution of multiple L2P access requests using multiple memory channels within a memory system according to embodiments of the present disclosure.

[0009] Figure 4 This is a block diagram illustrating the execution of multiple PMR access requests using multiple memory channels within a memory system according to embodiments of the present disclosure.

[0010] Figure 5 This is a block diagram illustrating CMB access requests utilizing multiple memory channels within a memory system according to embodiments of the present disclosure.

[0011] Figure 6 This is a block diagram of a method for executing an access request according to embodiments of the present disclosure. Detailed Implementation

[0012] Various embodiments of this disclosure describe methods, systems, and apparatus for operating memory channel controllers. Several embodiments may provide improved performance (e.g., reduced latency) and / or power savings by providing multiple channel controllers, which may operate independently or in parallel depending on the type of access request (e.g., from a client).

[0013] For example, a memory system may include a controller communicatively coupled to multiple memory devices. Each of the memory devices may contain an array of memory cells storing data values. The controller may receive access requests for accessing data values ​​in the memory cells from a communicatively coupled host. The controller may translate the access requests into commands for transmission to and execution by the multiple communicatively coupled memory devices. The controller may transmit commands and their responses on a memory bus. The width of the memory bus may correspond to the amount of data that can be transmitted across the memory bus during a single tick or clock cycle increment, timing, and / or synchronization of cross-bus data transmission. For example, a tick may correspond to a clock cycle increment during which an amount of data equal to the width of the memory bus can be transmitted between the controller and the memory devices. In some instances, the memory bus may be 64-bit wide, meaning that a maximum of 64 data bits can be transmitted between the controller and the memory devices during a single tick. In some instances, the memory bus may consist of multiple disparate channels operating between the controller and the memory devices. For example, the memory bus may include four 16-bit wide channels that together form a 64-bit wide memory bus interface.

[0014] In some instances, the controller and memory device can communicate on the memory bus in beat bursts. A burst can contain multiple beats during which data is transmitted. For example, a response to a command can contain 128 bytes of data. The 128 bytes of data can be transmitted to the controller on the memory bus in a burst of sixteen beats, with each beat containing a transmission of 64 bits (or 8 bytes) of data each time.

[0015] However, the execution of some access requests may involve the transfer of an amount of data smaller than the width of the memory bus during the burst duration. In one instance, the access request may be a relatively short access that contains a request to access data in an amount that will only consume a fraction of the memory bus width during the burst duration. For example, the access request may directly access 5 bytes of data in a firmware table stored on the memory device. In such instances, although only a portion is needed to complete the transfer, the entire width of the current memory bus is dedicated to providing data over the entire burst length.

[0016] In contrast, various embodiments of this disclosure enable channelized data storage and access across multiple memory devices in a memory system. For example, embodiments may partition data and its access across multiple memory devices accessible via multiple respective channels using multiple corresponding memory controllers. With the channelized data storage and access embodiments described herein, less than full capacity of the memory bus can be used to transfer data and / or multiple access requests can be executed in parallel to utilize any remaining capacity. Among other improvements, latency can be reduced by executing multiple shorter access requests in parallel, and power consumption can be reduced by utilizing only a minimum number of channels to execute access requests.

[0017] As used herein, “a / an” or “a number” can refer to one or more of something, and “a number” can refer to two or more of such things. For example, a memory device can refer to one or more memory devices, and multiple memory devices can refer to one or more memory devices.

[0018] The figures in this document follow a numbering rule, where the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits.

[0019] Figure 1This is a block diagram of a device in the form of a computing system 100 including a memory system 102, according to embodiments of the present disclosure. As used herein, the memory system 102 may include a controller 104, a plurality of memory channel controllers 106-1...106-N, and a plurality of memory devices 108-1...108-N. As used herein, the memory system 102, controller 104, the plurality of memory channel controllers 106-1...106-N, and / or the plurality of memory devices 108-1...108-N may also be individually considered as a “device”.

[0020] The computing system 100 includes a host 110 communicatively coupled (e.g., connected) to the memory system 102. The host may be a host system such as a personal laptop computer, desktop computer, digital camera, smartphone, memory card reader, and / or IoT-enabled device, as well as various other types of host systems. The host 110 may include a system motherboard and / or backplane, and may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry). The computing system 100 may include a separate integrated circuit, or the host 110 and the memory device 120 may both be on the same integrated circuit.

[0021] In some instances, host 110 may be communicatively coupled to memory system 102 and / or communicate with memory system via a host bus, which may be referred to as a system bus. The host may generate access requests to access data stored on memory system 102. Although Figure 1 A single host 110 is shown, but embodiments are not so limited. For example, multiple hosts may be coupled to memory system 102, each capable of making client requests (e.g., access requests) to controller 104 via a corresponding system bus. Additionally, host 110 may invoke one or more of multiple different clients 105-1...105-N associated with various data types included in and / or requested by the access requests. In some instances, more than one host may communicatively couple to memory system 102 and / or access data in said memory system. Each host 110 may include hardware, user profiles, and / or instruction sets (e.g., applications, programs, etc.) that, as part of its operation and / or execution, depend on sending client requests (e.g., access requests) to another set of hardware and / or instructions (e.g., memory system 102, etc.) for access to data, services, functionality, etc., provided from said other set of hardware and / or instructions in response to the client requests.

[0022] Clients 105-1...105-N may be associated with accessing specific types of data. For example, a first client may be associated with accessing Control Memory Buffer (CMB) type data stored in memory devices 108-1...108-N. A second client may be associated with accessing Persistent Memory Buffer (PMR) type data stored in memory devices 108-1...108-N. A third client may be associated with accessing Logical to Physical Table (L2P) type data stored in memory devices 108-1...108-N. CMB, PMR, and L2P data are some non-limiting examples of data types associated with corresponding clients 105-1...105-N. Clients 105-1...105-N may reside and / or be executable in memory device 102, reside and / or be executable in controller 104, and / or reside and / or be executable in host 110.

[0023] Memory system 102 may include a plurality of memory devices 108-1...108-N (collectively referred to as memory devices 108). Each of the plurality of memory devices 108-1...108-N may be a single memory device or multiple memory devices. A memory device may be a memory die comprising an array of memory cells. For example, a memory device may comprise an array or multiple arrays of memory cells arranged as memory cells, located on a single chip or distributed across multiple chips of the memory device. Memory device 108 may be a DRAM device; however, embodiments are not so limited. For example, a memory device may include a ferroelectric random access memory (FeRAM) device and various other types of volatile or non-volatile memory devices.

[0024] In some embodiments, each memory device may be individually addressed, for example, by a controller and / or a memory channel controller, as described in more detail below. Each memory device may include a system processor to control and / or schedule the execution and / or grouping of memory operations in response to instructions received from the system processor to perform memory operations.

[0025] Data can be stored in memory cells of memory devices 108-1...108-N. Host 110 can transmit access requests to memory system 102 to access data stored in memory cells of memory devices 108-1...108-N.

[0026] Memory system 102 includes controller 104. Controller 104 may include hardware and / or instructions for decoding access requests provided from host 110. These signals may include chip enable signals, write enable signals, and / or address latch signals, which can be used to control operations performed on the memory array of memory devices 108-1...108-N, including data sensing, data storage, data movement (e.g., copying, transferring, and / or delivering data values), data writing and / or data erasure operations, and other operations. In various embodiments, controller 104 may be responsible for scheduling the execution of instructions from host 110 and access to data on memory devices 108-1...108-N using memory channel controllers 106-1...106-N. Controller 104 may be a state machine, sequencer, or some other type of controller. In some instances, controller 104 and / or its instructions may be referred to as a memory manager component of memory system 102.

[0027] The memory system 102 includes a plurality of memory channel controllers 106-1...106-N. The memory channel controllers 106-1...106-N may be state machines, sequencers, or some other type of controller. Each of the plurality of memory channel controllers 106-1...106-N may be configured to execute instructions from the host 110 relative to a corresponding portion of the plurality of memory devices 108-1...108-N. For example, a first memory channel controller 106-1 may be responsible for accessing data of a first number of memory devices 108-1 associated with a first channel, a second memory channel controller 106-2 may be responsible for accessing data of a second number of memory devices 108-2 associated with a second channel, and so on.

[0028] Therefore, each of the plurality of memory channel controllers 106-1...106-N may include and / or utilize a physical interface or memory bus that communicatively couples the memory channel to a corresponding portion of the plurality of memory devices 108-1...108-N. For example, the first memory channel controller 106-1 may share a physical memory bus interface with the first memory device 108-1, the second memory channel controller 106-2 may share a physical memory bus interface with the second memory device 108-2, and so on.

[0029] The interface between memory devices 108-1…108-N and their corresponding memory channel controllers 106-1…106-N may have a data width corresponding to the amount of data that can be transferred across the memory bus during an increment, timing, and / or synchronization of cross-bus data transmission in a single beat or clock cycle. The total width of the memory bus interface between all memory devices 108-1…108-N and all their corresponding memory channel controllers 106-1…106-N may be the maximum total width of the memory bus interface achievable when all memory channel controllers 106-1…106-N are operated simultaneously. For example, the maximum total width of the memory bus interface achievable when all memory channel controllers 106-1…106-N are operated simultaneously may be 64 data bits. Therefore, in the case where there are only two memory channel controllers in the memory system, the memory bus width between the first memory channel controller and its corresponding memory device may be 32 bits, and the memory bus width between the second memory channel controller and its corresponding memory device may also be 32 bits. Extending the examples to a memory system with four memory channel controllers, each memory bus interface between each of the four memory channel controllers and its corresponding memory device can be 16 bits. These non-limiting examples illustrate the ways in which the maximum total width of the memory bus interface can be divided among any number of memory channel controllers included in a memory system.

[0030] Memory channel controllers 108-1...108-N can operate independently and / or simultaneously (e.g., in parallel) to provide different widths of data transfer capacity. For example, a first memory channel controller 106-1 can be used independently of the other memory channel controllers 106-2...106-N among the plurality of memory channel controllers 106-1...106-N, thereby providing a per-second data transfer width corresponding to the memory bus width dedicated to the first memory channel controller 106-1. Alternatively, the first memory channel controller 106-1 and the second memory channel controller 106-2 can be used simultaneously, thereby providing a per-second data transfer width corresponding to the memory bus width dedicated to the first memory channel controller 106-1 in addition to the memory bus width dedicated to the second memory channel controller 106-2.

[0031] For example, if each of the four memory channel controllers of the plurality of memory channel controllers 106-1...106-N communicates with its corresponding memory device 108-1...108-N via a 16-bit-per-beat wide memory bus interface, then operating a single memory channel controller independently will provide a data transfer capacity of 16 bits per beat, operating two memory channel controllers simultaneously will provide a total data transfer capacity of 32 bits per beat, operating three memory channel controllers simultaneously will provide a total data transfer capacity of 48 bits per beat, and / or operating four memory channel controllers simultaneously will provide a total data transfer capacity of 64 bits per beat.

[0032] By channelizing the data transmission between memory channel controllers 106-1...106-N and memory devices 108-1...108-N in this way, memory system 102 is able to scale the portion of the total width of the memory bus data transfer used to execute access requests. In some instances, smaller access requests that may not require the total width of the memory bus across all memory channel controllers 106-1...106-N for full execution can be executed using only a portion of the total width of the memory bus across all memory channel controllers 106-1...106-N for the full burst length required for full execution.

[0033] Therefore, the additional capacity of the total width of the memory bus across all memory channel controllers 106-1...106-N (e.g., the unused portion of the total width of the memory bus across all memory channel controllers 106-1...106-N) can be released. This released additional capacity may be unused, thereby reducing power and bandwidth consumption for executing access requests. That is, energy savings can be achieved by keeping only the minimum number of memory bus channels necessary for executing access requests active between the memory channel controllers 106-1...106-N communicating with their respective memory devices 108-1...108-N. Additionally, read-modify-write reduction is possible, and shorter bursts can be utilized on fewer channels than full bursts, allowing for the use of shorter error correction code (ECC) codewords.

[0034] Furthermore, the additional capacity can be used to execute other access requests simultaneously. For example, the freed-up capacity can be used to simultaneously execute additional, smaller access requests that would not require the total width of the memory bus across all memory channel controllers 106-1...106-N during the entire burst length of full execution. By simultaneously executing multiple access requests that were previously executed serially in a manner that would have wasted the total width of the memory bus across all memory channel controllers 106-1...106-N without utilizing full capacity in the burst, latency reduction can be achieved without increasing the I / O switching rate of memory system 102. In fact, in some instances, the I / O switching rate of memory system 102 can be reduced due to reduced power, ECC, and latency requirements of the system, resulting in further power savings.

[0035] As described herein, channelizing access to memory devices 108-1...108-N can restrict the data locations accessible to a particular memory channel controller 106-1...106-N. For example, a first memory channel controller 106-1 may only access a portion of the memory cells of the corresponding first memory device 108-1 of its shared physical memory bus interface. That is, the first memory channel controller 106-1 may only be able to cause successful execution of access requests and / or a portion of access requests relating to access to data stored in the first memory device 108-1 to which the first memory channel controller 106-1 is communicatively coupled. Similarly, the second memory channel controller 106-2 may only be able to successfully execute access requests and / or a portion of access requests relating to accessing data stored in the second memory device 108-2, the third memory channel controller 106-3 may only be able to successfully execute access requests and / or a portion of access requests relating to accessing data stored in the third memory device 108-3, the fourth memory channel controller 106-4 may only be able to successfully execute access requests and / or a portion of access requests relating to accessing data stored in the fourth memory device 108-4, and so on.

[0036] Therefore, as described in more detail below, the way data is stored in memory devices 108-1...108-N can be structured in such a way that various types of access requests can be fully executed in a manner that keeps a minimum number of memory bus channels in operation between memory channel controllers 106-1...106-N that communicate with their respective memory devices 108-1...108-N, and / or allows the simultaneous execution of different access requests and / or portions of access requests. For example, data can be stored according to its type. For example, data can be stored according to the amount of data transfer capacity involved in fully executing an access request involving the type of data. That is, data can be stored based on the size of the burst (e.g., the amount of data transfer capacity) associated with the execution of an access request for the data type. In some instances, controller 104 may be responsible for guiding the storage of data according to this scheme.

[0037] For example, the first type of data may be data associated with a relatively small burst size for executing the corresponding access request. For example, the first type of data may be data associated with a first type of access request that can be fully executed only a portion of the memory channel controllers 106-1...106-N. In some instances, the first type of data may be data associated with a first type of access request that can be fully executed using only a single memory channel controller among the plurality of memory channel controllers 106-1...106-N. For example, the first type of data may be data associated with a first type of access request that can be fully executed only a portion of the full memory bus width allocated to a single memory channel controller among the plurality of memory channel controllers 106-1...106-N. For example, the first type of data may be data associated with a first type of access request that can be fully executed using a 4-byte memory bus transfer capacity. Therefore, an access request associated with the first type of data can be fully executed using a single memory channel controller with a 16-bit memory bus transfer capacity, which will accommodate a data transfer capacity of 32 bytes in the 16 beats of the burst. For example, the first type of data may be logical-to-physical table (L2P) data. For example, the first type of data may include data associated with and / or in response to the execution of an L2P access request.

[0038] The second type of data can be data associated with a relatively moderate burst size (e.g., larger than the first type of data and smaller than the third type of data) that executes the corresponding access request. For example, the second type of data can be data associated with a second type of access request that can be fully executed using a portion of memory channel controllers 106-1...106-N that are larger than the first type and smaller than the third type. In some instances, the second type of data can be data associated with a second type of access request that can be fully executed using two of the plurality of memory channel controllers 106-1...106-N simultaneously. For example, the second type of data can be data associated with a second type of access request that can be fully executed using a portion of the full memory bus width allocated among the two memory channel controllers 106-1...106-N. For example, the second type of data can be data associated with a second type of access request that can be fully executed using two memory channel controllers, each with a 16-bit memory bus transfer capacity, which would accommodate a data transfer capacity of 64 bytes in a burst of 16 beats. For example, the second type of data may be persistent memory buffer (PMR) data. For example, the second type of data may include data associated with and / or in response to the execution of a PMR access request.

[0039] The third type of data can be data associated with a relatively large burst size (e.g., larger than the first type of data and larger than the second type of data) for executing the corresponding access request. For example, the third type of data can be data associated with a third type of access request that can be fully executed using a portion of memory channel controllers 106-1...106-N that are larger than the first type and larger than the second type. In some instances, the third type of data can be data associated with a third type of access request that can be fully executed using four of the plurality of memory channel controllers 106-1...106-N simultaneously. For example, the third type of data can be data associated with a third type of access request that can be fully executed using the full memory bus width allocated among the four memory channel controllers 106-1...106-N. For example, the third type of data can be data associated with a third type of access request that can be fully executed using four memory channel controllers, each with a 16-bit memory bus transfer capacity, which would accommodate 128 bytes of data transfer capacity in 16 beats of a burst. For example, the third type of data could be control memory buffer (CMB) data. For example, the third type of data could include data associated with and / or in response to the execution of a CMB access request.

[0040] Therefore, controller 104 can cause data values ​​of the first data type to be stored in the memory address range of memory devices 108-1...108-N, such that the data of the first type is substantially equally divided in the data channels of memory system 102 (e.g., the data channels are memory channel controllers and their corresponding memory devices). For example, the data values ​​of the first data type can be distributed in all data channels of memory system 102, such that each access request of the first data type can be executed using a single channel and that sequential access requests of the first data type can be executed in parallel using the corresponding data channels to execute each of the sequential access requests simultaneously. That is, the first data type can be stored in the address range distributed in the plurality of memory devices 108-1...108-N, such that multiple access requests involving the first data type can be executed simultaneously by executing each access request using different memory channels.

[0041] Similarly, controller 104 can cause data values ​​of the second data type to be stored in the memory address range of memory devices 108-1...108-N, such that the second type of data is divided substantially equally among the data channels of memory system 102. For example, the data values ​​of the second data type can be distributed across two sets of data channels in memory system 102, such that each access request for the second data type can be executed using multiple data channels constituting a smaller number than the full number of data channels in memory system 102. The second data type can be distributed, for example, across a set of data channels, such that sequential access requests for the second data type can be executed in parallel using the corresponding set of data channels to execute each of the sequential access requests simultaneously. That is, the second data type can be stored in address ranges distributed across the plurality of memory devices 108-1...108-N, such that multiple access requests involving the second data type can be executed simultaneously by executing each access request using different groups of memory channels. For example, if memory system 102 contains four data channels, then its execution of access requests involving access to the second data type can be performed using two of the four data channels. Therefore, the execution of two access requests involving access to the second type of data can be performed simultaneously using two of the four data channels used for each of the access requests.

[0042] The controller 104 can cause data values ​​of the third data type to be stored in the memory address range of memory devices 108-1...108-N, such that the third data type is divided substantially equally across all data channels of the memory system 102. For example, the data values ​​of the third data type can be distributed across each of the data channels of the memory system 102, such that each access request for the third data type can be executed using all data channels constituting the full amount of data channels in the memory system 102. In such instances, because access requests involving third data type can involve utilizing the full memory channel capacity of the memory system 102, the memory system 102 may not be suitable for the simultaneous execution of multiple access requests involving third data type.

[0043] Therefore, controller 104 can queue access requests for execution according to the data storage structure and the memory channel arrangement of memory system 102. For example, controller 104 can organize access requests in the execution queue of each memory channel controller 106-1...106-N according to the data type of the access request and / or the address range in which the data value involved is stored.

[0044] For example, when saving requested data in the address range corresponding to the first memory device 108-1, the controller 104 can queue the access request associated with the first data type for execution in the execution queue of the first memory channel controller 106-1. When saving requested data in the address range corresponding to the second memory device 108-2, the controller can queue the access request associated with the first data type for execution in the execution queue of the second memory channel controller 106-2. When saving requested data in the address range corresponding to the third memory device 108-3, the controller can queue the access request associated with the first data type for execution in the execution queue of the third memory channel controller 106-3. When saving requested data in the address range corresponding to the fourth memory device 108-N, the controller can queue the access request associated with the first data type for execution in the execution queue of the fourth memory channel controller 106-N. The controller 104 can examine the access request to determine its address range. Controller 104 may determine that each of a plurality of access requests associated with a first data type corresponds to a different address range of a different memory device accessed using a different memory channel controller. In such an example, controller 104 may queue the plurality of access requests associated with the first data type for simultaneous execution via each of their corresponding memory channels. Alternatively, controller 104 may determine that each of the plurality of access requests associated with the first data type utilizes the same address range and / or the same corresponding memory device accessed using the same memory channel controller. In such an example, controller 104 may delay or otherwise modify the order of access requests in the execution queue to prevent simultaneous execution of access requests involving conflicting memory channel accesses.

[0045] The controller 104 may queue access requests associated with a second data type for execution in an execution queue of a first set of memory channel controllers (e.g., first memory channel controller 106-1 and second memory channel controller 106-2) when the requested data is stored in an address range corresponding to the corresponding first memory device 108-1 and second memory device 108-2, and / or queue access requests associated with a second data type for execution in an execution queue of a second set of memory channel controllers (e.g., third memory channel controller 106-3 and fourth memory channel controller 106-N) when the requested data is stored in an address range corresponding to the corresponding third memory device 108-3 and fourth memory device 108-N. The controller 104 may examine the access requests to determine their address ranges. The controller 104 may determine that each of the plurality of access requests associated with the second data type corresponds to a different address range of one of the different first and second sets of memory channels associated with the access request for executing the second data type. In such instances, controller 104 may queue the plurality of access requests associated with the second data type for simultaneous execution via each of their corresponding sets of memory channels (e.g., a first access request is executed by a first set of memory channels including first memory channel controller 106-1, first memory device 108-1, second memory channel controller 106-2, and second memory device 108-2, and a second access request is executed by a second set of memory channels including third memory channel controller 106-3, third memory device 108-3, fourth memory channel controller 106-N, and fourth memory device 108-N). Alternatively, controller 104 may determine that each of the plurality of access requests associated with the second data type accesses the same address range and / or the same corresponding memory channel. In such instances, controller 104 may delay or otherwise modify the order of access requests in the execution queue to prevent simultaneous execution of access requests involving conflicting sets of memory channel access.

[0046] Controller 104 may also queue various combinations of access requests of different data types for simultaneous execution. A non-limiting example may include controller 104 queuing, where the corresponding memory address range allows, a first access request of a first data type for execution by a first memory channel (e.g., memory channel controller 106-1 and memory device 108-1), a second access request of the first data type for simultaneous execution by a second memory channel (e.g., memory channel controller 106-2 and memory device 108-2) with the first access request, and a third access request of the second data type for simultaneous execution by a third set of memory channels (e.g., memory channel controllers 106-3 and 106-N and memory channel devices 108-3...108-N) with the first and second access requests.

[0047] Controller 104 can queue access requests associated with the third data type for execution in the execution queues of all memory channel controllers 106-1...106-N. That is, since access requests associated with the third data type can utilize the entire width of the memory bus to be successfully executed during a burst, it may be necessary to utilize all memory channels simultaneously to execute the access request. While access requests for the third data type are being executed, access requests for the first and second data types may not be executed simultaneously because access requests for the third data type consume the entire bandwidth of the memory bus across all memory channel controllers 106-1...106-N during a burst.

[0048] Controller 104 may additionally queue access requests for execution based on the priority associated with the access request. For example, controller 104 may queue access requests such that a data-associated access request with a relatively higher priority may be executed before a data-associated access request with a relatively lower priority. Additionally, controller 104 may queue access requests such that a data-associated access request received from host 110 with a relatively higher priority may be executed before a data-associated access request received from the host with a relatively lower priority.

[0049] In one example, the operation of computing system 100 may involve the transfer of access requests from host 110 to memory system 102 via a host bus. Access requests may be received by controller 104. The controller may analyze the access requests to identify various characteristics of the access requests for use in queuing the access requests for execution.

[0050] For example, controller 104 may determine the priority of host 110 associated with the access request. Controller 104 may determine the data type associated with the access request. In some instances, controller 104 may determine the data type associated with the access request based on the size of the burst associated with the execution of the access request. For example, controller 104 may determine the data type associated with the access request based on the minimum size of the burst sufficient to fully execute the access request, said minimum size may be based on the amount of data to be accessed and / or transferred across the memory bus to execute the access request. Controller 104 may also determine the priority associated with the data type associated with the access request. Controller 104 may determine the memory address range of the data that the access request attempts to access.

[0051] The controller 104 can queue access requests such that, in response to determining that an access request is associated with data of a first type, the access request is executed using a first memory channel controller coupled to the first memory device to access a first memory address range allocated to the first memory device and associated with the first data type.

[0052] The controller 104 can queue access requests such that, in response to determining that an access request is associated with a second type of data, the access request is executed using a first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range allocated in the first memory device and the second memory device that is associated with the second data type.

[0053] The controller 104 can queue access requests such that, in response to determining that an access request is associated with a third type of data, the access request is executed using the first memory channel controller, the second memory channel controller, and the third memory channel controller coupled to the third memory channel device to access a second memory address range allocated in the first memory device, the second memory device, and the third memory device that is associated with the third data type.

[0054] Controller 104 can queue access requests and other access requests so that they can be executed simultaneously in parallel. That is, an access request can be queued so that it is executed as the first part of a burst, and another access request can be queued so that it is executed as the second part of the same burst. For example, as described above, access requests associated with different data types may require different amounts of memory bus capacity to be fully executed within a burst of, for example, sixteen clock cycles. In some instances, less than the full capacity of the memory bus can be used to fully execute some access requests. In the above examples, where access requests and other access requests can be executed within the same burst by simultaneously utilizing corresponding portions of the memory bus capacity allocated in the aforementioned memory channels, controller 104 can queue these access requests for simultaneous execution within the same burst using different memory channels. For example, an access request can be executed as the first part of a burst consisting of the data transfer capacity of one or more first memory channel controllers, and another access request can be executed as the second part of a burst consisting of the data transfer capacity of one or more second memory channel controllers.

[0055] However, controller 104 can queue access requests that would otherwise utilize less than the full capacity of the memory bus to be executed fully when those access requests have conflicting memory address ranges. For example, if an access request and another access request can both be within the full capacity of the memory bus allocated in a memory channel, but their address ranges map to the same or conflicting memory channels (e.g., both involving access to data values ​​in memory address ranges mapped to the same memory device or set of memory devices), then controller 104 can queue one access request to be executed later than the other. In some instances, the first access request to be executed among conflicting access requests can be determined based on associated priority assignments (e.g., for the source host, for the data type, etc.).

[0056] Figure 2 This is a block diagram of memory channels 212-1...212-N within a memory system according to embodiments of the present disclosure. In some instances, the memory system may be similar to... Figure 1 The memory system 102 in the middle.

[0057] Each memory channel 212-1...212-N includes a memory channel controller 206-1...206-N and a corresponding memory device 208-1...208-N. The memory device 208-1...208-N may include a DRAM memory device. The memory device 208-1...208-N may represent the DRAM storage capacity of the memory system. Data values ​​for the memory system may be stored in the memory device 208-1...208-N. The memory channel controller 206-1...206-N may include individual controllers, each controller being communicatively coupled to its corresponding memory device 208-1...208-N.

[0058] Individual memory channels among the plurality of memory channels 212-1...212-N can operate independently of the other channels. For example, the first memory channel 212-1 can operate independently of the second, third, and fourth memory channels 212-2...212-N. That is, the first memory channel 212-1 can be used to execute access requests separately from the second, third, and fourth memory channels 212-2...212-N during the same burst. Therefore, the first memory channel controller 206-1 can operate independently of the second, third, and fourth memory channel controllers 206-2...206-N. For example, the first memory channel controller 206-1 can execute access requests during a burst, while the second, third, and / or fourth memory channel controllers 206-2...206-N can independently execute different access requests during the burst.

[0059] Furthermore, the set of multiple memory channels 212-1...212-N can operate independently of other sets of memory channels. For example, a first set of memory channels, including the first memory channel 212-1 and the second memory channel 212-2, can operate independently of a second set of memory channels, including the third memory channel 212-3 and the fourth memory channel 212-N, during a burst. That is, the first memory channel controller 206-1 and the second memory channel controller 206-2 can operate as a group to cooperate in executing access requests during a burst, while the third memory channel controller 206-3 and the fourth memory channel controller 206-N can operate as a group to cooperate in executing different access requests independently of the first memory channel controller 206-1 and the second memory channel controller 206-2 during the burst.

[0060] Furthermore, the plurality of memory channels 212-1...212-N can operate cooperatively. That is, the first memory channel 212-1, the second memory channel 212-2, the third memory channel 212-3, and the fourth memory channel 212-N can be used in parallel during a burst to cooperatively execute access requests. Therefore, the first memory channel controller 206-1, the second memory channel controller 206-2, the third memory channel controller 206-3, and the fourth memory channel controller 206-N can operate in parallel during a burst to cooperatively execute access requests.

[0061] Each of the memory devices 208-1...208-N may include one or more memory devices. Each of the memory devices 208-1...208-N may store data values ​​in memory cells located within a memory array. Data values ​​may be stored in memory cells identified by and / or addressable by a memory address range. Specific memory address ranges may be assigned to specific memory devices 208-1...208-N. Therefore, specific memory address ranges may be assigned to specific memory channels 212-1...212-N.

[0062] In some instances, specific memory address ranges can be reserved for specific types of data. That is, specific memory address ranges can be specified to store specific types of data. Therefore, specific types of data can be stored in specific memory channels 212-1...212-N at specific memory devices 208-1...208-N. As described above, data channelization can be achieved by allowing access requests to be executed in parallel through independent operations of selective memory channels 212-1...212-N and / or a set thereof, thereby reducing power consumption, ECC codeword length, and latency.

[0063] As described above, different types of data associated with access requests can be categorized based on the minimum amount of data transfer capacity consumed in fully executing the access request. For example, a first data type may include short access data types that can be executed in a burst using a minimum of a single memory channel 212-1. A second data type may include intermediate access data types that can be executed cooperatively in a burst using a minimum pair of memory channels 212-1 and 212-2. A third data type may include long access data types that can be executed cooperatively in a burst using a minimum of all four memory channels 212-1...212-N.

[0064] Therefore, the first, second, and third types of data can be distributed accordingly in memory channels 212-1...212-N. In some instances, the data can be distributed vertically in memory channels 212-1...212-N.

[0065] For example, multiple memory address ranges can be reserved for data of the first data type. For example, multiple memory address ranges including a first memory address range 218-1, a second memory address range 218-2, a third memory address range 218-3, and / or a fourth memory address range 218-4 can be reserved from the data of the first data type. The multiple first data type memory address ranges 218-1...218-4 can be vertically allocated among the first memory device 208-1 of the first memory channel 212-1, the second memory device 208-2 of the second memory channel 212-2, the third memory device 208-3 of the third memory channel 212-3, and the fourth memory device 208-N of the fourth memory channel 212-N. Vertical storage can refer to the distribution of the first data type memory address range 218-1...218-4 in substantially equal portions across four memory channels 212-1...212-N, in a manner that allows independent access to each portion of the first data type memory address range 218-1...218-4 to execute corresponding access requests via their respective memory channel controllers 206-1...206-N. For example, if the first type of data constitutes 7,760 MB of data, then the first data type memory address range 218-1...218-N can be divided into four 1,940 MB portions of the first data type, where each equal portion is allocated to a separate memory channel having a separate and independently operable memory channel controller and memory device. Therefore, each portion of the plurality of first data type memory address ranges 218-1...218-4 can be individually and separately accessed by its corresponding memory channel controller 206-1...206-N to execute access requests associated with the first data type. Furthermore, each portion of the plurality of first data type memory address ranges 218-1...218-4 can be accessed individually and separately by its corresponding memory channel controllers 206-1...206-N to simultaneously execute multiple access requests associated with the first data type, provided that those multiple access requests are located within different portions of memory address ranges in different memory channels.

[0066] That is, data of the first data type can be stored across four distinct address ranges (e.g., 218-1, 218-, 218-3, and 218-4), and each of the address ranges can be confined to a corresponding memory channel (e.g., 212-1, 212-2, 212-3, and 212-N). The four distinct address ranges (e.g., 218-1, 218-, 218-3, and 218-4) can be processed differently for accessing the data stored therein. For example, access requests for data stored in the first data range 218-1, access requests for data stored in the second data range 218-2, access requests for data stored in the third data range 218-3, and / or access requests for data stored in the fourth data range 218-N can be executed independently and simultaneously via their respective memory channel controllers (206-1, 206-2, 206-3, and 206-N), as if each memory channel 212-1...212-N were independently addressable and separate memory systems, although they were merely logical segments of the same memory system that were independently addressable via their respective memory channel controllers.

[0067] In some instances, data can be distributed vertically and horizontally across memory channels 212-1...212-N. For example, multiple memory address ranges can be reserved for data of the second data type. For example, multiple memory address ranges including a first memory address range 216-1 and a second memory address range 216-2 can be reserved from the second data type. The multiple second data type memory address ranges 216-1...216-2 can be vertically allocated in a pair of memory channels among the four memory channels 212-1...212-N. In some instances, the second data type can contain 32MB of data. The 32MB of data can be distributed vertically and horizontally into equal 8MB blocks of data distributed across the four memory channels 212-1...212-N. The plurality of second data type memory address ranges 216-1...216-2 can be vertically allocated in two sets of memory channels (e.g., a first vertical group comprising memory channels 212-1 and 212-2, and a second vertical group comprising memory channels 212-3 and 212-N). Therefore, the plurality of second data type memory address ranges 216-1...216-2 can be allocated in two vertical groups. The first vertical group may contain second data type memory address ranges 216-1 horizontally distributed across memory channels 212-1 and 212-3. The second vertical group may contain second data type memory address ranges 216-2 horizontally distributed across memory channels 212-1 and 212-3. Again, vertical storage can refer to storing each vertical group containing second type data in substantially equal portions of the memory channels of the vertical group in a manner that allows independent access to each vertical group to execute corresponding independent access requests via its corresponding memory channel controller. Horizontal storage of second-type data spanning memory channels of a vertical group can refer to storing second-type data within a vertical group in a manner that allows two portions within the vertical group to be cooperatively accessed by their respective memory channel controllers to collaboratively execute the same access request, across substantially equal portions of the two memory channels constituting the vertical group. For example, data in memory channel 212-1 of the second-type data memory address range 216-1 can be accessed by memory channel controller 206-1, while data in memory channel 212-2 of the second-type data memory address range 216-1 is accessed by memory channel controller 206-2 to collaboratively execute the access request. Similarly, data in memory channel 212-3 of the second-type data memory address range 216-2 can be accessed by memory channel controller 206-3, while data in memory channel 212-N of the second-type data memory address range 216-2 is accessed by memory channel controller 206-N to collaboratively execute the access request.Furthermore, the second data type memory address range 216-1 of the first vertical memory channel group (212-1 and 212-2) and the second data type memory address range 216-2 of the second vertical memory channel group (212-3 and 212-N) can be accessed simultaneously and independently to execute multiple disparate access requests associated with the second data type, provided that those multiple access requests are located within disparate portions of the memory address ranges in disparate memory channel vertical groups.

[0068] That is, data of the second data type can be stored across two distinct address ranges (e.g., 216-1 and 216-2), and each of the address ranges can be confined within a corresponding set of memory channels (e.g., the first set 212-1 and 212-2, and the second set 212-3 and 212-N). The two distinct address ranges (e.g., 216-1 and 216-N) can be processed differently for accessing the data stored therein. For example, access requests for data stored in the first data range 216-1 and / or for data stored in the second data range 216-2 can be executed independently and simultaneously via their respective groups of memory channel controllers (e.g., first groups 206-1 and 206-2, second groups 206-3 and 206-N), as if each group of memory channels (e.g., first groups 212-1 and 212-2, second groups 212-3 and 212-N) were independently addressable and separate memory systems, although they were merely logical segments of the same memory system that were independently addressable via their respective groups of memory channel controllers.

[0069] A memory address range can be reserved for third data types. For example, a single memory address range such as memory address range 214-1 can be reserved for third data types. In some instances, the third data type may contain 400MB of data. The 400MB of data can be horizontally distributed into equal 100MB blocks of data distributed across four memory channels 212-1...212-N. Therefore, in a manner that allows all third data types stored within the third data type memory address range 214-1 distributed across all four memory channels 212-1...212-N to be cooperatively accessed by their respective memory channel controllers to cooperatively execute the same access request, the third data type can be equally allocated within the third data type memory address range 214-1 across the four memory channels 212-1...212-N. For example, data of the third data type stored in the first channel 212-1 within the third data type memory address range 214-1 can be accessed by the memory channel controller 206-1, while data of the third data type stored in the second channel 212-2 within the third data type memory address range 214-1 can be accessed by the memory channel controller 206-2, while data of the third data type stored in the third channel 212-1 within the third data type memory address range 214-1 can be accessed by the memory channel controller 206-3, and data of the third data type stored in the fourth channel 212-N within the third data type memory address range 214-1 can be accessed by the memory channel controller 206-N, so as to cooperatively execute access requests for third data of the third type that can be stored in one or more of the channels constituting the third data type memory address range 214-1 and / or stored across one or more of the channels.

[0070] That is, the third type of data can be stored across a single address range spanning all of the plurality of memory channels 212-1...212-N within the third data type memory address range 214-1. When an access request for accessing third data type data is received, all four memory channel controllers 206-1...206-N can be operated cooperatively to cooperatively provide access to the requested data, which may be located in one or more of the channels constituting the third data type memory address range 214-1 and / or across one or more locations in the channels.

[0071] In summary, Figure 2The memory system includes a first memory controller 206-1 coupled to a first memory device 208-1. A first memory address range 218-1 reserved for a first part of a first data type (e.g., data values ​​of the first data type stored vertically and mapped to the first data type memory address range 218-1 of the first memory device 208-1) is allocated to the first memory device 208-1. That is, the first part of the first data type is data stored vertically in the first data type memory address range 218-1 of the first memory device 208-1, the second part of the first data type will be data stored vertically in the first data type memory address range 218-2 of the second memory device 208-2, the third part of the first data type will be data stored vertically in the first data type memory address range 218-3 of the third memory device 208-3 (e.g., the sixth memory address range), and the fourth part of the first data type will be data stored vertically in the first data type memory address range 218-N of the fourth memory device 208-N (e.g., the seventh memory address range).

[0072] Additionally, the memory system includes a second memory controller 206-2 coupled to the second memory device 208-2. A second memory address range 216-1 is reserved for a first portion of the second data type (e.g., the data value of the second data type is vertically stored and mapped within the second memory address range 216-1 within the first memory channel 212-1 in the first memory device 208-1 and the second memory channel 212-2 in the second memory device 208-2) and allocated in the first memory device 208-1 and the second memory device 208-N. The memory system also includes a third memory address range 218-2 allocated to the second memory device 208-2 for a second portion of the first data type (e.g., the data value of the first data type is vertically stored and mapped to the first data type memory address range 218-2 in the second memory device 208-2). That is, the first part of the second data type is the data stored in the memory address range 216-1 of the second data type, which spans the first memory device 208-1 and the second memory device 208-2, while the second part of the second data type will be the data stored in the memory address range 216-2 of the second data type (e.g., the fifth memory address range), which spans the third memory device 208-3 and the fourth memory device 208-N.

[0073] Furthermore, the memory system includes a third memory controller 206-3 coupled to a third memory device 208-3 and a fourth memory controller 206-N coupled to a fourth memory device 208-N. The fourth memory address range 214-1 is reserved for a third data type and allocated among the first memory device 208-1, the second memory device 208-2, the third memory device 208-3, and the fourth memory device 208-N.

[0074] Although Figure 2 As not shown, the memory system may include a memory manager. (See also: Regarding...) Figure 1 As described, the memory manager may include a controller (e.g., controller 104) and / or instructions executable by the controller to perform access requests consistent with embodiments of this disclosure. The memory manager may, for example, determine a memory address range associated with a first access request and a memory address range associated with a second access request. The memory manager may utilize a first memory channel controller 206-1 and a second memory channel controller 206-2 to execute the first access request in response to the determination that the first access request is associated with a second memory address range 216-1. Alternatively, the memory manager may utilize the first memory controller 206-1 to execute the first access request in response to the determination that the first access request is associated with a first memory address range 218-1. Alternatively, the memory manager may utilize the second memory controller 206-2 in parallel with the execution of the first access request using the first memory controller 206-1, in response to the determination that the first access request is associated with a first memory address range 218-1 and the determination that the second access request is associated with a third memory address range 218-2.

[0075] In some instances, the first data type may contain L2P table data, the second data type may contain PMR data, and the third data type may contain CMB data. Furthermore, the memory manager can be configured to assign and / or modify the execution priority of each access request based on these data types. For example, the memory manager may assign a higher execution priority to controller memory buffer (CMB) access requests and persistent memory area (PMR) access requests in the access request execution queue than to logical-to-physical (L2P) access requests.

[0076] Figure 3 This is a block diagram illustrating the execution of multiple L2P access requests 320-1...320-N using multiple memory channels 312-1...312-N within a memory system according to embodiments of the present disclosure.

[0077] exist Figure 3In this system, the memory manager or controller may receive multiple access requests 320-1...320-N from a communicatively coupled host. The memory manager may determine the client and / or data type associated with each of the multiple access requests 320-1...320-N. That is, the memory manager may determine the type of data requested by each access request. Figure 3 In the example described, the memory manager can determine that the plurality of access requests are a plurality of L2P access requests 320-1...320-N. One of the four octet-wide memory channels can be used to execute the L2P access request.

[0078] The memory manager can queue the plurality of L2P access requests 320-1...320-N for execution by the plurality of memory channels 312-1...312-N of the memory system. The memory manager can determine whether any of the plurality of L2P access requests 320-1...320-N is attempting to access an L2P data entry in the same memory channel 312-1...312-N. If the memory manager determines that any of the plurality of L2P access requests 320-1...320-N is attempting to access an L2P data entry in the same memory channel 312-1...312-N, then the memory manager can selectively delay the execution of some of the L2P access requests to eliminate any conflicts. However, when the memory manager determines that none of the plurality of L2P access requests 320-1...320-N are attempting to access L2P data entries in the same memory channel 312-1...312-N, the memory manager may queue each of the plurality of L2P access requests 320-1...320-N in a separate memory channel 312-1...312-N for concurrent execution of the plurality of L2P access requests 320-1...320-N in the same burst.

[0079] For example, the memory manager can cause the first memory channel controller 306-1 to execute a first L2P access request 320-1 by accessing the requested L2P data in the L2P type memory address range 318-1 of the first memory device 308-1. The memory manager can simultaneously execute the first L2P access request 320-1 and access the requested L2P data in the L2P type memory address range 318-2 of the second memory device 308-2, thereby causing the second memory channel controller 306-2 to execute a second L2P access request 320-2. The memory manager can simultaneously execute the first L2P access request 320-1 and the second L2P access request 320-3 and access the requested L2P data in the L2P memory address range 318-3 of the third memory device 308-N, thereby causing the third memory channel controller 306-3 to execute a third L2P access request 320-3. The memory manager can cause the fourth memory channel controller 306-N to execute the fourth L2P access request 320-N by accessing the requested L2P data in the L2P memory address range 318-N in the fourth memory device 308-N while executing the first L2P access request 320-1, the second L2P access request 320-2, and the third L2P access request 320-3.

[0080] Figure 4 This is a block diagram illustrating the execution of multiple PMR access requests 422-1...422-N using multiple memory channels 412-1...412-N within a memory system according to embodiments of the present disclosure.

[0081] exist Figure 4 In this system, the memory manager or controller may receive multiple access requests 422-1...422-N from a communicatively coupled host. The memory manager may determine the data type associated with each of the multiple access requests 422-1...422-N. That is, the memory manager may determine the type of data requested by each access request. Figure 4 In the example described, the memory manager can determine that the plurality of access requests are a plurality of PMR access requests 422-1...422-N. The PMR access request can be executed using one of two 16-bit wide memory channels (e.g., composed of the cooperative operation of two 8-bit wide memory channels).

[0082] The memory manager can queue the plurality of PMR access requests 422-1...422-N for execution by the plurality of memory channels 412-1...412-N of the memory system. The PMR type memory address range 416-1...416-2 can be accessed as two separate groups of memory channels. The first group may include the first memory channel 412-1 and the second memory channel 412-2, while the second group may include the third memory channel 406-3 and the fourth memory channel 406-N. The memory manager can determine whether any of the plurality of PMR access requests 422-1…422-N is attempting to access a PMR data entry in the same group of memory channels (e.g., PMR access requests 422-1 and 422-N both involve accessing data in the same group of memory channels). If the memory manager determines that any one of the plurality of PMR access requests 422-1…422-N is attempting to access a PMR data entry in the same set of memory channels 412-1…412-N, the memory manager may selectively delay the execution of some of the PMR access requests 422-1…422-N to eliminate any conflicts. However, when the memory manager determines that none of the PMR access requests 422-1…422-N are attempting to access a PMR data entry in the same set of memory channels 412-1…412-N, the memory manager may queue each of the plurality of PMR access requests 422-1…422-N in a separate set of memory channels for concurrent execution of the PMR access requests 422-1…422-N in the same burst.

[0083] For example, the memory manager can cause the first memory channel controller 406-1 and the second memory channel controller 406-2 to cooperate in executing the first PMR access request 422-1 by accessing the requested PMR data in the PMR memory address range 416-1 in the first memory device 408-1 and the second memory device 408-2.

[0084] The memory manager can cause the third memory channel controller 406-3 and the fourth memory channel controller 406-N to execute the second PMR access request 422-N by simultaneously accessing the requested PMR data in the memory address range 416 in the third memory device 408-3 and the fourth memory device 408-N during the execution of the first PMR access request 422-1.

[0085] Although Figure 3 and Figure 4This describes an example of the execution of multiple access requests of the same type within the same burst, but other embodiments are contemplated within the scope of this disclosure. For example, a memory manager may cause access requests of different data types to be executed simultaneously within the same burst. For example, a memory manager may cause one or two L2P access requests and PMR access requests to be executed simultaneously within the same burst.

[0086] Figure 5 This is a block diagram of CMB access requests 524-1 utilizing multiple memory channels 512-1...512-N within a memory system according to an embodiment of the present disclosure.

[0087] exist Figure 5 In this context, the memory manager or controller of the memory system can receive access request 524-1 from a host that is communicatively coupled to it. The memory manager can determine the data type associated with access request 524-1. That is, the memory manager can determine the type of data that the access request is requesting. Figure 5 In the example described, the memory manager can determine that the access request is a CMB 524-1 access request. The CMB access request can be executed using a 32-bit wide memory channel (e.g., composed of the cooperative operation of four 8-bit wide memory channels).

[0088] The memory manager can queue CMB access requests 524-1 for execution by the plurality of memory channels 512-1...512-N of the memory system. The CMB type memory address range 514-1 can be accessed as a single group of memory channels 512-...512-N. The memory manager can queue the first CMB access request 524-1 for cooperative execution in parallel across memory channels 512-1...512-N during the same burst.

[0089] For example, the memory manager can access the CMB data in the memory address range 514-1 of the first memory device 508-1, the memory address range 514-1 of the second memory device 508-2, the memory address range 514-1 of the third memory device 508-3, and the memory address range 514-1 of the fourth memory device 508-4, thereby causing the first memory channel controller 506-1, the second memory channel controller 506-2, the third memory channel controller 506-3, and the fourth memory channel controller 506-N to cooperate in executing the first CMB access request 524-1.

[0090] Other anticipated instances may involve the memory manager causing the first memory channel controller 506-1, the second memory channel controller 506-2, and the third memory channel controller 506-3 to collaboratively execute a first CMB access request 524-1 by accessing CMB data in memory address range 514-1 of the first memory device 508-1, the second memory channel controller 508-2, and the third memory device 508-3. In such instances, an L2P access request may be executed simultaneously in the same burst using a fourth memory channel 512-N that is still unused by the CMB access request.

[0091] Figure 6 This is a block diagram of a method 630 for executing an access request according to an embodiment of the present disclosure. At 632, method 630 includes determining the data type associated with the access request. For example, an access request may be received from a host across a host interface of a memory system. The memory system may include DRAM memory devices incorporated on integrated circuits of a computing device.

[0092] An access request may contain a request to access a data value stored on a specific memory device. An access request can specify the data value it is requesting to access by identifying a memory address range. As described above, the data type associated with the access request can be determined from the access request. For example, the type of data associated with the access request can be determined based on the size of the burst associated with the execution of the access request. For example, a short access request may contain a relatively small data transfer capacity requirement executed during the burst, a medium access request may contain a relatively medium data transfer capacity requirement executed during the burst, and a long access request may contain a relatively large data transfer capacity requirement executed during the burst. Short access requests may be associated with a first data type, medium access requests may be associated with a second data type, and long access requests may be associated with a third data type.

[0093] The first data type may include the L2P table data type, which can be executed during a burst using a single 4-bit wide memory channel. The second data type may include the PMR data type, which can be executed during a burst using a pair of single 4-bit wide memory channels operating as a single 8-bit wide memory channel. The third data type may include the CMB data type, which can be executed during a burst using four single 4-bit wide memory channels operating as a single 32-bit wide memory channel.

[0094] Access requests can be queued for execution. Access requests can be placed in the execution queue at a position selected based on the priority assigned to the client issuing the access request. Alternatively, access requests can be placed in the execution queue at a position selected based on the memory address range specified in the access request.

[0095] In 634, method 630 may include executing an access request. For example, in response to determining that an access request is associated with a first data type, the access request may be executed using a first memory channel controller. The first memory channel controller may be coupled to a first memory device. The first memory channel controller may execute the access request by accessing a first memory address range. The first memory address range may be a range of memory addresses allocated to the first memory device. The first memory address range may be associated with a first data type.

[0096] In 636, method 630 may include performing the access request in an alternative manner. For example, in response to determining that an access request is associated with a second data type, the access request may be performed using a first memory channel controller and a second memory channel controller. The second memory channel controller may be coupled to a second memory device. The second memory channel device may perform the access request by accessing a second memory address range. The second memory address range may be allocated in the first memory device and the second memory device. The second memory address range may be associated with a second data type.

[0097] Alternatively, in response to determining that an access request is associated with a third data type, a first memory channel controller, a second memory channel controller, and a third memory channel controller coupled to a third memory channel device, the access request may be utilized. The first, second, and third memory controllers may be used to access a second memory address range allocated in the first, second, and third memory devices that is associated with the third data type.

[0098] Additionally, another access request can be executed concurrently with the aforementioned access request. For example, an access request can be executed as the first part of a burst, and another access request can be executed as the second part of a burst. However, since both the address range of the access request and the address range of the other access request are allocated to the first memory device, the access request can be queued to be executed after the other access request.

[0099] While specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of one or more embodiments of this disclosure. It should be understood that the above description has been carried out illustratively and not restrictively. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon review of the above description. The scope of one or more embodiments of this disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims together with the full scope of the equivalents given by such claims.

[0100] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is, in itself, a separate embodiment.

Claims

1. A method for performing memory operations, comprising: The data type associated with the access request is determined based on the size of the burst associated with the execution of the access request; The access request is executed by using a first memory channel controller coupled to the first memory device to access a first portion of a first memory address range associated with the first data type in response to determining that the access request is associated with a first data type. as well as The access request is executed by utilizing the first memory channel controller and the second memory channel controller coupled to the second memory device to access a second memory address range allocated in the first memory device and the second memory device that is associated with the second data type in response to determining that the access request is associated with the second data type.

2. The method according to claim 1, further comprising: The access request is executed by utilizing the first memory channel controller, the second memory channel controller, and the third memory channel controller coupled to the third memory device to access a third memory address range allocated in the first memory device, the second memory device, and the third memory device in response to determining that the access request is associated with a third data type.

3. The method according to claim 1, wherein the method further comprises: Another access request is executed in parallel with the access request, wherein the access request is executed as the first part of the burst and the other access request is executed as the second part of the burst.

4. The method according to claim 1, wherein the method further comprises: The execution of the access request is queued based on the priority assigned to the client that issued the access request.

5. The method according to claim 1, wherein the method further comprises: The execution of the access request is queued based on the address range specified in the access request.

6. The method according to claim 5, wherein the method further comprises: In response to the address range of the access request and the address range of another access request being allocated to the first memory device, the execution of the access request is queued to be performed after the other access request.

7. A memory device comprising: A first memory controller coupled to a first memory device, wherein a first memory address range reserved for a portion of a first data type is allocated to the first memory device; A second memory controller is coupled to a second memory device, wherein a second memory address range reserved for a portion of a second data type is allocated in the first memory device and the second memory device; as well as The memory manager is configured to: The data type associated with the access request is determined based on the size of the burst associated with the execution of the access request; The access request is executed using the first memory controller in response to the determination that the access request is associated with the first data type and in response to the determination that another access request to be executed in parallel with the access request is not for the first memory address range. as well as The access request is executed using the first memory controller and the second memory controller in response to the determination that the access request is associated with the second data type.

8. The memory device of claim 7, further comprising: A third memory controller is coupled to a third memory device, wherein a third memory address range reserved for a portion of a third data type is allocated among the first memory device, the second memory device, and the third memory device.

9. The memory device of claim 8, wherein the memory manager is configured to: The access request is executed using the first memory controller, the second memory controller, and the third memory controller in response to the determination that the access request is associated with the third data type.

10. The memory device of claim 8, wherein the third data type is a controller memory buffer (CMB) access request.

11. The memory device of claim 10, wherein the CMB access request is executed individually in a burst via a 32-bit wide memory channel.

12. The memory device of claim 7, wherein the first data type is a logical-to-physical L2P access request.

13. The memory device of claim 12, wherein the L2P access request is executed concurrently with three other L2P access requests in a single burst, each L2P access request utilizing one of four octet-wide memory channels.

14. The memory device of claim 7, wherein the second data type is a persistent memory area (PMR) access request.

15. The memory device of claim 14, wherein the PMR access request is executed concurrently with another PMR access request in a single burst, each PMR access request utilizing one of two sixteen-bit wide memory channels.

16. A memory system comprising: A first memory controller coupled to a first memory device, wherein a first memory address range reserved for a first portion of a first data type is allocated to the first memory device; A second memory controller, coupled to a second memory device, wherein: The second memory address range reserved for the first part of the second data type is allocated in both the first memory device and the second memory device, and The third memory address range reserved for the second part of the first data type is allocated to the second memory device; and The memory manager is configured to: The data type associated with the first access request is determined based on the size of the burst associated with the execution of the first access request; The data type associated with the second access request is determined based on the size of the burst associated with the execution of the second access request; The memory address range associated with the first access request is determined based on the data type associated with the first access request; The memory address range associated with the second access request is determined based on the data type associated with the second access request; The first access request is executed using the first memory controller and the second memory controller in response to the determination that the first access request is associated with the second memory address range; Execute the first access request using the first memory controller in response to the determination that the first access request is associated with the first memory address range; and In response to the determination that the first access request is associated with the first memory address range and the determination that the second access request is associated with the third memory address range, the second access request is executed using the second memory controller in parallel with the execution of the first access request using the first memory controller.

17. The memory system of claim 16, further comprising: A third memory controller, which is coupled to a third memory device; as well as A fourth memory controller, coupled to a fourth memory device, wherein a fourth memory address range reserved for a third data type is allocated among the first memory device, the second memory device, the third memory device, and the fourth memory device.

18. The memory system according to claim 17, wherein: The fifth memory address range reserved for the second part of the second data type is allocated in the third memory device and the fourth memory device. The sixth memory address range reserved for the third part of the first data type is allocated to the third memory device, and The seventh memory address range reserved for the fourth part of the first data type is allocated to the fourth memory device.

19. The memory system of claim 16, wherein the memory manager is configured to assign execution priority to controller memory buffer (CMB) access requests and persistent memory region (PMR) access requests in the access request execution queue to a higher priority than to logic-to-physical (L2P) access requests.

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