Driving circuit, method for generating target voltage signal, and display device

Abstract

The present application provides a driving circuit and a method for generating a target voltage signal, and a display device, which relate to the field of display technology, and include: a power supply unit; a target voltage signal generating unit in a power chip; a control unit and a pulse signal generating unit in a driving core; the control unit outputs a first control instruction; the pulse signal generating unit generates a pulse signal according to the first control instruction; and also includes an enable signal generating unit, which generates an enable signal according to the first control instruction; at least one of the pulse signal generating unit and the enable signal generating unit is electrically connected to the target voltage signal generating unit; the target voltage signal generating unit generates a target voltage signal under the control of the enable signal or the pulse signal, and transmits it to the driving chip. The driving circuit can reduce the load and improve the working efficiency of the driving chip.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit, a method for generating a target voltage signal, and a display device. Background Art

[0002] In the related art, a charge pump is provided in a display driver IC (DDIC), which can increase or decrease the input voltage and can also be used to generate a negative voltage. The display driver chip can be electrically connected to a shift register circuit, and a low level signal (VGL) is generated by the charge pump and transmitted to the shift register circuit.

[0003] However, as the performance requirements of display products gradually increase, the load of the display driver chip gradually increases. Directly providing a low-level signal (VGL) to the shift register circuit through the display driver chip will further increase the load of the display driver chip and reduce the working efficiency of the display driver chip. Summary of the invention

[0004] The present application provides a driving circuit, a method for generating a target voltage signal, and a display device. The driving circuit can reduce the load and improve the working efficiency of the driving chip.

[0005] The embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a driving circuit, including:

[0007] A power supply unit, configured to provide power to the driving circuit;

[0008] A power chip, electrically connected to the power supply unit, comprising a target voltage signal generating unit;

[0009] A driving chip, electrically connected to the power chip, comprising an electrically connected control unit and a pulse signal generating unit; the control unit is configured to output a first control instruction; the pulse signal generating unit is configured to generate a pulse signal according to the first control instruction;

[0010] Among them, the driving circuit also includes an enable signal generating unit, which is configured to generate an enable signal; at least one of the pulse signal generating unit and the enable signal generating unit is electrically connected to the target voltage signal generating unit; the target voltage signal generating unit is configured to generate the target voltage signal under the control of the enable signal or the pulse signal, and transmit the target voltage signal to the driving chip.

[0011] In some embodiments of the present application, the driver chip includes the enable signal generating unit;

[0012] Alternatively, the driving circuit further includes a terminal control chip, and the terminal control chip includes the enable signal generating unit.

[0013] In some embodiments of the present application, the pulse signal generating unit is electrically connected to the target voltage signal generating unit; and the pulse signal is configured to be able to control the target voltage signal generating unit to output the target voltage signal.

[0014] In some embodiments of the present application, the enable signal generating unit is electrically connected to the target voltage signal generating unit; and the enable signal is configured to be able to control the target voltage signal generating unit to output the target voltage signal.

[0015] In some embodiments of the present application, the pulse signal generating unit and the enable signal generating unit are electrically connected to the target voltage signal generating unit, respectively; the prior signal between the pulse signal and the enable signal is configured to be able to control the target voltage signal generating unit to output the target voltage signal.

[0016] In some embodiments of the present application, when the pulse signal generating unit and the enable signal generating unit are both in a power-off state, the target voltage signal generating unit stops outputting the target voltage signal;

[0017] When at least one of the pulse signal generating unit and the enable signal generating unit is in a powered-on state, the target voltage signal generating unit continuously outputs the target voltage signal.

[0018] In some embodiments of the present application, the target voltage signal generating unit includes a controller and a converter electrically connected, the pulse signal generating unit and the enable signal generating unit are electrically connected to the controller respectively, and the power supply unit is electrically connected to the converter;

[0019] In the case where the pulse signal is a prior signal, the controller is configured to convert the pulse signal into a second control instruction, wherein the second control instruction is configured to control the converter to generate the target voltage signal;

[0020] In the case where the enable signal is a prior signal, the controller is configured to convert the enable signal into a third control instruction, and the third control instruction is configured to control the converter to generate the target voltage signal.

[0021] In some embodiments of the present application, the target voltage signal generating unit is configured to be able to control the output time of the target voltage signal to control the timing of the target voltage signal.

[0022] In some embodiments of the present application, the driver chip also includes a first storage unit, which is electrically connected to the target voltage signal generating unit, and the first storage unit is configured to store a first time; the target voltage signal generating unit is configured to output the target voltage signal after delaying the first time after receiving the pulse signal.

[0023] In some embodiments of the present application, the pulse signal includes pulse information, which is configured to control the output time of the target voltage signal; the pulse information includes the number of pulses, which includes the start information, the close information and the delay information of the target voltage signal output.

[0024] In some embodiments of the present application, the driver chip also includes a second storage unit, which is electrically connected to the control unit and the target voltage signal generating unit, respectively, and the second storage unit is configured to store a preset relationship table of output time information and the number of pulses. The control unit is also configured to determine a delay time, and generate the first control instruction with the output time information according to the delay time and the preset relationship table; the pulse signal generating unit is configured to generate the pulse signal according to the first control instruction with the output time information, and the target voltage signal generating unit is configured to control the start output time and stop output time of the target voltage signal according to the preset relationship table and the pulse signal.

[0025] In some embodiments of the present application, the driver chip further includes a gamma voltage generating subcircuit and a switch control subcircuit, and the power chip further includes a first power signal generating unit, wherein the first power signal generating unit is electrically connected to the gamma voltage generating subcircuit and the switch control subcircuit, respectively, and the first power signal generating unit is also electrically connected to the pulse signal generating unit;

[0026] The pulse signal is configured to simultaneously control the target voltage signal generating unit to output the target voltage signal and control the first power signal generating unit to output the first power signal, and the first power signal is configured to supply power to the gamma voltage generating subcircuit and the switch controlling subcircuit.

[0027] In some embodiments of the present application, the target voltage signal includes a first level voltage signal and / or a second level voltage signal, the first level voltage signal includes a high level signal, and the second level voltage signal includes a low level signal;

[0028] The first level voltage signal and the second level voltage signal are both signals with constant voltage, and the first level voltage signal and the second level voltage signal are both configured to supply power to a shift register circuit in a display device.

[0029] In a second aspect, an embodiment of the present application provides a display device, comprising a driving circuit as described in any one of the first aspects, wherein a driving chip of the driving circuit is electrically connected to a shift register circuit in the display device.

[0030] In a third aspect, an embodiment of the present application provides a method for generating a target voltage signal, which is applied to the driving circuit described in any one of the first aspects, and the method includes:

[0031] The power supply unit supplies power to the target voltage signal generating unit in the power chip;

[0032] The control unit in the driving chip outputs a first control instruction;

[0033] The pulse signal generating unit of the driving chip obtains the first control instruction, and generates a pulse signal according to the first control instruction; and / or the enable signal generating unit obtains the first control instruction, and outputs an enable signal according to the first control instruction;

[0034] The target voltage signal generating unit receives at least one of the pulse signal and the enable signal, generates the target voltage signal according to the received signal, and transmits the target voltage signal to the driving chip.

[0035] In some embodiments of the present application, the target voltage signal generating unit receives at least one of the pulse signal and the enable signal, generates the target voltage signal according to the received signal, and transmits the target voltage signal to the driver chip, comprising:

[0036] The target voltage signal generating unit receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driving chip;

[0037] Alternatively, the target voltage signal generating unit receives the enable signal, generates the target voltage signal according to the enable signal and transmits the target voltage signal to the driving chip;

[0038] Alternatively, the target voltage signal generating unit receives a prior signal of the pulse signal and the enable signal, generates the target voltage signal according to the received signal, and transmits the target voltage signal to the driving chip.

[0039] In some embodiments of the present application, when the target voltage signal generating unit receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driver chip,

[0040] The step of the target voltage signal generating unit receiving the pulse signal, generating the target voltage signal according to the pulse signal and transmitting the target voltage signal to the driving chip includes:

[0041] The target voltage signal generating unit acquires the first time stored in the first storage unit of the driving chip;

[0042] receiving the pulse signal and generating the target voltage signal;

[0043] After the first time of receiving the pulse signal is completed, the target voltage signal is output to the driving chip.

[0044] In some embodiments of the present application, when the target voltage signal generating unit receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driver chip,

[0045] The step of the target voltage signal generating unit receiving the pulse signal, generating the target voltage signal according to the pulse signal and transmitting the target voltage signal to the driving chip includes:

[0046] The target voltage signal generating unit acquires a preset relationship table between output time information and pulse quantity stored in the second storage unit of the driving chip;

[0047] receiving the pulse signal and generating the target voltage signal;

[0048] Determining a delay time according to the preset relationship table;

[0049] The target voltage signal is output to the driving chip according to the delay time.

[0050] In some embodiments of the present application, the step of the control unit in the driver chip outputting the first control instruction includes:

[0051] The control unit determines the delay time and obtains the preset relationship table;

[0052] The first control instruction with the output time information is generated according to the delay time and the preset relationship table.

[0053] In some embodiments of the present application, after outputting the target voltage signal to the driver chip, the method further includes:

[0054] After receiving the pulse signal with shutdown information, the target voltage signal is stopped from being output.

[0055] An embodiment of the present application provides a driving circuit and a method for generating a target voltage signal, and a display device, wherein the driving circuit includes: a power supply unit configured to provide power to the driving circuit; a power supply chip electrically connected to the power supply unit and including a target voltage signal generating unit; a driving chip electrically connected to the power supply chip and including an electrically connected control unit and a pulse signal generating unit; the control unit is configured to output a first control instruction; the pulse signal generating unit is configured to generate a pulse signal according to the first control instruction; wherein the driving circuit also includes an enable signal generating unit, and the enable signal generating unit is configured to generate an enable signal; at least one of the pulse signal generating unit and the enable signal generating unit is electrically connected to the target voltage signal generating unit; the target voltage signal generating unit is configured to generate the target voltage signal under the control of the enable signal or the pulse signal, and transmit the target voltage signal to the driving chip.

[0056] In this way, the power chip generates a target voltage signal under the control of the driver chip and transmits the target voltage signal to the driver chip, which greatly reduces the workload of the driver chip, improves the working efficiency of the driver chip, and extends the service life of the driver chip. Therefore, when the driver chip is applied to a display device, the driver chip can efficiently provide a driving signal to the display device, thereby improving the product quality of the display device.

[0057] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1-Figure 12 A schematic diagram of the structures of twelve driving circuits provided in the embodiments of the present application;

[0060] Fig.13 and Fig.14 Two output timing diagrams of target voltage signals under the control of pulse signals provided in the embodiments of the present application;

[0061] Fig.15 A schematic diagram of the structure of another driving circuit provided in an embodiment of the present application;

[0062] Fig.16 A flow chart of a method for generating a target voltage signal provided in an embodiment of the present application;

[0063] Fig.17 A schematic diagram of the structure of a power chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0065] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0066] In the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0067] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0068] As the performance requirements of display products gradually increase, the load of display driver chips gradually increases. Directly providing a low-level signal (VGL) to the shift register circuit through the display driver chip will further increase the load of the display driver chip and reduce the working efficiency of the display driver chip.

[0069] The embodiment of the present application proposes a low-level signal (VGL) external supply technology. It should be noted that the low-level signal (VGL) external supply technology is relative to the technology of the display driver chip (DDIC) itself directly providing a low-level signal to the shift register circuit. The low-level signal (VGL) external supply technology can use a power chip (PMIC) to provide a low-level signal (VGL) to the display driver chip (hereinafter referred to as the driver chip), however, the power chip itself cannot provide a control signal to control the output of the low-level signal (VGL).

[0070] Considering that most current driver chips have two Swire interfaces (Dual Swire), including an A-Swire interface and an E-Swire interface, the A-Swire signal transmitted by the A-Swire interface controls the power-on and voltage of the AVDD power signal, and the E-Swire signal transmitted by the E-Swire interface controls the power-on and voltage of the ELVDD power signal and the ELVSS power signal. The Swire signal transmitted by the Swire interface is a pulse signal.

[0071] Embodiments of the present application provide a driving circuit and a method for generating a target voltage signal, and a display device, wherein the driving circuit includes: a power supply unit configured to provide power to the driving circuit; a power supply chip electrically connected to the power supply unit, including a target voltage signal generating unit; a driving chip electrically connected to the power supply chip, including an electrically connected control unit and a pulse signal generating unit; the control unit is configured to output a first control instruction; the pulse signal generating unit is configured to generate a pulse signal according to the first control instruction; wherein the driving circuit also includes an enable signal generating unit, the enable signal generating unit is configured to generate an enable signal; at least one of the pulse signal generating unit and the enable signal generating unit is electrically connected to the target voltage signal generating unit; the target voltage signal generating unit is configured to generate a target voltage signal under the control of the enable signal or the pulse signal, and transmit the target voltage signal to the driving chip.

[0072] The embodiment of the present application proposes a control method for controlling a power chip to provide a target voltage signal, such as a low-level signal (VGL), to a driver chip through one of a Swire signal and an enable signal. In this way, the power chip generates a target voltage signal under the control of the driver chip and transmits the target voltage signal to the driver chip. Compared with the driver chip itself generating the target voltage signal, the workload of the driver chip is greatly reduced, the working efficiency of the driver chip is improved, and the service life of the driver chip is extended. Therefore, when the driver chip is applied to a display device, the driver chip can efficiently provide a driving signal to the display device, thereby improving the product quality of the display device.

[0073] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0074] The embodiment of the present application provides a driving circuit, such as Figure 1-Figure 4 As shown, the driving circuit includes:

[0075] A power supply unit 1, configured to provide power to the driving circuit;

[0076] The power chip 3 is electrically connected to the power supply unit 1 and includes a target voltage signal generating unit 301;

[0077] The driving chip 2 is electrically connected to the power chip 3, and includes an electrically connected control unit 202 and a pulse signal generating unit 201; the control unit 202 is configured to output a first control instruction; the pulse signal generating unit 201 is configured to generate a pulse signal (e.g., a Swire pulse signal) according to the first control instruction;

[0078] Among them, the driving circuit also includes an enable signal generating unit 4, which is configured to be able to generate an enable signal (for example, an EN-VGL signal); at least one of the pulse signal generating unit 201 and the enable signal generating unit 4 is electrically connected to the target voltage signal generating unit 301; the target voltage signal generating unit 301 is configured to generate a target voltage signal under the control of an enable signal or a pulse signal, and transmit the target voltage signal to the driving chip.

[0079] In an exemplary embodiment, the power supply unit 1 may be any structure having an electric energy storage function, for example, a battery with good energy storage characteristics and low cost.

[0080] The power chip 3 can also be called a power management chip (Power Management Integrated Circuits, PMIC), which is a chip that is responsible for the conversion, distribution, detection and other power management of electric energy in the electronic equipment system, and is mainly responsible for converting the power supply voltage and current into power that can be used by downstream microprocessors, sensors or driver chips and other loads. The specific type of the power chip 3 is not limited here and can be determined according to the design of the actual product.

[0081] Fig.17 Figures (1) and (2) provide a schematic diagram of the interface distribution of various signals in the power chip 3, wherein: Fig.17 The front side of the power chip 3 in the middle (1) is shown. Fig.17 Figure (2) shows the back of the power chip 3. As can be seen from the figure, Fig.17 In the figure (1), the D4 position is the receiving interface of the pulse signal A-Swire, the E4 position is the receiving interface of the pulse signal E-Swire, and the D6 position is the receiving interface of the enable signal EN-VGL. Other interfaces in the power chip 3 are not introduced here, and the specific description can be referred to the description in the related art.

[0082] The target voltage signal generating unit 301 is a structure in the power chip that can generate a target voltage signal, and the specific structure of the target voltage signal generating unit 301 is not limited here.

[0083] Exemplarily, the target voltage signal generating unit 301 may include a controller (Controller) and an inverting buck boost converter (Inverting Buck Boost Converter) electrically connected together, wherein the controller (Controller) can directly receive the signal transmitted by the pulse signal generating unit 201 or the enable signal generating unit 4, and convert it into a signal for controlling the inverting buck boost converter, and the inverting buck boost converter can output the target voltage signal.

[0084] There is no limitation on the specific type of the driver chip 2. For example, the driver chip 2 may be a display driver chip (Display Driver Integrated Circuits, DDIC); or, the driver chip 2 may be a touch display integrated driver chip (Touch Display Driver Integrated Circuits, TDDIC).

[0085] The specific structure of the control unit 202 is not limited here. In an exemplary embodiment, the control unit 202 may be a microcontroller unit (MCU).

[0086] The specific structure of the pulse signal generating unit 201 is not limited here. In an exemplary embodiment, the pulse signal generating unit 201 may include components such as an oscillating circuit, a filter, and an amplifier. The specific structure of the pulse signal generating unit 201 can refer to related technologies and will not be described here.

[0087] In an exemplary embodiment, the enable signal is an electrical signal with a constant voltage.

[0088] The enable signal and the pulse signal can both control the target voltage signal generating unit 301 to generate the target voltage signal.

[0089] Among them, in some embodiments of the present application, such as Figure 3 As shown, the driver chip 2 includes an enable signal generating unit 4; at this time, the control unit 202 is electrically connected to the pulse signal generating unit 201 and the enable signal generating unit 4, respectively, and the control unit 202 is configured to be able to output a first control instruction; the pulse signal generating unit 201 is configured to generate a pulse signal (for example, a Swire pulse signal) according to the first control instruction, and the enable signal generating unit 4 is configured to generate an enable signal (for example, a VGL-EN signal) according to the first control instruction.

[0090] In other embodiments, Figure 2 As shown, the driving circuit also includes a terminal control chip 5 (AP), and the terminal control chip 5 includes an enable signal generating unit 4. At this time, the control unit 202 in the driving chip 2 is electrically connected to the pulse signal generating unit 201 and the enable signal generating unit 4, respectively, and the control unit 202 is configured to be able to output a first control instruction; the pulse signal generating unit 201 is configured to generate a pulse signal (such as a Swire pulse signal) according to the first control instruction, and the enable signal generating unit 4 is configured to generate an enable signal (such as a VGL-EN signal) according to the first control instruction. Alternatively, the terminal control chip 5 also includes a control unit, and the control unit in the terminal control chip 5 is electrically connected to the control unit 202 in the driving chip 2, and the control unit in the terminal control chip 5 can output a control instruction, and the control instruction can control the enable signal generating unit 4 to generate an enable signal (such as a VGL-EN signal).

[0091] In an exemplary embodiment, at least one of the pulse signal generating unit 201 and the enable signal generating unit 4 is electrically connected to the target voltage signal generating unit 301; the target voltage signal generating unit 301 is configured to generate a target voltage signal under the control of the enable signal or the pulse signal, and transmit the target voltage signal to the driver chip, including but not limited to the following cases:

[0092] First, Figure 6 and Figure 7 As shown, the pulse signal generating unit 201 is electrically connected to the target voltage signal generating unit 301; the pulse signal is configured to control the target voltage signal generating unit 301 to output the target voltage signal.

[0093] When the pulse signal generating unit 201 is electrically connected to the target voltage signal generating unit 301 , the target voltage signal generating unit 301 can receive the pulse signal transmitted from the pulse signal generating unit 201 , so that the pulse signal can be used to control the target voltage signal generating unit 301 to generate and transmit the target voltage signal.

[0094] Second, if Figure 4 and Figure 5 As shown, the enable signal generating unit 4 is electrically connected to the target voltage signal generating unit 301 ; the enable signal is configured to control the target voltage signal generating unit 301 to output the target voltage signal.

[0095] When the enable signal generating unit 4 is electrically connected to the target voltage signal generating unit 301 , the target voltage signal generating unit 301 can receive the enable signal transmitted from the enable signal generating unit 4 , so that the enable signal can be used to control the target voltage signal generating unit 301 to generate and transmit the target voltage signal.

[0096] Third, if Figure 8 and Fig. 9 As shown, the pulse signal generating unit 301 and the enable signal generating unit 4 are electrically connected to the target voltage signal generating unit 301 respectively; the former of the pulse signal and the enable signal is configured to control the target voltage signal generating unit 301 to output the target voltage signal.

[0097] When the pulse signal generating unit 301 and the enable signal generating unit 4 are electrically connected to the target voltage signal generating unit 301 respectively, the target voltage signal generating unit 301 can receive both the enable signal transmitted from the enable signal generating unit 4 and the pulse signal transmitted from the pulse signal generating unit 201. At this time, the signal among the pulse signal and the enable signal which is transmitted faster and is received first by the target voltage signal generating unit 301 controls the target voltage signal generating unit 301 to output the target voltage signal.

[0098] Exemplarily, if the target voltage signal generating unit 301 receives a pulse signal first, the pulse signal controls the target voltage signal generating unit 301 to output the target voltage signal. If the target voltage signal generating unit 301 can still receive an enable signal after the pulse signal generating unit 301 stops transmitting the pulse signal, the enable signal continues to control the target voltage signal generating unit 301 to output the target voltage signal until both the pulse signal and the enable signal stop being output.

[0099] In an exemplary embodiment, the target voltage signal may be an electrical signal with a constant voltage. The voltage value of the target voltage signal is not limited and may be determined according to product design.

[0100] In practical applications, the driver chip 2 is electrically connected to a GOA (Gate On Array, row drive shift register) cascade circuit in the display device. After receiving the target voltage signal, the driver chip transmits it to the GOA cascade circuit for controlling and driving the GOA cascade circuit.

[0101] The embodiment of the present application proposes a control method of controlling the power chip 3 to provide a target voltage signal, such as a low-level signal (VGL), to the driver chip 2 through one of a pulse signal and an enable signal. In this way, the power chip 3 generates a target voltage signal under the control of the driver chip 2 and transmits the target voltage signal to the driver chip 2. Compared with the driver chip itself generating the target voltage signal in the related art, the workload of the driver chip 2 is greatly reduced, the working efficiency of the driver chip 2 is improved, and the service life of the driver chip 2 is extended. Therefore, when the driver chip 2 is applied to a display device, the driver chip 2 can efficiently provide a driving signal to the display device, thereby improving the product quality of the display device.

[0102] In some embodiments of the present application, when the pulse signal generating unit 201 and the enable signal generating unit 4 are both in a powered-off state, the target voltage signal generating unit 301 stops outputting the target voltage signal;

[0103] When at least one of the pulse signal generating unit 201 and the enable signal generating unit 4 is in a powered-on state, the target voltage signal generating unit 301 continuously outputs the target voltage signal.

[0104] The above-mentioned “power-on” state refers to “electrical connection”, and the “power-off” state refers to “not electrically connected”. Only when electrically connected can the target voltage signal generating unit 301 receive a pulse signal or an enable signal.

[0105] Exemplarily, if the target voltage signal generating unit 301 is not electrically connected to the enable signal generating unit 4 and the pulse signal generating unit 201 , the target voltage signal generating unit 301 cannot receive the pulse signal and the enable signal.

[0106] Exemplarily, if the target voltage signal generating unit 301 receives a pulse signal, the pulse signal controls the target voltage signal generating unit 301 to output the target voltage signal.

[0107] Exemplarily, if the target voltage signal generating unit 301 is able to receive an enable signal, the enable signal controls the target voltage signal generating unit 301 to output the target voltage signal.

[0108] Exemplarily, if the target voltage signal generating unit 301 receives a pulse signal first, the pulse signal controls the target voltage signal generating unit 301 to output the target voltage signal. If the target voltage signal generating unit 301 can still receive an enable signal after the pulse signal generating unit 301 stops transmitting the pulse signal, the enable signal continues to control the target voltage signal generating unit 301 to output the target voltage signal until both the pulse signal and the enable signal stop being output.

[0109] The embodiment of the present application proposes a control method of controlling the power chip to provide a target voltage signal, such as a low-level signal (VGL), to the driver chip through one of a pulse signal and an enable signal. In this way, the power chip 3 generates a target voltage signal under the control of the driver chip 2 and transmits the target voltage signal to the driver chip 2. Compared with the driver chip itself generating the target voltage signal in the related art, the workload of the driver chip 2 is greatly reduced, the working efficiency of the driver chip 2 is improved, and the service life of the driver chip 2 is extended. Therefore, when the driver chip 2 is applied to a display device, the driver chip 2 can efficiently provide a driving signal to the display device, thereby improving the product quality of the display device.

[0110] In some embodiments of the present application, Fig.10 As shown, the target voltage signal generating unit 301 includes a controller and a converter that are electrically connected, the pulse signal generating unit 201 and the enable signal generating unit 4 are electrically connected to the controller respectively, and the power supply unit 1 is electrically connected to the converter;

[0111] In the case where the pulse signal (such as A-Swire) is the prior signal, the controller is configured to convert the pulse signal into a second control instruction, and the second control instruction is configured to control the converter to generate a target voltage signal;

[0112] In the case where the enable signal (eg, VGL-EN) is the prior signal, the controller is configured to convert the enable signal into a third control instruction, and the third control instruction is configured to control the converter to generate a target voltage signal.

[0113] Exemplarily, the converter may include an inverting buck boost converter (Inverting Buck Boost Converter), wherein the inverting buck boost converter is a DC-DC converter whose output voltage may be greater than or less than the input voltage. The specific structure of the inverting buck boost converter may be referred to the introduction in the relevant technology and will not be repeated here.

[0114] In some embodiments of the present application, the target voltage signal generating unit 301 is configured to be able to control the output time of the target voltage signal to control the timing of the target voltage signal.

[0115] In practical applications, after the target voltage signal is transmitted to the driver chip 2, the driver chip 2 will continue to transmit the signal to the GOA circuit of the display device. According to the driving process of the GOA circuit in the relevant technology, the signal driving the GOA circuit has timing requirements. In the embodiment of the present application, by setting the target voltage signal generating unit 301, the output time of the target voltage signal can be controlled to control the timing of the target voltage signal, thereby meeting the driving requirements of the GOA circuit.

[0116] In some embodiments of the present application, Fig.11 As shown, the driving chip also includes a first storage unit 203, which is electrically connected to the target voltage signal generating unit 301, and the first storage unit 203 is configured to store a first time; the target voltage signal generating unit 301 is configured to output a target voltage signal after delaying the first time after receiving the pulse signal.

[0117] In an exemplary embodiment, when the target voltage signal generating unit 301 includes a controller and a converter, the first storage unit 203 is directly electrically connected to the controller.

[0118] The first time is preset in the driver chip and has a fixed value. Fig.11 In the driving circuit shown in , the target voltage signal generating unit 301 is configured to always delay the first time before outputting the target voltage signal after receiving the pulse signal, and the delay time cannot be changed.

[0119] It should be noted that the delay time starts from the moment when the pulse signal is received.

[0120] The specific value of the first time is not limited here. It can be determined according to the timing signal of the GOA circuit in the display device that the driving circuit needs to match. Exemplarily, the first time can be 0ms, 5ms, 8ms, 10ms, 12ms, 15ms, 18ms, or 20ms.

[0121] In the driving circuit provided in the embodiment of the present application, when the timing signal of the GOA circuit in the display device that the driving circuit needs to match is determined, the first time can be stored in the first storage unit 203 of the driving chip 2 in advance, and the target voltage signal generating unit 301 can read the first time stored in the first storage unit 203, and after receiving the pulse signal, always delay the first time before outputting the target voltage signal. In this way, on the one hand, the timing of the target voltage signal can be controlled to meet the driving requirements of the GOA circuit; on the other hand, the design of the driving circuit can be simplified, and the workload of the first storage unit 203 and the target voltage signal generating unit 301 in the driving chip can be reduced, thereby improving the working efficiency of the driving chip 2 and extending the service life of the driving chip 2. When the driving chip 2 is applied to the display device, the driving chip 2 can efficiently provide the driving signal to the display device, thereby improving the product quality of the display device.

[0122] In some embodiments of the present application, the pulse signal includes pulse information, which is configured to control the output time of the target voltage signal; the pulse information includes the number of pulses, which includes the on information, off information and delay information of the target voltage signal output.

[0123] In some embodiments of the present application, Fig.12 As shown, the driver chip 2 also includes a second storage unit 204, which is electrically connected to the control unit 201 and the target voltage signal generating unit 301 respectively. The second storage unit 204 is configured to store a preset relationship table (such as A-Swire Table) of output time information and pulse quantity. The control unit 202 is also configured to determine the delay time and generate a first control instruction with output time information according to the delay time and the preset relationship table; the pulse signal generating unit 201 is configured to generate a pulse signal (such as A-Swire) according to the first control instruction with output time information, and the target voltage signal generating unit 201 is configured to control the start output time and stop output time of the target voltage signal according to the preset relationship table and the pulse signal.

[0124] In an exemplary embodiment, when the target voltage signal generating unit 301 includes a controller and a converter, the second storage unit 204 is directly electrically connected to the controller.

[0125] In actual operation, the control unit 202 first determines the delay time according to the timing requirements in the GOA circuit, and determines the number of pulses corresponding to the delayed output time by looking up the table according to the preset relationship table of the delay time and the stored output time information and the number of pulses, and outputs a first control instruction according to the determined number of pulses. The first control instruction carries the number of pulses representing the output time information, and the pulse signal generating unit 201 generates a pulse signal based on the pulse number information (one pulse number represents one output time information), thereby controlling the time for the target voltage signal generating unit 301 to output the target voltage signal through the pulse signal.

[0126] In some embodiments, the output time information includes two situations: directly starting the output without delay (ON) and stopping the output (OFF), such as the information in Table 1 below.

[0127] Table 1: Output state of target voltage signal and preset pulse quantity relationship table

[0128] Output status of target voltage signal Number of pulses in the pulse signal ON 103 OFF 104

[0129] Table 1 provides a preset relationship table between the number of pulses of a pulse signal and the output state of a target voltage signal. In an exemplary embodiment, Fig.13 As shown in the timing signal diagram in , when the target voltage signal generating unit 301 receives a pulse signal with a pulse number of 103 (e.g., an A-Swire pulse signal), at the moment when the pulse signal stops, the target voltage signal generating unit 301 outputs the target voltage signal (e.g., a VGL signal). In an exemplary embodiment, when the target voltage signal generating unit 301 receives a pulse signal with a pulse number of 104 (e.g., an A-Swire pulse signal), at the moment when the pulse signal stops, the target voltage signal generating unit 301 stops outputting the target voltage signal (e.g., a VGL signal).

[0130] In other embodiments, the output time information includes: output after a preset delay time, such as the information in Table 2. The delayed output time refers to the time between the completion of receiving the pulse signal and the start of outputting the target voltage signal.

[0131] Table 2 provides a preset relationship table of the number of pulses of a pulse signal and the delayed output state of a target voltage signal. In an exemplary embodiment, Fig.14 As shown in the timing signal diagram, when the target voltage signal generating unit 301 receives a pulse signal with a pulse number of 110 (for example, an A-Swire pulse signal), the target voltage signal generating unit 301 outputs a target voltage signal (for example, a VGL signal) starting 15 ms after the pulse signal stops.

[0132] It should be noted that the above Table 2 lists the corresponding relationship between the delayed output state and the number of pulses in 11. In practical applications, the preset relationship table can also include more situations. This is only an example and does not represent a limitation on the present application.

[0133] Table 2: Delayed output state of target voltage signal and preset pulse quantity

[0134] Delayed output state of target voltage signal Number of pulses in the pulse signal Delay output 10ms 105 Delay output 11ms 106 Delay output 12ms 107 Delay output 13ms 108 Delay output 14ms 109 Delay output 15ms 110 Delay output 16ms 111 Delay output 17ms 112 Delay output 18ms 113 Delay output 19ms 114 Delay output 20ms 115

[0135] In addition, in some embodiments, the second storage unit 204 of the driver chip 2 may store the corresponding relationships in Table 1 and Table 2 at the same time.

[0136] In an embodiment of the present application, by pre-storing a preset relationship table of output time information and the number of pulses in the second storage unit 204, the control unit 202 first determines the delay time, and determines the number of pulses corresponding to the delayed output time by looking up the table according to the delay time and the preset relationship table storing the output time information and the number of pulses, and outputs a first control instruction according to the determined number of pulses, the first control instruction carries the number of pulses representing the output time information, and the pulse signal generating unit 201 generates a pulse signal according to the pulse number information (one pulse number represents one output time information), thereby controlling the time when the target voltage signal generating unit 301 outputs the target voltage signal through the pulse signal; in this way, when the timing of the signal required by the GOA circuit of the display device changes, the drive circuit can adjust the output timing of the target voltage signal according to the demand, can enrich the function of the drive circuit, and make the drive circuit compatible with different types of display devices, expand its application scenarios, and reduce the development cost of the drive circuit corresponding to different models of display devices.

[0137] In an exemplary embodiment, the pulse signal may be an A-Swire pulse signal, or the pulse signal may be an E-Swire pulse signal. The embodiments and drawings of the present application are described by taking the A-Swire pulse signal controlling the target voltage signal as an example.

[0138] In some embodiments of the present application, Fig.15As shown, the driver chip 2 also includes a gamma voltage generating subcircuit 203 and a switch control subcircuit 204, and the power chip 3 also includes a first power signal generating unit 302, wherein the first power signal generating unit 302 is electrically connected to the gamma voltage generating subcircuit 203 and the switch control subcircuit 204 respectively, and the first power signal generating unit 302 is also electrically connected to the pulse signal generating unit 201 (first pulse signal generating unit); the pulse signal A-Swire is configured to be able to simultaneously control the target voltage signal generating unit 301 to output the target voltage signal and control the first power signal generating unit 302 to output the first power signal, such as the AVDD power signal, and the first power signal is configured to be able to supply power to the gamma voltage generating subcircuit 203 and the switch control subcircuit 204.

[0139] In an exemplary embodiment, Fig.15 As shown, the driver chip 2 may include two pulse signal generating units, namely, a first pulse signal generating unit 201 (providing an A-Swire pulse signal) and a second pulse signal generating unit 202 (providing an E-Swire pulse signal), wherein the embodiment of the present application is described by taking the pulse signal generating unit as the first pulse signal generating unit 201. The power chip 3 also includes a third power signal generating unit 303 and a fourth power signal generating unit 304; wherein the E-Swire pulse signal provided by the second pulse signal generating unit 202 is used to simultaneously control the third power signal generating unit 303 to output an ELVDD signal, and to control the fourth power signal generating unit 304 to output an ELVSS signal.

[0140] It should be noted that the switch control subcircuit 204 is used to provide a switch voltage to a transistor in the display device, and the gamma voltage generation subcircuit 203 is used to provide a grayscale voltage to the display device.

[0141] In an exemplary embodiment, the signals output by the third power signal generating unit 303 and the fourth power signal generating unit 304 are used as driving voltages of the light emitting device.

[0142] In some embodiments of the present application, the target voltage signal includes a first level voltage signal and / or a second level voltage signal, the first level voltage signal includes a high level signal, and the second level voltage signal includes a low level signal;

[0143] The first level voltage signal and the second level voltage signal are both signals with constant voltage, and the first level voltage signal and the second level voltage signal are both configured to supply power to a shift register circuit in the display device.

[0144] In an exemplary embodiment, the target voltage signal includes the first level voltage signal and / or the second level voltage signal in the following three cases:

[0145] 1. The target voltage signal includes a first level voltage signal, and the first level voltage signal includes a high level signal (VGH signal);

[0146] 2. The target voltage signal includes a second level voltage signal, and the second level voltage signal includes a low level signal (VGL signal);

[0147] 3. In some time periods, the target voltage signal includes a first level voltage signal, and the first level voltage signal includes a high level signal; in other time periods, the target voltage signal includes a second level voltage signal, and the second level voltage signal includes a low level signal. Specifically, it can be determined according to the voltage value and time period required by the shift register circuit determined by the control unit.

[0148] An embodiment of the present application provides a display device, comprising the driving circuit as described above, wherein a driving chip 2 of the driving circuit is electrically connected to a shift register circuit (GOA circuit) in the display device.

[0149] The display device provided in the embodiments of the present application may be an OLED (Organic Light Emitting Diode) display device, wherein the OLED display device may include a glass-based OLED display device and a silicon-based OLED display device.

[0150] In addition, the display device may be a display device such as an OLED display, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.

[0151] The display device provided in the embodiment of the present application controls the power chip 3 to provide a target voltage signal to the driver chip 2 through one of the pulse signal and the enable signal, such as a control method of a low-level signal (VGL). In this way, the power chip 3 generates a target voltage signal under the control of the driver chip 2 and transmits the target voltage signal to the driver chip 2. Compared with the driver chip itself generating the target voltage signal in the related art, the workload of the driver chip 2 is greatly reduced, the working efficiency of the driver chip 2 is improved, and the service life of the driver chip 2 is extended. Therefore, when the driver chip 2 is applied to the display device, the driver chip 2 can efficiently provide the drive signal to the display device, thereby improving the product quality of the display device.

[0152] The embodiment of the present application provides a method for generating a target voltage signal, which is applied to the driving circuit described above. Fig.16 As shown, the method includes:

[0153] S901, the power supply unit supplies power to the target voltage signal generating unit 301 in the power chip 3;

[0154] S902, the control unit 202 in the driver chip 2 outputs a first control instruction;

[0155] S903, the pulse signal generating unit 201 in the driver chip 2 obtains the first control instruction, and generates a pulse signal according to the first control instruction; and / or the enable signal generating unit 4 obtains the first control instruction, and outputs an enable signal according to the first control instruction;

[0156] S904 , the target voltage signal generating unit 301 receives at least one of the pulse signal and the enable signal, generates a target voltage signal according to the received signal, and transmits the target voltage signal to the driving chip 2 .

[0157] In some embodiments of the present application, Figure 3 As shown, the driver chip 2 includes an enable signal generating unit 4; at this time, the control unit 202 is electrically connected to the pulse signal generating unit 201 and the enable signal generating unit 4, respectively, and the control unit 202 is configured to be able to output a first control instruction; the pulse signal generating unit 201 is configured to generate a pulse signal (for example, a Swire pulse signal) according to the first control instruction, and the enable signal generating unit 4 is configured to generate an enable signal (for example, a VGL-EN signal) according to the first control instruction.

[0158] In other embodiments, Figure 2 As shown, the driving circuit also includes a terminal control chip 5 (AP), and the terminal control chip 5 includes an enable signal generating unit 4. At this time, the control unit 202 in the driving chip 2 is electrically connected to the pulse signal generating unit 201 and the enable signal generating unit 4, respectively, and the control unit 202 is configured to be able to output a first control instruction; the pulse signal generating unit 201 is configured to generate a pulse signal (such as a Swire pulse signal) according to the first control instruction, and the enable signal generating unit 4 is configured to generate an enable signal (such as a VGL-EN signal) according to the first control instruction. Alternatively, the terminal control chip 5 also includes a control unit, and the control unit in the terminal control chip 5 is electrically connected to the control unit 202 in the driving chip 2, and the control unit in the terminal control chip 5 can output a control instruction, and the control instruction can control the enable signal generating unit 4 to generate an enable signal (such as a VGL-EN signal).

[0159] The embodiment of the present application proposes a control method of controlling the power chip 3 to provide a target voltage signal, such as a low-level signal (VGL), to the driver chip 2 through one of a pulse signal and an enable signal. In this way, the power chip 3 generates a target voltage signal under the control of the driver chip 2 and transmits the target voltage signal to the driver chip 2. Compared with the driver chip itself generating the target voltage signal in the related art, the workload of the driver chip 2 is greatly reduced, the working efficiency of the driver chip 2 is improved, and the service life of the driver chip 2 is extended. Therefore, when the driver chip 2 is applied to a display device, the driver chip 2 can efficiently provide a driving signal to the display device, thereby improving the product quality of the display device.

[0160] In an exemplary embodiment, step S903, the pulse signal generating unit 201 in the driver chip 2 obtains the first control instruction, and generates a pulse signal according to the first control instruction; and / or the enable signal generating unit 4 obtains the first control instruction, and outputs the enable signal according to the first control instruction, including:

[0161] Step S9031: The pulse signal generating unit 201 in the driving chip 2 obtains a first control instruction, and generates a pulse signal according to the first control instruction.

[0162] or,

[0163] Step S9032: The enable signal generating unit 4 obtains a first control instruction, and outputs an enable signal according to the first control instruction.

[0164] or,

[0165] Step S9033: the pulse signal generating unit 201 in the driving chip 2 obtains the first control instruction, and generates a pulse signal according to the first control instruction, and the enable signal generating unit 4 obtains the first control instruction, and outputs an enable signal according to the first control instruction.

[0166] In some embodiments of the present application, step S904, the target voltage signal generating unit 301 receives at least one of the pulse signal and the enable signal, generates a target voltage signal according to the received signal, and transmits the target voltage signal to the driver chip 2, includes:

[0167] Step S9041, the target voltage signal generating unit 301 receives a pulse signal (such as an A-Swire pulse signal), generates a target voltage signal (such as a VGL signal) according to the pulse signal (such as an A-Swire pulse signal), and transmits the target voltage signal (such as a VGL signal) to the driving chip 2;

[0168] or,

[0169] Step S9042 : The target voltage signal generating unit 301 receives the enable signal, generates a target voltage signal according to the enable signal, and transmits the target voltage signal to the driving chip 2 .

[0170] or,

[0171] Step S9043 : The target voltage signal generating unit 301 receives the pulse signal and the enable signal, whichever comes first, generates a target voltage signal according to the received signal, and transmits the target voltage signal to the driving chip 2 .

[0172] In some embodiments of the present application, when the target voltage signal generating unit 301 receives a pulse signal (e.g., an A-Swire pulse signal), generates a target voltage signal (e.g., a VGL signal) according to the pulse signal (e.g., an A-Swire pulse signal), and transmits the target voltage signal (e.g., a VGL signal) to the driver chip 2,

[0173] Step S9041, the target voltage signal generating unit 301 receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driving chip 2, including:

[0174] Sub-step 11, the target voltage signal generating unit 301 obtains the first time stored in the first storage unit of the driving chip;

[0175] Sub-step 12: receiving a pulse signal and generating a target voltage signal;

[0176] Sub-step 13: after receiving the first time of the pulse signal, output the target voltage signal to the driving chip 2.

[0177] The first time is preset in the driver chip and has a fixed value. Fig.11 In the driving circuit shown in , the target voltage signal generating unit 301 is configured to always delay the first time before outputting the target voltage signal after receiving the pulse signal, and the delay time cannot be changed. It should be noted that the starting time of the delay time is: the time when the pulse signal is received.

[0178] In the driving circuit provided in the embodiment of the present application, when the timing signal of the GOA circuit in the display device that the driving circuit needs to match is determined, the first time can be stored in the first storage unit 203 of the driving chip 2 in advance, and the target voltage signal generating unit 301 can read the first time stored in the first storage unit 203, and after receiving the pulse signal, always delay the first time before outputting the target voltage signal. In this way, on the one hand, the timing of the target voltage signal can be controlled to meet the driving requirements of the GOA circuit; on the other hand, the design of the driving circuit can be simplified, and the workload of the first storage unit 203 and the target voltage signal generating unit 301 in the driving chip can be reduced, thereby improving the working efficiency of the driving chip 2 and extending the service life of the driving chip 2. When the driving chip 2 is applied to the display device, the driving chip 2 can efficiently provide the driving signal to the display device, thereby improving the product quality of the display device.

[0179] In some embodiments of the present application, when the target voltage signal generating unit receives a pulse signal, generates a target voltage signal according to the pulse signal and transmits the target voltage signal to the driver chip,

[0180] Step S9041, the target voltage signal generating unit 301 receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driving chip 2, including:

[0181] Sub-step 24, the target voltage signal generating unit 301 obtains a preset relationship table between output time information and pulse quantity stored in the second storage unit 204 of the driving chip;

[0182] Sub-step 25: receiving a pulse signal and generating a target voltage signal;

[0183] Sub-step 26: determining the delay time according to the preset relationship table;

[0184] Sub-step 27 : outputting a target voltage signal to the driving chip 2 according to the delay time.

[0185] In some embodiments of the present application, the step of the control unit 202 in the driver chip 2 outputting the first control instruction includes:

[0186] Sub-step 21, the control unit 202 determines the delay time and obtains the preset relationship table stored in the second storage unit 204;

[0187] Sub-step 22: generating a first control instruction with output time information according to the delay time and the preset relationship table.

[0188] In an embodiment of the present application, by pre-storing a preset relationship table of output time information and the number of pulses in the second storage unit 204, the control unit 202 first determines the delay time, and determines the number of pulses corresponding to the delayed output time by looking up the table according to the delay time and the preset relationship table storing the output time information and the number of pulses, and outputs a first control instruction according to the determined number of pulses, the first control instruction carries the number of pulses representing the output time information, and the pulse signal generating unit 201 generates a pulse signal according to the pulse number information (one pulse number represents one output time information), thereby controlling the time when the target voltage signal generating unit 301 outputs the target voltage signal through the pulse signal; in this way, when the timing of the signal required by the GOA circuit of the display device changes, the drive circuit can adjust the output timing of the target voltage signal according to the demand, can enrich the function of the drive circuit, and make the drive circuit compatible with different types of display devices, expand its application scenarios, and reduce the development cost of the drive circuit corresponding to different models of display devices.

[0189] In practical applications, taking the driving chip including the second storage unit 204 as an example, the generation process of the target voltage signal is specifically described as follows:

[0190] Sub-step 21, the control unit 202 determines the delay time and obtains the preset relationship table stored in the second storage unit 204;

[0191] Sub-step 22, generating a first control instruction with output time information according to the delay time and the preset relationship table;

[0192] Sub-step 23, the pulse signal generating unit 201 generates a pulse signal according to the first control instruction;

[0193] Sub-step 24, the target voltage signal generating unit 301 obtains a preset relationship table between output time information and pulse quantity stored in the second storage unit 204 of the driving chip;

[0194] Sub-step 25: receiving a pulse signal and generating a target voltage signal;

[0195] Sub-step 26: determining the delay time according to the preset relationship table;

[0196] Sub-step 27 : outputting a target voltage signal to the driving chip 2 according to the delay time.

[0197] The sub-step 24 and the sub-step 25 may be performed simultaneously, or the order of the sub-step 24 and the sub-step 25 may be swapped.

[0198] In some embodiments of the present application, after outputting the target voltage signal to the driver chip, the method further includes:

[0199] Sub-step 28: After receiving the pulse signal with shutdown information, stop outputting the target voltage signal.

[0200] In an exemplary embodiment, Fig.13 As shown in the timing signal diagram in , when the target voltage signal generating unit 301 receives a pulse signal with a pulse number of 104 (for example, an A-Swire pulse signal), at the moment when the pulse signal stops, the target voltage signal generating unit 301 stops outputting the target voltage signal (for example, a VGL signal).

[0201] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving circuit, characterized in that: include: A power supply unit, configured to provide power to the driving circuit; A power chip, electrically connected to the power supply unit, comprising a target voltage signal generating unit; A driving chip, electrically connected to the power chip, comprising an electrically connected control unit and a pulse signal generating unit; the control unit is configured to output a first control instruction; the pulse signal generating unit is configured to generate a pulse signal according to the first control instruction; Among them, the driving circuit also includes an enable signal generating unit, which is configured to generate an enable signal; at least one of the pulse signal generating unit and the enable signal generating unit is electrically connected to the target voltage signal generating unit; the target voltage signal generating unit is configured to generate the target voltage signal under the control of the enable signal or the pulse signal, and transmit the target voltage signal to the driving chip.

2. The driving circuit according to claim 1, characterized in that: The driving chip includes the enable signal generating unit; Alternatively, the driving circuit further includes a terminal control chip, and the terminal control chip includes the enable signal generating unit.

3. The driving circuit according to claim 2, characterized in that: The pulse signal generating unit is electrically connected to the target voltage signal generating unit; the pulse signal is configured to control the target voltage signal generating unit to output the target voltage signal.

4. The driving circuit according to claim 2, characterized in that: The enable signal generating unit is electrically connected to the target voltage signal generating unit; the enable signal is configured to control the target voltage signal generating unit to output the target voltage signal.

5. The driving circuit according to claim 2, characterized in that: The pulse signal generating unit and the enable signal generating unit are electrically connected to the target voltage signal generating unit respectively; the previous signal of the pulse signal and the enable signal is configured to control the target voltage signal generating unit to output the target voltage signal.

6. The driving circuit according to claim 5, characterized in that: When the pulse signal generating unit and the enable signal generating unit are both in a powered-off state, the target voltage signal generating unit stops outputting the target voltage signal; When at least one of the pulse signal generating unit and the enable signal generating unit is in a powered-on state, the target voltage signal generating unit continuously outputs the target voltage signal.

7. The driving circuit according to claim 5, characterized in that: The target voltage signal generating unit includes a controller and a converter which are electrically connected, the pulse signal generating unit and the enable signal generating unit are electrically connected to the controller respectively, and the power supply unit is electrically connected to the converter; In the case where the pulse signal is a prior signal, the controller is configured to convert the pulse signal into a second control instruction, wherein the second control instruction is configured to control the converter to generate the target voltage signal; In the case where the enable signal is a prior signal, the controller is configured to convert the enable signal into a third control instruction, and the third control instruction is configured to control the converter to generate the target voltage signal.

8. The driving circuit according to any one of claims 3, 5-7, characterized in that: The target voltage signal generating unit is configured to control an output time of the target voltage signal to control a timing of the target voltage signal.

9. The driving circuit according to claim 8, characterized in that: The driving chip further includes a first storage unit, the first storage unit is electrically connected to the target voltage signal generating unit, and the first storage unit is configured to store a first time; The target voltage signal generating unit is configured to output the target voltage signal after delaying the first time after receiving the pulse signal.

10. The driving circuit according to claim 8, characterized in that: The pulse signal includes pulse information, and the pulse information is configured to control the output time of the target voltage signal; The pulse information includes the number of pulses, and the number of pulses includes on information, off information, and delay information of the target voltage signal output.

11. The driving circuit according to claim 10, characterized in that: The driving chip also includes a second storage unit, which is electrically connected to the control unit and the target voltage signal generating unit respectively, and the second storage unit is configured to store a preset relationship table of output time information and the number of pulses. The control unit is also configured to determine a delay time, and generate the first control instruction with the output time information according to the delay time and the preset relationship table; the pulse signal generating unit is configured to generate the pulse signal according to the first control instruction with the output time information, and the target voltage signal generating unit is configured to control the start output time and stop output time of the target voltage signal according to the preset relationship table and the pulse signal.

12. The driving circuit according to any one of claims 3, 5-7, 9-11, characterized in that: The driving chip further includes a gamma voltage generating subcircuit and a switch control subcircuit, and the power chip further includes a first power signal generating unit, wherein the first power signal generating unit is electrically connected to the gamma voltage generating subcircuit and the switch control subcircuit respectively, and the first power signal generating unit is also electrically connected to the pulse signal generating unit; The pulse signal is configured to simultaneously control the target voltage signal generating unit to output the target voltage signal and control the first power signal generating unit to output the first power signal, and the first power signal is configured to supply power to the gamma voltage generating subcircuit and the switch controlling subcircuit.

13. The driving circuit according to claim 12, characterized in that: The target voltage signal includes a first level voltage signal and / or a second level voltage signal, the first level voltage signal includes a high level signal, and the second level voltage signal includes a low level signal; The first level voltage signal and the second level voltage signal are both signals with constant voltage, and the first level voltage signal and the second level voltage signal are both configured to supply power to a shift register circuit in a display device.

14. A display device, characterized in that: It comprises the driving circuit as claimed in any one of claims 1 to 13, wherein the driving chip of the driving circuit is electrically connected to the shift register circuit in the display device.

15. A method for generating a target voltage signal, characterized in that: The driving circuit according to any one of claims 1 to 13, wherein the method comprises: The power supply unit supplies power to the target voltage signal generating unit in the power chip; The control unit in the driving chip outputs a first control instruction; The pulse signal generating unit of the driving chip obtains the first control instruction, and generates a pulse signal according to the first control instruction; and / or the enable signal generating unit obtains the first control instruction, and outputs an enable signal according to the first control instruction; The target voltage signal generating unit receives at least one of the pulse signal and the enable signal, generates the target voltage signal according to the received signal, and transmits the target voltage signal to the driving chip.

16. The method according to claim 15, characterized in that The step of the target voltage signal generating unit receiving at least one of the pulse signal and the enable signal, generating the target voltage signal according to the received signal and transmitting the target voltage signal to the driver chip comprises: The target voltage signal generating unit receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driving chip; Alternatively, the target voltage signal generating unit receives the enable signal, generates the target voltage signal according to the enable signal and transmits the target voltage signal to the driving chip; Alternatively, the target voltage signal generating unit receives a prior signal of the pulse signal and the enable signal, generates the target voltage signal according to the received signal, and transmits the target voltage signal to the driving chip.

17. The method according to claim 16, characterized in that When the target voltage signal generating unit receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driving chip, The step of the target voltage signal generating unit receiving the pulse signal, generating the target voltage signal according to the pulse signal and transmitting the target voltage signal to the driving chip includes: The target voltage signal generating unit acquires the first time stored in the first storage unit of the driving chip; receiving the pulse signal and generating the target voltage signal; After the first time of receiving the pulse signal is completed, the target voltage signal is output to the driving chip.

18. The method according to claim 16, characterized in that When the target voltage signal generating unit receives the pulse signal, generates the target voltage signal according to the pulse signal and transmits the target voltage signal to the driving chip, The step of the target voltage signal generating unit receiving the pulse signal, generating the target voltage signal according to the pulse signal and transmitting the target voltage signal to the driving chip includes: The target voltage signal generating unit acquires a preset relationship table between output time information and pulse quantity stored in the second storage unit of the driving chip; receiving the pulse signal and generating the target voltage signal; Determining a delay time according to the preset relationship table; After the delay time, the target voltage signal is output to the driving chip.

19. The method according to claim 18, characterized in that The step of the control unit in the driver chip outputting the first control instruction comprises: The control unit determines the delay time and obtains the preset relationship table; The first control instruction with the output time information is generated according to the delay time and the preset relationship table.

20. The method according to claim 17 or 18, characterized in that After outputting the target voltage signal to the driver chip, the method further includes: After receiving the pulse signal with shutdown information, the target voltage signal is stopped from being output.

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