Rate adjustment of memory interfaces

Abstract

This application relates to rate adjustment of a memory interface. A host system can communicate with a memory system via an interface according to a plurality of data transfer rates. For example, the host system can configure the interface to operate according to a first rate. The host system can switch the interface from the first rate to a second rate in response to one or more commands from the host system satisfying one or more parameters, such as a threshold amount of data associated with a command, a threshold number of issued commands associated with at least the threshold amount of data, a threshold number of issued and unexecuted commands, or any combination thereof. Based on the switch, the host system can communicate with the memory system via the interface according to the second rate.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 889,660, filed August 17, 2022, entitled “RATE ADJUSTMENTS FOR A MEMORY INTERFACE”, by Chunchu et al., and U.S. Provisional Patent Application No. 63 / 237,306, filed August 26, 2021, entitled “RATE ADJUSTMENTS FOR A MEMORY INTERFACE”, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves speed adjustment of memory interfaces. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, and others. Memory devices can be volatile or non-volatile. Volatile memory cells (such as DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (such as NAND memory cells) can retain their programmed state for a long time, even in the absence of external power. Summary of the Invention

[0006] A device is described. The device may include a controller configured to communicate with a memory system via an interface. The controller may be configured such that the device: configures the interface to operate at a first rate, wherein the first rate is one of a set of rates each corresponding to a respective data transfer rate between the controller and the memory system via the interface; switches the interface from the first rate to a second rate of the set of rates based on one or more commands from the controller to the memory system satisfying one or more parameters, the one or more parameters including a threshold number of data associated with a command, a threshold number of commands issued associated with at least the threshold number of data, a threshold number of commands issued but not executed, or any combination thereof; and performs data communication with the memory system according to the second rate.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: configure an interface to operate according to a first rate, wherein the first rate is one of a set of rates each corresponding to a respective data transfer rate between a controller and a memory system via the interface; switch the interface from the first rate to a second rate of the set of rates based on one or more commands from the controller to the memory system satisfying one or more parameters, the one or more parameters including a threshold number of data associated with a command, a threshold number of commands issued associated with at least the threshold number of data, a threshold number of commands issued but not executed, or any combination thereof; and perform data communication with the memory system according to the second rate.

[0008] Describe a method. The method may include: configuring an interface to operate according to a first rate, wherein the first rate is one of a set of rates each corresponding to a corresponding data transfer rate between a controller and a memory system via the interface; switching the interface from the first rate to a second rate of the set of rates based on one or more commands from the controller to the memory system satisfying one or more parameters, the one or more parameters including a threshold number of data associated with a command, a threshold number of commands issued associated with at least the threshold number of data, a threshold number of commands issued but not executed, or any combination thereof; and performing data communication with the memory system according to the second rate. Attached Figure Description

[0009] Figure 1 This document describes an example of a system that supports rate adjustment of the memory interface, based on the examples disclosed herein.

[0010] Figure 2This document describes an example of a process flow for supporting speed adjustment of the memory interface, based on the examples disclosed herein.

[0011] Figure 3A and 3B This document describes an example of a parameter scheme that supports rate adjustment of the memory interface, based on the examples disclosed herein.

[0012] Figure 4 A block diagram illustrating a memory device that supports rate adjustment of the memory interface, based on examples disclosed herein.

[0013] Figure 5 The flowchart illustrates one or more methods for supporting rate adjustment of the memory interface based on the examples disclosed herein. Detailed Implementation

[0014] The host system and memory system can communicate via an interface (e.g., at the host system) according to various modes and data transfer rates. For example, the host system can configure the interface to operate according to a low-speed mode or a high-speed mode (e.g., burst mode), and possibly other modes. The host system can further configure the interface to operate at different data transfer rates within a mode. For example, when operating in a given mode, the host system can set the interface to one of a set of gears (e.g., gear rates) associated with the mode, where each gear may correspond to a different data transfer rate. In some instances, the host system can set the gear of the interface based on the frequency with which the host system issues commands to the memory system (e.g., commands that cause data to be transferred via the interface, such as read or write commands, and other commands). Therefore, in some cases, if the host system issues commands relatively infrequently, the host system can set the interface to a relatively low gear (e.g., corresponding to a relatively low data transfer rate), and if the host system issues commands relatively frequently, the host system can set the interface to a relatively high gear (e.g., corresponding to a relatively high data transfer rate).

[0015] However, in some cases, setting the interface level based on command frequency can reduce data rates, increase power consumption, or have one or more other disadvantages associated with the performance of the host system and memory system. For example, during video playback, the host system may issue commands (read commands) for a large amount of data (e.g., approximately every 200 milliseconds) relatively infrequently due to the transmission of such a large amount of data (e.g., 512 kilobytes (KB) of data). Therefore, in some cases, the host system may set the interface level to a low level based on issuing commands at a low frequency, which can result in slower data transmission compared to operating the interface at a high level, thereby increasing latency and reducing system performance. Additionally, in some cases, operating the interface at a low level can increase the power consumption of the host system (e.g., and the memory system). For example, a lower level may correspond to lower instantaneous power consumption than a higher level, but a higher level can support faster data transmission and therefore allow for earlier deactivation of one or more components of the host system and / or memory system. Therefore, depending on the difference in instantaneous power and duration of activation of various components, as well as other factors, using a lower power level may, in some cases, actually lead to increased total power consumption and longer data transmission time compared to using a higher power level. Thus, in some situations, operating the interface at a higher power level but for a shorter period can reduce power consumption (e.g., although a higher power level corresponds to increased instantaneous power consumption during the data transmission cycle).

[0016] This document describes techniques, systems, and apparatuses for level management of communication interfaces, which can improve level selection schemes. For example, a host system can configure an interface to operate according to a first level (e.g., a first data transfer rate) and can communicate data with a memory system via the interface according to the first level. The host system can adjust the level of the interface in response to one or more commands from the host system satisfying one or more parameters from a set of parameters. For example, the host system can determine whether the size of a command (e.g., the amount of data transferred based on the command) satisfies a threshold size. Alternatively, the host system can determine whether at least a threshold number of commands within a set of tracking commands have at least a threshold size. Alternatively, the host system can determine whether the queue depth (e.g., the number of commands issued but not executed) satisfies a threshold queue depth. If the host system determines that at least one of the parameters is satisfied (e.g., the command size satisfies a threshold size, at least a threshold number of commands have at least a threshold size, and the queue depth satisfies a threshold queue depth), then the host system can switch the interface to a second level (e.g., a second data transfer rate) and can communicate data with the memory system according to the second level. Alternatively, if the host system determines that each of the parameters has not been met, the host system may maintain the interface in the first tier. In some instances, the second tier may be higher than the first tier (e.g., corresponding to a higher data transfer rate than the first tier).

[0017] The aspects described in this article, and others, can lead to reduced power consumption, reduced data transmission latency, or other types of improved system performance. For example, at least some data transmissions can be performed at higher rates and lower latency compared to using other throttling techniques, which can further allow for earlier deactivation of various system components, thereby resulting in power savings.

[0018] Firstly, in reference Figure 1 The features of this disclosure are described within the context of the system. (Referencing...) Figure 2 , 3A The features of this disclosure are described in the context of the process flow and parameter scheme of 3B. (See references...) Figure 4 and 5 The device diagrams and flowcharts related to the rate adjustment of the memory interface further illustrate and describe these and other features of this disclosure in the context of the device diagrams and flowcharts.

[0019] Figure 1 This document describes an example of a system 100 that supports rate adjustment of the memory interface, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., an airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment or networked commercial device), or any other computing device that includes memory and processing devices.

[0022] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, host system 105 may use memory system 110 to write data to and read data from memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM slot interfaces supporting DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be included in host system controller 106 of host system 105 and memory system controller 115 of memory system 110, or may be supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface of each memory device 130 included in memory system 110 or via a corresponding physical host interface of each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 (e.g., via an interface) to perform operations such as reading data, writing data, erasing data, or refreshing data, and other such operations at the memory device 130, which are generally referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, discarded item collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system having dedicated (e.g., hard-coded) logic that performs the operations attributed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and the data may be subsequently retrieved or manipulated (e.g., updated) within local memory 120 by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0029] although Figure 1 The memory system 110 described herein has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 (which may be internal to the memory device 130) to perform the functions attributed herein to the memory system controller 115. Generally, one or more functions attributed herein to the memory system controller 115 may, in some cases, be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130, at least partially managed by the memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115 or perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described above, memory device 130-a may include local controller 135-a and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) when configured to store two bits of information, as three-level cells (TLC) when configured to store three bits of information, as four-level cells (QLC) when configured to store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells may provide greater storage density compared to SLC memory cells, but may involve narrower read or write margins or greater complexity in some cases to support the circuitry.

[0034] In some cases, plane 165 may refer to several groups of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which concurrent operations can occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d respectively within planes 165-a, 170-b, 170-c, and 170-d, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, concurrent operations performed in different planes 165 may be subject to one or more restrictions, such as concurrent operations performed on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared between planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level) but erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., partially concurrently programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., partially concurrently erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, an older page 175 may not be updated until the entire block 170 containing page 175 is erased in some cases.

[0037] In some instances, host system 105 and memory system 110 may transmit information (e.g., data, commands) via an interface such as a physical host interface. In some cases, memory system controller 115 may communicate with one or more of the memory devices 130 via an interface. The communication architecture of the interface may include multiple layers (e.g., layers of a protocol stack) through which information is transmitted. For example, the communication architecture may include an application layer, a UFS Transport Protocol (UTP) layer, a Unipro protocol stack (e.g., containing a UTP layer), and a physical layer (e.g., a UFS Interconnect (UIC) layer) or a combination thereof, and other layers. In some instances, the application layer manages Small Computer System Interface (SCSI) commands, such as task management functions for command queue control, device power management operations, commands communicating with the physical layer, and queue requests for modifying and / or retrieving configuration information associated with host system 105 (e.g., or memory system 110), as well as other commands and operations. In some cases, the Unipro protocol stack may be managed by a Device Management Entity (DME). The DME manages the transmission of commands, operations, requests, and so on, across the various layers of the communication architecture. For example, the DME can route commands received from a higher layer (e.g., the application layer) to the physical layer and can route commands and data received at the physical layer to higher layers. In some instances, commands and data can be transmitted between devices (e.g., between host system 105 and memory system 110, and between memory system controller 115 and memory device 130) via the physical layer. In some cases, the physical layer can operate according to the MPHY protocol.

[0038] In some instances, the interface can operate according to various operating modes. For example, the interface can operate according to a low-speed mode and a high-speed mode. In some cases, the high-speed mode may correspond to an operating mode in which information is transmitted in bursts of data (e.g., and thus may be called burst mode).

[0039] Within each operating mode, the interface can operate according to different data transfer rates (which may be referred to as gears). For example, if operating in a low-speed mode, the interface can operate according to one of the first set of gears associated with low-speed mode. Alternatively, if operating in a burst mode, the interface can operate according to one of the second set of gears associated with burst mode. In some instances, the controller (e.g., host system controller 106, memory system controller 115) can change the interface gear. For example, different commands can be associated with different speed requirements. For instance, commands associated with transmitting video data (e.g., read commands, write commands) can be associated with different speed requirements than commands associated with transmitting image data and other instances. Therefore, the controller can change the interface gear to meet the speed requirements associated with different commands. In some cases, the DME can support the controller changing (e.g., switching) the interface gear. For example, the Unipro stack may contain one or more registers that can be read or written via the DME, and a register among the one or more registers can store the current gear of the interface. Therefore, the controller (e.g., via DME) can determine the current gear of the interface by reading the register and can change the gear of the interface by writing the new gear to the register.

[0040] In some instances, the controller may set the interface level based on the frequency of commands issued by the controller (e.g., based on command density). However, in some cases, setting the level based on command frequency can reduce the data rate and performance of the host system 105 and the memory system 110. For example, during video playback, the controller may issue commands (read commands) for a large amount of data (e.g., approximately every 200 milliseconds) relatively infrequently due to the transmission of a relatively large amount of data (e.g., 512KB of data). Therefore, the controller may set the interface level to a low level based on the low frequency of command issuance, thus slowing down data transmission, increasing latency, and degrading system performance. Additionally, in some cases, operating the interface at a low level can increase power consumption at the host system 105 (e.g., and the memory system 110). For example, a lower level may correspond to lower instantaneous power consumption than a higher level, but a higher level can support faster data transmission and therefore allow for earlier deactivation of one or more components of the host system 105 and / or the memory system 110. Therefore, using a lower level may result in increased total power consumption and longer data transmission time compared to using a higher level.

[0041] To reduce power consumption and improve system performance, controllers (e.g., host system controller 106, memory system controller 115) may support an improved gear selection scheme. For example, the controller may configure the interface to operate according to a first gear and to communicate data with, for example, memory system 110 via the interface according to the first gear. The controller may switch the interface gear in response to one or more commands from the controller satisfying one or more of a set of parameters. For example, the controller may determine whether the command size satisfies a threshold size, whether the queue depth satisfies a threshold queue depth, whether at least a threshold number of commands within a set of tracking commands have at least a threshold size, or a combination thereof. If the controller determines that at least one of the parameters is satisfied (e.g., the command size satisfies a threshold size, at least a threshold number of commands have at least a threshold size, and the queue depth satisfies a threshold queue depth), then the controller may switch the interface to a second gear (e.g., a second data transfer rate) and communicate data with memory system 110 according to the second gear. Alternatively, if the controller determines that each of the parameters is not satisfied, then the controller may keep the interface in the first gear. In some instances, the second tier can be higher than the first tier (e.g., corresponding to a higher data transfer rate than the first tier). In this way, power savings can be achieved because at least some data transfers can be performed at a higher rate and with lower latency, thereby allowing for earlier deactivation of individual system components.

[0042] System 100 may include any number of non-transitory computer-readable media that support rate adjustment of the memory interface. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media containing instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0043] Figure 2 This describes an example of process flow 200 for supporting memory interface speed adjustment based on the examples disclosed herein. Process flow 200 can be generated by a host system (e.g., refer to [references to other systems]). Figure 1 The process flow 200 can be executed by components of the host system 105 (as described). For example, the process flow 200 can be executed by the host system (e.g., reference to...). Figure 1The process flow 200 describes the execution of a controller (e.g., host system controller 106). The process flow 200 can depict a process for selecting a data transfer rate, which can be implemented to reduce latency, increase data rate, improve system performance, reduce power consumption, and other benefits. Aspects of the process flow 200 can be implemented by the controller and other components. Alternatively, aspects of the process flow 200 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to the host system controller 106). For example, instructions, when executed by the controller (e.g., host system controller 106), can cause the controller to perform the operation of the process flow 200.

[0044] In the following description of process flow 200, operations may be performed in different orders or at different times. Some operations may also be omitted from process flow 200, and others may be added to process flow 200.

[0045] In 205, it can be configured for use in controller and memory systems (e.g., reference). Figure 1 An interface (e.g., a physical host interface) for transferring information between the described memory systems 110 operates according to a first rate (e.g., a first gear in a set of gears). For example, a controller (e.g., host system controller 106) can be configured to operate the interface according to the first rate. The first rate may correspond to a first data transfer rate between the controller and the memory system. In some instances, the controller can configure the interface to operate according to the first rate by issuing a DME command that writes a first rate (e.g., a value or exponent corresponding to the first rate) indicating the current rate of the interface to a register.

[0046] In some instances, rate groups may correspond to burst modes (e.g., high-speed modes) associated with the interface. For example, the controller may operate the interface according to various operating modes, such as low-speed and burst modes, and each operating mode may be associated with multiple rates (e.g., gears). In some cases, the controller may initially configure the interface to operate according to low-speed mode (e.g., after the host system is powered on or reset). The controller may switch the interface to operate according to burst mode (e.g., during normal operation of the host system) and may (e.g., initially) select and configure a first rate for the interface. In some instances, the first rate may correspond to a relatively low data transfer rate (e.g., a relatively low gear) associated with the burst mode. For example, the first rate may correspond to the minimum rate in the rate group (e.g., the lowest gear).

[0047] At 210, it can be evaluated whether a command from the controller to the memory system is associated with at least a threshold amount of data. For example, the controller can determine whether the size of the command meets (e.g., greater than, greater than, or equal to) a threshold size. The size of the command may correspond to the amount of data (e.g., the amount of data read from the memory system, the amount of data written to the memory system) based on command communication (e.g., transmission). Therefore, the controller can determine whether the amount of data associated with the command (e.g., transmitted in response to the command) meets a threshold amount of data (e.g., 4KB of data or some other amount of data). In some instances, the command may be an unissued command. In some instances, the command may correspond to a command that the controller can issue next.

[0048] If the controller determines at 210 that the size of the command fails to meet a threshold size, then the controller may execute 215. At 215, the number of issued but not executed commands from the controller to the memory system may be evaluated to see if it meets the threshold number of issued but not executed commands. For example, the controller may determine the queue depth of a queue of issued commands from the controller that remain unexecuted (e.g., via the memory system), where the queue depth corresponds to the number of commands contained in the queue. The controller may determine whether the queue depth meets (e.g., is greater than, greater than, or equal to) a threshold queue depth. That is, the controller may determine whether the number of issued but not executed commands from the controller to the memory system meets the threshold number of issued but not executed commands. Additional details related to determining whether the threshold queue depth is met are referenced below. Figure 3B describe.

[0049] If the controller determines at 215 that the queue depth fails to meet a threshold queue depth, then the controller may execute 220. At 220, the value of a historical flag (e.g., stored at the controller) may be evaluated. For example, the controller may determine whether the historical flag is set to a first value (e.g., bit value '1', bit value '0') indicating operation of the interface according to a second rate in a rate group (e.g., a second gear in a gear group). For example, the controller may be configured to track the history associated with commands issued from the controller to (e.g., executed by) the memory system. To track the history, the controller may track a first number of issued (e.g., executed) commands and determine how many commands within the first number of issued commands have at least a threshold size. For example, the controller may determine (e.g., track) whether at least a threshold number of commands in the first number of issued commands are associated with at least a threshold amount of data. That is, the controller may determine whether at least a threshold number of commands in the first number of issued commands have a size that meets (e.g., is greater than, greater than, or equal to) the threshold size.

[0050] If the first number of issued commands contains at least a threshold number of commands having at least a threshold size, then the controller may set the history flag to a first value. Alternatively, if the first number of issued commands fails to contain at least a threshold number of commands having at least a threshold size, then the controller may set the history flag to a second value (e.g., bit value '0', bit value '1') indicating operation of the interface according to the first rate. In some instances, the controller may set the history flag to a second value in response to the expiration of a timer associated with inactivity in communication between the controller and the memory system. Therefore, at 220, the controller may determine the value of the history flag and whether the history flag is set (e.g., previously set by the controller) to a first value or a second value. Additional details related to setting the history flag are referenced below. Figure 3A describe.

[0051] If the controller determines at 220 that the history flag is set to a second value, then the controller may execute 225. At 225, data may be transferred between the controller and the memory system via the interface according to a first rate. For example, the controller may prevent the interface from switching to a second rate in response to determining that the command size fails to meet a threshold size, the queue depth fails to meet a threshold queue depth, and the history flag is set to a second value (e.g., a first number of issued commands fails to contain at least a threshold number of commands with at least a threshold size). For example, the second rate may correspond to a relatively high data transfer rate associated with a burst mode (e.g., a relatively high gear), such as the maximum rate in a rate group (e.g., the highest gear in a gear group). The command size failing to meet the threshold size, the queue depth failing to meet the threshold queue depth, and the history flag being set to a second value may indicate to the controller that a relatively small amount of data (e.g., if present) will be transferred between the controller and the memory system (e.g., in the near future, due to currently issued and not executed commands, or due to the next issued command) or that the level of communication activity between the controller and the memory system may be relatively low. Therefore, a high data transfer rate is not required to transfer any such data. Therefore, in order to save power, the controller can maintain the interface configuration according to the first rate and can transmit data according to the first rate (e.g., if present).

[0052] If at 210 the controller determines that the command size meets the threshold size, then the controller may execute steps 230 to 245 as follows. Alternatively, if at 215 the controller determines that the queue depth meets the threshold queue depth, then the controller may execute steps 230 to 245 as follows. Alternatively, if at 220 the controller determines that the history flag is set to the first value, then the controller may execute steps 230 to 245 as follows. That is, if the controller determines that the command size meets the threshold size, the queue depth meets the threshold queue depth, the history flag is set to the first value, or any combination thereof, then the controller may execute steps 230 to 245 as follows.

[0053] At 230, the interface can be switched from a first rate to a second rate. For example, the controller can switch the interface from a first rate to a second rate in response to determining that the command size meets a threshold size, the queue depth meets a threshold queue depth, the history flag is set to a first value, or any combination thereof. For example, the command size meeting a threshold size, the queue depth meeting a threshold queue depth, and / or the history flag being set to a first value can indicate to the controller that a relatively large amount of data will be transferred between the controller and the memory system (e.g., in the near future, due to currently issued but not executed commands, or due to the next issued command) or that the level of communication activity between the controller and the memory system can be relatively high. Therefore, a high data transfer rate allows the controller and memory system to transfer any data faster, thereby allowing for earlier deactivation of individual system components and reduced power consumption. Therefore, the controller can switch the interface from a first rate to a second rate corresponding to a higher data transfer rate than the first rate (e.g., the maximum rate in a rate group). In some instances, the controller can switch the interface from a first rate to a second rate by issuing a DME command that writes a second rate (e.g., a value or exponent corresponding to the second rate) indicating the current rate of the interface to a register.

[0054] In 235, data can be transferred between the controller and the memory system at a second rate. For example, the controller can communicate with the memory system via the interface at the second rate by switching the interface to the second rate.

[0055] At 240, the interface can be switched from a second rate to a first rate. For example, the controller may determine that one or more commands from a second group of commands instruct the controller to switch the interface from a second rate to a first rate. For instance, the controller may determine that commands from the second group (e.g., commands to be issued next) failed to meet a threshold size, the queue depth associated with the second group failed to meet a threshold queue depth, and a history flag was set to a second value (e.g., based on the second group). Therefore, the controller can switch the interface from a second rate to a first rate. In some instances, the controller can switch the interface from a second rate to a first rate by issuing a DME command that writes a first rate (e.g., a value or exponent corresponding to the first rate) indicating the current rate of the interface to a register.

[0056] At 245, second data (e.g., associated with one or more commands of a second group) can be transferred between the controller and the memory system at a first rate. For example, the controller can communicate second data with the memory system at the first rate by switching the interface from the second rate to the first rate.

[0057] Figure 3A This describes an example of a parameter scheme 300 that supports memory interface rate adjustment, based on the examples disclosed herein. Parameter scheme 300 can be found in the reference... Figure 1 The components of the described host system 105 are implemented. For example, parameter scheme 300 may be implemented by the host system (e.g., reference...). Figure 1 The controller implementation of the host system controller 106 described herein. Parameter scheme 300 can be implemented by the controller to support a data transfer rate selection scheme, which can be implemented to reduce latency, increase data rate, improve system performance, reduce power consumption, and other benefits.

[0058] Parameter scheme 300 describes a history 305 that indicates whether the value of flag 320 is set to a first value or a second value. For example, history 305 may correspond to a set of issued (e.g., executed, not executed, or both) commands traced by the controller from the controller to the memory system. In some instances, the number of commands included in history 305 (e.g., traced by the controller) may be indicated by a maxCommand parameter stored at the controller (e.g., in a register). In some cases, the controller may set the value of the maxCommand parameter (e.g., and the value of the maxCommand parameter may be changed at any time during operation). In other cases, the value of the maxCommand parameter may be a defined value (e.g., a value programmed during controller manufacturing).

[0059] History 305 may include command 310 and / or command 315. For example, history may include command 310-a, command 310-b, command 310-c, command 310-d, command 315-a, command 315-b, and command 315-c. Command 310 may correspond to a command having a corresponding size that satisfies (e.g., greater than, greater than, or equal to) a threshold size. That is, command 310 may correspond to a command that causes at least a threshold amount of data to be transferred between the controller and the memory system. Command 315 may correspond to a command having a corresponding size that fails to satisfy the threshold size. It should be noted that, for illustrative purposes, Figure 3A History 305 is described as containing both commands 310 and 315; however, the principles disclosed herein are suitable for and applicable to history 305 containing any number of commands 310 and 315.

[0060] The controller can set the flag value based on the number of commands 310 included in history 305. For example, the controller can be configured to track whether the number of commands 310 meets (e.g., greater than, greater than, or equal to) a threshold number. If the controller determines that the number of commands 310 meets the threshold number, then the controller can set flag 320 to a first value (e.g., bit value '1', bit value '0'), where the first value indicates that the controller's interface (e.g., a physical host interface) operates at a first rate (e.g., in burst mode). Alternatively, if the controller determines that the number of commands 310 does not meet the threshold number, then the controller can set flag 320 to a second value (e.g., bit value '0', bit value '1'), where the second value indicates that the interface operates at a second rate (e.g., in burst mode). In some cases, the controller can configure the interface. In some instances, the first rate may correspond to a higher data transfer rate than the second rate. In some instances, the first rate may correspond to the maximum rate in burst mode and the second rate may correspond to the minimum rate in burst mode.

[0061] In some instances, the value of the threshold number can be indicated by the perfCommand parameter stored at the controller (e.g., in a register). That is, the number of commands 310 included in history 305 that cause the controller to set flag 320 to the first value can be indicated by the perfCommand parameter. In some cases, the controller can set the value of the perfCommand parameter (e.g., and the value of the perfCommand parameter can be changed at any time during operation). In other cases, the value of the perfCommand parameter can be a defined value (e.g., a value programmed during controller manufacturing).

[0062] In some instances, the controller may set the value of flag 320 based on timer 325 associated with inactivity in communication between the controller and the memory system. For example, timer 325 may run when no data is being transferred between the controller and the memory system. Therefore, timer 325 expiring may indicate that no data has been transferred between the controller and the memory system for at least the duration of timer 325. In some instances, the interface may be idle if no data is being actively transferred via the interface. In response to timer 325 expiring, the controller may set flag 320 to a second value that indicates the interface to operate at a second (e.g., lower) rate. In some cases, the controller may clear commands 310 and 315 contained in history 305 in response to timer 325 expiring and may begin tracking new commands issued after timer 325 expiring.

[0063] By tracking history 305, the controller can reduce the frequency of interface rate changes. For example, history 305 can indicate how frequently commands 310 with at least a threshold size have recently been issued. A high frequency of commands 310 can indicate that another command 310 is more likely to be issued. Therefore, even if the size of the next issued command fails to meet the threshold size and the queue depth of the queue of issued but not executed commands fails to meet the threshold queue depth, the controller can maintain the interface at a first (e.g., higher) rate when at least a threshold number of commands 310 have recently been issued. This reduced frequency of interface rate switching can lead to a decrease in latency associated with the interface rate switching, thereby improving system performance.

[0064] Figure 3B This describes an example of parameter scheme 330 that supports memory interface rate adjustment, based on the examples disclosed herein. Parameter scheme 330 can be found in the reference... Figure 1 The components of the described host system 105 are implemented. For example, parameter scheme 330 may be implemented by the controller of the host system (e.g., reference...). Figure 1 The host system controller 106 described is implemented. Parameter scheme 330 can be implemented by the controller to support a data transfer rate selection scheme, which can be implemented to reduce latency, increase data rate, improve system performance, reduce power consumption, and other benefits.

[0065] Parameter scheme 330 describes queue 335. Queue 335 may indicate whether the controller's interface (e.g., a physical host interface) will operate at a first rate corresponding to a high (e.g., maximum) data transfer rate (e.g., burst mode) or a second rate corresponding to a low (e.g., minimum) data transfer rate (e.g., burst mode). For example, the controller may issue a command to the memory system before a previously issued command has been completed (e.g., executed). Such issued commands may be contained in queue 335 and may be executed as the memory system becomes available to execute the command. For example, queue 335 may contain commands 340 corresponding to issued but not executed commands from the controller to the memory system. For example, queue 335 may contain commands 340-a, 340-b, and 340-c, each corresponding to issued but not executed commands (e.g., although any number of commands 340 contained in queue 335 is possible). In some instances, the number of commands 340 contained in queue 335 may be referred to as the queue depth of queue 335.

[0066] The controller can determine whether the queue depth of queue 335 meets (is greater than, greater than, or equal to) a threshold 345 and can determine the data transmission rate of the interface based on whether the threshold 345 is met. For example, if the queue depth meets the threshold 345, the controller can set (e.g., switch) the interface to a first rate or maintain the interface at the first rate (e.g., if the interface is currently set to the first rate). Alternatively, if the queue depth fails to meet the threshold 345, the controller can set (e.g., switch) the interface to a second rate or maintain the interface at the second rate (e.g., if the interface is currently set to the second rate). Figure 3B In an example, queue 335 may have a queue depth of three commands 340 and threshold 345 may correspond to a queue depth of two commands 340. Therefore, the controller may determine that the queue depth meets threshold 345 and may set the interface to (e.g., or maintain the interface at) a first rate corresponding to a high (e.g., maximum) data transfer rate.

[0067] Figure 4 A block diagram 400 illustrates a host system 420 that supports rate adjustment of the memory interface according to an example disclosed herein. The host system 420 may be used as a reference. Figure 1 Examples of aspects of the host system described in section 3. Host system 420 or its various components may be examples of components for performing various aspects of rate adjustment of the memory interface, as described herein. For example, host system 420 may include configuration component 425, switching component 430, communication component 435, parameter component 440, command component 445, flag component 450, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0068] Configuration component 425 may be configured to, or otherwise support, means for configuring the interface to operate at a first rate, wherein the first rate is one of a set of rates each corresponding to a respective data transfer rate between the controller and the memory system via the interface. Switching component 430 may be configured to, or otherwise support, means for switching the interface from the first rate to a second rate in the rate set based at least in part on one or more commands from the controller to the memory system satisfying one or more parameters, wherein the one or more parameters include a threshold number of data associated with a command, a threshold number of commands issued associated with at least a threshold number of data, a threshold number of commands issued but not executed, or any combination thereof. Communication component 435 may be configured to, or otherwise support, means for data communication with the memory system at the second rate.

[0069] In some instances, parameter component 440 may be configured to or otherwise support a component for determining whether a first command among one or more commands is associated with at least a threshold amount of data, wherein switching the interface from a first rate to a second rate is at least in part based on determining that the first command is associated with at least a threshold amount of data.

[0070] In some instances, parameter component 440 may be configured to, or otherwise support, a means for determining whether the number of issued and unexecuted commands contained in one or more commands meets a threshold number of issued and unexecuted commands, wherein switching the interface from a first rate to a second rate is based at least in part on determining that the number of issued and unexecuted commands meets the threshold number of issued and unexecuted commands.

[0071] In some instances, command component 445 may be configured to, or otherwise support means for tracking a first number of commands issued by the controller to the memory system, the first number of commands comprising one or more commands. In some instances, parameter component 440 may be configured to, or otherwise support means for determining whether the first number of commands contains at least a threshold number of issued commands associated with at least a threshold number of data, wherein switching the interface from a first rate to a second rate is at least in part based on determining that the first number of commands contains at least a threshold number of issued commands associated with at least a threshold number of data.

[0072] In some instances, the flag component 450 may be configured to or otherwise support the issuance of commands to set a flag to a first value based at least in part on determining a first number of commands, including at least a threshold number of data associated with a first threshold number, wherein the first value indicates operation of an interface according to a second rate, wherein switching the interface from the first rate to the second rate is at least in part based on setting the flag to the first value.

[0073] In some instances, the flag component 450 may be configured or otherwise support a component for setting the flag to a second value, at least in part based on the expiration of a timer associated with inactivity in communication between the controller and the memory system, after the flag has been set to a first value, the second value indicating operation of the interface according to the first rate.

[0074] In some instances, the flag component 450 may be configured to or otherwise support a component for setting the flag to a second value, at least in part based on a second number of commands issued by the controller to the memory system and tracked by the host system, which fail to include at least a threshold number of data associated with the second value, after the flag is set to a first value. The second value indicates the operation interface according to the first rate.

[0075] In some instances, the first rate corresponds to a first data transmission rate and the second rate corresponds to a second data transmission rate, wherein the second data transmission rate is higher than the first data transmission rate.

[0076] In some instances, the first rate corresponds to the minimum rate in the rate group and the second rate corresponds to the maximum rate in the rate group.

[0077] In some instances, the switching component 430 may be configured to, or otherwise support, a means for switching the interface from a second rate to a first rate based at least in part on the failure of a second set of commands from the controller to satisfy each of one or more parameters. In some instances, the communication component 435 may be configured to, or otherwise support, a means for performing second data communication with the memory system according to the first rate.

[0078] In some instances, one or more parameters are each contained within a set of parameters. In some instances, the switch component 430 may be configured to, or otherwise support, a component for switching the interface from a first rate to a second rate based at least in part on one or more commands satisfying any parameter in the parameter set.

[0079] In some instances, rate groups correspond to burst modes associated with an interface, which are different from low-speed modes associated with the interface, and burst modes are associated with higher data transfer rates than low-speed modes.

[0080] Figure 5 The flowchart illustrates a method 500 for adjusting the rate of a supported memory interface according to an example disclosed herein. The operation of method 500 can be implemented by a host system or its components described herein. For example, the operation of method 500 can be implemented by a reference... Figures 1 to 4 The host system described performs the function. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the host system may use dedicated hardware to perform aspects of the described function.

[0081] In 505, the method may include configuring an interface to operate according to a first rate, wherein the first rate is one of a set of rates, each corresponding to a respective data transfer rate between the controller and the memory system via the interface. Operation 505 may be performed according to the examples disclosed herein. In some instances, aspects of operation 505 may be provided by reference. Figure 4 The configuration component 425 described is executed.

[0082] In 510, the method may include switching an interface from a first rate to a second rate in a rate group based at least in part on one or more commands from the controller to the memory system satisfying one or more parameters, wherein the one or more parameters include a threshold number of data associated with the command, a threshold number of commands issued associated with at least a threshold number of data, a threshold number of commands issued but not executed, or any combination thereof. Operation 510 may be performed according to the examples disclosed herein. In some instances, aspects of operation 510 may be derived from references... Figure 4 The described switch component 430 is executed.

[0083] In step 515, the method may include data communication with a memory system at a second rate. Operation 515 may be performed according to the examples disclosed herein. In some instances, aspects of operation 515 may be derived from references... Figure 4 The described communication component 435 is executed.

[0084] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: configuring an interface to operate according to a first rate, wherein the first rate is one of a set of rates each corresponding to a respective data transfer rate between a controller and a memory system via the interface; switching the interface from the first rate to a second rate in the rate set based at least in part on one or more commands from the controller to the memory system satisfying one or more parameters, the one or more parameters including a threshold number of data associated with a command, a threshold number of commands issued associated with at least a threshold number of data, a threshold number of commands issued but not executed, or any combination thereof; and performing data communication with the memory system according to the second rate.

[0085] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for determining whether a first command among one or more commands can be associated with at least a threshold number of data, wherein switching an interface from a first rate to a second rate may be based at least in part on determining that the first command can be associated with at least a threshold number of data.

[0086] Some examples of the method 500 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for determining whether the number of issued and unexecuted commands included in one or more commands meets a threshold number of issued and unexecuted commands, wherein switching an interface from a first rate to a second rate may be based at least in part on determining that the number of issued and unexecuted commands meets the threshold number of issued and unexecuted commands.

[0087] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: tracking a first number of commands issued by a controller to a memory system, the first number of commands comprising one or more commands; and determining whether the first number of commands contains at least a threshold number of issued commands associated with at least a threshold number of data, wherein switching the interface from a first rate to a second rate may be based at least in part on determining that the first number of commands contains at least a threshold number of issued commands associated with at least a threshold number of data.

[0088] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for issuing commands to set a flag to a first value based at least in part on determining a first number of commands including at least a threshold number of data associated with a first threshold number of data, wherein the first value indicates operation of an interface according to a second rate, wherein switching the interface from the first rate to the second rate may be based at least in part on setting the flag to the first value.

[0089] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for setting a flag to a second value, at least in part based on the expiration of a timer associated with inactivity in communication between the controller and the memory system, after setting a flag to a first value, wherein the second value indicates operation of the interface according to the first rate.

[0090] Some examples of the method 500 and device described herein may further include operations, features, circuitry, logic, components, or instructions for setting a flag to a second value after setting a flag to a first value, based at least in part on a second number of commands issued by the controller to the memory system and tracked by the device that fail to include at least a threshold number of data associated with the second value indicating operation of the interface according to a first rate.

[0091] In some instances of the method 500 and apparatus described herein, the first rate corresponds to a first data transmission rate and the second rate corresponds to a second data transmission rate, wherein the second data transmission rate is higher than the first data transmission rate.

[0092] In some instances of the method 500 and device described herein, the first rate corresponds to the minimum rate in the rate group and the second rate corresponds to the maximum rate in the rate group.

[0093] Some examples of the method 500 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for: switching an interface from a second rate to a first rate based at least in part on the failure of a second set of commands from the controller to satisfy each of one or more parameters; and performing second data communication with the memory system according to the first rate.

[0094] In some instances of the methods 500 and devices described herein, one or more parameters may each be included in a set of parameters. Some instances of the methods 500 and devices described herein may further include operations, features, circuitry, logic, components, or instructions for switching an interface from a first rate to a second rate based at least in part on one or more commands satisfying any parameter in the parameter set.

[0095] In some instances of the method 500 and device described herein, the rate group corresponds to a burst mode associated with an interface, which is different from the low-speed mode associated with the interface, and the burst mode is associated with a higher data transmission rate than the low-speed mode.

[0096] It should be noted that the above methods describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0097] Describe an apparatus. The apparatus may include a controller configured to communicate with a memory system via an interface, wherein the controller is configured such that the apparatus: configures the interface to operate at a first rate, wherein the first rate is one of a set of rates each corresponding to a respective data transfer rate between the controller and the memory system via the interface; switches the interface from the first rate to a second rate of the set of rates based at least in part on one or more commands from the controller to the memory system satisfying one or more parameters, the one or more parameters including a threshold number of data associated with a command, a threshold number of commands issued associated with at least the threshold number of data, a threshold number of commands issued but not executed, or any combination thereof; and performs data communication with the memory system according to the second rate.

[0098] In some instances of the device, the controller may be further configured such that the device determines whether a first command of the one or more commands can be associated with at least the threshold amount of data, wherein switching the interface from the first rate to the second rate may be based at least in part on determining that the first command can be associated with at least the threshold amount of data.

[0099] In some instances of the device, the controller may be further configured such that the device determines whether the number of issued but not executed commands included in the one or more commands meets the threshold number of issued but not executed commands, wherein switching the interface from the first rate to the second rate may be based at least in part on determining that the number of issued but not executed commands meets the threshold number of issued but not executed commands.

[0100] In some instances of the device, the controller may be further configured such that the device: tracks a first number of commands issued by the controller to the memory system, the first number of commands including the one or more commands; and determines whether the first number of commands includes at least a threshold number of issued commands associated with at least a threshold number of data, wherein switching the interface from the first rate to the second rate may be based at least in part on determining that the first number of commands includes at least a threshold number of issued commands associated with at least a threshold number of data.

[0101] In some instances of the device, the controller may be further configured such that the device sets a flag to a first value based at least in part on determining that the first number of commands contain at least a threshold number of commands associated with at least a threshold number of data, the first value indicating operation of the interface according to the second rate, wherein switching the interface from the first rate to the second rate may be based at least in part on setting the flag to the first value.

[0102] In some instances of the device, the controller may be further configured such that the device, after setting the flag to the first value, sets the flag to a second value at least in part based on the expiration of a timer associated with inactive communication between the controller and the memory system, the second value indicating operation of the interface according to the first rate.

[0103] In some instances of the device, the controller may be further configured such that the device sets the flag to a second value after setting the flag to the first value, at least in part based on a second number of commands issued by the controller to the memory system and tracked by the device failing to include at least a threshold number of commands associated with at least a threshold number of data, the second value indicating operation of the interface according to the first rate.

[0104] In some instances of the device, the first rate corresponds to a first data transmission rate and the second rate corresponds to a second data transmission rate, wherein the second data transmission rate is higher than the first data transmission rate.

[0105] In some instances of the device, the first rate corresponds to the minimum rate in the set of rates and the second rate corresponds to the maximum rate in the set of rates.

[0106] In some instances of the device, the controller may be further configured such that the device: switches the interface from the second rate to the first rate based at least in part on the failure of a second set of commands from the controller to satisfy each of the one or more parameters; and performs second data communication with the memory system according to the first rate.

[0107] In some instances of the device, the one or more parameters may each be contained in a set of parameters and the controller may be configured such that the device switches the interface from the first rate to the second rate based at least in part on the one or more commands satisfying any of the parameters in the set of parameters.

[0108] In some instances of the device, the set of rates corresponds to a burst mode associated with the interface, which is different from the low-speed mode associated with the interface, and the burst mode is associated with a higher data transmission rate than the low-speed mode.

[0109] The information and signals described herein can be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0110] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if there is any conductive path between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) can be open or closed, depending on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0111] The term "coupling" refers to the condition that changes from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). If, for example, a component of a controller couples other components together, then the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0112] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch positioned between two components is turned on, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0113] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0114] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after or after one or more other intermediate conditions or actions).

[0115] Additionally, the terms "directly in response to" or "directly responding to" may refer to a condition or action occurring directly as a result of a preceding condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" this other condition or action.

[0116] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0117] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0118] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." The detailed descriptions include specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0119] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a concatenated character following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0120] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the above functions can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0121] For example, the various specification boxes and components described in connection with this disclosure may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0122] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0123] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave) is included in the media definition. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically copy data magnetically, while optical discs copy data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0124] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure will be made, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: One or more controllers configured to communicate with a memory system via an interface, wherein the one or more controllers are configured to cause the device to: The interface is configured to operate according to a first rate, wherein the first rate is one of a set of rates, each corresponding to a corresponding data transfer rate between the one or more controllers and the memory system via the interface; Determine whether a threshold number of commands issued from the one or more controllers to the memory system within a duration satisfies one or more parameters, wherein the one or more parameters include a threshold number of commands issued associated with data of at least a threshold number, a threshold number of commands issued but not executed, or any combination thereof, wherein the threshold number is greater than one. Based on the duration, a flag value is set at least in part based on whether the threshold number of commands issued from the one or more controllers to the memory system satisfies the one or more parameters, wherein a first value of the flag is based on the one or more parameters being satisfied and a second value of the flag is based on the one or more parameters failing to be satisfied; The interface is switched from the first rate to the second rate in the set of rates, at least in part based on setting the value of the flag to the first value; Data communication is performed with the memory system according to the second rate; and After the value of the flag is set to the first value, the value of the flag is set to the second value, at least in part, based on the expiration of a timer associated with inactive communication between the one or more controllers and the memory system, the second value indicating operation of the interface according to the first rate.

2. The device of claim 1, wherein the one or more controllers are further configured to cause the device to: Whether a first command in the command to determine the number of thresholds is associated with at least the number of thresholds of data, wherein setting the value of the flag to the first value is at least in part based on determining that the first command is associated with at least the number of thresholds of data.

3. The device of claim 1, wherein the one or more controllers are further configured such that the device: Determine whether the number of issued but not executed commands among the commands included in the threshold number satisfies the threshold number of issued but not executed commands, wherein setting the value of the flag to the first value is at least partially based on determining that the number of issued but not executed commands satisfies the threshold number of issued but not executed commands.

4. The device of claim 1, wherein the one or more controllers are further configured such that the device: Tracking a first number of commands issued to the memory system by the one or more controllers, the first number of commands including the threshold number of commands; and Determining whether the first number of commands at least includes at least a threshold number of issued commands associated with at least a threshold number of data, wherein setting the value of the flag to the first value is at least in part based on determining that the first number of commands at least includes at least a threshold number of issued commands associated with at least a threshold number of data.

5. The device according to claim 1, wherein the first rate corresponds to a first data transmission rate and the second rate corresponds to a second data transmission rate, the second data transmission rate being higher than the first data transmission rate.

6. The device of claim 1, wherein the first rate corresponds to the minimum rate in the set of rates and the second rate corresponds to the maximum rate in the set of rates.

7. The device of claim 1, wherein the one or more controllers are further configured such that the device: Switching the interface from the second rate to the first rate is based at least in part on setting the value of the flag to the second value; and Second data communication is performed with the memory system at the first rate.

8. The device according to claim 1, wherein: The one or more parameters are each contained in a set of parameters; and The one or more controllers are configured such that the device, at least in part based on the number of commands according to the threshold, satisfies any parameter in the set of parameters to set the value of the flag to the first value.

9. The device of claim 1, wherein the set of rates corresponds to a burst mode associated with the interface, the burst mode being different from a low-speed mode associated with the interface, and the burst mode being associated with a higher data transmission rate than the low-speed mode.

10. An apparatus comprising: One or more controllers configured to communicate with a memory system via an interface, wherein the one or more controllers are configured to cause the device to: The interface is configured to operate according to a first rate, wherein the first rate is one of a set of rates, each corresponding to a corresponding data transfer rate between the one or more controllers and the memory system via the interface; Tracking a first number of commands issued to the memory system by the one or more controllers, the first number of commands including one or more commands; Determine whether the first number of commands at least contains a threshold number of issued commands associated with at least a threshold number of data, wherein switching the interface from the first rate to the second rate is at least in part based on determining that the first number of commands at least contains the threshold number of issued commands associated with at least the threshold number of data; The flag is set to a first value at least in part based on determining that the first number of commands at least contain a threshold number of commands issued that are associated with at least the threshold number of data, the first value indicating operation of the interface according to the second rate, wherein switching the interface from the first rate to the second rate is at least in part based on the flag being set to the first value; and The interface is switched from the first rate to the second rate of the set of rates based at least in part on one or more commands from the one or more controllers to the memory system satisfying one or more parameters, the one or more parameters including the threshold number of data associated with the command, the threshold number of commands issued associated with at least the threshold number of data, the threshold number of commands issued but not executed, or any combination thereof. Data communication is performed with the memory system according to the second rate; After setting the flag to the first value, the flag is set to a second value at least in part based on the expiration of a timer associated with inactive communication between the one or more controllers and the memory system, the second value indicating operation of the interface according to the first rate.

11. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: The configuration interface operates according to a first rate, wherein the first rate is one of a set of rates, each corresponding to a corresponding data transfer rate between the controller and the memory system via the interface. Determine whether a threshold number of commands issued from the controller to the memory system within a duration satisfies one or more parameters, wherein the one or more parameters include a threshold number of commands issued associated with at least a threshold number of data, a threshold number of commands issued but not executed, or any combination thereof, wherein the threshold number is greater than one; The value of a flag is set based on the duration, at least in part, whether the threshold number of commands issued from the controller to the memory system satisfies one or more parameters, wherein a first value of the flag is based on the one or more parameters being satisfied and a second value of the flag is based on the one or more parameters failing to be satisfied; The interface is switched from the first rate to the second rate in the set of rates, at least in part based on setting the value of the flag to the first value. Data communication is performed with the memory system according to the second rate; and After the value of the flag is set to the first value, the value of the flag is set to the second value, at least in part, based on the expiration of a timer associated with inactive communication between one or more controllers and the memory system, the second value indicating operation of the interface according to the first rate.

12. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: Whether a first command in the command to determine the number of thresholds is associated with at least the number of thresholds of data, wherein setting the value of the flag to the first value is at least in part based on determining that the first command is associated with at least the number of thresholds of data.

13. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: Determine whether the number of issued but not executed commands among the commands included in the threshold number satisfies the threshold number of issued but not executed commands, wherein setting the value of the flag to the first value is at least partially based on determining that the number of issued but not executed commands satisfies the threshold number of issued but not executed commands.

14. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: Tracking a first number of commands issued by the controller to the memory system, the first number of commands including the threshold number of commands; and Determining whether the first number of commands at least includes at least a threshold number of issued commands associated with at least a threshold number of data, wherein setting the value of the flag to the first value is at least in part based on determining that the first number of commands at least includes at least a threshold number of issued commands associated with at least a threshold number of data.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: At least in part, based on determining the first number of commands, which at least include a threshold number of commands associated with at least the threshold number of data, the value of the flag is set to the first value, the first value indicating operation of the interface according to the second rate; and After setting the value of the flag to the first value, the value of the flag is set to the second value at least in part based on the failure of a second number of commands issued by the controller to the memory system and tracked by the electronic device to include at least the threshold number of commands issued associated with at least the threshold number of data, the second value indicating operation of the interface according to the first rate.

16. A method comprising: The configuration interface operates according to a first rate, wherein the first rate is one of a set of rates, each corresponding to a corresponding data transfer rate between the controller and the memory system via the interface. Determine whether a threshold number of commands issued from the controller to the memory system within a duration satisfies one or more parameters, wherein the one or more parameters include a threshold number of commands issued associated with at least a threshold number of data, a threshold number of commands issued but not executed, or any combination thereof, wherein the threshold number is greater than one; The value of a flag is set based on the duration, at least in part, whether the threshold number of commands issued from the controller to the memory system satisfies one or more parameters, wherein a first value of the flag is based on the one or more parameters being satisfied and a second value of the flag is based on the one or more parameters failing to be satisfied; The interface is switched from the first rate to the second rate in the set of rates, at least in part based on setting the value of the flag to the first value. Data communication is performed with the memory system according to the second rate; and After the value of the flag is set to the first value, the value of the flag is set to the second value, at least in part, based on the expiration of a timer associated with inactive communication between one or more controllers and the memory system, the second value indicating operation of the interface according to the first rate.

17. The method of claim 16, further comprising: Whether a first command in the command to determine the number of thresholds is associated with at least the number of thresholds of data, wherein setting the value of the flag to the first value is at least in part based on determining that the first command is associated with at least the number of thresholds of data.

18. The method of claim 16, further comprising: Determine whether the number of issued but not executed commands among the commands included in the threshold number satisfies the threshold number of issued but not executed commands, wherein setting the value of the flag to the first value is at least partially based on determining that the number of issued but not executed commands satisfies the threshold number of issued but not executed commands.

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