Methods, apparatus and non-transitory computer-readable media that support real-time corrector checking

Abstract

This application relates to real-time correction checking. A read command can be received from a host device at a memory device. As part of an error control operation, a first set of error control bits can be generated for a set of data. Based on the first set of error control bits, a failure of a matching operation associated with the error control operation can be determined. Based on the determination of the failure of the matching operation, a second set of error control bits, different from the first set of error control bits, can be transmitted to the host device. The second set of error control bits can indicate that the matching operation has failed at the memory device.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 820,085, entitled “REAL TIME SYNDROME CHECK”, filed August 16, 2022, and U.S. Provisional Patent Application No. 63 / 236,962, entitled “REAL TIME SYNDROME CHECK”, filed August 25, 2021, each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves real-time corrector checking. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of them. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time, even without external power. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from external power. Summary of the Invention

[0006] This document describes a method. The method may include: receiving a read command associated with a set of data from a host device; generating a first set of error control bits for the set of data as part of an error control operation; determining that the first set of error control bits causes a matching operation associated with the error control operation to fail; and transmitting a second set of error control bits, different from the first set of error control bits, to the host device based at least in part on the failure of the matching operation caused by the first set of error control bits.

[0007] This document describes a method. The method may include: transmitting a read command to a memory device; receiving a set of data and a set of error control bits, at least in part based on the transmission of the read command; determining, at least in part based on the set of error control bits, that the set of error control bits causes a matching operation associated with an error control operation at the memory device to fail; and processing the set of data, at least in part based on the determination.

[0008] This document describes an apparatus. The apparatus may include: a memory array comprising an array of memory cells, each including a capacitor storage element; and circuitry coupled to the memory array and configured to cause the apparatus to: receive a read command associated with a set of data from a host device; generate a first set of error control bits for the set of data as part of an error control operation; determine that the first set of error control bits causes a matching operation associated with the error control operation to fail; and transmit a second set of error control bits, different from the first set of error control bits, to the host device based at least in part on the failure of the matching operation caused by the first set of error control bits.

[0009] This document describes an apparatus. The apparatus may include: circuitry configured to cause the apparatus to: transmit a read command to a memory device; receive a set of data and a set of error control bits, at least in part based on the transmission of the read command; determine, at least in part based on the set of error control bits, that the set of error control bits causes a matching operation associated with an error control operation at the memory device to fail; and process the set of data, at least in part based on the determination.

[0010] This document describes a non-transitory computer-readable medium. The non-transitory computer-readable medium may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a read command associated with a set of data from a host device; as part of an error control operation, generate a first set of error control bits for the set of data; determine that the first set of error control bits causes a matching operation associated with the error control operation to fail; and transmit a second set of error control bits, different from the first set of error control bits, to the host device, at least in part based on the failure of the matching operation caused by the first set of error control bits. Attached Figure Description

[0011] Figure 1 This section describes an example of a system that supports real-time corrector checking, based on examples disclosed herein.

[0012] Figure 2 This document describes an example of a signal graph supporting real-time corrector checking, based on examples disclosed herein.

[0013] Figure 3 This describes a set of instances that support real-time corrector checking based on examples disclosed herein.

[0014] Figure 4 A block diagram of a memory device supporting real-time corrector checking is shown, based on examples disclosed herein.

[0015] Figure 5 A block diagram of a host device supporting real-time corrector checking is shown, based on examples disclosed herein.

[0016] Figure 6 and 7 The flowchart illustrates one or more methods for supporting real-time corrector checking based on examples disclosed herein. Detailed Implementation

[0017] A memory device can store data for a host device, which can later access the stored data. In some instances, failures can occur when data is transferred between the host device and the memory device. In some instances, failures can occur when the host device treats invalid data received from the memory device (or data determined to have been received from the memory device) as valid data. The acceptable failure rate associated with storing and accessing data stored in the memory device can be based on the consequences of the failure—for example, the acceptable failure rate for a system used in an autonomous vehicle might be more stringent than for other applications in desktop computing.

[0018] For security applications, enhanced techniques can be used to reduce the failure rate associated with memory devices. Error management signaling can be transmitted between the memory device and the host device to reduce the number of failures. Error management signaling may include valid operation signals (e.g., a valid read operation flag (VROF) signal), corrector check signals, master error log signals, link error correction code (ECC) signals, or any combination thereof. In some instances, a subset of available protocols for transmitting data between the host device and the memory device may support communication that complements one or more of the error management signals.

[0019] The host device may use protocols that do not support transmitting one or more of the valid operation signals, corrector check signals, or master error status signals—however, in some instances, the memory device may still generate the underlying data for the signals. For example, some such memory systems may implement communication protocols (e.g., special function selection protocols, such as the DSF+ protocol) that include dedicated intervals or bit sets for indicating that the master error log contains information from the host device. However, other memory systems may not implement communication protocols that include dedicated intervals or bit sets. Therefore, if the host device does not implement some protocols, it may be unable to exchange supplementary error management signaling with the memory device. For example, the host device may be unable to receive corrector check signals and therefore may be unable to determine the result of the corrector check operation performed at the memory device. As a result, communication errors between the memory device and the host device may increase (e.g., if the host device uses invalid data obtained based on incorrectly correcting a set of data containing multiple bit errors after determining that a set of data contains a unit error). Consequently, the failure rate associated with the memory device may also increase, and in some cases, may exceed a threshold.

[0020] To enable the transmission of calibration check information when using protocols that do not support explicit communication calibration check information, the calibration check information can be encoded into signaling supported by the protocol (e.g., existing or standardized protocols such as link ECC protocols). In some instances, the calibration check information can be encoded into error management signals (also known as link error management signals), which are used to prevent errors that may occur during data transmission. For example, the result of the calibration check can be indicated by transmitting a specific value during the duration of transmitting the link error management signal. Such a specific value can be used instead of a separate set of bits generated for transmitting the link error management signal. The specific value can indicate to the host device that the calibration check failed at the memory device—for example, the calibration bits stored for a requested set of data when written to the memory device do not match the calibration bits calculated for the requested set of data when retrieved from the memory device.

[0021] By replacing the parity value generated for the set of data with a specific value in the transmission link error management signal and an indication of a parity check fault (which may also be called a parity check error), the host device can detect a parity check fault at the memory device without using an explicit parity check signal.

[0022] The features of this disclosure are first described in the context of a system. The features of this disclosure are also described in the context of signal diagrams and process flows. These and other features of this disclosure are further illustrated and described with reference to device diagrams and flowcharts relating to real-time corrector checks.

[0023] Figure 1 This describes an example of a system 100 that supports real-time corrector checking, based on examples disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0024] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0025] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0026] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0027] Memory device 110 may be operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave or dependent device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0028] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0029] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such examples, processor 125 may be an example of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other examples. In some examples, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0030] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0031] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more segments), wherein each memory cell is operable to store at least one bit of data. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0032] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and is operable to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0033] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105, or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0034] Local memory controller 165 (e.g., locally for memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and local memory controller 165 or external memory controller 120 may perform the various functions described herein. Thus, local memory controller 165 is operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0035] External memory controller 120 may be operable to enable the transfer of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165) or vice versa.

[0036] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0037] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0038] In some instances, CA channel 186 may be operable to transmit commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, a command carried by CA channel 186 may include a read command with an address containing desired data. In some instances, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for decoding one or more of the address or command data.

[0039] In some instances, the CK channel 188 may be operable to transmit one or more clock signals between the host device 105 and the memory device 110. Each clock signal may be operable to oscillate between high and low states and may support coordination (e.g., in timing) between the actions of the host device 105 and the memory device 110. In some instances, the clock signal may be single-ended. In some instances, the clock signal may provide a timing reference for command and addressing operations of the memory device 110 or other system-level operations of the memory device 110. The clock signal may therefore be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., an oscillator, a crystal, logic gates, transistors).

[0040] In some instances, DQ channel 190 may be operable to transmit one or more data or control messages between host device 105 and memory device 110. For example, DQ channel 190 may transmit information to be written to memory device 110 (e.g., bidirectional) or information to be read from memory device 110.

[0041] Channel 115 may contain any number of signal paths (including a single signal path). In some instances, channel 115 may contain multiple individual signal paths. For example, the channel may be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (containing sixteen signal paths), etc.

[0042] In some instances, one or more other channels 192 may include one or more error management channels, which may be referred to as error control channels, error detection code channels, or ECC channels. Error management channels may be operable to transmit error detection signals such as checksums, thereby improving system reliability. Error management channels may contain any number of signal paths.

[0043] The package may be used to contain and provide access to and from the memory device 110. The package may include pins that provide access to and from components within the memory device 110 (e.g., memory controllers, such as device memory controller 155 or local memory controller 165, memory dies, such as memory die 160). In some instances, the package may include a DQ pin, which allows data to be input to or output from the memory controller. Furthermore, the package may include a write clock (WCK) pin for receiving a WCK signal from the host device 105—the WCK signal can be received when the host device 105 issues a read or write command and can be used to sample the data signal received at the DQ pin at the memory device 110. Additionally, the package may include a read data strobe (RDQS) pin for outputting a clock signal (which may also be referred to as the RDQS signal)—for example, when the memory device 110 is configured to operate using a frequency within a frequency range. In some instances, memory device 110 generates an RDQS signal based on a received WCK signal, and host device 105 can use the RDQS signal to sample the received data signal. Furthermore, the package may include a Data Mask Inversion (DMI) pin for outputting error management information—for example, information for detecting and / or correcting errors. In some instances, the package may similarly be used to contain and provide access to and from host device 105.

[0044] The package pins may also be coupled to a bus containing multiple channels 115. In some instances, the DQ pin of memory device 110 may be coupled to DQ channel 190, the RDQS pin may be coupled to CK channel 188 of the bus, and the DMI pin may be coupled to DMI channel 191 of the bus. In some instances, the package pins and / or bus channels 115 may be terminated (e.g., weakly) to a voltage source or voltage slot (e.g., ground reference). For example, the DQ pin and / or DQ channel 190 may be terminated to a ground reference—e.g., via an impedance. Therefore, when the bus is not in use (e.g., in an idle, inactive, or floating state), the voltage of the pins and channels 115 may tend to be the voltage of the coupled voltage source or voltage slot. In some instances, when the bus is not in use (e.g., may be in a floating state), the package pins and / or channels 115 may not be coupled to a voltage source or voltage slot. Alternatively, when the bus is used by the memory device 110 or the host device 105 (e.g., in an active state), the voltage of the channel 115 may be driven by the memory device 110 or the host device 105.

[0045] Communication between host device 105 and memory device 110 may fail. A failure may include a situation where host device 105 receives invalid data from memory device 110 without being certain that the data is invalid. In such cases, host device 105 may use the invalid data to perform operations. The failure rate of system 100, including host device 105 and memory device 110, can be determined by testing multiple systems with similar configurations for a period of time and determining the number of failures occurring per cumulative hour—for example, if one hundred systems are tested for one hundred hours, the failure rate can determine the number of failures occurring in approximately 10,000 hours. The test can produce the number of failures expected to occur in one billion hours of system operation, which may also be referred to as the failure times (FIT) rate. The system can be configured to have an acceptable FIT rate—for example, a FIT rate below a threshold. The threshold can be set based on the consequences of the failure. For example, the more severe the damage that a failure may cause, the more stringent the FIT rate may be—for example, if the system is deployed in an application for operating automobiles (e.g., in an autonomous vehicle), the threshold may be lower (e.g., less than 4 FITs).

[0046] The failure rate of a system can be affected by the type of package used for memory device 110—for example, the failure rate can increase as the package coverage area decreases or the package density increases, or both, and vice versa. In some instances, when memory device 110 is packaged in the current package, changing the package used to house memory device 110 can cause the FIT rate of system 100 (which previously met the FIT rate threshold when memory device 110 was packaged in a previous package) to exceed the FIT rate threshold—for example, due to an increased number of mechanical failures that may occur, such as soldering failures or short-circuit conditions. For example, packaging memory device 110 in a fine-pitch ball grid array can cause the FIT rate of system 100 to increase (e.g., to 25.5 FIT) relative to packaging memory device 110 in a ball grid array with a larger pitch (e.g., from 2.4 FIT).

[0047] Packaging errors that cause the bus between memory device 110 and host device 105 to inappropriately enter or remain in a floating state can significantly affect the FIT rate of system 100. In such cases, host device 105 may be unable to determine whether a signal on the bus is a data signal driven by memory device 110 (which may be referred to as a valid data signal) or a random data signal generated on the bus when the bus is in a floating state (which may be referred to as an invalid data signal). Furthermore, host device 105 may determine that the random data signal on the bus is a valid data signal and use invalid data obtained from the random data signal to perform operations, thereby increasing the FIT rate of the system.

[0048] System 100 may employ data reliability techniques to achieve an acceptable FIT rate. For example, system 100 may store parity bits along with data, wherein the parity bits can be used to detect and / or correct errors in the data when it is output to host device 105. In some instances, the parity bits may be used to generate one or more correction sub-bits indicating which bits in the data packet are defective.

[0049] Error protection can be applied to the link between memory device 110 and host device 105 (e.g., to data transmitted over DQ channel 190). This error protection may be referred to as link ECC. In such cases, parity information can be generated for the data to be transmitted to host device 105 (or vice versa). The parity information can then be transmitted along with a set of data during a corresponding read operation. The receiving device can use the parity information to determine whether any errors were introduced into the set of data during transmission, and in some instances, to correct detected errors.

[0050] Memory device 110 and / or host device 105 may include a parity check circuit. The parity check circuit at memory device 110 checks the parity bits associated with a set of data and generates an indication (which may be referred to as a parity check signal) for host device 105 indicating whether errors exist in the data (e.g., whether the parity bits contain any non-zero parity bits). In some instances, memory device 110 transmits the parity check signal to host device 105 during a corresponding read operation. Therefore, the parity check signal allows host device 105 to quickly identify whether received data contains one or more errors. The parity check circuit may also be configured to indicate additional information, such as the number of errors, phantom errors, error type, etc. In some instances, memory device 110 also transmits the parity bits used to generate the parity check signal to host device 105—for example, the memory device may use the parity bits as parity information for link ECC.

[0051] The host device 105 may use the correction bits to detect and / or correct one or more errors in the received data. In some instances, the host device 105 may compare the received correction bits with correction bits calculated for the received data to detect (and in some instances, correct) errors in the received data. In some instances, error management information provided by the correction check signal, combined with error management information determined using link ECC, may be used to reduce the likelihood that the host device 105 attempts to correct and use received data with multiple bit errors (based on the detection of a single bit error in the data from the link ECC). Therefore, the host device 105 may use this information to avoid faults that would otherwise affect the FIT rate.

[0052] The memory device 110 may also include master error circuitry to improve the reliability of data transmission. Master error circuitry enables the memory device 110 to identify errors caused by the memory controller. For example, master error circuitry can identify errors that occur when the memory device 110 writes data different from received data to memory, or outputs data different from data stored in memory to the host device 105—for example, by accessing incorrect rows when writing to or reading from memory.

[0053] To reduce the FIT rate of a system caused by the failure to detect an idle bus (e.g., due to bus package failure), memory device 110 can use a control signal (which may be referred to as a Valid Read Operation Flag (VROF) signal) to indicate when the bus connecting memory device 110 and host device 105 is in an idle state (e.g., a floating state) or when the bus is in an active state. That is, the Valid Read Operation Flag can be used to indicate whether a read operation is currently being performed by memory device 110 (e.g., using a high voltage) or whether a valid read operation is not currently being performed (e.g., using a low voltage). Therefore, in some instances, after determining that a corresponding data signal has been obtained from an idle bus (e.g., a floating bus) based on the receipt of the VROF signal, host device 105 may discard the decoded data.

[0054] In some instances, a VROF signal, a caliber check signal generated by the caliber check circuitry, a caliber bit signal containing the caliber bit, a master error status signal generated by the master error circuitry, or any combination thereof may be output on the DMI pin. The memory device 110 may include a multiplexer for switching between the VROF signal, the caliber check signal, the master error status signal, and the link ECC signal.

[0055] A first protocol—which may be referred to as the DSF+ protocol—can be used to enable the transmission of error management information between the memory device 110 and the host device 105. In such an example, a VROF signal may be output on the DMI pin during the first unit interval of a read operation; a corrector check signal may be output on the DMI pin during the next set of unit intervals of the read operation; a major error status signal may be output on the DMI pin during the subsequent set of unit intervals of the read operation; and a link ECC signal may be output on the DMI pin during the subsequent set of unit intervals of the read operation. Simultaneously, data associated with the read operation may be transmitted via the DQ pin during each period of the unit interval. In some examples, a second protocol can be used to enable the transmission of a portion of the error management information between the memory device 110 and the host device 105—for example, the VROF signal may not be transmitted during the first unit interval of the read operation, but when the second protocol is enabled, other error management signals may be transmitted during subsequent unit intervals, such as during the same set of unit intervals as the first protocol. The second protocol may be referred to as the DSF+ protocol. In some instances, a third protocol may be used that allows a smaller portion of error management information to be transmitted between the memory device 110 and the host device 105—for example, during a read operation, such as during the same set of unit intervals as the first and second protocols, only the link ECC signal may be transmitted.

[0056] In some instances, the unit interval can be determined based on the read clock signal output on the RDQS pin, where each unit interval corresponds to the duration between the falling edge of the read clock and its subsequent rising edge. The read clock can be aligned with the data packet output on the DQ pin. In some instances, the read clock is output by the memory device 110 when operating within a specific frequency range. When operating outside the frequency range, the memory device 110 may not output a read clock signal. In such cases, the unit interval can be determined based on the write clock signal generated at the host device 105. In some instances, the RDQS signal (which may be referred to as differential gating) can be generated using a differential signal (e.g., an inverted and non-inverted version of the write clock signal) corresponding to the write clock signal received from the host device 105. In other instances, the RDQS signal (which may be referred to as single-ended selection communication) can be generated using a non-inverted version of the write clock signal received from the host device 105.

[0057] The host device 105 may use a protocol that does not support transmitting one or more of the valid operation signal, the corrector check signal, or the main error status signal—however, in some instances, the memory device 110 may still generate the underlying data for the signal. Therefore, the host device 105 may fail to receive supplemental error management signaling from the memory device 110. For example, the host device 105 may fail to receive the corrector check signal and therefore may be unable to determine the result of the corrector check operation performed at the memory device 110. Consequently, communication errors between the memory device 110 and the host device 105 may increase (e.g., if the host device 105 uses invalid data obtained based on incorrectly correcting a set of data containing multiple bit errors after determining that a set of data contains a unit error). Therefore, the failure rate associated with the memory device may also increase, and in some instances, may exceed a threshold.

[0058] To enable the transmission of calibration check information when using protocols that do not support explicit communication calibration check information, the calibration check information can be encoded into signaling supported by the protocol. In some instances, the calibration check information can be encoded into an error management signal (also known as a link error management signal), which is used to prevent errors that may occur during data transmission. For example, the result of the calibration check can be indicated by transmitting a specific value (e.g., instead of a separate set of bits generated for transmitting the link error management signal) during the duration of the transmission of the link error management signal. In some instances, the specific value can indicate to the host device that the calibration check failed at the memory device—for example, the calibration bits stored for a requested set of data when written to the memory device do not match the calibration bits calculated for the requested set of data when retrieved from the memory device.

[0059] In some instances, memory device 110 may implement a communication protocol (e.g., a special function selection protocol, such as the DSF+ protocol) that includes dedicated intervals for indicating that a fault has occurred during a calibrator check. However, in other instances, memory device 110 may not implement a communication protocol that includes dedicated intervals.

[0060] Figure 2 This document describes an example of a signal graph supporting real-time corrector checking, based on examples disclosed herein.

[0061] Signal diagram 200 depicts a set of signals being transmitted during a time interval. Signal diagram 200 includes illustrations of one or more command signals 210, clock signals 215, one or more data signals 220, and one or more error signals 230. In some instances, command signals 210 may be present in a command / address channel (e.g., Figure 1 The clock signal 215 can be transmitted on the clock channel (e.g., CA channel 186). Figure 1 The data signal 220 can be transmitted on the data channel (e.g., CK channel 188). Figure 1 The error signal 230 can be transmitted on the DQ channel 190. And the error signal 230 can be transmitted on the error management channel (e.g., Figure 1 Transmitted on DMI channel 191.

[0062] Command 205 may be contained in command signal 210. Among other types of commands, command 205 may be a read command, a write command, or a combination thereof. Command 205 may trigger data to be transmitted in data signal 220. In some instances, a first command 205-1 triggers data to be transmitted during a first data duration 225-1. The first command 205-1 may also trigger a clock signal 215 to be generated. Clock signal 215 may be an RDQS clock signal. In some instances, clock signal 215 is used to indicate a unit interval 223, where the unit interval may span the duration between the rising and falling edges of a clock pulse. In some instances, a new set of information (e.g., a set of data, error management bits, etc.) may be transmitted at each unit interval. In some instances, a WCK signal is received before command 205 is received, where the start of the WCK signal indicates that command 205 is imminent. In some instances, an RDQS clock is generated based on the WCK signal. The period between receiving the WCK signal and receiving the command may be referred to as a time limit.

[0063] Error management information and data can be transmitted to detect and correct errors in the data. In some instances, error management information can be transmitted during corresponding durations. For example, a valid operation flag (e.g., VROF) can be transmitted during the first valid operation duration 233-1, a corrector check signal can be transmitted during the first corrector check duration 235-1, a master error status can be transmitted during the first master error duration 240-1, and an error correction code (e.g., parity bit) can be transmitted during the first link ECC duration 245-1. The first valid operation duration 233-1 can span the first unit interval of the first data duration 225-1, the first corrector check duration can span the next three unit intervals of the first data duration 225-1, the first master error duration 240-1 can span the last three unit intervals of the first data duration 225-1, and the first link ECC duration can span the last nine unit intervals of the first data duration 225-1.

[0064] One or more of the valid operation signal, corrector check signal, or main error status signal may not be transmitted—for example, if the configured communication protocol does not support the communication of this error management signaling. For instance, the VROF signal may not be transmitted during the valid operation duration 233, which may correspond to a first unit interval of the data duration 225. Alternatively, the corrector check signal may not be transmitted during the first corrector check duration 235-1. In such cases, when the DMI pin is not driven, the voltage of the error signal 230 may be at a first voltage level during the valid operation duration 233, the corrector check duration 235, the main error duration 240, or a combination thereof—for example, based on terminating the DMI pin to a voltage source or voltage slot providing the first voltage level. Or it may be at an indeterminate voltage level—for example, if the DMI pin is in a floating state when not driven.

[0065] When a parity check signal is not transmitted, the host device may not receive an indication of whether a set of parity bits generated during writing for a set of data and a set of parity bits calculated during retrieval for the same set of data do not match. This indication allows the host device to determine whether a detected error in a set of data is a unit error (which can be corrected using parity bits associated with the set of data) or a multi-bit error (which may be uncorrectable). Without this indication, for a set of data with multi-bit errors, the host device may incorrectly determine that the set of data has a unit error. In such cases, the host device may perform operations to correct unit errors based on a set of parity bits generated for a set of data, and use a corrected but still invalid set of data, thus causing a failure.

[0066] As described herein, in some instances, in order for a host device to determine whether a corrector check failure has occurred for a requested set of data, the memory device may transmit a specific value (e.g., 11011011) during the link ECC duration 245, instead of a set of ECC bits calculated for the corresponding set of data. In such cases, the host device may be configured to determine that a corrector check failure has occurred based on receiving a specific value during the link ECC duration 245—for example, instead of using the value of the received set of bits for detection—and in some instances, correct errors in the corresponding set of data.

[0067] Figure 3 This document describes an example of a process flow that supports real-time corrector checking, based on examples disclosed herein.

[0068] Process flow 300 can be executed by host device 305 and memory device 310, which may be the above-mentioned reference. Figure 1 and 2The described host device and memory device are corresponding examples. In some examples, process flow 300 illustrates an example sequence of operations executed to support real-time corrector checking. For example, process flow 300 depicts operations for indicating a corrector check failure by transmitting a specific error correction code (e.g., "11011011") during the link ECC duration.

[0069] The operations described in process flow 300 may be performed earlier or later in the process, omitted, substituted, supplemented, or combined with another operation. Furthermore, additional operations described herein that are not included in process flow 300 may be included.

[0070] At arrow 320, host device 305 can transmit commands to memory device 310. In some instances, the command is a read command that addresses the location in the memory array of memory device 310 where a set of data is stored.

[0071] At block 325, memory device 310 can retrieve a set of data addressed by a received command. Retrieving the set of data may include decoding the logical states stored in a set of memory cells at the addressed location.

[0072] At block 330, memory device 310 may perform a corrector check based on a retrieved set of data. In some instances, memory device 310 may retrieve a first set of error management bits (in some instances, the first set of error management bits may be referred to as corrector bits) generated when a stored set of data associated with the retrieved set of data is written to and stored in memory device 310. Memory device 310 may also generate a second set of error management bits based on the retrieved set of data. In some instances, the retrieved set of data may differ from the stored set of data—for example, due to internal storage errors such as bit flips. In some instances, memory device 310 may use the second set of error management bits as link ECC bits. In other instances, a third set of error management bits may be calculated for link ECC bits—for example, based on a corrected version of a set of data.

[0073] The memory device 310 may compare a first set of error management bits with a second set of error management bits. In some instances, the memory device 310 may determine that the first set of error management bits is different from the second set of error management bits—for example, if the stored set of data bits is different from the retrieved set of data bits.

[0074] At block 335, memory device 310 can detect a calibrator check failure based on the result of a calibrator check operation indicating different error management bits. In some instances, memory device 310 can generate a modified set of error management bits with specific values ​​(e.g., with the value 11011011) based on the determination that a calibrator check operation has failed. The modified set of error management bits can be transmitted using link ECC resources instead of error management bits generated for the retrieved set of data. In some instances, the modified set of error management bits may be referred to as a code or calibrator check failure code.

[0075] In some instances, the modified set of error management bits may be selected from a set of error management bits associated with non-aliasing errors (e.g., non-bit-flip error codes). The set of error management bits associated with aliasing errors (e.g., bit-flip error codes) may be a set of error management bits that can cause a unit "correction" to a set of data containing multiple bit errors—this correction may not actually correct the set of data, but may allow the set of data to be determined as valid. In some instances, bit-flip error codes may indicate unit / aliasing errors. While non-bit-flip error codes may be associated with multi-bit / non-aliasing errors, these multiple bit errors may be uncorrectable. In some instances, the first set of values ​​is associated with bit-flip error codes (e.g., in decimal form: 24-31, 40-63, 72-103, 152-183, 192-215, and 224-231), and the second set of values ​​is associated with non-bit-flip error codes (e.g., in decimal form: 1-23, 32-39, 64-71, 104-151, 184-191, 216-223, and 232-255). In some cases, a specific value for the error management bit is selected from the second set of values ​​(e.g., in binary form: 11011011, 11111111, etc.). In some instances, the value 11111111 is not selected as a specific value—for example, if the value is reserved to indicate other information, such as a non-driven condition.

[0076] At arrow 340, memory device 310 can transfer the retrieved set of data to host device 305. In some instances, memory device 310 can transfer a modified set of data based on the detection of a corrector check fault—for example, the modified set of data may contain all 1s (e.g., "11111111") or all 0s (e.g., "00000000"). The modified set of data can be used to indicate to host device 305 the occurrence of a corrector check fault.

[0077] At arrow 345, memory device 310 may transmit the modified group error management bit to host device 305. In some instances, memory device 310 may append a double error detection (DED) bit to the modified group error management bit. The DED bit can be used to indicate whether the bits constituting the data and the error management bit (e.g., the modified error management bit) contain an odd or even number of 1s. That is, the DED bit can be a parity bit used for the aggregation of data bits and error management bits.

[0078] The memory device 310 can calculate the DED bit based on the transmitted group data and the modified error management bit. In some instances, as another indication of a corrector check failure, the memory device 310 can invert the value of the DED bit obtained from the calculation of the DED bit.

[0079] At block 350, host device 305 can decode the received data signal and link ECC signal. Host device 305 can obtain a set of data bits based on the data signal and a set of error management bits based on the link ECC signal. The set of data bits can correspond to the retrieved set of data bits, and the set of error management bits can correspond to the modified set of error management bits—for example, if no error occurred during transmission.

[0080] At block 355, host device 305 may detect an indication that a corrector check failure has occurred at memory device 310—for example, based on determining that the value of the received error management bit is equal to a specific value (e.g., 11011011).

[0081] In other instances, the host device may not detect an indication of a parity check failure at memory device 310—for example, based on determining that the value of the received error management bit is equal to a value other than a specific value. In such cases, memory device 310 can use the received error management bit for detection, and in some instances, correct errors in the received set of data. Using the received error management bit may involve generating a set of parity bits for the received set of data and comparing the generated set of parity bits with the received set of parity bits to determine if a match exists. A match may indicate that no error occurred during transmission. A mismatch may indicate that one or more errors occurred during transmission. When an error is detected, host device 305 may determine the location of the error based on the result of a match (e.g., XOR) and the received error management bits, and invert the bits at the determined location. When multiple errors are detected, host device 305 may determine that the errors are uncorrectable and discard the data.

[0082] At box 360, host device 305 may determine that a calibrator check failure has occurred. In some instances, host device 305 may determine that a calibrator check failure has occurred solely based on determining that the received group error management bit has a specific value (i.e., a calibrator check failure code).

[0083] In some instances, host device 305 may determine that a corrector check failure has occurred based on the value of a DED bit transmitted along with a received error management bit. That is, based on the determination that the received group error management bit has a specific value, host device 305 may calculate the DED bit based on the aggregation of the received group data bits and the received group error management bit. Host device 305 may compare the calculated DED bit with the received DED bit, and if the calculated DED bit and the received DED bit have different values, then a corrector check failure is determined to have occurred. Otherwise, if the value of the calculated DED bit matches the received DED bit, then host device 305 may determine that the received group error management bit is intended for detecting errors in the group data.

[0084] In some instances, based on the determination that the received group error management bit has a specific value, the host device 305 can confirm the occurrence of a corrector check failure by performing the operations described in arrows 365 to box 385.

[0085] At arrow 365, host device 305 may transmit a command to memory device 310 to prevent the transmission of indications for calibrator check failures when using link ECC resources. In some instances, the command disables calibrator check operations at memory device 310. In some instances, the command disables reporting of the results of calibrator check operations at memory device 310.

[0086] At arrow 370, host device 305 can transmit a second command to memory device 310. Similar to the first command transmitted at arrow 320, the second command can be a read command and can address the same location in the memory array as the first command.

[0087] At arrow 375, memory device 310 may transfer a second set of data stored at the location to host device 305 based on receiving a second command. In some instances, the second set of data may be the same as the first set of data transferred at arrow 340.

[0088] At arrow 380, memory device 310 may transmit a set of error management bits associated with data to host device 305. In some instances, the error management bits are parity bits for the set of data. In some instances, the error management bits are based on the result of a corrector check performed on the set of data at memory device 310. In some instances, the error management bits are different from the modified error management bits transmitted at arrow 345. In such cases, the error management bits may be the same as the error management bits generated for the first set of data retrieved at box 325.

[0089] At box 385, host device 305 may determine whether a corrector check failure has occurred based on the modified error management bit received at arrow 345 and the second error management bit received at arrow 380. In some instances, if the modified error management bit does not match the second error management bit, then host device 305 determines that a corrector check failure has occurred—for example, because this could indicate that the error management bit received at arrow 345 was not an error management bit generated for the group of data received at arrow 340.

[0090] In an instance where an error management bit is sent at arrow 345 without modification, if a previously received error management bit matches a currently received error management bit, then host device 305 can determine that no corrector check failure has occurred—for example, because this could indicate that the previous error management bit was generated for the same group of data as the currently received error management bit. In such cases, host device 305 can determine that the received error management bit is being used for error management in the received group of data (rather than as an indication of a corrector check failure). In some instances, host device 305 may not use the received error management bit to correct errors, but may use it to identify erroneous codewords in the transmission of multiple codewords. By identifying erroneous codewords, host device 305 can request the retransmission of the erroneous codewords instead of retransmitting all codewords.

[0091] Figure 4 A block diagram 400 illustrates a memory device 420 supporting real-time corrector checking according to an example disclosed herein. The memory device 420 may be as described in the references... Figures 1 to 3 Examples of aspects of the described memory device. Memory device 420 or its various components may be examples of means for performing various aspects of the real-time corrector check as described herein. For example, memory device 420 may include command component 425, error management component 430, corrector check circuitry 435, output component 440, corrector check component 445, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0092] Command component 425 may be configured or otherwise supported for receiving a read command associated with a set of data from a host device. Error management component 430 may be configured or otherwise supported for generating a first set of error control bits for the set of data as part of an error control operation. Correction check circuit 435 may be configured or otherwise supported for determining that the first set of error control bits causes a matching operation associated with the error control operation to fail. Output component 440 may be configured or otherwise supported for transmitting a second set of error control bits, different from the first set of error control bits, to the host device based at least in part on the failure of the matching operation caused by the first set of error control bits.

[0093] In some instances, the calibrator checking circuit 435 may be configured or otherwise supported for retrieving a second set of error control bits from memory based at least in part on a failure of the matching operation, wherein the transmission of the second set of error control bits is based at least in part on the retrieval of the second set of error control bits.

[0094] In some instances, to support the determination that the first set of error control bits caused the matching operation to fail, the corrector checking circuit 435 may be configured or otherwise supported to include means for comparing the first set of error control bits with a third set of error control bits stored for the group of data. In some instances, to support the determination that the first set of error control bits caused the matching operation to fail, the corrector checking circuit 435 may be configured or otherwise supported to include means for determining that the value of the first set of error control bits differs from the value of the third set of error control bits.

[0095] In some instances, the error management component 430 may be configured or otherwise supported to generate a parity bit indicating an even or odd state of the combination, at least in part, based on the combination of the group data and the second set of error control bits. In some instances, the corrector checking circuit 435 may be configured or otherwise supported to invert the parity bit, at least in part, based on the first set of error control bits causing a failure in the matching operation. In some instances, the output component 440 may be configured or otherwise supported to indicate to the host device, at least in part, that the first set of error control bits has caused a failure in the matching operation, based on inverting the parity bit.

[0096] In some instances, the corrector checking component 445 may be configured or otherwise supported to generate a second set of data, each bit of which contains the same logical value, based at least in part on a first set of error control bits to cause a failure in the matching operation. In some instances, the output component 440 may be configured or otherwise supported to transmit the second set of data, at least in part on the generation of the second set of data. In some instances, the output component 440 may be configured or otherwise supported to indicate to the host device, at least in part on the fact that each bit of the second set of data contains the same logical value, that the first set of error control bits has caused a failure in the matching operation.

[0097] In some instances, the error management component 430 may be configured or otherwise support means for disabling a mode associated with the comparison correction sub-bit based at least in part on a request received from the host device, wherein determining the first set of error control bits to cause the matching operation to fail is based at least in part on enabling the mode associated with the comparison correction sub-bit.

[0098] In some instances, command component 425 may be configured or otherwise supported to support means for receiving a second read command associated with the group data from a host device and at least in part based on a deactivated mode. In some instances, error management component 430 may be configured or otherwise supported to support means for generating a first set of error control bits for the group data as part of a second error control operation. In some instances, output component 440 may be configured or otherwise supported to support means for transmitting the group data and the first set of error control bits, at least in part based on the generation of the first set of error control bits.

[0099] In some instances, the second set of error control bits indicates uncorrectable errors in the group of data.

[0100] In some instances, the second set of error control bits is associated with non-aliasing errors.

[0101] Figure 5 A block diagram 500 illustrates a host device 520 supporting real-time corrector checking according to an example disclosed herein. The host device 520 may be as described in the references... Figures 1 to 3 Examples of aspects of the described host device. Host device 520 or its various components may be examples of components for performing various aspects of the real-time corrector check as described herein. For example, host device 520 may include command component 525, input component 530, error management component 535, data component 540, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0102] Command component 525 may be configured or otherwise support means for transmitting a read command to a memory device. Input component 530 may be configured or otherwise support means for receiving a set of data and a set of error control bits, at least in part based on the transmission of a read command. Error management component 535 may be configured or otherwise support means for determining, at least in part based on the set of error control bits, that a matching operation associated with an error control operation at the memory device fails due to the set of error control bits. Data component 540 may be configured or otherwise support means for processing the set of data, at least in part based on the determination.

[0103] In some instances, to support the processing of the group data, the data component 540 may be configured or otherwise supported to discard the group data, at least in part, based on determining the group error control bit to cause the matching operation to fail.

[0104] In some instances, the error management component 535 may be configured or otherwise supported to determine, at least in part, that the group data contains uncorrectable errors based on determining that the group error control bit causes the matching operation to fail.

[0105] In some instances, the error management component 535 may be configured or otherwise supported to include means for comparing the value of the group error control bit with a stored value associated with a matching operation, wherein the group error control bit is determined to cause the matching operation to fail based at least in part on the value of the group error control bit matching the stored value.

[0106] In some instances, the error management component 535 may be configured or otherwise supported to include means for decoding a first parity bit indicating an even or odd state of a combination of the group data and the group error control bits. In some instances, the error management component 535 may be configured or otherwise supported to include means for generating a second parity bit, at least in part based on the group data and the group error control bits, associated with an even or odd state indicating a combination of the group data and the group error control bits. In some instances, the error management component 535 may be configured or otherwise supported to include means for comparing the first parity bit with the second parity bit.

[0107] In some instances, the error management component 535 may be configured or otherwise supported to determine, at least in part, that the group error control bit causes the matching operation to fail based on the fact that the value of the first parity bit is different from the value of the second parity bit.

[0108] In some instances, data component 540 may be configured or otherwise supported to receive the group data at least in part based on a transmission read command. In some instances, error management component 535 may be configured or otherwise supported to determine, at least in part based on the receipt of the group data, and at least in part based on the value of a first parity bit matching the value of a second parity bit, that the group error control bit indicates an error in the group data.

[0109] In some instances, the read command is associated with a second set of data stored in the memory device, and the error management component 535 may be configured to, or otherwise support means for comparing the value of the group error control bit with the stored value. In some instances, the read command is associated with a second set of data stored in the memory device, and the data component 540 may be configured to, or otherwise support means for determining that each bit of the group data contains the same logical value. In some instances, the read command is associated with a second set of data stored in the memory device, and the error management component 535 may be configured to, or otherwise support means for determining that the group error control bit causes a matching operation to fail, at least in part, based on the value of the group error control bit matching the stored value and the fact that each bit of the group data contains the same logical value.

[0110] In some instances, the error management component 535 may be configured to, or otherwise support means for comparing the value of the group error control bits with a stored value. In some instances, the error management component 535 may be configured to, or otherwise support means for determining that the value of the group error control bits matches a stored value. In some instances, the command component 525 may be configured to, or otherwise support means for transmitting a request to disable a mode associated with the comparison correction sub-bit to a memory device.

[0111] In some instances, command component 525 may be configured or otherwise supported to support means for transmitting a second command associated with reading the group data to a memory device. In some instances, input component 530 may be configured or otherwise supported to support means for receiving a second set of error control bits at least in part based on transmitting the second command. In some instances, error management component 535 may be configured or otherwise supported to support means for comparing the value of the group error control bits with the value of the second set of error control bits. In some instances, error management component 535 may be configured or otherwise supported to support means for determining, at least in part, that the group error control bits cause a matching operation to fail, based on a match between the value of the group error control bits and the value of the second set of error control bits.

[0112] Figure 6The flowchart illustrates a method 600 for supporting real-time corrector checking according to examples disclosed herein. Operation of method 600 may be implemented by a memory device or its components as described herein. For example, it may be implemented via reference to... Figures 1 to 4 The described memory device performs the operation of method 600. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0113] At 605, the method may include receiving a read command associated with a set of data from a host device. The operation at 605 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The described command component 425 performs the operation of 605.

[0114] At 610, the method may include a portion as an error control operation, generating a first set of error control bits for the group of data. The operation at 610 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The error management component 430 described performs the operations of 610.

[0115] At 615, the method may include determining a first set of error control bits to cause a fault in the matching operation associated with the error control operation. The operation at 615 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 4 The described aspect of the calibrator checking circuit 435 performs the operation of 615.

[0116] At 620, the method may include transmitting a second set of error control bits, different from the first set of error control bits, to the host device by at least partially faulting the matching operation based on the first set of error control bits. The operation at 620 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The output component 440 described performs the operation of 620.

[0117] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: receiving a read command associated with a set of data from a host device; generating a first set of error control bits for the set of data as part of an error control operation; determining that the first set of error control bits causes a matching operation associated with the error control operation to fail; and transmitting a second set of error control bits, different from the first set of error control bits, to the host device based at least in part on the failure of the matching operation caused by the first set of error control bits.

[0118] Some examples of the method 600 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for retrieving a second set of error control bits from memory based at least in part on a fault in a matching operation, wherein the transmission of the second set of error control bits may be based at least in part on the retrieval of the second set of error control bits.

[0119] In some instances of the method 600 and apparatus described herein, determining that a first set of error control bits causes a matching operation to fail may include operations, features, circuitry, logic, components, or instructions for performing the following: comparing the first set of error control bits with a third set of error control bits for the group of data stored, and determining that the value of the first set of error control bits may be different from the value of the third set of error control bits.

[0120] In some instances of the method 600 and apparatus described herein, a parity bit indicating an even or odd state of the combination is generated at least in part based on the combination of the group data and the second set of error control bits, the parity bit is inverted at least in part based on the first set of error control bits causing a failure in the matching operation, and the first set of error control bits is indicated to the host device at least in part based on the inversion of the parity bit to cause a failure in the matching operation.

[0121] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: generating a second set of data, each bit of the second set of data containing the same logic value, at least in part based on a first set of error control bits to cause a failure in the matching operation; transmitting the second set of data, at least in part based on the generation of the second set of data; and indicating to a host device, at least in part based on the first set of error control bits causing a failure in the matching operation, the first set of error control bits to cause a failure in the matching operation.

[0122] Some examples of the method 600 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for disabling a mode associated with a comparison correction sub-bit based at least in part on a request received from a host device, wherein determining a first set of error control bits to cause a failure in the matching operation may be based at least in part on enabling a mode associated with the comparison correction sub-bit.

[0123] Some examples of the method 600 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for performing the following: receiving a second read command associated with the group data from a host device and at least in part based on a deactivated mode; generating a first set of error control bits for the group data as part of a second error control operation; and transmitting the group data and the first set of error control bits at least in part based on the generation of the first set of error control bits.

[0124] In some instances of the method 600 and device described herein, a second set of error control bits indicates an uncorrectable error in the group of data.

[0125] In some instances of the method 600 and device described herein, the second set of error control bits may be associated with non-aliasing errors.

[0126] Figure 7 The flowchart illustrates a method 700 for supporting real-time corrector checking based on examples disclosed herein. Operation of method 700 can be implemented by a host device or its components as described herein. For example, it can be implemented via reference... Figures 1 to 3 The host device described in section 5 performs the operation of method 700. In some instances, the host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host device may use dedicated hardware to perform aspects of the described functions.

[0127] At 705, the method may include transmitting a read command to a memory device. The operation at 705 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 5 The described command component 525 performs the operation of 705.

[0128] At 710, the method may include receiving a set of data and a set of error control bits, at least in part based on a transmission read command. The operation of 710 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 5 The input component 530 described performs the operation of 710.

[0129] At 715, the method may include determining, at least in part, based on the group error control bit, that the group error control bit causes a matching operation associated with an error control operation at the memory device to fail. The operation at 715 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 5 The error management component 535 described performs the operations of 715.

[0130] At 720, the method may include processing the group data at least in part based on the determination. The operation at 720 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 5 The described data component 540 performs the operations of 720.

[0131] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: transmitting a read command to a memory device; receiving a set of data and a set of error control bits at least in part based on the transmission of the read command; determining, at least in part based on the set of error control bits, that the set of error control bits causes a matching operation associated with an error control operation at the memory device to fail; and processing the set of data at least in part based on the determination.

[0132] In some instances of the method 700 and apparatus described herein, processing the group data may include operations, features, circuitry, logic, components, or instructions for discarding the group data, at least in part, based on determining the group error control bit to cause a failure in the matching operation.

[0133] Some examples of the method 700 and apparatus described herein may further include determining, at least in part, that the group data contains an operation, feature, circuit system, logic, component, or instruction with an uncorrectable error based on determining that the group error control bit causes the matching operation to fail.

[0134] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for comparing the value of the group error control bit with a stored value associated with a matching operation, wherein the group error control bit is determined to cause the matching operation to fail based at least in part on the value of the group error control bit matching the stored value.

[0135] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: decoding a first parity bit indicating an even or odd state of a combination of the group data and the group error control bit; generating a second parity bit associated with an even or odd state of a combination of the group data and the group error control bit, at least in part based on the group data and the group error control bit; and comparing the first parity bit with the second parity bit.

[0136] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for determining the group error control bits to cause a failure in the matching operation based at least in part on the fact that the value of the first parity bit is different from the value of the second parity bit.

[0137] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: receiving the group data at least in part based on a transmission read command, and determining, at least in part based on receiving the group data, that the group error control bit indicates an error in the group data based at least in part on a value of a first parity bit matching the value of a second parity bit.

[0138] In some instances of the method 700 and apparatus described herein, a read command may be associated with a second set of data stored in a memory device, and the method, apparatus, and non-transitory computer-readable medium may include other operations, features, circuitry, logic, components, or instructions for performing: comparing the value of the group error control bit with a stored value; determining that each bit of the group data contains the same logical value; and determining that the group error control bit causes a failure in the matching operation based at least in part on the fact that the value of the group error control bit matches the stored value and that each bit of the group data contains the same logical value.

[0139] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: comparing the value of the group of error control bits with a stored value; determining that the value of the group of error control bits matches the stored value; and transmitting a request to disable the mode associated with the comparison correction sub-bit to a memory device.

[0140] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following: transmitting a second command associated with reading the group of data to a memory device; receiving a second set of error control bits at least in part based on transmitting the second command; comparing the value of the group of error control bits with the value of the second set of error control bits; and determining that the group of error control bits causes the matching operation to fail, at least in part based on the value of the group of error control bits matching the value of the second set of error control bits.

[0141] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0142] Another device is described. The device may include: a memory array comprising an array of memory cells, each containing a capacitor storage element; and circuitry coupled to the memory array and configured to cause the device to: receive a read command associated with a set of data from a host device; generate a first set of error control bits for the set of data as part of an error control operation; determine that the first set of error control bits causes a matching operation associated with the error control operation to fail; and transmit a second set of error control bits, different from the first set of error control bits, to the host device based at least in part on the failure of the matching operation caused by the first set of error control bits.

[0143] In some instances, the circuitry is configured to cause the device to retrieve a second set of error control bits from memory, at least in part, based on a failure of the matching operation, wherein the transmission of the second set of error control bits may be at least in part based on the retrieval of the second set of error control bits.

[0144] In some instances, to determine that the first set of error control bits causes the matching operation to fail, the circuitry is configured to compare the first set of error control bits with a third set of error control bits for the group of data stored, and to determine that the value of the first set of error control bits may be different from the value of the third set of error control bits.

[0145] In some instances of the device, the circuitry may be further configured to cause the device to: generate a parity bit indicating an even or odd state of the combination based at least in part on the combination of the group of data and the second group of error control bits; invert the parity bit to cause a failure in the matching operation based at least in part on the first group of error control bits; and indicate to the host device, at least in part on the inversion of the parity bit, that the first group of error control bits has caused a failure in the matching operation.

[0146] In some instances, the circuitry is configured to cause the device to: generate a second set of data, each bit of which contains the same logic value, at least in part based on a first set of error control bits causing a failure in the matching operation; transmit the second set of data, at least in part based on the generation of the second set of data; and indicate to the host device, at least in part based on the first set of error control bits causing a failure in the matching operation, the first set of error control bits.

[0147] In some instances, the circuitry is configured to disable the mode associated with the comparison correction sub-bit at least in part based on a request received from the host device, wherein determining the first set of error control bits to cause the matching operation to fail can be based at least in part on enabling the mode associated with the comparison correction sub-bit.

[0148] Describe another device. The device may include: circuitry configured to cause the device to: transmit a read command to a memory device; receive a set of data and a set of error control bits at least in part based on the transmission of the read command; determine, at least in part based on the set of error control bits, that the set of error control bits causes a matching operation associated with an error control operation at the memory device to fail; and process the set of data at least in part based on the determination.

[0149] In some instances, the circuitry is configured to cause the device to discard the group data, at least in part, based on determining that the group error control bit causes the matching operation to fail.

[0150] In some instances, the circuitry is configured such that the device determines, at least in part, that the group data contains an uncorrectable error based on the determination that the matching operation fails due to the group error control bit.

[0151] In some instances, the circuitry is configured to cause the device to compare the value of the group error control bit with a stored value associated with a matching operation, wherein the group error control bit is determined to cause the matching operation to fail based at least in part on the value of the group error control bit matching the stored value.

[0152] In some instances of the device, the circuitry may be further configured to cause the device to: decode a first parity bit indicating an even or odd state of the combination of the group data and the group error control bit; generate a second parity bit, at least in part based on the group data and the group error control bit, associated with the even or odd state of the combination of the group data and the group error control bit; and compare the first parity bit with the second parity bit.

[0153] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0154] The terms "electrical communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered to be electrically communicating (or electrically contacting, connected, or coupled) with each other if there is any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are electrically communicating (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used, for example, to interrupt the signal flow between connected components for a period of time.

[0155] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via conductive paths, while in a closed-circuit relationship, signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between other components via conductive paths that were previously not permitted.

[0156] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between them using previously permitted conductive paths.

[0157] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0158] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of the carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of the carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor is "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor is "turned off" or "deactivated."

[0159] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or illustration" and is not necessarily "preferred" or "advantageous over other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0160] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0161] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0162] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0163] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0164] Computer-readable media includes both non-transitory computer-readable storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0165] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: Receive a read command associated with a set of data from the host device; As part of the error control operation, a first set of error control bits is generated for the group data, wherein the first set of error control bits is associated with instructing the host device whether one or more errors are introduced into the group data during transmission to the host device; During the matching operation associated with the error control operation, it is determined that the first set of error control bits is different from the third set of error control bits stored for the group of data; and At least in part, based on the fact that the first set of error control bits is different from the third set of error control bits, a second set of error control bits, different from the first set of error control bits, is transmitted to the host device on the channel used to transmit the first set of error control bits and during the duration of the transmission of the first set of error control bits, wherein the second set of error control bits is associated with indicating a failure of the matching operation to the host device.

2. The method according to claim 1, further comprising: The second set of error control bits is retrieved from memory at least in part based on the failure of the matching operation, wherein the transmission of the second set of error control bits is at least in part based on the retrieval of the second set of error control bits.

3. The method according to claim 1, wherein determining that the first group of error control bits is different from the third group of error control bits includes: The first set of error control bits is compared with the third set of error control bits for the group of data stored; and The value of the first set of error control bits is determined to be different from the value of the third set of error control bits.

4. The method of claim 1, further comprising: Parity bits indicating an even or odd state of the combination are generated, at least in part, based on the combination of the group of data and the second group of error control bits. The parity bit is inverted at least in part because the first set of error control bits is different from the third set of error control bits; and The first set of error control bits is indicated to the host device as different from the third set of error control bits, at least in part, by inverting the parity bits.

5. The method of claim 1, further comprising: The second set of data is generated at least in part based on the fact that the first set of error control bits is different from the third set of error control bits, and each bit of the second set of data includes the same logical value; The second set of data is transmitted at least in part based on the generation of the second set of data; and The host device is instructed, at least in part, that the first set of error control bits is different from the third set of error control bits, based on the fact that each bit of the second set of data includes the same logical value.

6. The method of claim 1, further comprising: The mode associated with the comparison correction sub-bit is disabled at least in part based on a request received from the host device, wherein the determination that the first set of error control bits is different from the third set of error control bits is at least in part based on enabling the mode associated with comparing the correction sub-bit.

7. The method of claim 6, further comprising: Receive a second read command associated with the group of data from the host device and at least in part based on disabling the mode; As part of the second error control operation, the first set of error control bits is generated for the group of data; and The group of data and the first set of error control bits are transmitted at least in part based on the generation of the first set of error control bits.

8. The method of claim 1, wherein the second set of error control bits indicates an uncorrectable error in the group of data.

9. The method of claim 1, wherein the second set of error control bits is associated with a non-aliasing error.

10. A method comprising: Transmit the read command to the memory device; A set of data and a first set of error control bits are received at least in part based on the transmission of the read command. The first set of error control bits is received from the channel for receiving a second set of error control bits and during the duration of receiving the second set of error control bits, wherein the second set of error control bits is associated with indicating whether one or more errors are introduced into the set of data during the transmission of the set of data. The determination of whether a matching operation associated with an error control operation failed at the memory device is based at least in part on the first set of error control bits, rather than on whether one or more errors were introduced into the group of data during the transmission. and The group of data is processed at least in part based on the determination that the matching operation has failed at the memory device.

11. The method of claim 10, wherein processing the group data comprises: The group of data is discarded, at least in part, based on the determination that the matching operation failed at the memory device.

12. The method of claim 10, further comprising: The group of data is determined to contain uncorrectable errors, at least in part, based on the finding that the matching operation failed at the memory device.

13. The method of claim 10, further comprising: The value of the first set of error control bits is compared with a stored value associated with a failed match operation, wherein the match operation is determined to have failed at the memory device based at least in part on the match between the value of the first set of error control bits and the stored value.

14. The method of claim 10, further comprising: Decode the first parity bit indicating the even or odd state of the combination of the group of data and the first group of error control bits; A second parity bit is generated, at least in part based on the group data and the first set of error control bits, and is associated with the even or odd state of the combination of the group data and the first set of error control bits; and The first parity bit is compared with the second parity bit.

15. The method of claim 14, further comprising: The matching operation was determined to have failed at the memory device, at least in part, based on the fact that the value of the first parity bit is different from the value of the second parity bit.

16. The method of claim 14, further comprising: The group of data is received at least in part based on the transmission of the read command; and The first set of error control bits indicates an error in the group of data, based at least in part on the receipt of the group of data and at least in part on the matching of the value of the first parity bit with the value of the second parity bit.

17. The method of claim 10, wherein the read command is associated with a second set of data stored in the memory device, the method further comprising: The value of the first set of error control bits is compared with the stored value associated with the failed match operation; It is determined that each bit of the group of data includes the same logical value; and The matching operation is determined to have failed at the memory device if at least in part the values ​​of the first set of error control bits are matched to the stored value and each bit of the set of data has the same logical value.

18. The method of claim 10, further comprising: The value of the first set of error control bits is compared with the stored value associated with the failed match operation; Determine that the value of the first set of error control bits matches the stored value; and A request to disable the mode associated with the comparison correction subbit is transmitted to the memory device.

19. An apparatus comprising: A memory array comprising an array of memory cells, each including a capacitor storage element; and A circuit, coupled to the memory array and configured to cause the device to perform the following operations: Receive a read command associated with a set of data from the host device; As part of the error control operation, a first set of error control bits is generated for the group data, wherein the first set of error control bits is associated with instructing the host device whether one or more errors are introduced into the group data during transmission to the host device; During the matching operation associated with the error control operation, it is determined that the first set of error control bits is different from the third set of error control bits stored for the group of data; and At least in part, based on the fact that the first set of error control bits is different from the third set of error control bits, a second set of error control bits, different from the first set of error control bits, is transmitted to the host device on the channel used to transmit the first set of error control bits and during the duration of the transmission of the first set of error control bits, wherein the second set of error control bits is associated with indicating a failure of the matching operation to the host device.

20. The device of claim 19, wherein the circuitry is further configured to cause the device to perform the following operations: The second set of error control bits is retrieved from memory at least in part based on the failure of the matching operation, wherein the transmission of the second set of error control bits is at least in part based on the retrieval of the second set of error control bits.

21. The device according to claim 19, wherein, To determine that the first set of error control bits differs from the third set of error control bits, the circuit is further configured to cause the device to perform the following operations: Compare the first set of error control bits with the third set of error control bits for the group of data stored; and The value of the first set of error control bits is determined to be different from the value of the third set of error control bits.

22. The device of claim 19, wherein the circuitry is further configured to cause the device to perform the following operations: Parity bits indicating an even or odd state of the combination are generated, at least in part, based on the combination of the group of data and the second group of error control bits. The parity bit is inverted at least in part because the first set of error control bits is different from the third set of error control bits; and The first set of error control bits is indicated to the host device as different from the third set of error control bits, at least in part, by inverting the parity bits.

23. The device of claim 19, wherein the circuitry is further configured to cause the device to perform the following operations: The second set of data is generated at least in part based on the fact that the first set of error control bits is different from the third set of error control bits, and each bit of the second set of data includes the same logical value; The second set of data is transmitted at least in part based on the generation of the second set of data; and The host device is instructed, at least in part, that the first set of error control bits is different from the third set of error control bits, based on the fact that each bit of the second set of data includes the same logical value.

24. The device of claim 19, wherein the circuitry is further configured to cause the device to perform the following operations: The mode associated with the comparison correction sub-bit is disabled at least in part based on a request received from the host device, wherein the determination that the first set of error control bits is different from the third set of error control bits is at least in part based on enabling the mode associated with comparing the correction sub-bit.

25. An apparatus comprising: A circuit configured to cause the device to perform the following operations: Transmit the read command to the memory device; A set of data and a first set of error control bits are received at least in part based on the transmission of the read command. The first set of error control bits is received from the channel for receiving a second set of error control bits and during the duration of receiving the second set of error control bits, wherein the second set of error control bits is associated with indicating whether one or more errors are introduced into the set of data during the transmission of the set of data. The determination of whether a matching operation associated with an error control operation failed at the memory device is based at least in part on the first set of error control bits, rather than on whether one or more errors were introduced into the group of data during the transmission. and The group of data is processed at least in part based on the determination that the matching operation has failed at the memory device.

26. The device of claim 25, wherein the circuitry is further configured to cause the device to perform the following operations: The group of data is discarded, at least in part, based on the determination that the matching operation failed at the memory device.

27. The device of claim 25, wherein the circuitry is further configured to cause the device to perform the following operations: The group of data is determined to contain uncorrectable errors, at least in part, based on the finding that the matching operation failed at the memory device.

28. The device of claim 25, wherein the circuitry is further configured to cause the device to perform the following operations: The value of the first set of error control bits is compared with a stored value associated with a failed match operation, wherein the match operation is determined to have failed at the memory device based at least in part on the match between the value of the first set of error control bits and the stored value.

29. The device of claim 25, wherein the circuitry is further configured to cause the device to perform the following operations: Decode the first parity bit indicating the even or odd state of the combination of the group of data and the first group of error control bits; A second parity bit is generated, at least in part based on the group data and the first set of error control bits, and is associated with the even or odd state of the combination of the group data and the first set of error control bits; and The first parity bit is compared with the second parity bit.

30. A non-transitory computer-readable medium comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: Receive a read command associated with a set of data from the host device; As part of the error control operation, a first set of error control bits is generated for the group data, wherein the first set of error control bits is associated with instructing the host device whether one or more errors are introduced into the group data during transmission to the host device; During the matching operation associated with the error control operation, it is determined that the first set of error control bits is different from the third set of error control bits stored for the group of data; and At least in part, based on the fact that the first set of error control bits is different from the third set of error control bits, a second set of error control bits, different from the first set of error control bits, is transmitted to the host device on the channel used to transmit the first set of error control bits and during the duration of the transmission of the first set of error control bits, wherein the second set of error control bits is associated with indicating a failure of the matching operation to the host device.

31. The non-transitory computer-readable medium of claim 30, wherein the instructions are further executable by the processor to cause the electronic device to perform the following operations: The second set of error control bits is retrieved from memory at least in part based on the failure of the matching operation, wherein the transmission of the second set of error control bits is at least in part based on the retrieval of the second set of error control bits.

32. The non-transitory computer-readable medium of claim 30, wherein the instructions are further executable by the processor to cause the electronic device to perform the following operations: Parity bits indicating an even or odd state of the combination are generated, at least in part, based on the combination of the group of data and the second group of error control bits. The parity bit is inverted at least in part because the first set of error control bits is different from the third set of error control bits; and The first set of error control bits is indicated to the host device as different from the third set of error control bits, at least in part, by inverting the parity bits.

33. The non-transitory computer-readable medium of claim 30, wherein the instructions are further executable by the processor to cause the electronic device to perform the following operations: The second set of data is generated at least in part based on the fact that the first set of error control bits is different from the third set of error control bits, and each bit of the second set of data includes the same logical value; The second set of data is transmitted at least in part based on the generation of the second set of data; and The host device is instructed, at least in part, that the first set of error control bits is different from the third set of error control bits, based on the fact that each bit of the second set of data includes the same logical value.

34. The non-transitory computer-readable medium of claim 30, wherein the instructions are further executable by the processor to cause the electronic device to: disable a mode associated with the comparison correction sub-bit based at least in part on a request received from the host device, wherein determining that the first set of error control bits is different from the third set of error control bits is based at least in part on enabling the mode associated with comparing the correction sub-bit.

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