A display panel, a driving method thereof and a display device

Abstract

The present invention discloses a display panel, a driving method thereof and a display device. Since a data output circuit includes at least one gating circuit group and an even number of first gating circuits, the even number of first gating circuits can ensure that the data lines connected to the first gating circuits are symmetrically distributed in the frame area. Since the number of data lines connected to a gating circuit group is the same as the number of data lines connected to a first gating circuit, the gating circuit group includes at least two second gating circuits, that is, the number of data lines connected to the second gating circuits is less than the number of data lines connected to a first gating circuit, and there are at least two paired second gating circuits, it can ensure that the data lines connected to the second gating circuits are symmetrically distributed in the frame area or reduce the asymmetry of the distribution of the data lines connected to the second gating circuits in the frame area, that is, solve or improve the display abnormality problem caused by the asymmetric distribution of the data lines in the frame area.

Description

[0001] This application is a divisional application with the application date of December 27, 2019, application number 201911380359.5, and name “A display panel, its driving method and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel, a driving method thereof and a display device. Background Art

[0003] With the continuous development of display technology, organic light emitting diode (OLED) display panels have been widely used in the field of display technology due to their many advantages such as active luminescence, high contrast, no viewing angle limitation, and flexible display.

[0004] The OLED display panel includes a display area and a frame area located around the display area, wherein the display area includes multiple sub-pixels and various signal lines, such as data lines, gate lines, power supply voltage signal lines, etc., and the frame area is used to set peripheral circuits connected to various signal lines, such as gate drive circuits connected to each gate line, and selection circuits connected to data lines.

[0005] In order to reduce the border width of the display panel, such as Figure 1 As shown, Figure 1 It is a structural diagram of the relevant display panel; a gating circuit 01 is generally connected to multiple data lines data', and each data line data in the display area A' extends to the border area B' and is connected to the gating circuit 01 in the border area B'. Considering the overall layout design of the panel, it is necessary to set the gating circuit 01 on both sides of the symmetry axis Y of the display panel along the data line direction. If the number of gating circuits 01 in the border area B' of the display panel is an even number, the number of gating circuits 01 on both sides of the symmetry axis Y is the same. If the number of gating circuits 01 in the border area B' of the display panel is an odd number, the number of gating circuits 01 on both sides of the symmetry axis Y will be inconsistent, resulting in an asymmetric distribution of the data lines data' in the border area B', which will lead to display abnormalities such as split screen display. Summary of the invention

[0006] The embodiments of the present invention provide a display panel, a driving method thereof and a display device, which improve the display abnormality problem caused by the asymmetric distribution of data lines in the frame area.

[0007] In a first aspect, an embodiment of the present invention provides a display panel comprising:

[0008] Display area and border area;

[0009] The display area includes a plurality of pixels and a plurality of data lines extending along a first direction;

[0010] The frame area includes a data output circuit, and an output end of the data output circuit is electrically connected to the data line;

[0011] The data output circuit includes at least one gating circuit group and 2L first gating circuits, wherein L is a positive integer and L≥1;

[0012] One of the gating circuit groups is electrically connected to the M data lines, and one of the first gating circuits is electrically connected to the N data lines, wherein M=N≥2, and M and N are positive integers respectively;

[0013] The gating circuit group includes at least two second gating circuits, and the second gating circuits are electrically connected to A data lines, wherein N>A≥1, and A is a positive integer;

[0014] The at least two second gating circuits share a set of clock signal buses, wherein some of the second gating circuits are connected to some of the clock signal buses of the set of clock signal buses, and another part of the second gating circuits are connected to another part of the clock signal buses of the set of clock signal buses.

[0015] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising any of the above-mentioned display panels provided by an embodiment of the present invention.

[0016] In a third aspect, based on the same inventive concept, an embodiment of the present invention further provides a driving method for any of the above display panels, comprising:

[0017] Receive frame image data to be displayed;

[0018] According to the frame image data to be displayed, the driving chip simultaneously outputs signals to each of the gating circuits; wherein,

[0019] The signal output by the driving chip to each of the first gating circuits is a grayscale signal obtained according to the frame image data to be displayed;

[0020] The signal output by the driving chip to the enabling circuit in the enabling circuit group is a high-impedance signal or a grayscale signal obtained according to the frame image data to be displayed, and when the signal output by the driving chip to one of the enabling circuits in the enabling circuit group is a grayscale signal, the signal output by the driving chip to the other enabling circuits in the enabling circuit group is a high-impedance signal.

[0021] The beneficial effects of the present invention are as follows:

[0022] In the display panel, driving method and display device provided by the embodiment of the present invention, since the data output circuit includes at least one gating circuit group and an even number of first gating circuits, the even number of first gating circuits can ensure that the data lines connected to the first gating circuits are symmetrically distributed in the frame area. Since the number of data lines connected to a gating circuit group is the same as the number of data lines connected to a first gating circuit, each gating circuit group includes a plurality of second gating circuits, that is, the number of data lines connected to each second gating circuit is less than the number of data lines connected to a first gating circuit, and there are at least two pairs of second gating circuits, it can ensure that the data lines connected to the second gating circuits are symmetrically distributed in the frame area or reduce the asymmetry of the distribution of the data lines connected to the second gating circuits in the frame area, that is, solve or improve the display abnormality problem caused by the asymmetric distribution of the data lines in the frame area. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the structure of a related display panel;

[0024] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of another structure of a display panel provided in an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0029] Figure 7 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0030] Figure 8 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0031] Fig. 9 A schematic diagram of the structure of a gating circuit provided by an embodiment of the present invention;

[0032] Fig.10 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0033] Fig.11 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0034] Fig.12 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0035] Fig.13 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0036] Fig.14 A flow chart of a method for driving a display panel provided by an embodiment of the present invention;

[0037] Fig.15 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and examples. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportions.

[0039] It should be noted that specific details are described in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a representative embodiment of the implementation of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application.

[0040] The display panel, the driving method thereof and the display device provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] An embodiment of the present invention provides a display panel, such as Figures 2 to 4 As shown, Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 3 A schematic diagram of another structure of a display panel provided in an embodiment of the present invention is shown. Figure 4 A schematic diagram of another structure of a display panel provided in an embodiment of the present invention; the display panel comprises:

[0042] Display area A and border area B;

[0043] The display area A includes a plurality of pixels (not shown in the figure) and a plurality of data lines data extending along a first direction X;

[0044] The frame area B includes a data output circuit, and an output end of the data output circuit is electrically connected to the data line data;

[0045] The data output circuit includes at least one gating circuit group 10 and 2L first gating circuits 11, wherein L is a positive integer and L≥1;

[0046] A gating circuit group 10 is electrically connected to M data lines data, and a first gating circuit 11 is electrically connected to N data lines data, wherein M=N≥2, and M and N are positive integers respectively;

[0047] Each gating circuit group 10 includes a plurality of second gating circuits 12, and each second gating circuit 12 is electrically connected to A data lines data, wherein N>A≥1, and A is a positive integer.

[0048] Specifically, the display panel provided by the embodiment of the present invention is as follows: Figures 2 to 4 As shown, the data output circuit connected to the data line data includes at least one gating circuit group 10 and 2L first gating circuits 11. Since the number of the first gating circuits 11 in the frame area B is an even number, it can be ensured that the number of the first gating circuits 11 on both sides of the first symmetry axis X0 extending along the first direction X of the display panel is the same, thereby ensuring that the data lines data connected to the first gating circuits 11 are symmetrically distributed in the frame area B. Figure 2 As shown, when the number of the gate circuit groups 10 is an even number, the number of the gate circuit groups 10 on both sides of the first symmetry axis X0 can be ensured to be the same, thereby ensuring that the data lines data connected to the gate circuit groups 10 are symmetrically distributed in the border area B. Figure 3 As shown, when the number of the gate circuit group 10 is an odd number ( Figure 3 Taking one gating circuit group as an example, if each gating circuit group 10 includes an even number of second gating circuits 12, it can be ensured that the number of second gating circuits 12 on both sides of the first symmetry axis X0 is the same, thereby also ensuring that the data lines data connected to the second gating circuits 12 are symmetrically distributed in the border area B. Figure 4 As shown, when each group of gating circuits 10 includes an odd number of second gating circuits 12 ( Figure 4Taking three second selection circuits as an example), since the number of data lines data connected to a selection circuit group 10 is the same as the number of data lines data connected to a first selection circuit 11, and each selection circuit group 10 includes multiple second selection circuits 12, the number of data lines data connected to each second selection circuit 12 is at least half of the number of data lines data connected to a first selection circuit 11. When the number of second selection circuits 12 on both sides of the first symmetry axis X0 differs by one, the fewer the number of data lines connected to the second selection circuit 12, the smaller the difference in the number of data lines data on both sides of the symmetry axis X0 can be ensured, thereby reducing the distribution asymmetry of the data lines data connected to the second selection circuit 12 in the border area B.

[0049] Therefore, in the above-mentioned display panel provided by the embodiment of the present invention, since the data output circuit includes at least one gating circuit group and an even number of first gating circuits, the even number of first gating circuits can ensure that the data lines connected to the first gating circuits are symmetrically distributed in the border area. Since the number of data lines connected to a gating circuit group is the same as the number of data lines connected to a first gating circuit, each gating circuit group includes a plurality of second gating circuits, that is, the number of data lines connected to each second gating circuit is at least half of the number of data lines connected to a first gating circuit, it can ensure that the data lines connected to the second gating circuits are symmetrically distributed in the border area or reduce the asymmetry of the distribution of the data lines connected to the second gating circuits in the border area. That is, the display abnormality problem caused by the asymmetric distribution of the data lines in the border area is solved or improved.

[0050] Optionally, in the display panel provided in the embodiment of the present invention, Figure 2 and Figure 3 As shown, the display area A has a first symmetry axis X0, and the first symmetry axis X0 extends along the first direction X; all the gating circuits as a whole, that is, an even number of first gating circuits 11 and a plurality of second gating circuits 12, are symmetrically distributed with the first symmetry axis X0 as the symmetry axis. Thus, it is ensured that all data lines data connected to the data output circuit are symmetrically distributed in the frame area.

[0051] Optionally, in the display panel provided in the embodiment of the present invention, Figure 3As shown, M is an even number, that is, one gating circuit group 10 is connected to an even number of data, and the display panel includes one gating circuit group 10, and the gating circuit group 10 includes two second gating circuits 12. That is, the data output circuit includes 2L first gating circuits 11 and 2 second gating circuits 12, which can ensure that the first gating circuits 11 and the second gating circuits 12 are symmetrically distributed on both sides of the first symmetry axis X0, thereby ensuring that the data lines data connected to the gating circuits are symmetrically distributed in the frame area, and can also ensure that the number of gating circuits in the frame area B is minimal. A small number of gating circuits means that the occupied area of ​​the frame area is small, which is conducive to a narrow frame design.

[0052] Optionally, in the display panel provided in the embodiment of the present invention, Figure 3 As shown, as long as the 2L first gating circuits 11 are symmetrically distributed on both sides of the first symmetry axis X0 and the 2 second gating circuits 12 are symmetrically distributed on both sides of the first symmetry axis X0, the positions of the second gating circuits 12 can be set arbitrarily and are not limited here.

[0053] Optionally, in the display panel provided in the embodiment of the present invention, Figure 5 As shown, Figure 5 Another structural diagram of a display panel provided by an embodiment of the present invention; two second gating circuits 12 are arranged adjacent to each other, and L first gating circuits 11 are arranged on both sides of 10. Figure 3 Compared with the arrangement shown in FIG. 1 , two second gating circuits 12 are arranged adjacent to each other, which can ensure that only one side of each second gating circuit 12 is provided with the first gating circuit 11. In this way, if the display effect is different due to the different structures of the second gating circuit 12 and the first gating circuit 11, there are only two display difference intersection lines on the full screen, which is different from the first gating circuit 11. Figure 3 There will be four display difference boundary lines, which can improve the display effect.

[0054] Of course, this is just to prevent the different display effects caused by the different structures of the second selection circuit 12 and the first selection circuit 11. In theory, the second selection circuit 12 and the first selection circuit 11 only differ in the number of output terminals, which will not cause different display effects.

[0055] Optionally, in the display panel provided in the embodiment of the present invention, Figure 6 As shown, Figure 6 Schematic diagram of another structure of a display panel provided by an embodiment of the present invention; 2L first gating circuits 11 are sequentially arranged between two second gating circuits 12. That is, the data line data connected to the second gating circuit 12 is located near the display panel. Figure 6In the left and right border areas, if the display effect is different due to the different structures of the second selection circuit 12 and the first selection circuit 11, the data line data connected to the second selection circuit 12 is close to the border area, and the display difference near the border area of ​​the display panel is not easy to be recognized by the human eye, so the display effect can be guaranteed.

[0056] Optionally, in the display panel provided in the embodiment of the present invention, Figure 7 As shown, Figure 7 Another structural schematic diagram of a display panel provided by an embodiment of the present invention; L first gating circuits 11 and one second gating circuit 12 that are adjacent to each other in sequence form a circuit group 100, and two circuit groups 100 are provided in the frame area B;

[0057] There is a gap between the two circuit groups 100;

[0058] The display area A is also provided with a plurality of signal lines S1;

[0059] The gap is also provided with a first wire S2 extending along the first direction X, and the first wire S2 is electrically connected to the signal wire S1. The signal wire S1 in the display area A is connected to the first wire S1 located in the gap between the two circuit groups 100, so that the subsequent driving chip provides a signal to the signal wire S1 in the display area A through the first wire S2.

[0060] In specific implementation, the signal line is determined according to the properties of the display panel itself. For example, when the display panel is an OLED display panel, the signal line may include a fixed power supply line, a reference signal line, etc., which is not limited here. Generally, the first wirings connected to the signal lines with the same voltage are the same, which can reduce the number of wirings in the frame area and is conducive to narrow frame design.

[0061] Optionally, in the display panel provided in the embodiment of the present invention, Figure 8 As shown, Figure 8 Another structural schematic diagram of a display panel provided for an embodiment of the present invention; the signal line includes a fixed power supply voltage line PVDD. The driver chip can apply a signal to each power supply voltage line PVDD through the first line S1. In a specific implementation, since the signals on all the power supply voltage lines PVDD in the display area are the same, all the power supply voltage lines PVDD can be connected to a first line S2, so that the signal is transmitted to all the power supply voltage lines PVDD through the first line S2; of course, in a specific implementation, all the power supply voltage lines PVDD can also be connected to multiple first lines S2, so that the signal is transmitted to all the power supply voltage lines PVDD at the same time through multiple first lines S2, but more first lines S2 are not conducive to the design of the frame, so the fewer the first lines S2, the lower the frame width can be.

[0062] In specific implementation, Fig. 9 As shown, Fig. 9 A schematic diagram of the structure of a gating circuit provided by an embodiment of the present invention; the gating circuit generally includes a plurality of transistors: T1, T2, T3, T4, T5 and T6. In the figure, 6 transistors are taken as an example, each transistor is connected to a clock signal line and a data line, for example, transistor T1 is connected to the clock signal line CLKI and the data line data1, transistor T2 is connected to the clock signal line CLK2 and the data line data2, transistor T3 is connected to the clock signal line CLK3 and the data line data3, transistor T4 is connected to the clock signal line CLK4 and the data line data4, transistor T5 is connected to the clock signal line CLK5 and the data line data5, transistor T6 is connected to the clock signal line CLK6 and the data line data6, and the 6 transistors are connected to the same input terminal IN. The gating circuit receives the grayscale signal generated by the driver chip according to the image data through the input terminal IN; and only one transistor of a gating circuit can be turned on at the same time, for example, when the clock signal line CLKI controls the transistor T1 to be turned on, the other transistors T2 to T6 are all turned off, and the gating circuit provides the signal output by the driver chip to the data line data1.

[0063] In specific implementation, the driving chip is generally bound to the frame area of ​​the display panel through a printed circuit board.

[0064] Optionally, in the display panel provided in the embodiment of the present invention, Fig.10 As shown, Fig.10 Another structural schematic diagram of a display panel provided by an embodiment of the present invention; the frame area B also includes a plurality of clock signal lines CLK1 to CLK6 arranged along the first direction X and electrically connected to each gating circuit 11 or 12;

[0065] A plurality of clock signal buses CK1 to CK6 extending along the first direction are also arranged at the gap;

[0066] The clock signal lines CLK1-CLK6 electrically connected to the different gating circuits 11 or 12 and having the same signal are extended to the gap and then electrically connected to the corresponding clock signal buses CK1-CK6. That is, two circuit groups 100 share one set of clock signal buses CK1-CK6, which can reduce the number of clock signal buses in the frame area, thereby facilitating a narrow frame design.

[0067] Optionally, in the display panel provided in the embodiment of the present invention, Fig.10As shown, in order to ensure that the clock signal lines CLK1-CLK6 correspondingly connected to the two circuit groups 100 can be symmetrically distributed so as to ensure that the loads on the clock signal lines CLK1-CLK6 are consistent, the clock signal buses CK1-CK6 are arranged near the first symmetry axis X0, for example Fig.10 In the embodiment, three clock signal buses CK1-CK3 are arranged on the left side of the first symmetry axis X0, and three clock signal buses CK4-CK5 are arranged on the right side of the first symmetry axis X0. In this case, two first wires S2 connected to the fixed power supply voltage line PVDD can be arranged, and the two first wires S2 are located on both sides of the clock signal buses CK1-CK6. Thus, the connection between the fixed power supply voltage line PVDD and the second wire S2 on the left and right sides of the display panel is symmetrically arranged.

[0068] Optionally, in the display panel provided by the embodiment of the present invention, as Fig.11 and Fig.12 As shown, Fig.11 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.12 Another structural schematic diagram of a display panel provided by an embodiment of the present invention; M is an odd number, that is, each gating circuit group 10 is connected to an odd number of data lines, and the gating circuit group 10 includes two second gating circuits 12 and one third gating circuit 13, and the third gating circuit 13 is electrically connected to B data lines, wherein A>B≥1, and B is a positive integer. In this way, the two second gating circuits 12 can be symmetrically distributed about the first symmetry axis X0, thereby also ensuring that the data lines data connected to the second gating circuits 12 are symmetrically distributed in the frame area B, and the third gating circuits 13 themselves are symmetrically distributed about the first symmetry axis X0, thereby also ensuring that the data lines data connected to the third gating circuits 13 are symmetrically distributed in the frame area B.

[0069] Optionally, in the display panel provided by the embodiment of the present invention, as Fig.11 and Fig.12 As shown, A is an even number, B is an odd number, and the third gating circuit 13 is located between the two second gating circuits.

[0070] Optionally, in the display panel provided by the embodiment of the present invention, as Fig.11 As shown, L first gating circuits 11 are respectively arranged on both sides of the gating circuit group 10. That is, the two second gating circuits 12 are symmetrically distributed about the first symmetry axis X0, the 2L first gating circuits 11 are symmetrically distributed about the first symmetry axis X0, and the third gating circuit 13 itself is symmetrically distributed about the first symmetry axis X0, thereby ensuring that the data lines data connected to each gating circuit are symmetrically distributed about the first symmetry axis X0 in the frame area B as a whole.

[0071] Optionally, in the display panel provided by the embodiment of the present invention, as Fig.12 As shown, 2L first gating circuits 11 are sequentially arranged between two second gating circuits 12, and L first gating circuits 11 are respectively arranged on both sides of the third gating circuit 13. That is, in the gating circuit group 10, the third gating circuit 13 itself is symmetrically distributed about the first symmetry axis X0, and the data line data connected to the second gating circuit 12 is located near the display panel. Fig.12 In the left and right border areas, if the display effect is different due to the different structures of the second selection circuit 12 and the first selection circuit 11, the data line data connected to the second selection circuit 12 is close to the border area, and the display difference near the border area of ​​the display panel is not easy to be recognized by the human eye, so the display effect can be guaranteed.

[0072] In a specific implementation, in the display panel provided in the embodiment of the present invention, the shape of the display area can be any symmetrical shape about the first symmetry axis, which is not limited here. Fig.13 As shown, Fig.13 Another structural schematic diagram of a display panel provided in an embodiment of the present invention; the shape of the display area A is circular, and in this case the display panel may be a smart watch, etc., or the shape of the display area A is rectangular, etc.

[0073] Based on the same inventive concept, an embodiment of the present invention further provides a driving method for any of the above display panels provided by the embodiment of the present invention, such as Fig.14 As shown, Fig.14 A flow chart of a method for driving a display panel provided by an embodiment of the present invention; comprising:

[0074] S101, receiving frame image data to be displayed;

[0075] S102, driving the chip to output signals to each gating circuit simultaneously according to the frame image data to be displayed; wherein:

[0076] The signal output by the driving chip to each first selection circuit is a grayscale signal obtained according to the frame image data to be displayed; the signal output by the driving chip to the selection circuit in the selection circuit group is a high-impedance signal or a grayscale signal obtained according to the frame image data to be displayed, and when the signal output by the driving chip to one of the selection circuits in the selection circuit group is a grayscale signal, the signal output by the driving chip to other selection circuits in the selection circuit group is a high-impedance signal.

[0077] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including any of the above display devices provided by the embodiment of the present invention. The display device may be: a smart watch, such as Fig.15The mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and any other product or component with display function can be shown. The implementation of the display device can refer to the above-mentioned display panel embodiment, and the repeated parts will not be repeated.

[0078] A display panel, a driving method thereof and a display device provided by an embodiment of the present invention, since the data output circuit includes at least one gating circuit group and an even number of first gating circuits, the even number of first gating circuits can ensure that the data lines connected to the first gating circuits are symmetrically distributed in the border area. Since the number of data lines connected to a gating circuit group is the same as the number of data lines connected to a first gating circuit, each gating circuit group includes a plurality of second gating circuits, that is, the number of data lines connected to each second gating circuit is at least half of the number of data lines connected to a first gating circuit, it can ensure that the data lines connected to the second gating circuits are symmetrically distributed in the border area or reduce the asymmetry of the distribution of the data lines connected to the second gating circuits in the border area. That is, the display abnormality problem caused by the asymmetric distribution of the data lines in the border area is solved or improved.

[0079] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, characterized in that: include: Display area and border area; The display area includes a plurality of pixels and a plurality of data lines extending along a first direction; The frame area includes a data output circuit, and an output end of the data output circuit is electrically connected to the data line; The data output circuit includes at least one gating circuit group and 2L first gating circuits, wherein L is a positive integer and L≥1; One of the gating circuit groups is electrically connected to the M data lines, and one of the first gating circuits is electrically connected to the N data lines, wherein M=N≥2, and M and N are positive integers respectively; The gating circuit group includes at least two second gating circuits, and the second gating circuits are electrically connected to A data lines, wherein N>A≥1, and A is a positive integer; The at least two second gating circuits share a set of clock signal buses, wherein some of the second gating circuits are connected to some of the clock signal buses of the set of clock signal buses, and another part of the second gating circuits are connected to another part of the clock signal buses of the set of clock signal buses.

2. The display panel according to claim 1, wherein: The display area has a first symmetry axis, and the first symmetry axis extends along the first direction; All the gating circuits are symmetrically distributed around the first symmetry axis.

3. The display panel according to claim 1, wherein: M is an even number, the display panel includes one gating circuit group, and the gating circuit group includes two second gating circuits.

4. The display panel according to claim 1, wherein: M is an odd number, the gating circuit group includes two of the second gating circuits and one third gating circuit, the third gating circuit is electrically connected to B of the data lines, wherein A>B≥1, and B is a positive integer.

5. The display panel according to claim 4, wherein: A is an even number, B is an odd number, and the third gating circuit is located between two of the second gating circuits.

6. The display panel according to claim 3, wherein: 2L first gating circuits are arranged adjacent to each other in sequence between two second gating circuits.

7. The display panel according to claim 3, wherein: The two second gating circuits are arranged adjacent to each other, and L first gating circuits are respectively arranged on both sides of the gating circuit group.

8. The display panel according to claim 6 or 7, characterized in that: The display area has a first symmetry axis, and the first symmetry axis extends along the first direction; The second gating circuits are all electrically connected to C data lines, and C is a positive integer; The second selection circuit located on one side of the first symmetry axis is connected to the first C / 2 clock signal buses in sequence, and the second selection circuit located on the other side of the first symmetry axis is connected to the remaining C / 2 clock signal buses in sequence.

9. The display panel according to claim 4, wherein: 2L first gating circuits are sequentially arranged between two second gating circuits, and L first gating circuits are respectively arranged on both sides of the third gating circuit.

10. The display panel according to claim 5, wherein: L first gating circuits are respectively arranged on both sides of the gating circuit group.

11. The display panel according to claim 6 or 7, characterized in that: L sequentially adjacent first gating circuits and one second gating circuit form a circuit group, and the border area is provided with two circuit groups; There is a gap between the two circuit groups; The display area is also provided with a plurality of signal lines; A first wiring extending along a first direction is also disposed in the gap, and the first wiring is electrically connected to the signal line.

12. The display panel according to claim 11, wherein: The signal line includes a fixed power supply voltage line.

13. The display panel according to claim 11, wherein: The frame area further includes a plurality of clock signal lines arranged along the first direction and electrically connected to the gating circuits; A plurality of clock signal buses extending along a first direction are also arranged at the gap; The clock signal lines electrically connected to the different gating circuits and having the same signal are extended to the gaps and then electrically connected to the corresponding clock signal buses.

14. The display panel according to claim 1, wherein: The display area is circular in shape.

15. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-14.

16. A driving method for a display panel according to any one of claims 1 to 14, characterized in that: include: Receive frame image data to be displayed; According to the frame image data to be displayed, the driving chip simultaneously outputs signals to each of the gating circuits; wherein, The signal output by the driving chip to each of the first gating circuits is a grayscale signal obtained according to the frame image data to be displayed; The signal output by the driving chip to the enable circuit in the enable circuit group is a high-impedance signal or a grayscale signal obtained according to the frame image data to be displayed, and when the signal output by the driving chip to one of the enable circuits in the enable circuit group is a grayscale signal, the signal output by the driving chip to the other enable circuits in the enable circuit group is a high-impedance signal.

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