Display device

Abstract

The disclosure relates to a display device, and more particularly, a display device includes a display panel including a display area, a non-display area, scan lines, power supply lines, and pixels connected to the scan lines and the power supply lines in the display area, a gate driver configured to supply a scan signal to the pixels through the scan lines, and a bias driver configured to supply a bias voltage to the pixels through the power supply lines, wherein a driving period of the pixels includes first and second frames different from each other, the first frame includes a first refresh period in which a first data voltage is written and a first reset period in which the first data voltage is maintained, the second frame includes a second refresh period in which a second data voltage is written and a second reset period in which the second data voltage is maintained, and a first voltage pulse of the bias voltage during the first refresh period and a second voltage pulse of the bias voltage during the second refresh period are different from each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0186162, filed on December 23, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to display devices, and more specifically, to a display device capable of improving display anomalies by applying different driving timings to pixel circuits. Background Technology

[0004] Display devices that display various information on a screen are an important technology in the information and communication era, and they have been continuously developing towards thinner, lighter, more portable, and higher-performance designs. Therefore, display devices that can be manufactured in a lightweight and slim form have always attracted much attention. Display devices using self-emissive elements not only have advantages in power consumption due to low-voltage operation, but also offer excellent high-speed response, high luminous efficiency, wide viewing angle, and high contrast, and are being researched as next-generation display devices. Display devices realize images through multiple sub-pixels arranged in a matrix. Each of these sub-pixels includes a light-emitting device and pixel circuitry such as multiple transistors that independently drive the light-emitting device.

[0005] Specific examples of such display devices (e.g., flat panel displays) can include liquid crystal displays (LCDs), quantum dot displays (QDs), field emission display devices (FEDs), organic light-emitting diode (OLED) displays, and the like. Organic light-emitting diode (OLED) displays, which do not require a separate light source and are gaining attention as devices for compact devices and lifelike color displays, use organic light-emitting diodes (OLEDs) to emit light themselves and have advantages such as fast response time, high contrast, high luminous efficiency, high brightness, and wide viewing angle.

[0006] Organic light-emitting diode (OLED) display devices, including OLEDs, offer various advantages because they display images based on light generated by light-emitting devices within pixels. However, image anomalies can occur when a short circuit occurs between signal lines within a pixel during pixel driving.

[0007] Therefore, various driving techniques have been developed to address image anomalies, and to improve image quality, it is necessary to improve operational performance by controlling the driving conditions of pixels. Summary of the Invention

[0008] The purpose of this disclosure is to provide a display device that can prevent defects such as short circuits caused by potential differences between signal lines by applying different driving timings to the pixel circuits.

[0009] In one embodiment, a display device includes: a display panel including a display area, a non-display area, scan lines, power supply lines, and pixels connected to the scan lines and the power supply lines in the display area; a gate driver configured to supply scan signals to the pixels via the scan lines; and a bias driver configured to supply a bias voltage to the pixels via the power supply lines, wherein a driving cycle (period) of the pixel includes a first frame and a second frame different from the first frame, the first frame including a first refresh period in which a first data voltage is written and a first reset period in which the first data voltage is maintained, the second frame including a second refresh period in which a second data voltage is written and a second reset period in which the second data voltage is maintained, wherein a first voltage pulse of the bias voltage during the first refresh period is different from a second voltage pulse of the bias voltage during the second refresh period.

[0010] In one embodiment, a display device includes: a display panel including a plurality of pixels configured to display an image at one of a plurality of different refresh frequencies, the plurality of different refresh frequencies including a first refresh frequency and a second refresh frequency different from the first refresh frequency; a data driver configured to apply a data voltage to the plurality of pixels; and a gate driver configured to apply a scan signal to the plurality of pixels, wherein at least one of the plurality of pixels includes: a driving element including a gate electrode of the driving element connected to a first node, a first electrode of the driving element connected to a second node, and a second electrode of the driving element connected to a third node, wherein a data voltage from the plurality of data voltages is applied to the second node; a light-emitting element configured to emit light by being driven by a current from the driving element; and a first switching element configured to supply a bias voltage from a power line to the third node connected to the second electrode of the driving element when the light-emitting element is not emitting light, wherein the frequency at which the bias voltage is supplied to the third node during the first refresh frequency is the same as the frequency at which the bias voltage is supplied to the third node during the second refresh frequency.

[0011] In one embodiment, a display panel includes: a light-emitting device; a driving transistor configured to drive the light-emitting device; a bias transistor configured to control the connection between a drain electrode (drain electrode) or a source electrode (source electrode) of the driving transistor and a power supply line; and a data supply transistor configured to control the connection between the drain electrode or a source electrode of the driving transistor and a data line according to a scan signal supplied from a scan line, wherein the scan line and the power supply line are arranged adjacent to each other in a non-display area located outside the display area in which an image is displayed.

[0012] In addition to the technical problems of this disclosure described above, other features and advantages of this disclosure may be described below, or will be clearly understood by those skilled in the art from such description.

[0013] According to embodiments of this disclosure, display abnormalities can be improved by preventing short circuits between two signal lines.

[0014] The effects of this disclosure are not limited to those illustrated above, and may include many other different effects. Attached Figure Description

[0015] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0016] Figures 2A to 2C This is an exemplary circuit diagram of a pixel circuit in a display device according to an embodiment of the present disclosure.

[0017] Figure 3A and Figure 3B The embodiments of this disclosure are used for explanation. Figures 2A to 2C The graphic shown depicts the driving pattern of the pixel circuitry in the display device.

[0018] Figure 4A and Figure 4B This is a schematic plan view of a display panel in a display device according to an embodiment of the present disclosure.

[0019] Figure 5A and Figure 5B This is a diagram used to explain the driving of pixel circuits in a display device according to embodiments of the present disclosure.

[0020] Figure 6 The figure illustrates a configuration in a display device according to an embodiment of the present disclosure, in which a frame is composed of a refresh frame and a reset frame according to the refresh rate. Detailed Implementation

[0021] The advantages and features of this disclosure and its methods will become apparent from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but will be implemented in various different forms. These embodiments are provided merely to explain that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification will be defined by the scope of the claims.

[0022] The shapes, sizes, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to explain the embodiments in this specification are exemplary, and the embodiments in this specification are not limited to the illustrated matters. Furthermore, in describing embodiments, detailed descriptions of related known technologies will be omitted if it is determined that such detailed descriptions may unnecessarily obscure the essential points of the embodiment.

[0023] In this specification, the use of terms such as “comprising,” “having,” or “including” should be understood to imply that additional parts or elements can be added, unless “only” is used. When an element is represented by a singular number, it is understood to include the plural unless otherwise expressly stated.

[0024] In addition, when interpreting components, even if there is no separate explicit description, it should be interpreted as including the error range.

[0025] In descriptions related to spatial relationships, such as when using terms like “on,” “above,” “above,” “below,” “below,” “under,” “below,” “near,” “close to,” or “adjacent” to describe the positional relationship between two elements, unless terms like “directly” or “only” are used, it should be interpreted as one or more elements being able to be further “inserted” between the elements.

[0026] When describing temporal relationships, such as when the temporal relationship is described as "after", "next", "immediately following", "then", "before", discontinuous situations may be included unless "immediately" or "directly" is used.

[0027] When terms such as "first" and "second" are used herein to describe various elements or components (assemblies), it should be understood that these elements or components are not limited thereto. These terms are used only herein to distinguish one element from other elements. Therefore, the first element mentioned below may be a second element within the technical concept of this disclosure.

[0028] The term "at least one" should be understood to include all possible combinations of one or more related elements. For example, "at least one of the first, second, and third elements" may mean all combinations of two or more of the first, second, and third elements, as well as each of the first, second, and third elements.

[0029] The features of the various embodiments in this specification can be combined or coupled to each other in part or in whole, and can be linked or operated in various ways. Furthermore, the various embodiments can be implemented independently of each other, or they can be implemented together in a related manner.

[0030] In the following description, embodiments of the display device according to the present disclosure will be described with reference to the accompanying drawings. When adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible, even if they are indicated in different drawings. In addition, since the proportions of the components shown in the drawings may differ from the actual proportions for ease of description, the proportions shown in the drawings are not limited thereto.

[0031] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0033] refer to Figure 1 The display device 10 may include: a display panel 100 including a plurality of pixels P, a controller 200, a gate driver 300 supplying gate signals to each of the plurality of pixels P, a data driver 400 supplying data signals to each of the plurality of pixels P, a light emission signal generator 500 for supplying emission signals to each of the plurality of pixels P, and a bias driver 600.

[0034] The controller 200 can process RGB image data input from the external display device 10 according to the size and resolution of the display panel 100, and supply the processed image data to the data driver 400. The controller 200 can use an externally input synchronization signal SYNC, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsyn, to generate multiple gate control signals GCS, data control signals DCS, and transmit control signals ECS. The generated multiple gate control signals GCS, data control signals DCS, and transmit control signals ECS can be supplied to the gate driver 300, the data driver 400, and the light-emitting signal generator 500 to control the gate driver 300, the data driver 400, and the light-emitting signal generator 500, respectively.

[0035] The controller 200 can be configured in combination with various processors, depending on the device on which the controller is installed, such as microprocessors, mobile processors, application processors, etc.

[0036] The controller 200 can generate signals to drive the plurality of pixels P at various refresh rates. That is, the controller 200 can generate drive-related signals to drive each pixel in variable refresh rate (VRR) mode or to switch between a first refresh rate and a second refresh rate. For example, the controller 200 can simply change the speed of a clock signal, generate a synchronization signal to generate horizontal or vertical spacing, or drive the gate driver 300 using a masking method to drive the plurality of pixels P at various refresh rates.

[0037] Each of the plurality of pixels P can be driven by a combination of refresh frames and reset frames according to the refresh rate within a frame. Thus, a frame in which an image is displayed includes a refresh frame period (e.g., a display period) and a reset frame period (e.g., horizontal or vertical blanking).

[0038] For example, if the refresh rate is driven at 120Hz, pixel P can be driven with refresh frames (no reset frames), and if the refresh rate is driven at 10Hz (or 60Hz), refresh frames and reset frames can be driven alternately. In particular, for example, if the refresh rate is driven at 1Hz, one refresh frame and multiple reset frames can be configured as a group within a frame and can be driven repeatedly.

[0039] Additionally, the controller 200 can generate various signals for driving pixels at a first refresh rate. Specifically, when driving pixels at the first refresh rate, the controller 200 can generate a transmit control signal ECS for the light-emitting signal generator 500 to generate a transmit signal EM(n) with a first duty cycle. Thereafter, the controller 200 can operate (run) to drive pixels at a second refresh rate and can generate various signals for driving pixels at the second refresh rate. Specifically, when driving pixels at the second refresh rate, the controller can generate the transmit control signal ECS so that the light-emitting signal generator 500 generates a transmit signal EM(n) with a second duty cycle different from the first duty cycle.

[0040] The gate driver 300 can supply a scan signal SC to the gate line GL according to the gate control signal GCS supplied from the controller 200. Although Figure 1 The figure shows the gate driver 300 spaced apart from one side of the display panel 100, but the number and arrangement of the gate drivers 300 are not limited to this. That is, the gate drivers 300 can be arranged on one or both sides of the display panel 100 using the gate in-panel (GIP) method.

[0041] The data driver 400 converts image data RGB into data voltage Vdata according to the data control signal DCS supplied from the controller 200, and supplies the converted data voltage Vdata to the pixels through the data line DL.

[0042] In the display panel 100, multiple gate lines GL, multiple emitter lines EL, and multiple data lines DL can intersect each other, and each of the multiple pixels can be connected to the gate lines GL, emitter lines EL, and data lines DL. Specifically, a pixel receives a gate signal from a gate driver 300 via the gate line GL, a data signal from a data driver 400 via the data line DL, an emitter signal EM(n) via the emitter line EL, and various power supplies via power lines. Here, the gate line GL supplies the scan signal SC, the emitter line EL supplies the emitter signal EM(n), and the data line DL supplies the data voltage Vdata. However, according to various embodiments, the gate line GL may include multiple scan signal lines, and the data line DL may additionally include multiple power supply lines VL. Moreover, the emitter line EL may include multiple emitter signal lines. In addition, a pixel receives a high potential voltage or a first power supply voltage ELVDD and a low potential voltage or a second power supply voltage ELVSS. In addition, first and second bias voltages V1 and V2 can be supplied via one or more power supply lines VL. The first bias voltage V1 can be supplied from the bias driver 600.

[0043] In addition, each pixel includes a light-emitting device (ELD) and a pixel circuit for controlling the ELD. Here, the ELD includes an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The pixel circuit includes multiple switching devices, driving switching devices, and a capacitor. Here, the switching devices can be composed of TFTs, and in the pixel circuit, the driving TFT controls the amount of current supplied to the ELD based on the difference between the data voltage charged in the capacitor and a reference voltage, thereby adjusting the amount of light emitted by the ELD. Furthermore, the multiple switching TFTs receive a scan signal SC(n) supplied through the gate line GL and an emission signal EM(n) supplied through the emission line EL to charge the capacitor with a data voltage Vdata.

[0044] Figures 2A to 2C This is an exemplary circuit diagram of a pixel circuit in a display device according to an embodiment of the present disclosure.

[0045] Figures 2A to 2CA pixel circuit for illustrative purposes is illustrated, but the method is not limited thereto, as long as it has a structure capable of controlling the light emission of the light-emitting device ELD by applying an emission signal EM(n). For example, the pixel circuit may include an additional scan signal, a switching TFT connected thereto, and a switching TFT with an applied initialization voltage, and the connection relationships between the switching devices or the connection positions of the capacitors can be configured differently. That is, if the light emission of the light-emitting device ELD is controlled according to the change in the duty cycle of the emission signal EM(n) and the light emission can be controlled according to the refresh rate, pixel circuits with various structures can be used. For example, various pixel circuits such as 3T1C, 4T1C, 6T1C, 7T1C, and 7T2C can be used. In the following description, for convenience, the following will describe... Figures 2A to 2C A display device with a 7T1C type pixel circuit.

[0046] refer to Figure 2A Each of the plurality of pixels P may include a pixel circuit and a light-emitting device ELD connected to the pixel circuit, wherein the pixel circuit includes a driving transistor DT.

[0047] The pixel circuit can drive the light-emitting device (ELD) by controlling the drive current Id flowing through it. The pixel circuit may include a drive transistor DT, first to sixth transistors T1 to T6, and a storage capacitor Cst. Each of transistors DT and T1 to T6 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode, and the other of the first and second electrodes may be a drain electrode.

[0048] Each of transistors DT and T1 through T6 can be a PMOS transistor or an NMOS transistor. Figure 2A and Figure 2B In this embodiment, the first transistor T1 is an NMOS transistor, while the remaining transistors DT and T2 through T6 are PMOS transistors. Additionally, in... Figure 2C In one embodiment, the first transistor T1 is configured as a PMOS transistor instead of an NMOS transistor.

[0049] In the following description, an exemplary case will be provided in which the first transistor T1 is an NMOS transistor, while the remaining transistors DT, T2 through T6 are PMOS transistors. Therefore, the first transistor T1 is turned on by applying a logic high voltage, while the other transistors DT, T2 through T6 are turned on by applying a logic low voltage.

[0050] According to the example, the first transistor T1 constituting the pixel circuit can be used as a compensation transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 and the fourth transistor T4 can be used as light-emitting control transistors, and the fifth transistor T5 and the sixth transistor T6 can be used as bias transistors.

[0051] A light-emitting device (ELD) may include a pixel electrode (or anode electrode) and a cathode electrode. The pixel electrode of the ELD may be connected to a fifth node N5, while the cathode electrode may be connected to a second power voltage ELVSS.

[0052] The driving transistor DT may include a first electrode connected to a second node N2, a second electrode connected to a third node N3, and a gate electrode connected to a first node N1. The driving transistor DT may provide a driving current Id to the light-emitting device ELD based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst, which will be described later).

[0053] The first transistor T1 may include a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate electrode that receives a first scan signal SC1(n) via a first scan line SL1. The scan signal SC1(n) may vary between a first level and a second level, wherein the first level is greater than the second level. The first transistor T1 may be turned on in response to the first scan signal SC1(n) and may transmit a data signal Vdata to the first node N1. The first transistor T1 may be diode-connected between the first node N1 and the third node N3 to sample the threshold voltage Vth of the driving transistor DT. The first transistor T1 may be a compensation transistor.

[0054] A capacitor Cst can be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst can store or maintain the provided data signal Vdata.

[0055] The second transistor T2 has a first electrode connected to the data line DL (or receiving the data signal Vdata), a second electrode connected to the second node N2, and a gate electrode that receives the second scan signal SC2(n) via the second scan line SL2. The second transistor T2 can be turned on via the second scan line SL2 in response to the second scan signal SC2(n), and can transmit the data signal Vdata to the second node N2. The second transistor T2 can be a data supply transistor.

[0056] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) can be connected between the first power voltage ELVDD and the light-emitting device ELD, and can form a current movement path through which the driving current Id generated by the driving transistor DT flows.

[0057] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive the first power voltage ELVDD, a second electrode connected to the second node N2, and a gate electrode for receiving the transmit signal EM(n) via the transmit line EL.

[0058] Similarly, the fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fourth node N5 (or the pixel electrode of the light-emitting device ELD), and a gate electrode that receives the emission signal EM(n) through the emission line EL.

[0059] The third transistor T3 and the fourth transistor T4 can be turned on in response to the emission signal EM(n), and in this case, the drive current Id is provided to the light-emitting device ELD, and the light-emitting device ELD can emit light with a brightness corresponding to the drive current Id.

[0060] The fifth transistor T5 may include a first electrode connected to the third node N3, a second electrode receiving a first bias voltage V1 via a first power supply line VL1, and a gate electrode receiving a third scan signal SC3(n) via a third scan line SL3. Here, the power supply line VL may include a first power supply line VL1 and a second power supply line VL2.

[0061] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode receiving a second bias voltage V2 via a second power supply line VL2, and a gate electrode receiving a third scan signal SC3(n) via a third scan line SL3. Figure 2A In this embodiment, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to jointly receive the third scan signal SC3(n) through the third scan line SL3. However, this disclosure is not limited thereto, and as such... Figure 2B and Figure 2C As shown, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to receive separate third scan signals SC3_a(n) and SC3_b(n) through separate (discrete) third scan lines SL3a and SL3b that will be independently controlled (separated).

[0062] The sixth transistor T6 can be turned on in response to the third scan signal SC3(n) before (or after) the light-emitting device (ELD) emits light, and the pixel electrode (or anode electrode) of the ELD can be initialized using the second bias voltage V2. The ELD may have a parasitic capacitor formed between the pixel electrode and the cathode electrode. Furthermore, the parasitic capacitor is charged while the ELD emits light, allowing the pixel electrode of the ELD to have a specific voltage. Therefore, by applying the second bias voltage V2 to the pixel electrode of the ELD via the sixth transistor T6, the amount of charge accumulated in the ELD can be initialized.

[0063] Figure 3A and Figure 3B This is based on an embodiment for explanation. Figures 2A to 2C The graphic shown depicts the driving pattern of the pixel circuitry in the display device.

[0064] refer to Figure 3A and Figure 3B Each of the plurality of pixels P can initialize the voltage charged or remaining in the pixel circuit. Specifically, the influence of the data voltage Vdata and driving voltage VDD stored in the previous frame can be removed. Therefore, each of the plurality of pixels P can display an image corresponding to the new data voltage Vdata.

[0065] The operation of the pixel circuit can be performed by including at least one initialization period, a sampling period, and an emission period, but this is just an example and is not necessarily limited to this order.

[0066] A display device according to embodiments of the present disclosure can be driven by dividing a frame into refresh frames and reset frames. In a refresh frame, a data voltage Vdata can be programmed in each pixel P, and a light-emitting device (ELD) can emit light. Additionally, a reset frame can be a vertical (vertical) blank frame, during which the anode electrode of the light-emitting device (ELD) is reset. In this disclosure, "frame," "refresh frame," and "reset frame" can be concepts of time periods, and in some cases, can have the meaning of an image or driving mode.

[0067] In a display device according to an embodiment of the present disclosure, a refresh frame can be divided into a conduction bias stress period Tobs (hereinafter referred to as a "stress period"), an initial period Ti, a sampling period Ts, and an emission period Te. The stress period Tobs is the period during which bias stress is applied to the first node N1, which serves as the gate electrode of the driving transistor DT. The initial period Ti is the period used to initialize the voltage at the third node N3, which serves as the drain electrode of the driving transistor DT. The sampling period Ts is the period used to sample the threshold voltage Vth of the driving transistor DT and program the data voltage Vdata. The emission period Te is the period during which the light-emitting device ELD emits light according to the drive current generated by the programming source-gate voltage of the driving transistor DT.

[0068] Specifically, refer to the example shown that illustrates a refresh frame. Figure 3A During the first stress period Tobs, the third scan signal SC3(n), especially as Figure 2B and Figure 2C The third scan signal SC3_a(n) shown is a low level, which serves as the on-state. Therefore, the fifth transistor T5 is turned on to apply a first bias voltage V1 from the power supply line VL to the third node N3. The first bias voltage V1 can be a stress voltage Vobs or an initialization voltage Vini. The stress voltage Vobs can be selected within a voltage range sufficiently higher than the operating voltage of the light-emitting device ELD, and can be set to be equal to or lower than the first drive power ELVDD. That is, a bias stress can be applied to the third node N3, which serves as the drain electrode of the drive transistor DT, during the first stress period Tobs to reduce the gate-source voltage Vgs of the drive transistor DT. Therefore, the hysteresis effect of the drive transistor DT can be reduced by allowing the source-drain current Ids of the drive transistor DT to flow during the first stress period Tobs.

[0069] Additionally, the sixth transistor T6 is turned on to apply a reset voltage VAR to the fifth node N5. That is, the anode electrode of the light-emitting device (ELD) is reset to the second bias voltage V2. The second bias voltage V2 can be the reset voltage VAR.

[0070] In addition, refer to Figure 3ADuring the initial period Ti, the first scan signal SC1(n) is at a high level as the on-state, and the third scan signal SC3(n) is at a low level as the on-state. Therefore, the first transistor T1 and the fifth transistor T5 are turned on to apply the initialization voltage Vini from the power supply line VL to the third node N3. As a result, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the light-emitting device ELD, and can be set to be equal to or lower than the second drive power VSSEL. Additionally, during the initial period Ti, the sixth transistor T6 is turned on again to apply the reset voltage VAR to the fifth node N5.

[0071] Additionally, refer to Figure 3A During the sampling period Ts, the first scan signal SC1(n) is at a high level as the on-state, and the second scan signal SC2(n) is at a low level as the on-state. During the sampling period Ts, the second transistor T2 is turned on, and the data voltage Vdata is applied to the second node N2. Additionally, when the first transistor T1 is also turned on, the driving transistor DT is diode-connected, and the gate and drain electrodes of the driving transistor DT are short-circuited, causing the driving transistor DT to operate like a diode.

[0072] During the sampling period Ts, the current Ids flows between the source and drain of the driving transistor DT. Since the gate and drain electrodes of the driving transistor DT are in a diode connection state, the voltage of the second node N2 increases through the current flowing from the source electrode to the drain electrode until the gate-source voltage Vgs of the driving transistor DT is Vth.

[0073] Further, refer to Figure 3A During the second stress period Tobs, the third scan signal SC3(n), especially as Figure 2B and Figure 2C The third scan signal SC3_b(n) shown is a low level, which serves as the on-state. Therefore, the sixth transistor T6 is turned on to apply a reset voltage VAR to the fifth node N5. That is, the anode electrode of the light-emitting device (ELD) is reset to the reset voltage VAR. Furthermore, the fifth transistor T6 is turned on to apply a stress voltage Vobs to the third node N3. In other words, the hysteresis effect of the driving transistor DT can be mitigated by applying bias stress to the third node N3, which serves as the drain electrode of the driving transistor DT, during the second stress period Tobs.

[0074] Additionally, refer to Figure 3ADuring the transmission period Te, the transmitted signal EM(n) is at a low level, which is the on-state. Therefore, the third transistor T3 is turned on to apply the first drive power ELVDD to the first node N1. Additionally, since the second node N2 is coupled to the first drive power ELVDD through the storage capacitor Cst, the first drive power ELVDD is also reflected in the second node N2. Furthermore, the fourth transistor T4 is also turned on to form a current path between the third node N3 and the fourth node N4. As a result, the drive current Ioled through the source and drain electrodes of the driving transistor DT is applied to the light-emitting device ELD.

[0075] Additionally, refer to the example of a reset frame. Figure 3B During the reset frame, the first scan signal SC1(n) is maintained at a low level as a turn-off level (for Figure 2A and Figure 2B (As in the example), the second scan signal SC2(n) is also maintained at a high level as a shutdown level. Therefore, during the reset frame, the data voltage Vdata is not programmed into each pixel P.

[0076] However, the third scan signal SC3(n) can oscillate periodically (alternate). That is, when the third scan signal SC3(n) oscillates periodically, the reset frame can include multiple stress periods Tobs. However, this disclosure is not limited thereto, and as... Figure 3B As shown, a stress period Tobs can be included in the reset frame.

[0077] In other words, during the reset frame, the anode electrode of the light-emitting device ELD is reset to the reset voltage VAR, and bias stress is applied to the third node N3, which serves as the drain electrode of the driving transistor DT.

[0078] As a result, in the display device according to embodiments of the present disclosure, the anode electrode of the light-emitting device (ELD) can be periodically reset during refresh frames and reset frames. Therefore, it is possible to prevent the voltage of the anode electrode of the ELD from continuously increasing due to leakage current, allowing the anode electrode of the ELD to maintain a constant voltage level. Consequently, brightness variations in the display device can be reduced, thereby improving image quality.

[0079] Figure 4A and Figure 4B This is a schematic plan view of a display panel in a display device according to an embodiment of the present disclosure.

[0080] refer to Figure 4A The display panel 100 may include a display area (or effective area) AA and a non-display area (or non-effective area) NA.

[0081] The display area AA is the region where pixels P are arranged to display the image.

[0082] The non-display area NA can be set around the display area AA. For example, the non-display area NA can be set along the edge of the display area AA. The non-display area NA can refer to all areas other than the display area AA, and can be a border area.

[0083] A method for driving pixel P can be provided in the non-display area NA (e.g., such as...). Figure 4A The drivers for pixels P1 and P2 shown are included. The drivers may include, for example, a gate driver 300, a light emission signal generator 500, and a bias driver 600.

[0084] Pixel P can have Figures 2A to 2C The pixel circuit structure is shown. Therefore, the gate driver 300, the light emission signal generator 500, and the bias driver 600 can supply the first to third scan signals SC1(n) to SC3(n) and the emission signal EM(n) to the pixel P.

[0085] The gate driver 300 may include a first scan driver 310 for outputting a first scan signal SC1(n) to multiple first scan lines SL1, a second scan driver 320 for outputting a second scan signal SC2(n) to multiple second scan lines SL2, and a third scan driver 330 for outputting a third scan signal SC3(n) to multiple third scan lines SL3. The light-emitting signal generator 500 may output an emission signal EM(n) to multiple emission lines EL. Further, the bias driver 600 may output a first bias voltage V1 to multiple power supply lines VL.

[0086] In a display device according to an embodiment of the present disclosure, at least one of the first to third scan drivers 310, 320, and 330 may be configured to include a first driver that outputs odd-numbered scan signals and a second driver that outputs even-numbered scan signals. For example, the second scan driver 320 may include a second-1 driver 321 for outputting a second odd-numbered scan signal SC2_O to a first set of scan lines of the second scan line SL2 and a second-2 driver 322 for outputting a second even-numbered scan signal SC2_E to a second set of scan lines of the second scan line SL2. In this case, the first set of scan lines that outputs the second odd-numbered scan signal SC2_O may be the second odd-numbered scan line SL2_O, and the second set of scan lines that outputs the second even-numbered scan signal SC2_E may be the second even-numbered scan line SL2_E.

[0087] The first to third scan drivers 310, 320, and 330, the light-emitting signal generator 500, and the bias driver 600 can be integrally formed in the non-display area NA of the display panel 100 according to the gate in-panel (GIP) method. For example, the first to third scan drivers 310, 320, and 330, the light-emitting signal generator 500, and the bias driver 600 can be disposed on both the right (or upper) and left (or lower) sides of the display area NA.

[0088] In one embodiment, the first scan driver 310 and the third scan driver 330 can be disposed in the right frame region of the display area AA, i.e., the right non-display area NA, while the light-emitting signal generator 500 and the bias driver 600 can be disposed in the left frame region of the display area AA, i.e., the left non-display area NA. The first scan driver 310 and the third scan driver 330 can be disposed adjacent to each other in the row direction in the right frame region. The light-emitting signal generator 500 and the bias driver 600 can be disposed adjacent to each other in the row direction in the left frame region.

[0089] In this embodiment, the first scan driver 310 and the third scan driver 330 can simultaneously apply signals with the same waveform to each of the first and third scan lines SL1 and SL3 from one side (i.e., the left or right side) of the display area AA. Additionally, the light emission signal generator 500 and the bias driver 600 can also simultaneously apply signals with the same waveform to each of the emission line EL and the power supply line VL from either the left or right side of the display area AA.

[0090] In one embodiment, a plurality of second scan drivers 320 are provided in the left and right bezel regions. Each of the second scan drivers 320 can provide a second scan signal SC2(n) to the second odd-numbered scan line SL2_O and the second even-numbered scan line SL2_E. The second-1 drivers 321 and the second-2 drivers 322 of the second scan drivers 320 can be arranged adjacent to each other in the column direction in the bezel regions. That is, the second-1 drivers 321 and the second-2 drivers 322 are aligned (aligned) in the direction in which the data lines extend in the display panel 100.

[0091] In this embodiment, the second scan driver 320 can be configured to simultaneously apply a second scan signal SC2(n) of the same waveform to a second scan line SL2 from both sides.

[0092] refer to Figure 4B The second odd-numbered scan line SL2_O and the power supply line VL can be set adjacent to each other.

[0093] In one embodiment, if the data driver 400 is manufactured as a driver chip, the data driver 400 can be mounted on a flexible film using a chip-on-film (COF) method. The COF-type flexible film can be attached to the display panel 100, and the area where the flexible film contacts the display panel 100 can be referred to as the film-on-panel (FOP) portion.

[0094] When driven in a high-temperature, high-humidity environment, display abnormalities may occur. Specifically, because the second odd-numbered scan line SL2_O, which has a higher potential voltage level, and the power supply line VL, which has a lower potential voltage level than the second scan signal SC2 applied to the second odd-numbered scan line SL2_O, are positioned adjacent to each other, defects may occur due to the large potential difference between the second odd-numbered scan line SL2_O and the power supply line VL. In other words, dendrite formation may occur from the low-potential power supply line VL to the high-potential second odd-numbered scan line SL2_O on the FOP section. In this case, the power supply line VL and the second odd-numbered scan line SL2_O may short-circuit. With the low-potential power supply line VL and the high-potential second odd-numbered scan line SL2_O short-circuited, an overcurrent flows. Furthermore, to prevent damage caused by this, the power supply circuit (not shown) may be shut off based on an internal feedback signal. Therefore, the display panel 100 may not display an image.

[0095] Figure 5A and Figure 5B This is a diagram used to explain the driving of pixel circuits in a display device according to embodiments of the present disclosure.

[0096] refer to Figure 5A and Figure 5B To prevent a short circuit between the low-potential power supply line VL and the high-potential second odd-numbered scan line SL2_O, the refresh frame can be configured to include multiple refresh frames, such as a first refresh frame RF1 and a second refresh frame RF2 having a different driving timing than the first refresh frame RF1, based on a first bias voltage V1. Similarly, like the refresh frame, the reset frame can be configured to include multiple reset frames, including a first reset frame AR1 and a second reset frame AR2 with different driving timings. Although not shown in the figures, it should be noted that, if necessary, the refresh frame can be configured to include a third or more refresh frames having a different driving timing than the first refresh frame RF1 and the second refresh frame RF2, and the reset frame can be configured to include a third or more reset frames having a different driving timing than the first reset frame AR1 and the second reset frame AR2.

[0097] refer to Figure 5AThe first refresh frame RF1 can be driven at a high level (e.g., a first level voltage) such that a first bias voltage V1 with a high level is applied as the stress voltage Vobs during the stress period Tobs, and the first refresh frame RF1 can be driven at a low level (e.g., a second level voltage) such that a first bias voltage V1 with a low level is applied as the initialization voltage Vini during the initial period Ti. Furthermore, the first bias voltage V1 applied at a high level during the stress period Tobs can switch back to a low level after the stress period Tobs ends.

[0098] When the first bias voltage V1 is driven to the first stress voltage Vobs, the high level can be maintained for, for example, at least 8 horizontal time periods (e.g., a first duration), and when the first bias voltage V1 is driven to the second stress voltage Vobs, the high level can be maintained for, for example, at least 16 horizontal time periods (e.g., a second duration). Additionally, when the first bias voltage V1 is driven to the initialization voltage Vini, the first bias voltage V1 can be maintained at a low level for, for example, at least 20 horizontal time periods.

[0099] In the second refresh frame RF2, the first bias voltage V1, applied at a high level during the second stress period Tobs, can remain high without switching back to a low level. In other words, the first bias voltage V1 can be high for all remaining periods except for at least 20 horizontal periods between stress periods Tobs driven by the first and second stress voltages Vobs. Therefore, during the second refresh frame RF2, the first bias voltage V1 is low between the first and second stress periods Tobs, but after the second stress period, the first bias voltage is high for a certain period of time. In other words, the voltage pulse of the first bias voltage V1 during the second stress period of the second refresh frame is different from the voltage pulse of the first bias voltage V1 during the second stress period of the first refresh frame. Figure 5A As shown, the voltage pulse of the first bias voltage V1 during the second stress period of the second refresh frame is wider than the voltage pulse of the first bias voltage V1 during the second stress period of the first refresh frame.

[0100] refer to Figure 5B The first reset frame AR1 can be driven high, such that a first bias voltage V1 with a high level is applied as a stress voltage Vobs during the stress period Tobs, and can be switched back to low after the stress period Tobs ends. In the first reset frame AR1, when the first bias voltage V1 is driven as the third stress voltage Vobs, the high level can be maintained for, for example, at least 44 level periods.

[0101] In the second reset frame AR2, the first bias voltage V1 may not switch to a low level, but may remain at a high level during the second reset frame AR2.

[0102] Figure 6 The figure illustrates a configuration in a display device according to an embodiment of the present disclosure, in which a frame is composed of refresh frames and reset frames according to a refresh rate (e.g., refresh frequency). In one embodiment, the refresh rate can be selected from a plurality of different refresh rates. For example, the plurality of different refresh rates may have a fastest refresh rate (e.g., 120Hz), a slowest refresh rate (e.g., 1Hz), and one or more intermediate refresh rates (e.g., 60Hz) between the fastest and slowest refresh rates. Due to the timing of the refresh frames and reset frames, the frequency at which the bias voltage V1 is supplied to the third node N3 is the same during the different refresh frequencies.

[0103] refer to Figure 6 When the refresh rate is driven at 120Hz (e.g., the fastest refresh rate), the display device can be driven by only refresh frames, and when the refresh rate is driven at 60Hz (e.g., an intermediate refresh rate), refresh frames and reset frames can operate alternately. In particular, for example, if the refresh rate is driven at 1Hz (e.g., the slowest refresh rate), one refresh frame and multiple reset frames can be configured as a group and driven repeatedly within a single frame.

[0104] When driving the display device at a refresh rate of 120Hz only during the driving timing of the first refresh frame RF1, stress may occur due to the approximately 99% potential difference per frame between the adjacent high-potential second odd-numbered scan line SL2_O and the low-potential power supply line VL. Therefore, driving the display device only with the first refresh frame RF1 is not desirable.

[0105] On the other hand, when the first refresh frame RF1 and the second refresh frame RF2 are applied alternately, the stress may be halved due to the potential difference between the adjacent high-potential second odd-numbered scan line SL2_O and the low-potential power supply line VL. At a refresh rate of 60Hz, a first refresh frame RF1 and a first reset frame AR1 constitute a frame, and can be operated alternately with another frame including a second refresh frame RF2 and a second reset frame AR2.

[0106] Similarly, at a refresh rate of 1Hz, a first refresh frame RF1 and 119 first reset frames AR1 can constitute a frame, and likewise, can be operated alternately with another frame including a second refresh frame RF2 and a second reset frame AR2. Due to the application of a first bias voltage V1 during at least one of the first refresh period RF1, the second refresh period RF2, the first reset period AR1, or the second reset period AR2, the frequency at which the bias voltage V1 is supplied to the third node N3 during different refresh frequencies matches one of a plurality of different refresh frequencies. In one embodiment, the frequency at which the bias voltage V1 is supplied to the third node N3 during different refresh frequencies matches the fastest refresh frequency among the plurality of different refresh frequencies.

[0107] Therefore, dendrite formation caused by the potential difference between the second odd scan line SL2_O and the power supply line (VL) can be reduced, thus preventing short circuits between the two signal lines and improving display abnormalities.

[0108] The display device according to embodiments of this specification can be described as follows.

[0109] In one embodiment, a display device includes: a display panel including a display area, a non-display area, scan lines, power lines, and pixels connected to the scan lines and the power lines in the display area; a gate driver configured to supply scan signals to the pixels via the scan lines; and a bias driver configured to supply a bias voltage to the pixels via the power lines, wherein the driving cycle of the pixels includes a first frame and a second frame different from the first frame, the first frame including a first refresh period in which a first data voltage is written and a first reset period in which the first data voltage is maintained, the second frame including a second refresh period in which a second data voltage is written and a second reset period in which the second data voltage is maintained, and wherein a first voltage pulse of the bias voltage during the first refresh period is different from a second voltage pulse of the bias voltage during the second refresh period.

[0110] In one embodiment, the first refresh period alternately includes two or more first level bias periods and two or more second level bias periods, wherein in the first level bias period, the bias voltage has a first voltage, and in the second level bias period, the bias voltage has a second voltage less than the first voltage, and wherein the second refresh period includes one second level bias period and two first level bias periods, wherein in the second level bias period, the bias voltage has a second voltage, and in the first level bias period, the bias voltage has a first voltage.

[0111] In one embodiment, the first refresh period includes: a first period in which the scan signal has a first level greater than the second level of the scan signal; a second period after the first period in which the bias voltage has a first level voltage; and a third period after the second period in which the bias voltage has a second level voltage less than the first level of the bias voltage; wherein the second refresh period includes: a fourth period in which the scan signal has the first level (horizontal) of the scan signal; and a fifth period after the fourth period in which the bias voltage maintains the first level of the bias voltage.

[0112] In one embodiment, during the first reset period, the level of the bias voltage changes once or more between a first level and a second level lower than the first level, and during the second reset period, the bias voltage is maintained at the first level.

[0113] In one embodiment, the scan lines and the power supply lines are adjacent to each other in a non-display area located outside the display area where the image is displayed.

[0114] In one embodiment, the gate driver includes a first scan driver, a plurality of second scan drivers, and a third scan driver, wherein the first scan driver and the third scan driver are disposed in a non-display area on a first side of the display area, and the plurality of second scan drivers are disposed in a non-display area on the first side of the display area and on a second side of the display area opposite to the first side.

[0115] In one embodiment, the plurality of second scan drivers disposed in the non-display areas on the first and second sides of the display area are configured to simultaneously apply the scan signal to the scan line.

[0116] In one embodiment, the first scan driver and the third scan driver are disposed in a non-display area on the first side of the display area, and the bias driver is disposed in a non-display area on the second side of the display area.

[0117] In one embodiment, the display panel includes a plurality of scan lines, and the plurality of second scan drivers include a scan driver configured to apply a scan signal to odd-numbered scan lines from the plurality of scan lines during the first refresh frame, and another scan driver configured to apply a scan signal to even-numbered scan lines from the plurality of scan lines during the first refresh frame.

[0118] In one embodiment, the display panel includes a plurality of data lines, and the plurality of second scan drivers are arranged in the direction in which the plurality of data lines extend in the display panel.

[0119] In one embodiment, one of the plurality of scan lines and the power supply line are directly adjacent to each other in the display panel.

[0120] In one embodiment, a display device includes: a display panel including a plurality of pixels configured to display an image at one of a plurality of different refresh frequencies, the plurality of different refresh frequencies including a first refresh frequency and a second refresh frequency different from the first refresh frequency; a data driver configured to apply a data voltage to the plurality of pixels; and a gate driver configured to apply a scan signal to the plurality of pixels, wherein at least one of the plurality of pixels includes: a driving element including a gate electrode of the driving element connected to a first node, a first electrode of the driving element connected to a second node, and a second electrode of the driving element connected to a third node, wherein a data voltage from the plurality of data voltages is applied to the second node; a light-emitting element configured to emit light by being driven by a current from the driving element; and a first switching element configured to supply a bias voltage from a power line to the third node connected to the second electrode of the driving element when the light-emitting element is not emitting light, wherein the frequency at which the bias voltage is supplied to the third node during the first refresh frequency is the same as the frequency at which the bias voltage is supplied to the third node during the second refresh frequency.

[0121] In one embodiment, the frequency at which the bias voltage is supplied during the first refresh frequency and the frequency at which the bias voltage is supplied during the second refresh frequency are matched with a first frequency from the plurality of different refresh frequencies, wherein the first frequency is greater than the second frequency.

[0122] In one embodiment, in response to the refresh frequency being the first frequency, the frame period of the display device includes a first refresh frame and a second refresh frame following the first refresh frame. The first refresh frame has a first timing sequence during which the bias voltage is applied according to the first timing sequence. The second refresh frame has a second timing sequence different from the first timing sequence during which the bias voltage is applied according to the second timing sequence. The first timing sequence is a first time period during which the bias voltage is applied to the third node at the first time period, and the second timing sequence is a second time period during which the bias voltage is applied to the third node at the second time period, the second time period being longer than the first time period.

[0123] In one embodiment, in response to the refresh frequency being the second frequency, a first frame period of the display device includes a first refresh frame and one or more first reset frames following the first refresh frame, wherein during the first refresh frame, the data voltage is written, and the first refresh frame has a first refresh timing, during which the bias voltage is applied to the third node according to the first refresh timing; during the first reset frame, the written data voltage is maintained, and the first reset frame has a first reset timing, during which the bias voltage is applied to the third node according to the first reset timing; wherein a second frame period of the display device following the first frame period includes a second refresh frame and one or more second reset frames following the second refresh frame, wherein during the second refresh frame, another data voltage is written, and the second refresh frame has a second refresh timing, during which the bias voltage is applied to the third node according to the second refresh timing; During the second reset frame, another data voltage is maintained, and the second reset frame has a second reset timing, wherein the bias voltage is applied to the third node during the first reset frame in the second reset timing, wherein the first refresh timing is a first refresh time period, during the first refresh frame, the bias voltage is applied to the third node at the first refresh time period, and the second refresh timing is a second refresh time period, during the second refresh frame, the bias voltage is applied to the third node at the second refresh time period, the second refresh time period being longer than the first refresh time period, and wherein the first reset timing is a first reset time period, during the first reset frame, the bias voltage is applied to the third node at the first reset time period, and the second reset timing is a second reset time period, during the second reset frame, the bias voltage is applied to the third node at the second reset time period, the second reset time period being longer than the first reset time period.

[0124] In one embodiment, at least one of the plurality of pixels further includes: a first switching element that connects the first node and the third node diode; a second switching element configured to apply the data voltage to the second node; a third switching element configured to apply a high potential voltage from the fourth node to the second node; a fifth switching element configured to apply another bias voltage to the anode electrode of the light-emitting device; and a storage capacitor having a first electrode connected to the first node and a second electrode connected to the fourth node.

[0125] In one embodiment, the other bias voltage is applied to the anode electrode of the light-emitting device, while the bias voltage is applied to the third node.

[0126] In one embodiment, a display panel includes: a light-emitting device; a driving transistor configured to drive the light-emitting device; a bias transistor configured to control the connection between the drain or source electrode of the driving transistor and a power supply line; and a data supply transistor configured to control the connection between the drain or source electrode of the driving transistor and a data line according to a scan signal supplied from a scan line, wherein the scan line and the power supply line are arranged adjacent to each other in a non-display area located outside the display area in which an image is displayed.

[0127] In one embodiment, the power line supplies a bias voltage to one of the drain or source electrodes of the driving transistor.

[0128] In one embodiment, the drive cycle includes a first frame and a second frame different from the first frame, wherein the first frame includes a first refresh period in which a first data voltage is written and a first reset period in which the first data voltage is maintained, the second frame includes a second refresh period in which a second data voltage is written and a second reset period in which the second data voltage is maintained, and wherein a first voltage pulse of the bias voltage during the first refresh period is different from a second voltage pulse of the bias voltage during the second refresh period.

[0129] The features, structures, effects, etc., described in the examples above in this disclosure are included in at least one embodiment of this disclosure, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc., exemplified in at least one example of this disclosure can be combined or modified by those skilled in the art with respect to other examples. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of this disclosure.

[0130] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the invention. Therefore, the embodiments disclosed herein are not intended to limit the spirit of the invention, but rather to exemplify the invention, and the scope of the spirit of the invention is not limited by these embodiments. Thus, it should be understood that the above embodiments are illustrative and not restrictive in all respects. The scope of protection of the invention should be interpreted by the following claims, and all technical concepts within their equivalents should be interpreted as being included within the scope of the invention.

Claims

1. A display device comprising: A display panel includes a display area, a non-display area, scan lines, power lines, and pixels connected to the scan lines and the power lines in the display area; A gate driver configured to supply a scan signal to the pixel via the scan line; as well as A bias driver configured to supply a bias voltage to the pixel via the power supply line. The driving cycle of the pixel includes a first frame and a second frame different from the first frame. The first frame includes a first refresh period in which the first data voltage is written and a first reset period in which the first data voltage is maintained. The second frame includes a second refresh period in which the second data voltage is written and a second reset period in which the second data voltage is maintained. The first voltage pulse of the bias voltage during the first refresh period is different from the second voltage pulse of the bias voltage during the second refresh period.

2. The display device according to claim 1, wherein The first refresh period alternately includes two or more first level bias periods and two or more second level bias periods, wherein during the first level bias period, the bias voltage has a first voltage, and during the second level bias period, the bias voltage has a second voltage less than the first voltage. The second refresh period includes a second level bias period and two first level bias periods. During the second level bias period, the bias voltage has a second voltage, while during the first level bias period, the bias voltage has a first voltage.

3. The display device according to claim 1, wherein The first refresh period includes: In the first time period, the scanning signal has a first level that is greater than the second level of the scanning signal; In a second time period following the first time period, wherein in the second time period, the bias voltage has a first level voltage, and In a third time period following the second time period, wherein in the third time period, the bias voltage has a second level voltage that is lower than the first level of the bias voltage, The second refresh period includes: A fourth time period, wherein in the fourth time period, the scan signal has a first level; and In a fifth period following the fourth period, the bias voltage maintains the first bias voltage.

4. The display device according to claim 1, wherein During the first reset period, the level of the bias voltage changes once or more between a first level and a second level lower than the first level, and during the second reset period, the bias voltage is maintained at the first level.

5. The display device according to claim 1, wherein In a non-display area located outside the display area where the image is displayed, the scan lines and the power supply lines are adjacent to each other.

6. The display device according to claim 1, wherein The gate driver includes a first scan driver, a plurality of second scan drivers, and a third scan driver. The first scan driver and the third scan driver are disposed in the non-display area on the first side of the display area, and the plurality of second scan drivers are disposed in the non-display areas on the first side of the display area and the second side of the display area opposite to the first side.

7. The display device of claim 6, wherein, The plurality of second scan drivers disposed in the non-display areas on the first and second sides of the display area are configured to simultaneously apply the scan signal to the scan line.

8. The display device of claim 6, wherein, The first scan driver and the third scan driver are disposed in the non-display area on the first side of the display area, and the bias driver is disposed in the non-display area on the second side of the display area.

9. The display device according to claim 7, wherein The display panel includes a plurality of scan lines, and the plurality of second scan drivers include a scan driver configured to apply a scan signal to odd-numbered scan lines from the plurality of scan lines during the first refresh period, and another scan driver configured to apply a scan signal to even-numbered scan lines from the plurality of scan lines during the first refresh period.

10. The display device of claim 9, wherein, The display panel includes multiple data lines, and the multiple second scan drivers are arranged in the direction in which the multiple data lines extend in the display panel.

11. The display device of claim 9, wherein, One of the plurality of scan lines and the power supply line are directly adjacent to each other in the display panel.

12. A display device comprising: A display panel includes a plurality of pixels configured to display an image at one of a plurality of different refresh frequencies, the plurality of different refresh frequencies including a first refresh frequency and a second refresh frequency different from the first refresh frequency; A data driver configured to apply a data voltage to the plurality of pixels; as well as A gate driver configured to apply a scan signal to the plurality of pixels. Wherein, at least one of the plurality of pixels includes: A driving element includes a gate electrode of the driving element connected to a first node, a first electrode of the driving element connected to a second node, and a second electrode of the driving element connected to a third node, wherein a data voltage from the data driver is applied to the second node, and wherein the first node is connected to a storage capacitor; A light-emitting element configured to emit light by being driven by a current from the driving element; and A first switching element is configured to supply a bias voltage from the power line to the third node connected to the second electrode of the driving element when the light-emitting element is not emitting light. The frequency at which the bias voltage is supplied to the third node during the first refresh frequency is the same as the frequency at which the bias voltage is supplied to the third node during the second refresh frequency.

13. The display device of claim 12, wherein, The frequency at which the bias voltage is supplied during the first refresh frequency and the frequency at which the bias voltage is supplied during the second refresh frequency are matched with a first frequency from the plurality of different refresh frequencies, wherein the first frequency is greater than the second frequency.

14. The display device of claim 13, wherein, In response to the refresh frequency being the first frequency, the frame period of the display device includes a first refresh frame and a second refresh frame following the first refresh frame. The first refresh frame has a first timing sequence during which the bias voltage is applied according to the first timing sequence. The second refresh frame has a second timing sequence different from the first timing sequence during which the bias voltage is applied according to the second timing sequence. Wherein, the first timing sequence is a first time period, during which the bias voltage is applied to the third node at the first time period during the first refresh frame, and the second timing sequence is a second time period, during which the bias voltage is applied to the third node at the second time period during the second refresh frame, and the second time period is longer than the first time period.

15. The display device of claim 13, wherein, In response to the refresh frequency being the second frequency, the first frame period of the display device includes a first refresh frame and one or more first reset frames following the first refresh frame, wherein during the first refresh frame, the data voltage is written, and the first refresh frame has a first refresh timing, during which the bias voltage is applied to the third node according to the first refresh timing; during the first reset frame, the written data voltage is maintained, and the first reset frame has a first reset timing, during which the bias voltage is applied to the third node according to the first reset timing. The second frame cycle of the display device following the first frame cycle includes a second refresh frame and one or more second reset frames following the second refresh frame. During the second refresh frame, another data voltage is written, and the second refresh frame has a second refresh timing. During the second refresh frame, the bias voltage is applied to the third node according to the second refresh timing. During the second reset frame, the written data voltage is maintained, and the second reset frame has a second reset timing. During the first reset frame, the bias voltage is applied to the third node according to the second reset timing. Wherein, the first refresh timing is a first refresh time period, during which the bias voltage is applied to the third node at the first refresh time period; and the second refresh timing is a second refresh time period, during which the bias voltage is applied to the third node at the second refresh time period; the second refresh time period is longer than the first refresh time period. Wherein, the first reset timing is a first reset time period, during which the bias voltage is applied to the third node at the first reset time period during the first reset frame, and the second reset timing is a second reset time period, during which the bias voltage is applied to the third node at the second reset time period during the second reset frame, and the second reset time period is longer than the first reset time period.

16. The display device of claim 12, wherein, At least one of the plurality of pixels further includes: A first switching element connects the diodes of the first node and the third node; A second switching element is configured to apply the data voltage to the second node; A third switching element is configured to apply a high potential voltage from a fourth node connected to the storage capacitor to the second node; A fifth switching element is configured to apply another bias voltage to the anode electrode of the light-emitting element; and The storage capacitor has a first electrode connected to the first node and a second electrode connected to the fourth node.

17. The display device of claim 16, wherein, The other bias voltage is applied to the anode electrode of the light-emitting element, while the bias voltage is also applied to the third node.

18. A display panel comprising: Light-emitting devices; A driving transistor configured to drive the light-emitting device; A bias transistor configured to control the connection between the drain or source electrode of the driving transistor and a power supply line, wherein the power supply line supplies a bias voltage to one of the drain or source electrodes of the driving transistor; and A data supply transistor is configured to control the connection between the drain or source electrode of the drive transistor and the data line according to a scan signal supplied from the scan line. In the non-display area located outside the display area where the image is displayed, the scan lines and the power supply lines are arranged adjacent to each other, and The driving cycle includes a first frame and a second frame that is different from the first frame. The first frame includes a first refresh period in which the first data voltage is written and a first reset period in which the first data voltage is maintained. The second frame includes a second refresh period in which the second data voltage is written and a second reset period in which the second data voltage is maintained. The first voltage pulse of the bias voltage during the first refresh period is different from the second voltage pulse of the bias voltage during the second refresh period.

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