Slope compensation circuit for multi-phase dc-dc converter

Abstract

Embodiments of the present disclosure provide a slope compensation circuit for a multi-phase DC-DC converter, which includes a plurality of cascaded slope compensation sub-circuits. The i-th slope compensation sub-circuit generates an i-th slope compensation signal, an i-th slope compensation time sampling signal and an i-th reset signal under the control of a PWM signal of an i-th phase and an (i-1)-th slope compensation time sampling signal output by an (i-1)-th slope compensation sub-circuit. A rising time of the i-th slope compensation signal is less than or equal to a rising time of the (i-1)-th slope compensation signal. The first slope compensation sub-circuit generates a first slope compensation signal and a first slope compensation time sampling signal according to a PWM signal of a main phase and a system switching frequency signal. The slope compensation time sampling signal of each stage is used to record the rising time of the slope compensation signal of the stage. The reset signal of each stage is used to reset the slope compensation time sampling signal of the previous stage when the slope compensation signal of the stage stops rising. i is an integer greater than 1.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a slope compensation circuit for a multiphase DC-DC converter. Background Technology

[0002] DC-DC converters are commonly used for DC voltage conversion in various electronic devices. In current multiphase DC-DC converters (which can also be referred to as multiphase control systems in this context), when the main phase loop is designed with adaptive turn-on or turn-off time control, the secondary phase loop can achieve balanced power stage energy distribution through sequential delay control. Taking a multiphase control system with the main phase loop designed with adaptive turn-off time control as an example, the first secondary phase uses the rising edge of the main phase PWM (Pulse Width Modulation) signal as the clock signal for turning on the upper power transistor and turning off the lower power transistor in its own loop. When the peak value of its own inductor current reaches the amplitude of the error amplification signal, it turns off the upper power transistor and turns on the lower power transistor, thus completing the loop adjustment for each cycle. Similarly, the (i+1)th sub-phase will also use the rising edge of the PWM signal of the ith sub-phase as the clock signal for turning on the upper power transistor and turning off the lower power transistor in its own loop. When the peak value of its own inductor current reaches the amplitude of the error amplification signal, it will turn off the upper power transistor and turn on the lower power transistor, thus completing the loop adjustment for each cycle. Based on the above principle, all sub-phases except the primary phase follow the peak current mode control mode. Therefore, each phase loop needs to introduce a slope compensation circuit to avoid subharmonic oscillations in applications with a duty cycle greater than 50%, while maintaining power stage energy balance. Summary of the Invention

[0003] The embodiments described herein provide a ramp compensation circuit for a multiphase DC-DC converter, and a multiphase DC-DC converter.

[0004] According to a first aspect of this disclosure, a slope compensation circuit for a multiphase DC-DC converter is provided. The slope compensation circuit includes multiple cascaded slope compensation sub-circuits. The i-th stage slope compensation sub-circuit is configured to generate an i-th stage slope compensation signal, an i-th stage slope compensation time sampling signal, and an i-th stage reset signal under the control of the PWM signal of the i-th phase and the (i-1)-th stage slope compensation time sampling signal output by the (i-1)-th stage slope compensation sub-circuit. The rise time of the i-th stage slope compensation signal is controlled to be less than or equal to the rise time of the (i-1)-th stage slope compensation signal. The first stage slope compensation sub-circuit is configured to generate a first stage slope compensation signal and a first stage slope compensation time sampling signal based on the PWM signal of the main phase and the system switching frequency signal. The slope compensation time sampling signal of each stage is used to record the rise time of the slope compensation signal of that stage. The reset signal of each stage is used to reset the slope compensation time sampling signal of the previous stage when the slope compensation signal of that stage stops rising. i is an integer greater than 1.

[0005] In some embodiments of this disclosure, the first-stage slope compensation sub-circuit includes: a main-phase slope signal control circuit, a main-phase slope signal generation circuit, and a main-phase slope compensation time sampling circuit. The main-phase slope signal control circuit is configured to generate a main-phase control signal based on the main-phase PWM signal and the system switching frequency signal. The main-phase slope signal generation circuit is configured to generate a first-stage slope compensation signal based on the main-phase control signal. The main-phase slope compensation time sampling circuit is configured to generate a first-stage slope compensation time sampling signal based on the main-phase control signal and a next-stage reset signal. The main-phase control signal is used to control the rise time of the first-stage slope compensation signal.

[0006] In some embodiments of this disclosure, the main phase ramp signal control circuit includes: a rise time control circuit, a main phase first AND gate, and a main phase first inverter. The first input terminal of the main phase first AND gate is provided with a main phase PWM signal. The rise time control circuit is provided with the main phase PWM signal and a system switching frequency signal, and is configured to: start timing from the rising edge of the main phase PWM signal, determine a preset time period based on the system switching frequency signal, and output a low-level signal when the preset time period is completed. The output terminal of the rise time control circuit is coupled to the second input terminal of the main phase first AND gate. The output terminal of the main phase first AND gate is coupled to the input terminal of the main phase first inverter. A main phase control signal is output from the output terminal of the main phase first inverter.

[0007] In some embodiments of this disclosure, the main phase ramp signal generation circuit includes: a main phase first transistor, a main phase first capacitor, a main phase first current source, a main phase voltage-controlled current source, and a first resistor. The control terminal of the main phase first transistor is provided with a main phase control signal. The first stage of the main phase first transistor is coupled to the first terminal of the main phase first current source and the first terminal of the main phase first capacitor. The second stage of the main phase first transistor is coupled to a second voltage terminal. The second terminal of the main phase first capacitor is coupled to the second voltage terminal. The second terminal of the main phase first current source is coupled to the first voltage terminal. The first input terminal of the main phase voltage-controlled current source is coupled to the first terminal of the main phase first capacitor. The second input terminal of the main phase voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the main phase voltage-controlled current source is coupled to the first voltage terminal. The second output terminal of the main phase voltage-controlled current source is coupled to the first terminal of the first resistor. A first-stage ramp compensation signal is output from the second terminal of the first resistor.

[0008] In some embodiments of this disclosure, the main-phase ramp-compensated time sampling circuit includes: a main-phase second AND gate, a main-phase second transistor, a main-phase second capacitor, a main-phase second current source, a main-phase second inverter, a main-phase first voltage-controlled switch, a main-phase second voltage-controlled switch, and a main-phase third voltage-controlled switch. The first input terminal of the main-phase second AND gate is provided with a main-phase control signal. The second input terminal of the main-phase second AND gate is provided with a reset signal for the next stage. The output terminal of the main-phase second AND gate is coupled to the control stage of the main-phase second transistor. The first stage of the main-phase second transistor is coupled to the first terminal of the main-phase first voltage-controlled switch and the first terminal of the main-phase second capacitor. The second stage of the main-phase second transistor is coupled to a second voltage terminal. The second terminal of the main-phase second capacitor is coupled to a second voltage terminal. The controlled terminal of the main-phase first voltage-controlled switch is coupled to the output terminal of the main-phase second inverter and the controlled terminal of the main-phase third voltage-controlled switch. The second terminal of the main-phase first voltage-controlled switch is coupled to the first terminal of the main-phase second current source. The second terminal of the main-phase second current source is coupled to the first voltage terminal. The controlled terminal of the second voltage-controlled switch of the main phase is provided with a main phase control signal. The first terminal of the second voltage-controlled switch of the main phase is coupled to the first terminal of the second capacitor of the main phase. The second terminal of the second voltage-controlled switch of the main phase is coupled to the first terminal of the third voltage-controlled switch of the main phase. The first-stage ramp compensation time sampling signal is output from the second terminal of the second voltage-controlled switch of the main phase. The second terminal of the third voltage-controlled switch of the main phase is coupled to the first voltage terminal. The input terminal of the second inverter of the main phase is provided with a main phase control signal.

[0009] In some embodiments of this disclosure, the i-th level slope compensation sub-circuit includes: an i-th compensation time limiting circuit, an i-th slope signal control circuit, an i-th slope signal generation circuit, and an i-th slope compensation time sampling circuit. The i-th compensation time limiting circuit is configured to generate an i-th level reset signal based on the PWM signal of the i-th phase, the (i-1)-th level slope compensation time sampling signal, and a first voltage from a first voltage terminal. The i-th slope signal control circuit is configured to generate an i-th control signal based on the PWM signal of the i-th phase and the i-th level reset signal. The i-th slope signal generation circuit is configured to generate an i-th level slope compensation signal based on the i-th control signal. The i-th slope compensation time sampling circuit is configured to generate an i-th level slope compensation time sampling signal based on the i-th control signal and the next-level reset signal. The duration of the i-th level reset signal being at an effective level is less than or equal to the rise time of the (i-1)-th level slope compensation signal. The duration of the i-th control signal being at an effective level is less than or equal to the duration of the i-th level reset signal being at an effective level. The i-th control signal is used to control the rise time of the i-th level slope compensation signal.

[0010] In some embodiments of this disclosure, the i-th ramp signal control circuit includes: an i-th phase first AND gate, an i-th phase first inverter, and an i-th phase second inverter. The first input terminal of the i-th phase first AND gate is provided with the i-th phase PWM signal. The second input terminal of the i-th phase first AND gate is coupled to the output terminal of the i-th phase second inverter. The output terminal of the i-th phase first AND gate is coupled to the input terminal of the i-th phase first inverter. The input terminal of the i-th phase second inverter is provided with the i-th stage reset signal. The i-th control signal is output from the output terminal of the i-th phase first inverter.

[0011] In some embodiments of this disclosure, the i-th ramp signal generation circuit includes: an i-th phase first transistor, an i-th phase first capacitor, an i-th phase first current source, an i-th phase voltage-controlled current source, and an i-th resistor. The control electrode of the i-th phase first transistor is provided with an i-th control signal. The first stage of the i-th phase first transistor is coupled to the first terminal of the i-th phase first current source and the first terminal of the i-th phase first capacitor. The second stage of the i-th phase first transistor is coupled to a second voltage terminal. The second terminal of the i-th phase first capacitor is coupled to the second voltage terminal. The second terminal of the i-th phase first current source is coupled to the first voltage terminal. The first input terminal of the i-th phase voltage-controlled current source is coupled to the first terminal of the i-th phase first capacitor. The second input terminal of the i-th phase voltage-controlled current source is coupled to the second voltage terminal. The first output terminal of the i-th phase voltage-controlled current source is coupled to the first voltage terminal. The second output terminal of the i-th phase voltage-controlled current source is coupled to the first terminal of the i-th resistor. The i-th phase ramp compensation signal is output from the second terminal of the i-th resistor.

[0012] In some embodiments of this disclosure, the i-th ramp-compensated time sampling circuit includes: an i-th phase second AND gate, an i-th phase second transistor, an i-th phase second capacitor, an i-th phase second current source, an i-th phase third inverter, an i-th phase first voltage-controlled switch, an i-th phase second voltage-controlled switch, and an i-th phase third voltage-controlled switch. The first input terminal of the i-th phase second AND gate is provided with an i-th control signal. The second input terminal of the i-th phase second AND gate is provided with a reset signal for the next stage. The output terminal of the i-th phase second AND gate is coupled to the control stage of the i-th phase second transistor. The first stage of the i-th phase second transistor is coupled to the first terminal of the i-th phase first voltage-controlled switch and the first terminal of the i-th phase second capacitor. The second stage of the i-th phase second transistor is coupled to a second voltage terminal. The second terminal of the i-th phase second capacitor is coupled to the second voltage terminal. The controlled terminal of the i-th phase first voltage-controlled switch is coupled to the output terminal of the i-th phase third inverter and the controlled terminal of the i-th phase third voltage-controlled switch. The second terminal of the i-th phase first voltage-controlled switch is coupled to the first terminal of the i-th phase second current source. The second terminal of the second current source in phase i is coupled to the first voltage terminal. The controlled terminal of the second voltage-controlled switch in phase i is provided with the i-th control signal. The first terminal of the second voltage-controlled switch in phase i is coupled to the first terminal of the second capacitor in phase i. The second terminal of the second voltage-controlled switch in phase i is coupled to the first terminal of the third voltage-controlled switch in phase i. The i-th level ramp compensation time sampling signal is output from the second terminal of the second voltage-controlled switch in phase i. The second terminal of the third voltage-controlled switch in phase i is coupled to the first voltage terminal. The input terminal of the third inverter in phase i is provided with the i-th control signal.

[0013] In some embodiments of this disclosure, the i-th compensation time limiting circuit includes: an i-th phase fourth inverter, an i-th phase third transistor, an i-th phase third capacitor, an i-th phase third current source, an i-th phase fifth inverter, an i-th phase fourth voltage-controlled switch, an i-th phase fifth voltage-controlled switch, an i-th phase sixth voltage-controlled switch, and an i-th comparator. The input terminal of the i-th phase fourth inverter is provided with the i-th phase PWM signal. The output terminal of the i-th phase fourth inverter is coupled to the control stage of the i-th phase third transistor. The first stage of the i-th phase third transistor is coupled to the first terminal of the i-th phase fourth voltage-controlled switch and the first terminal of the i-th phase third capacitor. The second stage of the i-th phase third transistor is coupled to a second voltage terminal. The second terminal of the i-th phase third capacitor is coupled to the second voltage terminal. The controlled terminal of the i-th phase fourth voltage-controlled switch is provided with the i-th phase PWM signal. The second terminal of the i-th phase fourth voltage-controlled switch is coupled to the first terminal of the i-th phase third current source. The second terminal of the i-th phase third current source is coupled to the first voltage terminal. The controlled terminal of the i-th phase fifth voltage-controlled switch is provided with the i-th phase PWM signal. The first terminal of the fifth voltage-controlled switch of phase i is coupled to the first terminal of the third capacitor of phase i. The second terminal of the fifth voltage-controlled switch of phase i is coupled to the first terminal of the sixth voltage-controlled switch of phase i and the first input terminal of the i-th comparator. The controlled terminal of the sixth voltage-controlled switch of phase i is coupled to the output terminal of the fifth inverter of phase i. The second terminal of the sixth voltage-controlled switch of phase i is coupled to the first voltage terminal. The input terminal of the fifth inverter of phase i is provided with the PWM signal of phase i. The second input terminal of the i-th comparator is provided with the (i-1)th stage ramp compensation time sampling signal. The i-th stage reset signal is output from the output terminal of the i-th comparator.

[0014] According to a second aspect of this disclosure, a multiphase DC-DC converter is provided. The multiphase DC-DC converter includes the slope compensation circuit described in the first aspect of this disclosure. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0016] Figure 1 This is an exemplary circuit diagram of a multiphase DC-DC converter;

[0017] Figure 2 This is an exemplary circuit diagram of a slope compensation circuit;

[0018] Figure 3 It is used to include Figure 2 The timing diagram of some signals of the multiphase DC-DC converter shown in the slope compensation circuit;

[0019] Figure 4This is a schematic block diagram of a slope compensation circuit for a multiphase DC-DC converter according to embodiments of the present disclosure;

[0020] Figure 5 yes Figure 4 A schematic block diagram of the first-stage slope compensation sub-circuit in the slope compensation circuit shown.

[0021] Figure 6 yes Figure 4 A schematic block diagram of the i-th level slope compensation sub-circuit in the slope compensation circuit shown.

[0022] Figure 7 yes Figure 5 An exemplary circuit diagram of the first-stage ramp compensator sub-circuit is shown;

[0023] Figure 8 yes Figure 6 An exemplary circuit diagram of the i-th level ramp compensator sub-circuit is shown;

[0024] Figure 9 yes Figure 8 An exemplary circuit diagram of the i-th compensation time limiting circuit in the i-th level ramp compensator sub-circuit is shown; and

[0025] Figure 10 It is used to include Figure 4 The timing diagram of some signals of the multiphase DC-DC converter shown in the slope compensation circuit is shown.

[0026] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0028] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0029] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0030] Figure 1 An exemplary circuit diagram of a multiphase DC-DC converter is shown. This multiphase DC-DC converter is used to convert an input voltage VIN into an output voltage VOUT. The multiphase DC-DC converter includes: multiple drive circuits (including a first drive circuit, a second drive circuit, ..., an i-th drive circuit, an i+1-th drive circuit), multiple upper power transistors S1_1, S1_2, ..., S1_i, S1_i+1, multiple lower power transistors S2_1, S2_2, ..., S2_i, S2_i+1, multiple inductors L1, L2, ..., Li, Li+1, multiple sampling resistors Ri (each corresponding to one sampling resistor), a superposition circuit, an output capacitor COUT, resistors r1 and r2, an error amplifier EA, a PWM comparator COMP, an adaptive turn-off time and phase delay control circuit 110, and a slope compensation circuit 120. Figure 1 The load ILOAD is also shown.

[0031] The adaptive turn-off time and phase delay control circuit 110 outputs the PWM signal PWM_i for each phase, and controls the on and off of the upper and lower power transistors through the corresponding drive circuits. The sampling resistor Ri of each phase samples the inductor currents IL1, IL2, ..., ILi, Li+1 flowing through the corresponding inductors L1, L2, ..., Li, Li+1, and generates the peak inductor current sampling signal VCS_i for each phase. The slope compensation circuit 120 is coupled to a superposition circuit through node O_i. The superposition circuit can superimpose the peak inductor current sampling signal VCS_i of each phase with the slope compensation signal output by the slope compensation circuit 120 to generate the superimposed signal VSUM_i.

[0032] The non-inverting input of error amplifier EA is coupled to the reference voltage terminal VREF, and the inverting input is coupled to the feedback node FB. Error amplifier EA amplifies the error voltage between the reference voltage from the reference voltage terminal VREF and the feedback voltage at the feedback node FB, and provides the amplified error signal EAO to the PWM comparator COMP. The signal output by PWM comparator COMP controls the adaptive turn-off time and phase delay control circuit 110 to generate the corresponding PWM signal PWM_i. When the superimposed signal VSUM_i reaches the error amplified signal EAO, PWM comparator COMP outputs a high-level signal to control the PWM signal of the i-th phase to flip to a low level.

[0033] Figure 2 An exemplary circuit diagram of a ramp compensation circuit 220 is shown. The ramp compensation circuit 220 includes multiple ramp compensation sub-circuits. Since each ramp compensation sub-circuit has the same structure, for ease of display, ... Figure 2 Only one exemplary circuit structure of the ramp compensation sub-circuit is shown in the diagram. Figure 2 In the example, i represents the phase order of the current PWM signal, where i ≥ 1. When i equals 1, the current phase is the dominant phase. When i equals 2, the current phase is the first sub-phase, and so on.

[0034] The PWM signal PWM_i can be input to a rise time control circuit. This rise time control circuit can be, for example, a delay circuit. For instance, the rise time control circuit can start timing from the rising edge of the PWM signal PWM_i. After a certain time has elapsed, the output signal of the rise time control circuit flips to a low level, thereby controlling the AND gate ANDi to output a low-level signal. This low-level signal is input to the inverter NGI, causing NGI to output a high-level signal. The high-level signal controls the transistor Mi to turn on, releasing the charge stored in the capacitor Ci.

[0035] The current source IBIASi outputs a fixed bias current. During each switching cycle of phase i, when the upper power transistor S1_i is turned on and the lower power transistor S2_i is turned off, the PWM signal PWM_i flips from low to high, causing transistor Mi to turn off. The current source IBIASi charges capacitor Ci, generating a ramp voltage signal VRAMP_i on the upper plate of capacitor Ci. The ramp voltage signal VRAMP_i is input to the voltage-controlled current source VCCSi, where Gi is the gain of the voltage-controlled current source VCCSi. The voltage-controlled current source VCCSi converts the ramp voltage signal VRAMP_i into a ramp current signal IRAMP_i. The ramp current signal IRAMP_i can be superimposed on the peak inductor current sampling signal VCS_i through resistor Ri to generate a superimposed signal VSUM_i. The timing duration of the rise time control circuit determines the duration from the start of the ramp voltage signal VRAMP_i's rise to zero; this timing duration can be adaptively adjusted according to the current system's switching frequency Freq. For example, when the system switching frequency signal Freq is set to F SW The timing duration can be set to K×1 / F. SW , where K is a pre-designed fixed proportional coefficient.

[0036] Figure 3 Showing for including Figure 2 The diagram shows the timing of some signals in a multiphase DC-DC converter with a ramp-compensated circuit. In this multiphase DC-DC converter with sequential phase delays, after a certain delay (referred to in the context as the inductor current valley delay point) starting from the inductor current valley point of phase i, the PWM signal of phase i+1 flips to a high level, thus achieving sequential phase delay. Figure 3 In a multi-phase DC-DC converter, when the applied load ILOAD switches from light load to heavy load, the error amplification signal EAO will surge due to the drop in output voltage VOUT. As mentioned above, when the superimposed signal VSUM_i of the i-th phase reaches the error amplification signal EAO, the PWM comparator COMP outputs a high-level signal to control the PWM signal of the i-th phase to flip to a low level, thereby turning off the upper power transistor S1_i. Because the error amplification signal EAO increases, the superimposed signal takes longer to reach the error amplification signal EAO. Therefore, the phase loop in a high duty cycle application will experience a prolonged period of operation with the upper power transistor S1_i on.

[0037] exist Figure 3In the diagram, the inductor current valley delay point of phase i+1 (marked as point 1 in the diagram after a certain delay) causes phase i+2 to enter a state where the upper power transistor is on for an extended period. During the continuous on-state of the upper power transistor in phase i+1, due to the presence of the compensation voltage signal VRAMP_i+1, the superimposed signal VSUM_i+1 rises rapidly to reach the error amplification signal EAO, meaning the inductor current of phase i quickly reaches its peak value, completing the process of the upper power transistor turning on and the lower power transistor turning off. Subsequently, phase i+1 enters the second switching cycle, while phase i+2 will miss the second inductor current valley delay point of phase i+1 (marked as point 2 in the diagram after a certain delay) due to the continuous on-state of the upper power transistor. During the period between the peak value of the inductor current in phase i+2 and the arrival of the third inductor current valley delay point of phase i+1 (marked as point 3 in the diagram after a certain delay), phase i+2 will enter a state where the lower power transistor is on for an extended period. Therefore, the DC current of the inductor in phase i+2 will be lower than that of phase i+1, and this difference in DC current will intensify with each cycle of system adjustment until both phase loops enter their respective "steady" states. Figure 3 In this process, because the superimposed signal VSUM_i+2 misses the inductor current valley delay point of phase i+1 once during the rise of each switching cycle, the switching cycle of the PWM signal PWM_i+2 of phase i+2 is ultimately maintained at twice the switching cycle of the PWM signal PWM_i+1 of phase i+1. More seriously, multiple phase loops of the multiphase DC-DC converter can operate in multiple different states due to the phase-by-phase propagation of the above problem, thus compromising the overall stability of the multiphase DC-DC converter.

[0038] To maintain the overall stability of a multiphase DC-DC converter, embodiments of this disclosure propose a slope compensation circuit for multiphase DC-DC converters. Figure 4 A schematic block diagram of a slope compensation circuit 420 for a multiphase DC-DC converter according to an embodiment of the present disclosure is shown. The slope compensation circuit 420 includes a plurality of cascaded slope compensation sub-circuits 421-1, 421-2, 421-3…421-i, 421-i+1. A first-stage slope compensation sub-circuit 421-1 is used to perform slope compensation on the main phase loop. A second-stage slope compensation sub-circuit 421-2 is used to perform slope compensation on the first sub-phase loop. A third-stage slope compensation sub-circuit 421-3 is used to perform slope compensation on the second sub-phase loop, and so on.

[0039] The first-stage slope compensation sub-circuit 421-1 can be coupled to the second-stage slope compensation sub-circuit 421-2. The first-stage slope compensation sub-circuit 421-1 can be configured to generate a first-stage slope compensation signal and a first-stage slope compensation time sampling signal VC_O_1 based on the main phase's PWM signal PWM_1 and the system switching frequency signal Freq. The first-stage slope compensation signal is output from the first node O_1. The first-stage slope compensation signal can be superimposed with the main phase's inductor current peak sampling signal VCS_1 to generate the main phase's superimposed signal VSUM_1.

[0040] The i-th level slope compensation sub-circuit 421-i can be coupled to the (i-1)-th level slope compensation sub-circuit (not shown) and the (i+1)-th level slope compensation sub-circuit 421-i+1. The i-th level slope compensation sub-circuit can be configured to generate the i-th level slope compensation signal, the i-th level slope compensation time sampling signal VC_O_i, and the i-th level reset signal VC_CLR_i under the control of the PWM signal of the i-th phase (i.e., the (i-1)-th sub-phase) and the (i-1)-th level slope compensation time sampling signal output by the (i-1)-th level slope compensation sub-circuit. The rise time of the i-th level slope compensation signal is controlled to be less than or equal to the rise time of the (i-1)-th level slope compensation signal. The i-th level slope compensation signal is output from the i-th node O_i. The i-th level slope compensation signal can be superimposed with the inductor current peak sampling signal VCS_i of the i-th phase to generate the superimposed signal VSUM_i of the i-th phase.

[0041] In the ramp compensation circuit 420 according to an embodiment of the present disclosure, the ramp compensation time sampling signal of each stage is used to record the rise time of the ramp compensation signal of that stage. The reset signal of each stage is used to reset the ramp compensation time sampling signal of the previous stage when the ramp compensation signal of that stage stops rising. Figure 4 In the example, i is an integer greater than 1.

[0042] For ease of understanding, in Figure 4The diagram also shows ramp compensation sub-circuits for i=2 and i=3. The second-stage ramp compensation sub-circuit 421-2 is coupled to the first-stage ramp compensation sub-circuit 421-1 and the third-stage ramp compensation sub-circuit 421-3. The second-stage ramp compensation sub-circuit 421-2 can be configured to generate a second-stage ramp compensation signal, a second-stage ramp compensation time sampling signal VC_O_2, and a second-stage reset signal VC_CLR_2 under the control of the PWM signal PWM_2 of the second phase (i.e., the first sub-phase) and the first-stage ramp compensation time sampling signal VC_O_1 output from the first-stage ramp compensation sub-circuit 421-1. The first-stage ramp compensation time sampling signal VC_O_1 can be input to the second-stage ramp compensation sub-circuit 421-2 through the reference voltage input terminal VC_I_2. The rise time of the second-stage ramp compensation signal is controlled to be less than or equal to the rise time of the first-stage ramp compensation signal. The second-stage ramp compensation signal is output from the second node O_2. The second-stage ramp compensation signal can be superimposed on the peak inductor current sampling signal of the first sub-phase to generate the superimposed signal of the first sub-phase. The second-stage reset signal VC_CLR_2 can reset the first-stage ramp compensation time sampling signal VC_O_1 when the second-stage ramp compensation signal stops rising.

[0043] The third-stage slope compensation sub-circuit 421-3 is coupled to the second-stage slope compensation sub-circuit 421-2 and the fourth-stage slope compensation sub-circuit (not shown). The third-stage slope compensation sub-circuit 421-3 can be configured to generate a third-stage slope compensation signal, a third-stage slope compensation time sampling signal, and a third-stage reset signal VC_CLR_3 under the control of the PWM signal PWM_3 of the third phase (i.e., the second sub-phase) and the second-stage slope compensation time sampling signal VC_O_2 output by the second-stage slope compensation sub-circuit 421-3. The second-stage slope compensation time sampling signal VC_O_2 can be provided to the third-stage slope compensation sub-circuit 421-3 through the reference voltage input terminal VC_I_3. The rise time of the third-stage slope compensation signal is controlled to be less than or equal to the rise time of the second-stage slope compensation signal. The third-stage slope compensation signal is output from the third node O_3. The third-stage slope compensation signal can be superimposed with the peak inductor current sampling signal of the second sub-phase to generate a superimposed signal for the second sub-phase. The third-level reset signal VC_CLR_3 can reset the second-level slope compensation time sampling signal VC_O_2 when the third-level slope compensation signal stops rising.

[0044] According to embodiments of the present disclosure, the slope compensation circuit for a multiphase DC-DC converter can limit the rise time of each stage of the slope compensation signal to be less than or equal to the rise time of the previous stage's slope compensation signal, thereby enabling the difference between the DC level of the inductor current in each phase and the previous phase to converge periodically, thus maintaining the overall stability of the multiphase DC-DC converter.

[0045] Figure 5 Show Figure 4 The diagram shows a schematic block diagram of the first-stage slope compensation sub-circuit 521-1 in the slope compensation circuit. The first-stage slope compensation sub-circuit 521-1 may include: a main phase slope signal control circuit 5211, a main phase slope signal generation circuit 5212, and a main phase slope compensation time sampling circuit 5213.

[0046] The main phase ramp signal control circuit 5211 can provide the main phase PWM signal PWM_1 and the system switching frequency signal Freq. The output of the main phase ramp signal control circuit 5211 can be coupled to the main phase ramp signal generation circuit 5212 and the main phase ramp compensation time sampling circuit 5213. The main phase ramp signal control circuit 5211 can be configured to generate a main phase control signal RAMP_CLR_1 based on the main phase PWM signal PWM_1 and the system switching frequency signal Freq. In some embodiments of this disclosure, the main phase control signal RAMP_CLR_1 flips to a low level when the main phase PWM signal PWM_1 flips to a high level. The main phase control signal RAMP_CLR_1 flips to a high level after a delay from the rising edge of the main phase PWM signal PWM_1. The system switching frequency signal Freq is used to control the length of this delay. When the system switching frequency signal Freq is set to F... SW At this time, the timing duration can be set to K / F. SW , where K is a pre-designed fixed proportional coefficient.

[0047] The main phase ramp signal generation circuit 5212 can be coupled to the output of the main phase ramp signal control circuit 5211 to obtain the main phase control signal RAMP_CLR_1. The main phase ramp signal generation circuit 5212 can be configured to generate a first-level ramp compensation signal based on the main phase control signal RAMP_CLR_1. The first-level ramp compensation signal is output from the first node O_1. The main phase control signal RAMP_CLR_1 is used to control the rise time of the first-level ramp compensation signal. In some embodiments of this disclosure, the first-level ramp compensation signal begins to rise when the main phase control signal RAMP_CLR_1 flips to a low level. The first-level ramp compensation signal stops rising when the main phase control signal RAMP_CLR_1 flips to a high level.

[0048] The main phase ramp compensation time sampling circuit 5213 can be coupled to the output of the main phase ramp signal control circuit 5211 to obtain the main phase control signal RAMP_CLR_1. The main phase ramp compensation time sampling circuit 5213 can also be coupled to the reset signal output of the second-stage ramp compensation sub-circuit to obtain the second-stage reset signal VC_CLR_2. The main phase ramp compensation time sampling circuit 5213 can be configured to generate the first-stage ramp compensation time sampling signal VC_O_1 based on the main phase control signal RAMP_CLR_1 and the next-stage reset signal (i.e., the second-stage reset signal VC_CLR_2). The main phase control signal RAMP_CLR_1 and the next-stage reset signal are used to jointly control the rise time of the first-stage ramp compensation signal.

[0049] Figure 6 Show Figure 4 The diagram shows a schematic block diagram of the i-th level slope compensation sub-circuit in the slope compensation circuit. The i-th level slope compensation sub-circuit 621-i may include: an i-th compensation time limiting circuit 6214, an i-th slope signal control circuit 6211, an i-th slope signal generation circuit 6212, and an i-th slope compensation time sampling circuit 6213.

[0050] The i-th compensation time limiting circuit 6214 can be coupled to the reference voltage input terminal VC_I_i of the i-th stage. The ramp compensation time sampling signal VC_O_i-1 of the (i-1)-th stage is provided to the i-th compensation time limiting circuit 6214 through the reference voltage input terminal VC_I_i. The i-th compensation time limiting circuit 6214 can also be provided with the PWM signal PWM_i of the i-th phase. The i-th compensation time limiting circuit 6214 can be configured to generate the i-th stage reset signal VC_CLR_i based on the PWM signal PWM_i of the i-th phase, the ramp compensation time sampling signal VC_O_i-1 of the (i-1)-th stage, and the first voltage V1 from the first voltage terminal V1.

[0051] The i-th ramp signal control circuit 6211 can be coupled to the output of the i-th compensation time limiting circuit 6214 to receive the i-th stage reset signal VC_CLR_i. The i-th ramp signal control circuit 6211 can also be provided with the i-th phase PWM signal PWM_i. The i-th ramp signal control circuit 6211 can be configured to generate the i-th control signal RAMP_CLR_i based on the i-th phase PWM signal PWM_i and the i-th stage reset signal VC_CLR_i.

[0052] The i-th ramp signal generation circuit 6212 can be coupled to the output of the i-th ramp signal control circuit 6211 to receive the i-th control signal RAMP_CLR_i. The i-th ramp signal generation circuit 6212 can be configured to generate an i-th level ramp compensation signal based on the i-th control signal RAMP_CLR_i. The i-th level ramp compensation signal can be output via the i-th node O_i.

[0053] The i-th ramp compensation time sampling circuit 6213 can be coupled to the output of the i-th ramp signal control circuit 6211 to receive the i-th control signal RAMP_CLR_i. The i-th ramp compensation time sampling circuit 6213 can also be coupled to the reset signal output of the (i+1)-th stage ramp compensation sub-circuit to obtain the (i+1)-th stage reset signal VC_CLR_i+1. The i-th ramp compensation time sampling circuit 6213 can be configured to generate the i-th stage ramp compensation time sampling signal VC_O_i based on the i-th control signal RAMP_CLR_i and the next-stage reset signal (i.e., the (i+1)-th stage reset signal VC_CLR_i+1). The duration of the i-th stage reset signal VC_CLR_i being at an active level is less than or equal to the rise time of the (i-1)-th stage ramp compensation signal. The duration of the i-th control signal RAMP_CLR_i being at an active level is less than or equal to the duration of the i-th stage reset signal VC_CLR_i being at an active level. The i-th control signal RAMP_CLR_i is used to control the rise time of the i-th level ramp compensation signal. Therefore, the rise time of the i-th level ramp compensation signal is less than or equal to the rise time of the (i-1)-th level ramp compensation signal.

[0054] Figure 7 Show Figure 5 An exemplary circuit diagram of the first-stage ramp compensation sub-circuit 721-1 is shown. The main phase ramp signal control circuit 7211 may include: a rise time control circuit 72111, a main phase first AND gate AND1, and a main phase first inverter NG1. The first input of the main phase first AND gate AND1 is provided with the main phase PWM signal PWM_1. The rise time control circuit 72111 is provided with the main phase PWM signal PWM_1 and the system switching frequency signal Freq, and is configured to: start timing from the rising edge of the main phase PWM signal PWM_1, determine a preset time period according to the system switching frequency signal Freq, and output a low-level signal when the preset time period is completed. The output of the rise time control circuit 72111 is coupled to the second input of the main phase first AND gate AND1. The output of the main phase first AND gate AND1 is coupled to the input of the main phase first inverter NG1. The main phase control signal RAMP_CLR_1 is output from the output of the main phase first inverter NG1.

[0055] The main phase ramp signal generation circuit 7212 may include: a main phase first transistor M1, a main phase first capacitor C1, a main phase first current source IBIAS1_1, a main phase voltage-controlled current source VCCS1, and a first resistor R_1. The control terminal of the main phase first transistor M1 is provided with a main phase control signal RAMP_CLR_1. The first stage of the main phase first transistor M1 is coupled to the first terminal of the main phase first current source IBIAS1_1 and the first terminal of the main phase first capacitor C1. The second stage of the main phase first transistor M1 is coupled to a second voltage terminal V2. The second terminal of the main phase first capacitor C1 is coupled to the second voltage terminal V2. The second terminal of the main phase first current source IBIAS1_1 is coupled to the first voltage terminal V1. The first input terminal of the main phase voltage-controlled current source VCCS1 is coupled to the first terminal of the main phase first capacitor C1. The second input terminal of the main phase voltage-controlled current source VCCS1 is coupled to the second voltage terminal V2. The first output terminal of the main phase voltage-controlled current source VCCS1 is coupled to the first voltage terminal V1. The second output terminal of the main phase voltage-controlled current source VCCS1 is coupled to the first terminal of the first resistor R_1. The first-stage slope compensation signal is output from the second terminal of the first resistor R_1 (i.e., the first node O_1).

[0056] The main phase ramp compensation time sampling circuit 7213 may include: a main phase second AND gate AND2, a main phase second transistor M2, a main phase second capacitor C2, a main phase second current source IBIAS2_1, a main phase second inverter NG2_1, a main phase first voltage-controlled switch SC_1_1, a main phase second voltage-controlled switch SC_1_2, and a main phase third voltage-controlled switch SC_1_3. The first input terminal of the main phase second AND gate AND2 is provided with the main phase control signal RAMP_CLR_1. The second input terminal of the main phase second AND gate AND2 is provided with the next stage reset signal VC_CLR_2. The output terminal of the main phase second AND gate AND2 is coupled to the control stage of the main phase second transistor M2. The first stage of the main phase second transistor M2 is coupled to the first terminal of the main phase first voltage-controlled switch SC_1_1 and the first terminal of the main phase second capacitor C2. The second stage of the main phase second transistor M2 is coupled to the second voltage terminal V2. The second terminal of the main phase second capacitor C2 is coupled to the second voltage terminal V2. The controlled terminal of the first voltage-controlled switch SC_1_1 of the main phase is coupled to the output terminal of the second inverter NG2_1 of the main phase and the controlled terminal of the third voltage-controlled switch SC_1_3 of the main phase. The second terminal of the first voltage-controlled switch SC_1_1 of the main phase is coupled to the first terminal of the second current source IBIAS2_1 of the main phase. The second terminal of the second current source IBIAS2_1 of the main phase is coupled to the first voltage terminal V1. The controlled terminal of the second voltage-controlled switch SC_1_2 of the main phase is provided with the main phase control signal RAMP_CLR_1. The first terminal of the second voltage-controlled switch SC_1_2 of the main phase is coupled to the first terminal of the second capacitor C2 of the main phase. The second terminal of the second voltage-controlled switch SC_1_2 of the main phase is coupled to the first terminal of the third voltage-controlled switch SC_1_3 of the main phase. The first-stage ramp compensation time sampling signal VC_O_1 is output from the second terminal of the second voltage-controlled switch SC_1_2 of the main phase. The second terminal of the third voltage-controlled switch SC_1_3 of the main phase is coupled to the first voltage terminal V1. The input of the second inverter NG2_1 is provided with the main phase control signal RAMP_CLR_1.

[0057] Figure 8 Show Figure 6 The diagram shows an exemplary circuit of the i-th stage ramp compensation sub-circuit 821-i. The i-th stage ramp signal control circuit 8211 may include: an i-th stage first AND gate AND1_i, an i-th stage first inverter NG1_i, and an i-th stage second inverter NG2_i. The first input terminal of the i-th stage first AND gate AND1_i is provided with the i-th stage PWM signal PWM_i. The second input terminal of the i-th stage first AND gate AND1_i is coupled to the output terminal of the i-th stage second inverter NG2_i. The output terminal of the i-th stage first AND gate AND1_i is coupled to the input terminal of the i-th stage first inverter NG1_i. The input terminal of the i-th stage second inverter NG2_i is provided with the i-th stage reset signal VC_CLR_i. The i-th stage control signal RAMP_CLR_i is output from the output terminal of the i-th stage first inverter NG1_i.

[0058] The i-th ramp signal generation circuit 8212 may include: an i-th phase first transistor M1_i, an i-th phase first capacitor C1_i, an i-th phase first current source IBIAS1_i, an i-th phase voltage-controlled current source VCCSi, and an i-th resistor R_i. The control terminal of the i-th phase first transistor M1_i is provided with an i-th control signal RAMP_CLR_i. The first stage of the i-th phase first transistor M1_i is coupled to the first terminal of the i-th phase first current source IBIAS1_i and the first terminal of the i-th phase first capacitor C1_i. The second stage of the i-th phase first transistor M1_i is coupled to a second voltage terminal V2. The second terminal of the i-th phase first capacitor C1_i is coupled to the second voltage terminal V2. The second terminal of the i-th phase first current source IBIAS1_i is coupled to the first voltage terminal V1. The first input terminal of the i-th phase voltage-controlled current source VCCSi is coupled to the first terminal of the i-th phase first capacitor C1_i. The second input terminal of the i-th phase voltage-controlled current source VCCSi is coupled to the second voltage terminal V2. The first output terminal of the i-th phase voltage-controlled current source VCCSi is coupled to the first voltage terminal V1. The second output terminal of the i-th phase voltage-controlled current source VCCSi is coupled to the first terminal of the i-th resistor R_i. The i-th level slope compensation signal is output from the second terminal of the i-th resistor R_i (i.e., the i-th node O_i).

[0059] The i-th ramp compensation time sampling circuit 8213 may include: an i-th phase second AND gate AND2_i, an i-th phase second transistor M2_i, an i-th phase second capacitor C2_i, an i-th phase second current source IBIAS2_i, an i-th phase third inverter NG3_i, an i-th phase first voltage-controlled switch SC_i_1, an i-th phase second voltage-controlled switch SC_i_2, and an i-th phase third voltage-controlled switch SC_i_3. The first input terminal of the i-th phase second AND gate AND2_i is provided with the i-th control signal RAMP_CLR_i. The second input terminal of the i-th phase second AND gate AND2_i is provided with the next stage reset signal VC_CLR_i+1. The output terminal of the i-th phase second AND gate AND2_i is coupled to the control stage of the i-th phase second transistor M2_i. The first stage of the i-th phase second transistor M2_i is coupled to the first terminal of the i-th phase first voltage-controlled switch SC_i_1 and the first terminal of the i-th phase second capacitor C2_i. The second stage of the second transistor M2_i in phase i is coupled to the second voltage terminal V2. The second terminal of the second capacitor C2_i in phase i is coupled to the second voltage terminal V2. The controlled terminal of the first voltage-controlled switch SC_i_1 in phase i is coupled to the output terminal of the third inverter NG3_i in phase i and the controlled terminal of the third voltage-controlled switch SC_i_3 in phase i. The second terminal of the first voltage-controlled switch SC_i_1 in phase i is coupled to the first terminal of the second current source IBIAS2_i in phase i. The second terminal of the second current source IBIAS2_i in phase i is coupled to the first voltage terminal V1. The controlled terminal of the second voltage-controlled switch SC_i_2 in phase i is provided with the i-th control signal RAMP_CLR_i. The first terminal of the second voltage-controlled switch SC_i_2 in phase i is coupled to the first terminal of the second capacitor C2_i in phase i. The second terminal of the second voltage-controlled switch SC_i_2 in phase i is coupled to the first terminal of the third voltage-controlled switch SC_i_3 in phase i. The i-th level ramp compensation time sampling signal VC_O_i is output from the second terminal of the second voltage-controlled switch SC_i_2 of the i-th phase. The second terminal of the third voltage-controlled switch SC_i_3 of the i-th phase is coupled to the first voltage terminal V1. The input terminal of the third inverter NG3_i of the i-th phase is provided with the i-th control signal RAMP_CLR_i.

[0060] Figure 9 Show Figure 8An exemplary circuit diagram of the i-th compensation time limiting circuit 8214 in the i-th level ramp compensation sub-circuit is shown. In some embodiments of this disclosure, the i-th compensation time limiting circuit 8214 may include: an i-th phase fourth inverter NG4_i, an i-th phase third transistor M3_i, an i-th phase third capacitor C3_i, an i-th phase third current source IBIAS3_i, an i-th phase fifth inverter NG5_i, an i-th phase fourth voltage-controlled switch SC_i_4, an i-th phase fifth voltage-controlled switch SC_i_5, an i-th phase sixth voltage-controlled switch SC_i_6, and an i-th comparator CMPi. The input terminal of the i-th phase fourth inverter NG4_i is provided with the i-th phase PWM signal PWM_i. The output terminal of the i-th phase fourth inverter NG4_i is coupled to the control stage of the i-th phase third transistor M3_i. The first stage of the i-th phase third transistor M3_i is coupled to the first terminal of the i-th phase fourth voltage-controlled switch SC_i_4 and the first terminal of the i-th phase third capacitor C3_i. The second stage of the third transistor M3_i in phase i is coupled to the second voltage terminal V2. The second terminal of the third capacitor C3_i in phase i is coupled to the second voltage terminal V2. The controlled terminal of the fourth voltage-controlled switch SC_i_4 in phase i is provided with the PWM signal PWM_i for phase i. The second terminal of the fourth voltage-controlled switch SC_i_4 in phase i is coupled to the first terminal of the third current source IBIAS3_i in phase i. The second terminal of the third current source IBIAS3_i in phase i is coupled to the first voltage terminal V1. The controlled terminal of the fifth voltage-controlled switch SC_i_5 in phase i is provided with the PWM signal PWM_i for phase i. The first terminal of the fifth voltage-controlled switch SC_i_5 in phase i is coupled to the first terminal of the third capacitor C3_i in phase i. The second terminal of the fifth voltage-controlled switch SC_i_5 in phase i is coupled to the first terminal of the sixth voltage-controlled switch SC_i_6 in phase i and the first input terminal of the comparator CMPi in phase i. The controlled terminal of the sixth voltage-controlled switch SC_i_6 of phase i is coupled to the output terminal of the fifth inverter NG5_i of phase i. The second terminal of the sixth voltage-controlled switch SC_i_6 of phase i is coupled to the first voltage terminal V1. The input terminal of the fifth inverter NG5_i of phase i is provided with the PWM signal PWM_i of phase i. The second input terminal of the comparator CMPi is provided with the ramp compensation time sampling signal VC_O_i-1 of stage i-1. The reset signal VC_CLR_i of stage i is output from the output terminal of the comparator CMPi.

[0061] exist Figures 7 to 9 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. All transistors are NMOS transistors. The first input terminal of all voltage-controlled current sources is a non-inverting input terminal. The second input terminal of all voltage-controlled current sources is an inverting input terminal. The first input terminal of all comparators is a non-inverting input terminal. The second input terminal of all comparators is an inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figures 7 to 9Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figures 7 to 9 The examples shown have different settings.

[0062] Figure 10 Showing for including Figure 4 The following is a timing diagram of some signals of the multiphase DC-DC converter with the slope compensation circuit shown. (See below for details.) Figures 7 to 10 The following example illustrates the operation of a slope compensation circuit for a multiphase DC-DC converter according to embodiments of the present disclosure.

[0063] exist Figure 7 In the first-stage slope compensation sub-circuit 721-1 shown, the main phase second current source IBIAS2_1 can output a fixed bias current of the same magnitude as the main phase first current source IBIAS1_1. The main phase second capacitor C2 has the same size as the main phase first capacitor C1. When the main phase control signal RAMP_CLR_1 flips to a low level as the main phase PWM signal PWM_1 flips to a high level in each switching cycle, the main phase first transistor M1 and the main phase second transistor M2 are simultaneously turned off, and the main phase first voltage-controlled switch SC_1_1 and the main phase third voltage-controlled switch SC_1_3 are closed. The signal VC_INT_1 stored on the upper plate of the main phase second capacitor C2 and the signal VRAMP_1 stored on the upper plate of the main phase first capacitor C1 start from 0V synchronously and rise at the same slope. At this time, the second voltage-controlled switch SC_1_2 of the main phase is opened, and the first-stage ramp compensation time sampling signal VC_O_1 is set to the first voltage V1 to ensure that the reset signal VC_CLR_2 output by the comparator in the next stage (first sub-phase) ramp compensation sub-circuit is set to 0. Opening the second voltage-controlled switch SC_1_2 of the main phase prevents the signal VC_INT_1, which has not yet been fully established, from being interfered with by subsequent stage signals. Figure 7 In the process, when the main phase control signal RAMP_CLR_1 flips to a high level as the main phase PWM signal PWM_1 flips to a low level in each switching cycle, or flips to a high level because the ramp charging time reaches the delay set by the rise time control circuit 72111, the main phase first voltage-controlled switch SC_1_1 and the main phase third voltage-controlled switch SC_1_3 are opened, and the main phase second voltage-controlled switch SC_1_2 is closed. The signal VC_INT_1, which completes the charging in a single cycle, samples the rise time of the first-stage ramp compensation signal and outputs it to the second input terminal VC_I_2 of the comparator of the first sub-phase in the form of the first-stage ramp compensation time sampling signal VC_O_1. When the next stage (first sub-phase) reset signal VC_CLR_2 flips to a high level, the main phase second AND gate AND2 outputs a high-level signal, thereby turning on the main phase second transistor M2, and the first-stage ramp compensation time sampling signal VC_O_1 is reset to zero.

[0064] The following example uses i=2. Figure 8 The working process is explained below. In the i-th compensation time limiting circuit 8214 (refer to...) Figure 9 ), where signal VC_I_i is the first-level slope compensation time sampling signal VC_O_1 received by the i-th level slope compensation sub-circuit, containing the main phase slope charging time information. Figure 9 In the process, when the PWM signal PWM_i of the i-th phase in each switching cycle flips to a high level, the fourth voltage-controlled switch SC_i_4 and the fifth voltage-controlled switch SC_i_5 of the i-th phase close, and the sixth voltage-controlled switch SC_i_6 of the i-th phase opens, and the signal VP_i and... Figure 8 The VRAMP_i signal in the circuit starts from 0V and charges at the same slope. During this process, the VC_I_i signal switches from V1 to the fixed level VC_INT_1 due to the completion of charging of the previous ramp signal (when i=2, because the main phase control signal RAMP_CLR_1 flips to a high level). Figure 9 In the process, when the signal VP_i rises to the level of signal VC_INT_1 and the PWM signal PWM_i of the i-th phase of the current cycle remains high, the i-th stage reset signal VC_CLR_i output by the i-th comparator CMPi flips from low to high and is output to... Figure 7 The second-stage reset signal VC_CLR_2, as described above, flips to a high level, which resets the first-stage ramp compensation time sampling signal VC_O_1 to zero. (See reference...) Figure 8 The i-th stage reset signal VC_CLR_i can also clear the i-th stage ramp compensation signal of the current cycle in this stage of the ramp compensation sub-circuit. Thus, the continuous ramp compensation that begins with the arrival of the switching cycle (the rising edge of the PWM signal PWM_i of the i-th phase) ends, and the i-th phase of the current cycle can maintain the same ramp compensation time as the (i-1)-th phase of the corresponding sequentially delayed cycle. Figure 9 In the current cycle, when the PWM signal PWM_i changes from high to low before the signal VP_i has reached its charging peak, the fourth voltage-controlled switch SC_i_4 and the fifth voltage-controlled switch SC_i_5 of the i-th phase open, and the sixth voltage-controlled switch SC_i_6 of the i-th phase closes, thus clearing the signal VP_i to zero. (Reference) Figure 8 It can be seen that at this time, both the signal VRAMP_i and the main phase signal VC_INT_1 are cleared to zero. Under this condition, the slope compensation time of the first sub-phase is lower than the slope compensation time of the main phase corresponding to its sequential delay period.

[0065] Therefore, whether the signal VP_i is charged to the signal VC_I_i or the signal VP_i has not yet been charged to the signal VC_I_i but the PWM signal PWM_i of the current cycle has flipped from high to low, the ramp compensation time of the first sub-phase will not exceed the ramp compensation time of the main phase corresponding to its sequential delay period.

[0066] exist Figure 8 In the example, with Figure 7 Similarly, the second current source IBIAS2_i of phase i can output a fixed bias current of the same magnitude as the first current source IBIAS1_i of phase i. The size of the second capacitor C2_i of phase i is the same as that of the first capacitor C1_i of phase i. When the reset signal VC_CLR_i+1 of the next stage is at a low level, when the control signal RAMP_CLR_i of phase i flips to a low level as the PWM signal PWM_i of phase i flips to a high level in each switching cycle, the first transistor M1_i and the second transistor M2_i of phase i are turned off simultaneously, the first voltage-controlled switch SC_i_1 and the third voltage-controlled switch SC_i_3 of phase i are closed, and the signal VC_INT_i stored on the upper plate of the second capacitor C2_i of phase i and the signal VRAMP_i stored on the upper plate of the first capacitor C1_i of phase i start from 0 synchronously and rise at the same slope. At this time, the second voltage-controlled switch SC_i_2 of the i-th phase is opened, and the i-th stage ramp compensation time sampling signal VC_O_i is set to the first voltage V1 to ensure that the reset signal VC_CLR_i+1 output by the comparator in the next stage ramp compensation sub-circuit is set to 0. Opening the second voltage-controlled switch SC_i_2 of the i-th phase prevents the signal VC_INT_i, which has not yet been fully established, from being interfered with by signals from subsequent stages. Figure 7 In the process, when the i-th phase control signal RAMP_CLR_i flips to a high level as the i-th phase PWM signal PWM_i flips to a low level in each switching cycle, or flips to a high level because the ramp charging time reaches the ramp charging time of the previous stage, the i-th phase first voltage control switch SC_i_1 and the i-th phase third voltage control switch SC_i_3 are opened, and the i-th phase second voltage control switch SC_i_2 is closed. The signal VC_INT_i that completes the charging in a single cycle samples the rise time of the i-th stage ramp compensation signal and outputs it to the second input terminal VC_I_i+1 of the i+1 stage comparator in the form of the i-th stage ramp compensation time sampling signal VC_O_i.

[0067] like Figure 10As shown, when a load transition occurs, even if the peak sampling signal VCS_i+2 of the inductor current in phase i+2 misses multiple valley delay points of phase i+1 during the long period of power transistor operation, its DC level can still rise to match the previous phase with subsequent cycle adjustments. This is because the sampling of the slope compensation time is passed sequentially, and the slope of the superimposed signal of the current phase from its initial rise to the signal EAO will never exceed that of the previous phase. Therefore, the difference between the DC level of the inductor current in the current phase and that of the previous phase converges cycle by cycle, thus fundamentally avoiding the unstable state of different phases entering the cross-cycle "stable" process.

[0068] In summary, the slope compensation circuit for a multiphase DC-DC converter according to the embodiments of this disclosure avoids the problem of large differences in the switching cycles of each phase when the applied load switches from light load to heavy load by limiting the rise time of the slope compensation signal of the subsequent phase to no more than the rise time of the slope compensation signal of the preceding phase, thereby maintaining the overall stability of the multiphase DC-DC converter.

[0069] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0070] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0071] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A slope compensation circuit for a multiphase DC-DC converter, comprising: Multiple cascaded ramp compensator sub-circuits, The i-th level slope compensation sub-circuit is configured to generate the i-th level slope compensation signal, the i-th level slope compensation time sampling signal, and the i-th level reset signal under the control of the PWM signal of the i-th phase and the i-1 level slope compensation time sampling signal output by the (i-1)-th level slope compensation sub-circuit. The rise time of the i-th level slope compensation signal is controlled to be less than or equal to the rise time of the (i-1)-th level slope compensation signal. The first-stage slope compensation sub-circuit is configured to generate a first-stage slope compensation signal and a first-stage slope compensation time sampling signal based on the PWM signal of the main phase and the system switching frequency signal. The slope compensation time sampling signal for each level is used to record the rise time of the slope compensation signal for that level, and the reset signal for each level is used to reset the slope compensation time sampling signal of the previous level when the slope compensation signal of that level stops rising. i is an integer greater than 1.

2. The slope compensation circuit according to claim 1, wherein, The first-stage slope compensation sub-circuit includes: a main-phase slope signal control circuit, a main-phase slope signal generation circuit, and a main-phase slope compensation time sampling circuit. The main phase ramp signal control circuit is configured to generate a main phase control signal based on the main phase PWM signal and the system switching frequency signal. The main phase ramp signal generation circuit is configured to generate the first-level ramp compensation signal based on the main phase control signal. The main phase ramp compensation time sampling circuit is configured to generate the first-stage ramp compensation time sampling signal based on the main phase control signal and the next-stage reset signal. The main phase control signal is used to control the rise time of the first-stage slope compensation signal.

3. The slope compensation circuit according to claim 2, wherein, The main phase ramp signal control circuit includes: a rise time control circuit, a main phase first AND gate, and a main phase first inverter. The first input terminal of the main phase first AND gate is provided with the PWM signal of the main phase; The rise time control circuit is provided with the PWM signal of the main phase and the system switching frequency signal, and is configured to: start timing from the rising edge of the PWM signal of the main phase, determine a preset time period according to the system switching frequency signal, and output a low-level signal when the preset time period is completed; The output of the rise time control circuit is coupled to the second input of the main phase first AND gate; The output terminal of the first AND gate of the main phase is coupled to the input terminal of the first inverter of the main phase. The main phase control signal is output from the output terminal of the first inverter of the main phase.

4. The slope compensation circuit according to claim 2, wherein, The main phase ramp signal generation circuit includes: a main phase first transistor, a main phase first capacitor, a main phase first current source, a main phase voltage-controlled current source, and a first resistor. The control electrode of the first transistor of the main phase is provided with the main phase control signal, the first stage of the first transistor of the main phase is coupled to the first terminal of the first current source of the main phase and the first terminal of the first capacitor of the main phase, and the second stage of the first transistor of the main phase is coupled to the second voltage terminal. The second terminal of the first capacitor of the main phase is coupled to the second voltage terminal; The second terminal of the first current source of the main phase is coupled to the first voltage terminal; The first input terminal of the main phase voltage-controlled current source is coupled to the first terminal of the main phase first capacitor, the second input terminal of the main phase voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the main phase voltage-controlled current source is coupled to the first voltage terminal, and the second output terminal of the main phase voltage-controlled current source is coupled to the first terminal of the first resistor. The first-stage slope compensation signal is output from the second end of the first resistor.

5. The slope compensation circuit according to claim 2, wherein, The main phase ramp compensation time sampling circuit includes: a main phase second AND gate, a main phase second transistor, a main phase second capacitor, a main phase second current source, a main phase second inverter, a main phase first voltage-controlled switch, a main phase second voltage-controlled switch, and a main phase third voltage-controlled switch. Wherein, the first input terminal of the main phase second AND gate is provided with the main phase control signal, the second input terminal of the main phase second AND gate is provided with the next stage reset signal, and the output terminal of the main phase second AND gate is coupled to the control stage of the main phase second transistor; The first stage of the main phase second transistor is coupled to the first terminal of the main phase first voltage-controlled switch and the first terminal of the main phase second capacitor, and the second stage of the main phase second transistor is coupled to the second voltage terminal; The second terminal of the main phase second capacitor is coupled to the second voltage terminal; The controlled terminal of the first voltage-controlled switch of the main phase is coupled to the output terminal of the second inverter of the main phase and the controlled terminal of the third voltage-controlled switch of the main phase, and the second terminal of the first voltage-controlled switch of the main phase is coupled to the first terminal of the second current source of the main phase. The second terminal of the main phase second current source is coupled to the first voltage terminal; The controlled terminal of the main phase second voltage-controlled switch is provided with the main phase control signal. The first terminal of the main phase second voltage-controlled switch is coupled to the first terminal of the main phase second capacitor. The second terminal of the main phase second voltage-controlled switch is coupled to the first terminal of the main phase third voltage-controlled switch. The first-level ramp compensation time sampling signal is output from the second terminal of the main phase second voltage-controlled switch. The second terminal of the main phase third voltage-controlled switch is coupled to the first voltage terminal; The input terminal of the second inverter of the main phase is provided with the main phase control signal.

6. The slope compensation circuit according to claim 1, wherein, The i-th level ramp compensation sub-circuit includes: an i-th compensation time limiting circuit, an i-th ramp signal control circuit, an i-th ramp signal generation circuit, and an i-th ramp compensation time sampling circuit. The i-th compensation time limiting circuit is configured to generate the i-th stage reset signal based on the PWM signal of the i-th phase, the (i-1)-th stage ramp compensation time sampling signal, and the first voltage from the first voltage terminal. The i-th ramp signal control circuit is configured to generate the i-th control signal based on the PWM signal of the i-th phase and the i-th stage reset signal; The i-th ramp signal generation circuit is configured to generate the i-th level ramp compensation signal according to the i-th control signal; The i-th ramp compensation time sampling circuit is configured to generate the i-th level ramp compensation time sampling signal based on the i-th control signal and the next level reset signal; Wherein, the time during which the i-th level reset signal is at an effective level is less than or equal to the rise time of the (i-1)-th level ramp compensation signal, the time during which the i-th level control signal is at an effective level is less than or equal to the time during which the i-th level reset signal is at an effective level, and the i-th level control signal is used to control the rise time of the i-th level ramp compensation signal.

7. The slope compensation circuit according to claim 6, wherein, The i-th ramp signal control circuit includes: a first AND gate for the i-th phase, a first inverter for the i-th phase, and a second inverter for the i-th phase. Wherein, the first input terminal of the first AND gate of the i-th phase is provided with the PWM signal of the i-th phase, the second input terminal of the first AND gate of the i-th phase is coupled to the output terminal of the second inverter of the i-th phase, and the output terminal of the first AND gate of the i-th phase is coupled to the input terminal of the first inverter of the i-th phase; The input terminal of the i-th phase second inverter is provided with the i-th stage reset signal; The i-th control signal is output from the output terminal of the i-th phase first inverter.

8. The slope compensation circuit according to claim 6, wherein, The i-th ramp signal generation circuit includes: an i-th phase first transistor, an i-th phase first capacitor, an i-th phase first current source, an i-th phase voltage-controlled current source, and an i-th resistor. Wherein, the control electrode of the first transistor of the i-th phase is provided with the i-th control signal, the first stage of the first transistor of the i-th phase is coupled to the first terminal of the first current source of the i-th phase and the first terminal of the first capacitor of the i-th phase, and the second stage of the first transistor of the i-th phase is coupled to the second voltage terminal; The second terminal of the first capacitor of the i-th phase is coupled to the second voltage terminal; The second terminal of the first current source of the i-th phase is coupled to the first voltage terminal; The first input terminal of the i-th phase voltage-controlled current source is coupled to the first terminal of the i-th phase first capacitor, the second input terminal of the i-th phase voltage-controlled current source is coupled to the second voltage terminal, the first output terminal of the i-th phase voltage-controlled current source is coupled to the first voltage terminal, and the second output terminal of the i-th phase voltage-controlled current source is coupled to the first terminal of the i-th resistor. The i-th level slope compensation signal is output from the second terminal of the i-th resistor.

9. The slope compensation circuit according to claim 6, wherein, The i-th ramp compensation time sampling circuit includes: a second AND gate for the i-th phase, a second transistor for the i-th phase, a second capacitor for the i-th phase, a second current source for the i-th phase, a third inverter for the i-th phase, a first voltage-controlled switch for the i-th phase, a second voltage-controlled switch for the i-th phase, and a third voltage-controlled switch for the i-th phase. Wherein, the first input terminal of the i-th phase second AND gate is provided with the i-th control signal, the second input terminal of the i-th phase second AND gate is provided with the next stage reset signal, and the output terminal of the i-th phase second AND gate is coupled to the control stage of the i-th phase second transistor; The first stage of the i-th phase second transistor is coupled to the first terminal of the i-th phase first voltage-controlled switch and the first terminal of the i-th phase second capacitor, and the second stage of the i-th phase second transistor is coupled to the second voltage terminal; The second terminal of the second capacitor of the i-th phase is coupled to the second voltage terminal; The controlled terminal of the first voltage-controlled switch of the i-th phase is coupled to the output terminal of the third inverter of the i-th phase and the controlled terminal of the third voltage-controlled switch of the i-th phase, and the second terminal of the first voltage-controlled switch of the i-th phase is coupled to the first terminal of the second current source of the i-th phase. The second terminal of the second current source of the i-th phase is coupled to the first voltage terminal; The controlled terminal of the i-th phase second voltage-controlled switch is provided with the i-th control signal. The first terminal of the i-th phase second voltage-controlled switch is coupled to the first terminal of the i-th phase second capacitor. The second terminal of the i-th phase second voltage-controlled switch is coupled to the first terminal of the i-th phase third voltage-controlled switch. The i-th level ramp compensation time sampling signal is output from the second terminal of the i-th phase second voltage-controlled switch. The second terminal of the third voltage-controlled switch of the i-th phase is coupled to the first voltage terminal; The input terminal of the i-th phase third inverter is provided with the i-th control signal.

10. The slope compensation circuit according to claim 6, wherein, The i-th compensation time limiting circuit includes: a fourth inverter for the i-th phase, a third transistor for the i-th phase, a third capacitor for the i-th phase, a third current source for the i-th phase, a fifth inverter for the i-th phase, a fourth voltage-controlled switch for the i-th phase, a fifth voltage-controlled switch for the i-th phase, a sixth voltage-controlled switch for the i-th phase, and an i-th comparator. The input terminal of the fourth inverter of the i-th phase is provided with the PWM signal of the i-th phase, and the output terminal of the fourth inverter of the i-th phase is coupled to the control stage of the third transistor of the i-th phase. The first stage of the third transistor of the i-th phase is coupled to the first terminal of the fourth voltage-controlled switch of the i-th phase and the first terminal of the third capacitor of the i-th phase, and the second stage of the third transistor of the i-th phase is coupled to the second voltage terminal; The second terminal of the third capacitor of the i-th phase is coupled to the second voltage terminal; The controlled terminal of the fourth voltage-controlled switch of the i-th phase is provided with the PWM signal of the i-th phase, and the second terminal of the fourth voltage-controlled switch of the i-th phase is coupled to the first terminal of the third current source of the i-th phase. The second terminal of the third current source of the i-th phase is coupled to the first voltage terminal; The controlled terminal of the fifth voltage-controlled switch of the i-th phase is provided with the PWM signal of the i-th phase. The first terminal of the fifth voltage-controlled switch of the i-th phase is coupled to the first terminal of the third capacitor of the i-th phase. The second terminal of the fifth voltage-controlled switch of the i-th phase is coupled to the first terminal of the sixth voltage-controlled switch of the i-th phase and the first input terminal of the i-th comparator. The controlled terminal of the sixth voltage-controlled switch of the i-th phase is coupled to the output terminal of the fifth inverter of the i-th phase, and the second terminal of the sixth voltage-controlled switch of the i-th phase is coupled to the first voltage terminal; The input terminal of the fifth inverter of the i-th phase is provided with the PWM signal of the i-th phase; The second input terminal of the i-th comparator is provided with the (i-1)th level ramp compensation time sampling signal, and the i-th level reset signal is output from the output terminal of the i-th comparator.

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