Display substrate and its preparation method, display device

Abstract

A display substrate, a method for manufacturing the same, and a display device are disclosed. The display substrate includes a display area and a first dicing area. The display substrate includes a substrate and a composite insulating layer disposed on the substrate. The composite insulating layer located in the first dicing area includes intermittent grooves. The arrangement direction of the intermittent grooves intersects the direction from the first dicing area to the display area, and the grooves expose the surface of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, OLED technology is increasingly being used in flexible display devices.

[0003] The inventors of this application have discovered a problem with poor wiring when bonding the display substrate to the chip-on-flex (COF) film. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and its preparation method, as well as a display device, to solve the problem of poor wiring when the display substrate is bonded to the flip-chip film.

[0006] In a first aspect, embodiments of this disclosure provide a display substrate, including a display area and a first dicing area. The display substrate includes a substrate and a composite insulating layer disposed on the substrate. The composite insulating layer located in the first dicing area includes discontinuous grooves. The arrangement direction of the discontinuous grooves intersects with the direction from the first dicing area to the display area. The grooves expose the surface of the substrate.

[0007] In one exemplary embodiment, the discontinuous grooves are arranged along the extension direction of a second cutting path located in the first cutting area, the second cutting path being a precision cutting path.

[0008] In one exemplary embodiment, the first cutting area includes an inner cutting area, a cutting channel area, and an outer cutting area; the cutting channel area is located in the middle of the first cutting area, the inner cutting area is located on the side of the cutting channel area adjacent to the display area, and the outer cutting area is located on the side of the cutting channel area away from the display area.

[0009] In one exemplary embodiment, the cut inner region includes a stepped structure formed by the substrate and the composite insulating layer, wherein the height of the steps in the stepped structure increases sequentially along the direction from the first cut region to the display area.

[0010] In one exemplary embodiment, the composite insulating layer of the first cut area includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on the substrate.

[0011] In one exemplary embodiment, the groove includes a first groove and a second groove; the first groove is disposed on the fourth insulating layer, the third insulating layer and the second insulating layer, and the first groove exposes the surface of the first insulating layer; the second groove is disposed on the substrate and the first insulating layer, and the second groove exposes the surface of the substrate; the first groove exposes the second groove.

[0012] In one exemplary embodiment, the sidewalls of the first groove and the second groove are sloped surfaces.

[0013] In one exemplary embodiment, the orthographic projection of the first groove on the substrate includes the orthographic projection of the second groove on the substrate.

[0014] In one exemplary embodiment, a dam is formed between adjacent grooves; when bonding the display substrate and the flip-chip film, the orthographic projection of the gap between adjacent bonding pins of the flip-chip film on the substrate at least partially overlaps with the orthographic projection of the dam on the substrate.

[0015] In one exemplary embodiment, the orthographic projection of the gap between adjacent bonding pins of the flip-chip film onto the substrate includes the orthographic projection of the dam onto the substrate.

[0016] In one exemplary embodiment, the orthographic projection of the groove on the substrate includes the orthographic projection of the bonding pins of the flip-chip film on the substrate.

[0017] Secondly, embodiments of this disclosure provide a display device, including a display substrate as described above.

[0018] Thirdly, embodiments of this disclosure provide a method for fabricating a display substrate, the display substrate including a display area and a first dicing area, the method including: forming a driving structure layer on a substrate of the display area and the first dicing area, the driving structure layer of the first dicing area including a composite insulating layer; forming discontinuous grooves on the composite insulating layer of the first dicing area, the arrangement direction of the discontinuous grooves intersecting the direction from the first dicing area to the display area, the grooves exposing the surface of the substrate.

[0019] The display substrate proposed in this disclosure features intermittent grooves formed on the composite insulating layer of the first dicing area. The arrangement direction of these intermittent grooves intersects the direction from the first dicing area to the display area, and dams are formed between adjacent grooves, preventing residual metal from remaining at the dams. When bonding the display substrate and the flip-chip film, the bonding leads of the flip-chip film extend to the areas where the grooves and dams are located. Due to the obstruction of the dams, adjacent bonding leads of the flip-chip film are not short-circuited by residual metal. This solves the problem of poor wiring during the bonding of the display substrate and the flip-chip film.

[0020] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0021] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0022] Figure 1 This is a schematic diagram of the structure of an electronic device;

[0023] Figure 2 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0024] Figure 3 This is a schematic diagram showing the arrangement of multiple display substrates on the display motherboard;

[0025] Figure 4 This is a schematic diagram of residual metal on the fourth insulating layer of the display substrate;

[0026] Figure 5 This is a schematic diagram illustrating the bonding connection between a display substrate and a flip-chip film in some technologies;

[0027] Figure 6 This is a schematic cross-sectional view of the display substrate provided in the embodiments of this disclosure;

[0028] Figure 7 This is a top view of a display substrate in an exemplary embodiment;

[0029] Figure 8 for Figure 7 A schematic diagram of the AA direction. Detailed Implementation

[0030] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0031] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0032] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0033] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0034] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0035] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0036] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0037] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0038] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0039] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0040] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0041] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0042] Figure 1 This is a schematic diagram of the structure of an electronic device. For example... Figure 1As shown, the electronic device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the data signal lines, and the light-emitting signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0043] Figure 2 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 2As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit includes a data signal terminal D, a first scan signal terminal S1, a second scan signal terminal S2, a light emission signal terminal E, an initial signal terminal INIT, a first power supply terminal VDD, and a second power supply terminal VSS. Each terminal is connected to the corresponding signal line or power supply line.

[0044] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0045] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0046] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0047] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0048] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0049] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal terminal D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0050] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.

[0051] The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0052] In an exemplary embodiment, the light-emitting device may be an OLED, which includes a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it may be a QLED, which includes a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0053] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal terminal S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal terminal S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal terminal S1 is S(n), and the second scan signal terminal S2 is S(n-1). The second scan signal terminal S2 of this display row and the first scan signal terminal S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0054] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0055] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0056] In an exemplary implementation, to Figure 2 Taking the example that all seven transistors in the pixel driving circuit shown are P-type transistors, the operation of the pixel driving circuit can include:

[0057] In the first stage, A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal INIT is provided to the second node N2 to initialize the storage capacitor C, clearing the original data voltage within it. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the OLED does not emit light.

[0058] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal at the first scan signal terminal S1 is low, while the signals at the second scan signal terminal S2 and the light emission signal terminal E are high. The data signal terminal D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal at the first scan signal terminal S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal terminal D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal terminal D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal terminal D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal terminal INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal at the second scan signal terminal S2 is a high-level signal, causing the first transistor T1 to turn off. The signal at the light emission signal terminal E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0059] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal E is at a low level, while the first scan signal S1 and the second scan signal S2 are at high levels. The low level of the light-emitting signal E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply terminal VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0060] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vd - |Vth|, the driving current of the third transistor T3 is:

[0061] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0062] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal terminal D, and Vdd is the power supply voltage received by the first power supply terminal VDD from the first power supply line 81.

[0063] Currently, the process of manufacturing OLED display devices involves first preparing a display motherboard, and then cutting the display motherboard into multiple display substrates. Each of these separate display substrates can be used to form a single OLED display device. Figure 3 This is a schematic diagram showing the arrangement of multiple display substrates on a display motherboard. (Example) Figure 3 As shown, multiple substrate regions 300 on the display motherboard 100 are arranged in a periodic and regular pattern, and the cutting region 400 is located outside the substrate regions 300. Each substrate region 300 includes at least a display region 310, which comprises multiple pixels arranged in a matrix. A first cutting track 701 and a second cutting track 702 are provided within the cutting region 400. The first cutting region 410 is located on the side of the first cutting track 701 closest to the display region 310. The second cutting track 702 and an ET (Electric Test) unit 420 are located within the first cutting region 410, allowing for ET testing of the display substrate. After all film layers of the display motherboard are prepared, the cutting equipment performs rough cutting and fine cutting along the first cutting track 701 and the second cutting track 702, respectively, to form the display substrate.

[0064] Research has revealed that poor bonding during the bonding of display substrates to COF (Chip-on-Flush) is due to metal residue in the cutting area during the fabrication process. A fabrication process for the cutting area of ​​a display substrate includes: sequentially forming a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer on a substrate. To reduce the cutting thickness and difficulty in subsequent cutting processes, grooves exposing the substrate are formed on the insulating layers in the cutting area. This creates a stepped groove structure with sloping sidewalls. Subsequently, a metal thin film is deposited, and the metal thin film is patterned using a patterning process to form a metal conductive layer pattern on the fourth insulating layer. During the patterning of the metal thin film, PR (preservative adhesive) may accumulate near the boundary of the fourth insulating layer close to the cutting path. Residue from the PR adhesive remains during exposure, resulting in residual metal a near the boundary of the fourth insulating layer close to the cutting path. Figure 4 As shown. When bonding the display substrate to the COF, because the bonding pins 51 of the COF are relatively long, after bonding with the bonding terminals 50 on the display substrate, the bonding pins 51 extend beyond the boundary of the fourth insulating layer near the dicing line, as shown. Figure 5As shown, residual metal a at the boundary of the fourth insulating layer will short-circuit the adjacent COF bonding pin 51, causing poor wiring.

[0065] This disclosure provides a display substrate including a display area and a first dicing area. The display substrate includes a substrate and a composite insulating layer disposed on the substrate. The composite insulating layer located in the first dicing area includes discontinuous grooves. The arrangement direction of the discontinuous grooves intersects with the direction from the first dicing area to the display area. The grooves expose the surface of the substrate.

[0066] The display substrate proposed in this embodiment features intermittent grooves formed on the composite insulating layer of the first cutting area. The arrangement direction of these intermittent grooves intersects the direction from the first cutting area to the display area, and dams are formed between adjacent grooves, preventing metal residue at the dams. When bonding the display substrate and the flip-chip film, the bonding leads of the flip-chip film extend to the areas where the grooves and dams are located. The dams prevent short circuits between adjacent bonding leads of the flip-chip film due to residual metal. The intermittent grooves result in minimal increase in film thickness at the cutting path of the display substrate, thus not affecting the cutting process of the display substrate.

[0067] In one exemplary embodiment, the discontinuous grooves are arranged along the extension direction of a second cutting path located in the first cutting area, the second cutting path being a precision cutting path.

[0068] In one exemplary embodiment, the first cutting area includes an inner cutting area, a cutting channel area, and an outer cutting area; the cutting channel area is located in the middle of the first cutting area, the inner cutting area is located on the side of the cutting channel area adjacent to the display area, and the outer cutting area is located on the side of the cutting channel area away from the display area.

[0069] In one exemplary embodiment, the cut inner region includes a stepped structure formed by the substrate and the composite insulating layer, wherein the height of the steps in the stepped structure increases sequentially along the direction from the first cut region to the display area.

[0070] In one exemplary embodiment, the composite insulating layer of the first cut area includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on the substrate.

[0071] In one exemplary embodiment, the groove includes a first groove and a second groove; the first groove is disposed on the fourth insulating layer, the third insulating layer and the second insulating layer, and the first groove exposes the surface of the first insulating layer; the second groove is disposed on the substrate and the first insulating layer, and the second groove exposes the surface of the substrate; the first groove exposes the second groove.

[0072] In one exemplary embodiment, the sidewalls of the first groove and the second groove are sloped surfaces.

[0073] In one exemplary embodiment, the orthographic projection of the first groove on the substrate includes the orthographic projection of the second groove on the substrate.

[0074] In one exemplary embodiment, a dam is formed between adjacent grooves; when bonding the display substrate and the flip-chip film, the orthographic projection of the gap between adjacent bonding pins of the flip-chip film on the substrate at least partially overlaps with the orthographic projection of the dam on the substrate.

[0075] In one exemplary embodiment, the orthographic projection of the gap between adjacent bonding pins of the flip-chip film onto the substrate includes the orthographic projection of the dam onto the substrate.

[0076] In one exemplary embodiment, the orthographic projection of the groove on the substrate includes the orthographic projection of the bonding pins of the flip-chip film on the substrate.

[0077] Figure 6 This is a cross-sectional view of the display substrate provided in an embodiment of the present disclosure, illustrating the structure of a sub-pixel. Figure 7 This is a top view of a display substrate bonded to a flip-chip film in an exemplary embodiment. Figure 8 for Figure 7 A schematic diagram of the AA direction. (See diagram below.) Figures 6 to 8 As shown, the display substrate includes a display area 310 and a first cutting area 410. The display substrate includes a substrate 10 and a composite insulating layer disposed on the substrate 10. The composite insulating layer located in the first cutting area 410 includes intermittent grooves. The arrangement direction of the intermittent grooves intersects with the direction from the first cutting area 410 to the display area 310. The grooves expose the surface of the substrate 10.

[0078] In an exemplary embodiment, the intermittent grooves may be arranged along the extension direction of the second cutting channel 702 located in the first cutting area 410, the second cutting channel 702 being a fine cutting channel.

[0079] In an exemplary embodiment, the composite insulating layer of the first cutting region 410 includes a plurality of inorganic insulating layers, including a first insulating layer 11, a second insulating layer 12, a third insulating layer 13 and a fourth insulating layer 14 stacked on the substrate 10.

[0080] In an exemplary embodiment, the first cutting area 410 further includes a test pad 421 disposed on the composite insulating layer. The test pad 421 is a pad of the ET test unit 420.

[0081] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate of the display area 310 may include a substrate 10, a driving circuit layer, a planarization layer 60, a light-emitting structure layer, and an encapsulation layer 40 sequentially disposed on the substrate 10. The driving circuit layer includes: a first insulating layer 11 disposed on the substrate 10, an active layer disposed on the first insulating layer 11, a second insulating layer 12 covering the active layer, a first conductive layer disposed on the second insulating layer, a third insulating layer 13 covering the first conductive layer, a second conductive layer disposed on the third insulating layer 13, and a fourth insulating layer 14 covering the second conductive layer. The driving circuit layer may include a pixel driving circuit, which includes a transistor 21A and a storage capacitor 21B. The light-emitting structure layer includes a pixel definition layer 31 and a light-emitting element, which includes an anode 301, an organic light-emitting layer 302, and a cathode 303.

[0082] In an exemplary embodiment, the first cutting area 410 includes an inner cutting area 411, a cutting channel area 412, and an outer cutting area 413. The cutting channel area 412 is located in the middle of the first cutting area 410, the inner cutting area 411 is located on the side of the cutting channel area 412 adjacent to the display area 310, and the outer cutting area 413 is located on the side of the cutting channel area 412 away from the display area 310. The second cutting channel 702 may be located in the cutting channel area 412.

[0083] In an exemplary embodiment, the inner cutting area 411 includes a stepped structure formed by the substrate 10 and a composite insulating layer, wherein the height of the steps in the stepped structure increases sequentially along the direction from the first cutting area 410 to the display area.

[0084] In an exemplary embodiment, the groove includes a first groove 41 and a second groove 42. The first groove 41 is disposed on the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12, and the first groove 41 exposes the surface of the first insulating layer 11. The second groove 42 is disposed on the substrate 10 and the first insulating layer 11, and the second groove 42 exposes the surface of the substrate 10. The first groove exposes the second groove.

[0085] In an exemplary embodiment, the sidewalls of the first groove and the second groove are sloped surfaces.

[0086] In an exemplary embodiment, the orthographic projection of the first groove on the substrate 10 includes the orthographic projection of the second groove on the substrate 10.

[0087] In an exemplary embodiment, a dam is formed between adjacent grooves. When bonding the display substrate and COF, one end of the COF bonding pin 51 is connected to the bonding terminal 50 on the display substrate, and the other end of the COF bonding pin 51 extends beyond the boundary of the fourth insulating layer 14 near the second cut 702. The orthographic projection of the gap between adjacent COF bonding pins 51 on the substrate 10 at least partially overlaps with the orthographic projection of the dam on the substrate 10. Since no metal remains on the dam, the dam can prevent the residual metal a at the edge of the fourth insulating layer 14 from causing short circuits in adjacent COF bonding pins 51.

[0088] In an exemplary embodiment, the orthographic projection of the gap between adjacent COF bonding pins 51 onto the substrate 10 includes the orthographic projection of the dam onto the substrate 10.

[0089] In an exemplary embodiment, the orthographic projection of the groove on the substrate 10 at least partially overlaps with the orthographic projection of the COF bonding pin 51 on the substrate 10.

[0090] In an exemplary embodiment, the orthogonal projection of the groove on the substrate 10 includes the orthogonal projection of the COF bonding pin on the substrate 10.

[0091] In this embodiment, by setting the orthogonal projection of the groove on the substrate 10 to include the orthogonal projection of the COF bonding pin on the substrate 10, the length of the dam between adjacent grooves is reduced, which helps to reduce the film stress during the cutting of the display substrate and makes the cutting process of the display substrate easier. Theoretically, the smaller the size of the dam between adjacent grooves, the more beneficial it is to the cutting process. In practical applications, the size of the dam can be set as needed, and this disclosure does not impose any limitations on this.

[0092] The structure of the display substrate of this disclosure is illustrated below through an example of the display substrate fabrication process. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." When the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0093] In an exemplary embodiment, Figure 6 The fabrication process of the display substrate shown may include the following steps.

[0094] (1) Forming a driving circuit layer pattern. In an exemplary embodiment, forming a driving circuit layer pattern may include:

[0095] A first insulating film and a semiconductor film are sequentially deposited on a substrate 10. The semiconductor film is patterned by a patterning process to form a first insulating layer 11 covering the substrate and a semiconductor layer pattern disposed on the first insulating layer 11. The semiconductor layer pattern may include at least a plurality of active layers located in the display area 310.

[0096] Subsequently, a second insulating film and a first conductive film are deposited sequentially. The first conductive film is patterned using a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer. The first conductive layer pattern may include at least a gate electrode and a first electrode plate located in the display area 310.

[0097] Subsequently, a third insulating film and a second conductive film are deposited sequentially. The second conductive film is patterned using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer. The second conductive layer pattern may include at least a second electrode plate located in the display area 310, wherein the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate.

[0098] Subsequently, a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer pattern covering the second conductive layer pattern. Multiple active vias are formed on the fourth insulating layer. The multiple active vias may include at least two active vias located in the display area 310, and the at least two active vias expose the two ends of the active layer respectively.

[0099] In an exemplary embodiment, during this patterning process, intermittent grooves can be formed in the first cutting area 410. The first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 in the grooves are removed to expose the surface of the substrate 10. The first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 between adjacent grooves are retained to form a dam.

[0100] In an exemplary embodiment, a two-step patterning process can be used to form discontinuous grooves in the first cutting area 410. For example, firstly, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 are etched using a first mask (Etch Bending A Mask, abbreviated as EBA Mask) to form a discontinuous first groove 41 in the first cutting area 410, and a plurality of active vias are formed in the display area 310. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the first groove 41 are etched away, exposing the surface of the first insulating layer 11. Then, the first insulating layer 11 within the first groove 41 in the first cutting area 410 is etched using a second mask (Etch Bending B Mask, abbreviated as EBB Mask) to form a second groove 42 on the first insulating layer 11. The first insulating layer 11 within the second groove 42 is etched away, exposing the surface of the substrate 10. In the first cutting area 410, the first groove 41 exposes the second groove 42, forming a stepped groove structure. By forming intermittent grooves in the first cutting area 410, with dams between adjacent grooves, the dams can separate residual metal at the edge of the fourth insulating layer 14. When bonding the display substrate and COF, the orthographic projection of the gap between adjacent bonding pins of COF on the substrate 10 at least partially overlaps with the orthographic projection of the dams on the substrate 10, which can prevent short circuits between adjacent COF bonding pins. In addition, the removal of the composite insulating layer in the groove can reduce the film stress near the second cutting track 702 and prevent cracks from forming on the display substrate during the cutting process.

[0101] like Figure 8 As shown, the first cutting area 410 can be divided into an inner cutting area 411, a cutting channel area 412, and an outer cutting area 413. The cutting channel area 412 is located in the middle of the first cutting area 410 and is the area where the cut is formed when cutting the display mother board. The inner cutting area 411 is located on the side of the cutting channel area 412 adjacent to the display area 310, and the outer cutting area 413 is located on the side of the cutting channel area 412 away from the display area 310. After the display mother board is cut to form the display substrate, the cutting channel area 412 and the outer cutting area 413 are cut off, and the inner cutting area 411 is retained, forming the edge area of ​​the display substrate. The second cutting channel 702 can be located in the cutting channel area 412. When bonding the display substrate and COF, the bonding pins of COF extend to the inner cutting area 411, located outside the boundary of the fourth insulating layer 14 near the cutting channel area 412. There may be residual metal a at the boundary of the fourth insulating layer 14 near the cutting channel area 412, while the metal on the dam between adjacent grooves can be cleaned. Therefore, by setting the orthographic projection of the gap between adjacent COF bonding pins on the substrate 10 to at least partially overlap with the orthographic projection of the dam on the substrate 10, it is possible to prevent the residual metal a from short-circuiting the adjacent COF bonding pins.

[0102] Subsequently, a third conductive film is deposited and patterned using a patterning process to form a third conductive layer pattern on the fourth insulating layer 14. The third conductive layer pattern may include at least: a source electrode and a drain electrode located in the display area 310, and a test pad 421 located in the first dicing area 410. The test pad 421 is the pad of the ET test unit 420, which can transmit test signals to the display substrate. The test pad 421 may be located in the outer dicing area 413. The source electrode and drain electrode are connected to the active layer through active vias.

[0103] At this point, the driving circuit layer pattern is complete. The driving circuit layer located in the display area 310 may include a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, a fourth insulating layer 14, and a third conductive layer stacked on the substrate 10. The driving circuit layer located in the first dicing area 410 may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, and a third conductive layer stacked on the substrate 10. The driving circuit layer located in the first dicing area 410 also includes intermittent grooves.

[0104] In an exemplary embodiment, the display area 310 driving circuit layer may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 6 The example shown uses a pixel driving circuit comprising a transistor 21A and a storage capacitor 21B. Transistor 21A may include an active layer, a gate electrode, a source electrode, and a drain electrode, while storage capacitor 21B may include a first plate and a second plate. In an exemplary embodiment, transistor 21A may be a driving transistor in the pixel driving circuit, and the driving transistor may be a thin-film transistor (TFT).

[0105] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be made of materials such as glass or quartz, while the flexible substrate may be made of materials such as polyimide (PI). The flexible substrate may be a single-layer structure or a laminated structure composed of inorganic material layers and flexible material layers, which is not limited herein.

[0106] In an exemplary embodiment, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second and third insulating layers can be called (GI) layers, and the fourth insulating layer can be called an interlayer insulating (ILD) layer. The first, second, and third conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The planarization layer can be made of organic materials, such as resin. The semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology, but this disclosure does not limit them.

[0107] (2) Forming a planarization layer pattern. In an exemplary embodiment, forming a planarization layer pattern may include:

[0108] A planar thin film is coated on the substrate on which the aforementioned pattern is formed. The planar thin film is patterned by a patterning process to form a planar layer 60 pattern covering the pattern of the third conductive layer. The planar thin film located in the first cutting area 410 is developed away, exposing the surface of the fourth insulating layer 14 and the test pad 421. At least one connection via is formed on the planar layer of the display area 310, and the connection via exposes the surface of the drain electrode.

[0109] In an exemplary embodiment, the planarization layer may be made of organic materials, such as resin.

[0110] (3) Forming a light-emitting structure layer pattern. In an exemplary embodiment, forming a light-emitting structure layer pattern may include:

[0111] A fourth conductive thin film is deposited on the substrate on which the aforementioned pattern is formed. The fourth conductive thin film is then patterned using a patterning process to form an anode electrode layer pattern in the display area 310. The anode electrode layer pattern may include at least an anode 301, which is connected to the drain electrode of transistor 21A via a connecting via. After this patterning process, the film structure of the first dicing region 410 remains unchanged.

[0112] Subsequently, a pixel definition film is coated on the substrate on which the aforementioned pattern is formed. Through masking, exposure, and development processes, a pixel definition layer 31 is formed in the display area 310. Pixel openings are formed on the pixel definition layer, and the pixel definition film within the pixel openings is developed away, exposing the surface of the anode 301. After this patterning process, the film structure of the first cutting area 410 remains unchanged.

[0113] Subsequently, an organic light-emitting layer 302 and a cathode 303 are sequentially formed on the substrate with the aforementioned pattern. The organic light-emitting layer 302 includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and is formed within the pixel opening of the display area 310, thereby connecting the organic light-emitting layer 302 to the anode 301. Since the anode 301 is connected to the drain electrode of the transistor 21A, the light emission of the organic light-emitting layer 302 is controlled. The cathode 303 is connected to the organic light-emitting layer 302, thus enabling the organic light-emitting layer 302 to be simultaneously connected to both the anode 301 and the cathode 303. After this patterning process, the film structure of the first cutting area 410 remains unchanged.

[0114] At this point, the luminescent structure layer pattern has been successfully prepared.

[0115] In an exemplary embodiment, the fourth conductive film may be made of a metal material, a transparent conductive material, or a multilayer composite structure of a metal material and a transparent conductive material. The metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). The multilayer composite structure may be ITO / Al / ITO, etc.

[0116] In an exemplary embodiment, the material of the pixel-defining film may include polyimide or acrylic, etc. The material of the pixel-defining film may also be an inorganic material, and this disclosure is not limiting in this regard.

[0117] In an exemplary embodiment, the cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0118] (4) An encapsulation layer 40 is formed based on the aforementioned pattern. In an exemplary embodiment, the encapsulation layer 40 is formed in the display area 310, employing a stacked structure of inorganic / organic / inorganic materials, with the organic material layer disposed between the two inorganic material layers. After this patterning process, the film structure of the first cutting area 410 remains unchanged.

[0119] After the above preparation, the structure of the obtained display substrate is as follows: Figure 6As shown. The display substrate may also include other film layer structures, such as touch structure layers, protective layers, etc., which can be fabricated according to actual needs, and will not be elaborated here.

[0120] The structures and fabrication processes shown in the exemplary embodiments of this disclosure are merely illustrative. In actual implementation, the corresponding structures and patterning processes can be modified and added or reduced as needed, and this disclosure does not impose any limitations.

[0121] This disclosure also provides a display device, including the display substrate described in any of the above embodiments. The display device can be any product or component with display function, such as an OLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and this disclosure is not limited thereto.

[0122] This disclosure also provides a method for fabricating a display substrate, the display substrate including a display area and a first dicing area, the method including: forming a driving structure layer on a substrate of the display area and the first dicing area, the driving structure layer of the first dicing area including a composite insulating layer; forming discontinuous grooves on the composite insulating layer of the first dicing area, the arrangement direction of the discontinuous grooves intersecting the direction from the first dicing area to the display area, the grooves exposing the surface of the substrate.

[0123] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area and a first cutting area. The display substrate includes a base and a composite insulating layer disposed on the base. The composite insulating layer located in the first cutting area includes discontinuous grooves. The arrangement direction of the discontinuous grooves intersects with the direction from the first cutting area to the display area. The grooves expose the surface of the base. The intermittent grooves are arranged along the extension direction of the second cutting path located in the first cutting area; The composite insulation layer of the first cutting area includes a first insulation layer, a second insulation layer, a third insulation layer and a fourth insulation layer stacked sequentially on the substrate; The adjacent grooves form a barrier; when bonding the display substrate and the flip-chip film, the orthographic projection of the gap between adjacent bonding pins of the flip-chip film on the substrate at least partially overlaps with the orthographic projection of the barrier on the substrate. The dam is configured to prevent residual metal at the edge of the fourth insulating layer from short-circuiting adjacent bonding pins of the flip-chip film.

2. The display substrate according to claim 1, characterized in that, The second cutting path is a precision cutting path.

3. The display substrate according to claim 1 or 2, characterized in that, The first cutting area includes an inner cutting area, a cutting channel area, and an outer cutting area; the cutting channel area is located in the middle of the first cutting area, the inner cutting area is located on the side of the cutting channel area adjacent to the display area, and the outer cutting area is located on the side of the cutting channel area away from the display area.

4. The display substrate according to claim 3, characterized in that, The inner cutting area includes a stepped structure formed by the substrate and the composite insulating layer, wherein the height of the steps in the stepped structure increases sequentially from the first cutting area to the display area.

5. The display substrate according to claim 4, characterized in that, The groove includes a first groove and a second groove; the first groove is disposed on the fourth insulating layer, the third insulating layer and the second insulating layer, and the first groove exposes the surface of the first insulating layer; the second groove is disposed on the substrate and the first insulating layer, and the second groove exposes the surface of the substrate; The first groove exposes the second groove.

6. The display substrate according to claim 5, characterized in that, The sidewalls of the first groove and the second groove are sloped.

7. The display substrate according to claim 5, characterized in that, The orthographic projection of the first groove on the substrate includes the orthographic projection of the second groove on the substrate.

8. The display substrate according to claim 1, characterized in that, The orthographic projection of the gap between adjacent bonding pins of the flip-chip film onto the substrate includes the orthographic projection of the dam onto the substrate.

9. The display substrate according to claim 1, characterized in that, The orthographic projection of the groove on the substrate includes the orthographic projection of the bonding pins of the flip-chip film on the substrate.

10. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 9.

11. A method for preparing a display substrate, characterized in that, The display substrate includes a display area and a first cutting area, and the method includes: A driving structure layer is formed on the substrate of the display area and the first cutting area, wherein the driving structure layer of the first cutting area includes a composite insulating layer; Intermittent grooves are formed on the composite insulating layer of the first cutting area, the arrangement direction of the intermittent grooves intersects the direction from the first cutting area to the display area, and the grooves expose the surface of the substrate; The intermittent grooves are arranged along the extension direction of the second cutting path located in the first cutting area; The composite insulation layer of the first cutting area includes a first insulation layer, a second insulation layer, a third insulation layer and a fourth insulation layer stacked sequentially on the substrate; The adjacent grooves form a barrier; when bonding the display substrate and the flip-chip film, the orthographic projection of the gap between adjacent bonding pins of the flip-chip film on the substrate at least partially overlaps with the orthographic projection of the barrier on the substrate. The dam is configured to prevent residual metal at the edge of the fourth insulating layer from short-circuiting adjacent bonding pins of the flip-chip film.

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