A Differential Fault Analysis Method Based on Formal Verification

Abstract

The present invention discloses a differential fault analysis method based on formal verification, which first establishes a cryptographic algorithm fault effect propagation model; then performs a fault effect propagation model simulation test; then performs fault effect feature attribute extraction; then performs a fault injection attack; finally, based on the attack analysis of formal verification, a formal verification tool is used to screen key information that meets the attribute based on the attribute constraint, and the information is the encryption key. The present invention is based on a formal verification method, and a small amount of fault information can be used to screen out encryption keys that meet the attribute constraint during analysis, and the exact location of the fault can also be analyzed, thereby realizing the automation of fault attack analysis.

Description

Technical Field

[0001] The present invention belongs to the technical field of cryptography, and in particular relates to a differential fault analysis method based on formal verification. Background Art

[0002] Fault injection attack is an effective active side channel attack method. Fault injection attack changes the working conditions of the cryptographic system, or causes errors in the execution of the cryptographic algorithm through external interference, and recovers the sensitive parameters of the cryptographic system by differential analysis of correct and incorrect encryption results or statistical analysis of incorrect encryption results. Fault injection attack is generally divided into two stages: fault injection and fault analysis. In the fault injection stage, the attacker needs to interfere with the operation of the cryptographic system to make the encryption result of the cryptographic system wrong. Common fault injection methods include voltage, electromagnetic, laser, temperature and clock glitches. The fault analysis stage refers to the attacker comparing and analyzing the obtained faulty ciphertext with the correct ciphertext, or performing statistical analysis on the incorrect ciphertext, so as to infer the sensitive parameters of the cryptographic system.

[0003] Common fault analysis methods include differential fault analysis (DFA), which uses the relationship between the correct ciphertext output when the cryptographic system works normally and the incorrect ciphertext output when a fault occurs to crack the key. DFA is the most representative fault analysis method, but the analysis process requires complex mathematical derivation and a deep understanding of the encryption transformation of the cryptographic algorithm. Statistical fault analysis (SFA) is to recover the key based on statistical analysis of the erroneous ciphertext data. Ineffective fault analysis (IFA) refers to faults that have no effect on the encryption result, and can also be used to obtain sensitive information of the encryption system. Persistent fault analysis (PFA) injects persistent faults during the execution of the cryptographic algorithm and recovers the key by counting the frequency of ciphertext data.

[0004] It can be seen that the existing fault analysis methods require complex mathematical analysis to crack the key. This has high requirements on the location of the fault and the type of injected fault. There are few fault injection attack models or fault attack analysis that use formal methods to solve the key. Summary of the invention

[0005] In order to overcome the shortcomings of the prior art, the present invention provides a differential fault analysis method based on formal verification, firstly, a cryptographic algorithm fault effect propagation model is established; then a fault effect propagation model simulation test is performed; next, fault effect characteristic attribute extraction is performed; then a fault injection attack is performed; finally, attack analysis based on formal verification is performed and then based on attribute constraints, a formal verification tool is used to screen key information that meets the attributes, and this information is the encryption key. The present invention is based on a formal verification method, and a small amount of fault information can be used during analysis to screen out encryption keys that meet attribute constraints, and the exact location of the fault can also be analyzed, thereby realizing the automation of fault attack analysis.

[0006] The technical solution adopted by the present invention to solve the technical problem includes the following steps:

[0007] Step 1: Establish a cryptographic algorithm failure effect propagation model;

[0008] The fault attribute label is added to the signal of the cryptographic algorithm IP core through the cryptographic algorithm fault effect propagation model: when the signal fails, the corresponding attribute label is 1, otherwise the attribute label is 0;

[0009] Step 2: Fault effect propagation model simulation test;

[0010] The cryptographic algorithm fault effect propagation model established in step 1 is simulated with different incentives to observe the distribution characteristics of fault effect propagation after faults are injected at different positions of the encryption transformation, and the fault information is obtained according to the value of the attribute label;

[0011] Step 3: Extraction of fault effect characteristic attributes;

[0012] According to the fault information extracted in step 2, analyze the correlation between fault information; use the SAT solver to solve the Boolean expression satisfied by the fault information pair, and extract the expression as the characteristic attribute satisfied by the fault effect; use the formal method to verify whether all fault information pairs satisfy the attribute. If the verification proves that the attribute is universal, it is a true attribute and can be used as an attribute constraint for fault analysis; otherwise, it is a false attribute.

[0013] Step 4: Fault injection attack;

[0014] Conduct fault injection attacks on cryptographic algorithms; after the cryptographic device is operating normally and obtaining the correct ciphertext, the normal operating conditions of the cryptographic device are interfered with to cause the cryptographic device to fail and obtain the corresponding incorrect ciphertext;

[0015] Step 5: Attack analysis based on formal verification;

[0016] The fault information difference is extracted according to the correct and incorrect ciphertexts obtained in step 4, and then the key information that meets the attributes is screened using formal verification tools based on the attribute constraints. This information is the encryption key.

[0017] Preferably, the cryptographic algorithm fault effect propagation model established in step 1 is input in the form of register transfer level code or gate level netlist of the cryptographic algorithm to obtain the corresponding fault effect model.

[0018] Preferably, when performing the fault effect propagation model simulation test in step 2, the simulation tool used is ModelSim or GTKWave.

[0019] Preferably, when extracting fault effect characteristic attributes in step 3, the SAT logic simplification function in the Yosys tool is used to perform extraction verification.

[0020] Preferably, in step 4, during the fault injection attack, a voltage fault injection device is used to interfere with the normal operation of the device.

[0021] Preferably, the attack analysis based on formal verification in step 5 is to perform fault analysis and crack the key through the formal verification tool of Yosys.

[0022] The beneficial effects of the present invention are as follows:

[0023] Compared with the existing fault injection analysis technology, the present invention proposes a fault analysis method based on formal verification, which can automatically establish fault propagation models for different cryptographic algorithms without complex formula derivation and mathematical operations, and has no strict requirements on the location of fault injection. It can judge the flow of fault information according to the setting of the attribute label of the fault effect propagation model and then extract the fault effect attribute characteristics for fault injection attack analysis. Based on the formal verification method, a small amount of fault information can be used to screen out encryption keys that meet the attribute constraints during analysis, and the exact location of the fault can also be analyzed to realize the automation of fault attack analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a block diagram of the overall solution of the present invention.

[0025] Figure 2 1 is a structural diagram of a two-input NAND gate fault effect propagation model according to an embodiment of the present invention, wherein (a) is a two-input NAND gate, and (b) is a two-input NAND gate fault effect propagation model.

[0026] Figure 3 It is a flow chart of obtaining fault information by simulating and testing the fault effect propagation model of the present invention.

[0027] Figure 4 It is a flow chart of fault effect characteristic attribute extraction of the present invention.

[0028] Figure 5 It is a flow chart of fault injection analysis of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0030] Existing fault analysis methods often require complex mathematical analysis, require knowing the exact location where the fault occurs, and usually need to inject a specific type of fault at a specific location, which has great limitations. The purpose of the present invention is to provide a differential fault analysis method based on formal verification, establish a cryptographic algorithm fault effect propagation model, analyze the fault effect propagation behavior of the cryptographic algorithm, extract attribute constraints from the fault effect propagation characteristics, and recover the key by checking whether the correct and incorrect ciphertext pairs meet the extracted attribute constraints. The method proposed by the present invention can realize automated attack analysis without knowing the location of fault injection, and filter out key information that meets the attribute constraints.

[0031] The present invention can perform fault injection attack analysis on the implementation of cryptographic algorithms, involving two stages: attribute extraction and fault injection attack analysis. Attribute extraction is to extract the characteristics of the propagation of cryptographic algorithm fault effects. By establishing a cryptographic algorithm fault effect propagation model, attributes are extracted from the behavior of fault effect propagation. It mainly includes two modules: establishment of a cryptographic algorithm fault effect propagation model and extraction of fault effect propagation characteristics. Fault injection attack analysis is actually composed of two parts: fault injection attack and fault injection analysis. Fault injection attack interferes with the normal execution of cryptographic devices to obtain the difference between correct and incorrect ciphertexts, and uses formal verification tools to screen key information that meets the extracted attribute constraints, that is, the encryption key.

[0032] A differential fault analysis method based on formal verification includes the following steps:

[0033] 1. Establish a cryptographic algorithm failure effect propagation model

[0034] Establish a fault effect propagation model for cryptographic algorithms to describe the propagation of fault information. Add fault attribute labels to the signals of the cryptographic algorithm IP core. When a signal fails, the corresponding attribute label is 1, otherwise the attribute label is 0.

[0035] Since the implementation of the cryptographic algorithm IP core is generally mapped to a gate-level netlist or basic logic unit, the cryptographic algorithm fault effect propagation model actually adds attribute labels to each logic unit to identify the flow of fault information. The propagation of fault information must meet the logical constraints of the basic unit. When a fault occurs in the input signal, the impact of the fault on the output signal must be considered. When the input signal attribute label is set to 1, if it has an impact on the output signal, the attribute label of the output signal is 1, otherwise the attribute label is 0. Therefore, the propagation strategy of the fault effect propagation model is that the attribute label corresponding to the input information can be propagated to the attribute label domain corresponding to the output data only when the input data has an impact on the value of the output data. The establishment of the cryptographic algorithm fault effect propagation model is to input the register transfer level code or gate-level netlist of the cryptographic algorithm to obtain the corresponding fault effect model.

[0036] like Figure 2 As shown in the figure, a fault effect propagation model based on a two-input NAND gate is used as an example to demonstrate the behavior flow of fault information in the fault effect propagation model. A and B are the input signals of the AND gate, and O is the output signal. t , b t , o t The fault attribute label of the corresponding signal indicates the flow of fault information. The partial truth table is shown in Table 1. The logical expression of the output signal attribute label of the fault effect propagation model of the two-input NAND gate is o t =Ab t +Ba t +a t b t That is, if and only if the input signals A and B fail and have an impact on the output signal O, the attribute label of the fault information will flow into the label of the output signal, and the output label O t It is only 1.

[0037] Table 1 Partial truth table of the fault effect propagation model of two-input NAND gate

[0038]

[0039] 2. Fault effect propagation model simulation test;

[0040] This step is to simulate the fault effect propagation model to obtain fault information. The fault effect propagation model can be simulated using simulation tools such as ModelSim or GTKWave, and the test data can be generated using random numbers. Figure 3 As shown, different stimuli are given to the cryptographic algorithm fault effect propagation model established in step 1 for simulation, and the distribution characteristics of the fault effect propagation after the fault is injected at different positions of the encryption transformation are observed, and the fault information is obtained according to the value of the attribute label.

[0041] 3. Extraction of fault effect characteristic attributes;

[0042] According to the fault information extracted in step 2, the correlation between the fault information is analyzed, and the fault attribute extraction verification can be performed using the SAT logic simplification function in the Yosys tool. Figure 4 As shown in the figure, the Boolean expression satisfied by the fault information pair is solved by the SAT solver, and the expression can be extracted as the characteristic attribute satisfied by the fault effect. Since the attribute is extracted based on a few fault information pairs and may be accidental, it is necessary to verify the universality of the attribute. Formal methods can be used to verify whether all fault information pairs satisfy the attribute. If the verification shows that the attribute is universal, it is a true attribute and can be used as an attribute constraint for fault analysis. Otherwise, it is a false attribute.

[0043] 4. Fault injection attacks

[0044] Steps 1 to 3 are to complete the extraction of fault effect propagation feature attributes. Step 4 begins the fault injection attack on the cryptographic algorithm. Figure 5 As shown, after the cryptographic device operates normally and obtains the correct ciphertext, the normal operating conditions of the cryptographic device, such as voltage and clock, are interfered with to cause the cryptographic device to fail and obtain the corresponding erroneous ciphertext.

[0045] 5. Attack Analysis Based on Formal Verification

[0046] Extract the fault information difference based on the correct and incorrect ciphertext obtained in step 4, and then use the formal verification tool to screen the key information that meets the attribute based on the attribute constraint. This information is the encryption key. Fault injection attacks can use voltage fault injection devices to interfere with the normal operation of the device. Attack analysis based on formal verification can be performed through Yosys' formal verification tool to crack the key through fault analysis. Specific embodiment:

[0048] The hardware environment used for implementation: Intel i7, Ubuntu 18.0, voltage fault injection equipment. The method proposed in the present invention is implemented using the gcc compilation environment and Yosys formalization tool.

[0049] The present invention is specifically implemented as follows:

[0050] 1. Establish AES fault effect propagation model

[0051] The AES encryption algorithm is implemented with Verilog, and a fault effect propagation model is established by adding attribute tags to the AES encryption algorithm. According to the fault propagation strategy of the present invention, an AES fault effect propagation model is established, and then an incentive file is written to perform model simulation.

[0052] 2. Extract the attribute characteristics of AES fault effect propagation

[0053] The fault information of AES injected faults at different positions is extracted, and the characteristics of the fault information are analyzed. Taking the injection of fault in the first byte of the 9th round of AES encryption byte substitution as an example, there are 4 fault bytes of information after encryption iteration, which are marked as diff_byte1, diff_byte2, diff_byte3, and diff_byte4 in the order of fault bytes. Their satisfied attribute relationship is shown in Table 2, and it has been verified that the attribute is universal. The information of fault bytes diff_byte2 and diff_byte3 is consistent, and the fault bytes diff_byte1 and diff_byte4 are correlated with diff_byte2 and diff_byte3 respectively, satisfying the logical expression in Table 2.

[0054] Table 2 Boolean expressions satisfied by fault information

[0055]

[0056] Similarly, a SAT solver can be used to establish a logical expression for a pair of fault information injected at different locations. After verifying the logical expression, it can be analyzed as a property specific of fault effect propagation.

[0057] 3. Implementing AES fault injection attack

[0058] Inject faults into the AES encryption process to interfere with the normal operation of the device and obtain correct or incorrect ciphertext.

[0059] 4. Attack Analysis Based on Formal Verification

[0060] Based on the obtained correct and incorrect ciphertexts and attribute relationships, formal verification tools combined with attribute constraints are used to crack the encryption key. Experiments have shown that this method only requires two correct and incorrect ciphertext pairs to crack the key, and the specific location of the fault injection can be known.

Claims

1. A differential fault analysis method based on formal verification, characterized in that: The steps include: Step 1: Establish a cryptographic algorithm failure effect propagation model; The fault attribute label is added to the signal of the cryptographic algorithm IP core through the cryptographic algorithm fault effect propagation model: when the signal fails, the corresponding attribute label is 1, otherwise the attribute label is 0; Step 2: Fault effect propagation model simulation test; The cryptographic algorithm fault effect propagation model established in step 1 is simulated with different incentives to observe the distribution characteristics of fault effect propagation after faults are injected at different positions of the encryption transformation, and the fault information is obtained according to the value of the attribute label; Step 3: Extraction of fault effect characteristic attributes; According to the fault information extracted in step 2, analyzing the correlation between the fault information; The Boolean expression satisfied by the fault information pair is solved by the SAT solver, and the expression is extracted as the characteristic attribute satisfied by the fault effect; a formal method is used to verify whether all fault information pairs satisfy the attribute. If the verification proves that the attribute is universal, it is a true attribute and can be used as an attribute constraint for fault analysis; otherwise, it is a false attribute. Step 4: Fault injection attack; Conduct fault injection attacks on cryptographic algorithms; After the cryptographic device is operating normally and obtaining the correct ciphertext, the cryptographic device is disturbed in its normal operating conditions to cause the cryptographic device to fail and obtain the corresponding erroneous ciphertext; Step 5: Attack analysis based on formal verification; The fault information difference is extracted according to the correct and incorrect ciphertexts obtained in step 4, and then the key information that meets the attributes is screened using formal verification tools based on the attribute constraints. This information is the encryption key.

2. The differential fault analysis method based on formal verification according to claim 1, characterized in that: In the step 1, the cryptographic algorithm fault effect propagation model is established by inputting the register transfer level code or gate level netlist of the cryptographic algorithm to obtain the corresponding fault effect model.

3. The differential fault analysis method based on formal verification according to claim 1, characterized in that: When performing the fault effect propagation model simulation test in step 2, the simulation tool used is ModelSim or GTKWave.

4. The differential fault analysis method based on formal verification according to claim 1, characterized in that: When extracting fault effect characteristic attributes in step 3, the SAT logic simplification function in the Yosys tool is used to perform extraction verification.

5. The differential fault analysis method based on formal verification according to claim 1, characterized in that: In step 4, during the fault injection attack, a voltage fault injection device is used to interfere with the normal operation of the device.

6. The differential fault analysis method based on formal verification according to claim 1, characterized in that: The attack analysis based on formal verification in step 5 is to crack the key by performing fault analysis through the formal verification tool of Yosys.

Images