A multi-scroll conservative chaotic system and pseudo-random signal generator

Abstract

This invention discloses a multi-scroll conservative chaotic system and pseudo-random signal generator. Its technical features include the following steps: Step 1: Establishing a multi-scroll conservative chaotic system that satisfies Hamiltonian energy conservation and volume conservation, exhibiting strong ergodicity and pseudo-randomness; Step 2: Conducting NIST testing to verify the ability to generate pseudo-random signals that meet three standard conditions; and Step 3: Verifying the physical feasibility of the system using FPGA technology. This invention provides a multi-scroll conservative chaotic system model and pseudo-random signal generator for application research in image encryption and information encryption.

Description

Technical Field

[0001] The present invention provides a multi-scroll conservative chaotic system and a pseudo-random signal generator, belonging to the field of signal generation. Background Art

[0002] Pseudorandom sequence generation technology integrates multiple disciplines, including mathematics, computer science, electronics, and communications. Since the late 20th century, this technology has been a research hotspot both domestically and internationally. Initially, pseudorandom signals generated from chaotic systems were typically generated using analog circuits and further applied to secure communications research. However, the components of analog circuits are susceptible to factors such as temperature and external magnetic field strength, which can affect the performance of pseudorandom signals. In recent years, the rapid development of electronic technology has made it possible to design pseudorandom signal generators using digital circuits. Field-programmable gate arrays (FPGAs), as an effective implementation method for digital chaotic circuits, can effectively address the problems encountered in analog circuits. Currently, FPGAs are widely used in communications equipment. Designing pseudorandom signal generators based on chaotic systems using FPGAs will provide a new physical model for secure communications. Furthermore, compared to conservative chaotic systems with single-scroll or double-scroll attractors, conservative chaotic systems with multiple-scroll attractors offer advantages such as improved ergodicity and complexity, stronger pseudorandomness, and chaotic sequences similar to uniformly distributed white noise, making them more suitable for secure communications. Therefore, this paper relates to a multi-scroll conservative chaotic system, which provides a pseudo-random signal that meets the NIST test standard, and uses FPGA technology to implement this system and provide a pseudo-random signal generator. Summary of the Invention

[0003] The present invention aims to overcome the shortcomings of the prior art and meet the needs of image encryption and other tasks. It proposes a multi-scroll conservative chaotic system and a pseudo-random signal generator. To solve the above technical problems, the present invention adopts the following technical solutions:

[0004] Step 1: Establish a new type of multi-scroll conservative chaotic system with the following characteristics:

[0005] (1)Satisfy Hamiltonian energy conservation and volume conservation.

[0006] (2) It has multi-scroll dynamics with controllable direction and number of scrolls and complex dynamic behavior.

[0007] Step 2: Perform NIST testing on this multi-scroll conservative chaotic system. The randomness of the sequence to be tested is comprehensively considered from the 15 test results. The three test conditions are met, namely, (1) the P value of each test result should be greater than the significance level α = 0.01, and (2) the pass rate of the test sequence falls within the confidence interval. (3) The distribution of the P value of each test result obeys uniformity. This shows that the pseudo-random sequence generated by this multi-scroll Hamiltonian conservative chaotic system has good randomness and can be used for secure communication.

[0008] Step 3: FPGA has a rich set of computing units and a very fast computing speed. This invention adopts the DSP-builder method provided by Altera Corporation and uses FPGA technology to implement this multi-volume conservative chaotic system, verifying its physical feasibility and generating pseudo-random signals.

[0009] The beneficial effects of the present invention are:

[0010] Based on a conservative chaotic system, this paper proposes a multi-scroll conservative chaotic system and pseudo-random signal generator, enriching the variety of pseudo-random signal generators based on conservative chaotic systems. Using FPGA technology, this paper provides a multi-scroll conservative chaotic system model and pseudo-random signal generator for research applications such as image encryption and information encryption. This provides valuable insights into the application of chaotic systems in secure communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings:

[0012] Figure 1 The numerical analysis results of the system established for the present invention when the parameters are Q1=Q2=0, N1=N2=2π, and the initial value is (π, 1, 1, 1);

[0013] Figure 2 Distribution of P-values ​​for non-overlapping module matching sequences tested by NIST for the system established by the present invention;

[0014] Figure 3 .f(x) module circuit connection diagram of the present invention;

[0015] Figure 4 FIG. 1 is a connection structure diagram of the f(y) module circuit of the present invention;

[0016] Figure 5 A circuit connection diagram of the system established for the present invention;

[0017] Figure 6 FPGA physical experiment results of the system established for this invention. DETAILED DESCRIPTION

[0018] The present invention will be described in detail below with reference to the accompanying drawings.

[0019] Step 1: The present invention establishes the following multi-scroll conservative chaotic system:

[0020]

[0021] Where x, y, z, w are state variables, , N1=2n1π, Q1=-2n2π, N2=2n3π, Q2=-2n4π, n1, n2, n3, n4∈N.

[0022] Take the parameters Q1=Q2=0, N1=N2=2π, initial value (π, 1, 1, 1), according to Figure 1 It can be observed that the system phase diagram is a five-volume conservative chaotic flow at this time.

[0023] Step 2, the pseudo-randomness test method used in the present invention is the most representative and widely recognized NISTSP800-22 standard. This standard uses an ideal random sequence as a reference and tests the deviation degree of the pseudo-random sequence from different angles in terms of statistical characteristics. It includes 15 test indicators, and all 15 test results are expressed as P values. The sequence that can pass the test has good pseudo-random performance. All tests in this experiment take the significance level α=0.01. For 15 groups of test sequences, the confidence interval of the pass rate can be defined as (0.9702, 1.0098). Generally, the test can be passed only when the following three conditions are met:

[0024] (1) The P value for each test result is greater than the significance level α = 0.01. (2) The pass rate of the test sequence falls within the confidence interval (0.9702, 1.0098). (3) The distribution of P values ​​should follow a uniform distribution. During the test process, the specific NIST test parameter settings are shown in Table 1.

[0025] Table 1

[0026]

[0027] The NIST test results are shown in Table 2. From the test data in Table 2, it can be seen that the P values ​​of the 15 tests of system (1) are all greater than the significance level α=0.01, and the percentage of the passing results of the 15 tests of system (1) are all within the confidence interval, so the system meets conditions (1) and (2). The P values ​​of the 15 groups of data should all obey the uniform distribution. The present invention uses non-overlapping module matching as an example for verification. The histogram of the P value distribution is Figure 2 ,It can be observed that the distribution of the P value of non-overlapping module matching is relatively uniform, and there is no interval with obvious distribution gap, that is, condition (3) is met.

[0028] Table 2

[0029]

[0030]

[0031] Step 3: Use FPGA technology to realize this pseudo-random signal generator. When designing the circuit model, the discretization method used is Euler method. First, the system is discretized.

[0032]

[0033] ΔT is the discrete sampling time, and ΔT=0.00001; x(n), y(n), z(n), and w(n) are the iterative sequence of the current time; x(n+1), y(n+1), z(n+1), and w(n+1) represent the iterative sequence of the next cycle.

[0034] A multi-scroll conservative chaotic system and a pseudo-random signal generator circuit are connected therein:

[0035] The circuit model of f(x) is connected as follows: the output of adder A3 is connected to port a of comparator C1 through AltBus1; port b of comparator C1 is connected to constant 6.2832; the output of comparator C1 is connected to port 0 of bus B1; the output of adder A3 is connected to port a of comparator C2 through AltBus1; port b of comparator C2 is connected to constant 0; the output of comparator C2 is connected to port 1 of bus B1; the output of bus B1 is connected to port sel of multiplexer MP7; the output of adder A3 is connected to port a of divider D1 through AltBus1; port b of divider D1 is connected to constant 6.2832; the output q of divider D1 is connected to port a of comparator C3; the output r of divider D1 is connected to port 1 of adder A11 and port 0 of multiplexer MP5 respectively; port b of comparator C3 is connected to port 0 of multiplexer MP5 respectively. Connect the constant 0 to port 2 of adder A11; connect the constant 6.2832 to port 1 of multiplexer Mp5 to port 2 of adder A11; connect the output of multiplexer Mp5 to port 1 of multiplexer Mp5; connect the output of multiplexer Mp5 to port 1 of comparator C4, port 2 of comparator C5, port 1 of adder A12, and port 1 of adder A13 respectively; connect the constant -4.7124 to port 2 of comparator C4; connect the output of comparator C4 to port 0 of bus B2; connect the constant -1.5708 to port 2 of comparator C5; connect the output of comparator C5 to port 1 of bus B2; connect the output of bus B2 to port sel of multiplexer Mp6; connect the constant -3.1416 to port 2 of adder A12; connect the output of adder A12 to port 0 of multiplexer Mp6 via AltBus5; connect the constant 6 to port 2 of adder A13.2832; the output of adder A13 is connected to port 1 of multiplexer Mp6 through AltBus6; the output of adder A3 is connected to port 2 of multiplexer Mp6 through AltBus1; the output of multiplexer Mp6 is connected to port a and port b of multiplier M3, port b of multiplier M4, port b of multiplier M5, port b of multiplier M6, port b of multiplier M7, and port b of multiplier M8 respectively , the b port of multiplier M9 and the b port of multiplier M10; the output of multiplier M3 is connected to the a port of M4; the output of multiplier M4 is connected to the 2 port of adder A16 through the gain G15; the a port of multiplier M5 is connected to the output of multiplier M4; the output of multiplier M5 is connected to the a port of multiplier M6; the output of multiplier M6 is connected to the 3 port of adder A16 through the gain G16; the a port of multiplier M7 is connected to the multiplier The output of M6; the output of multiplier M7 is connected to port a of multiplier M8; the output of multiplier M8 is connected to port 4 of adder A16 through gain G17; the output of multiplier M9 is connected to port a of multiplier M8; the output of multiplier M9 is connected to port a of multiplier M10; the output of multiplier M10 is connected to port 5 of adder A16 through gain G18; the output of adder A16 is connected to port 0 of multiplexer Mp7 The output of adder A3 is connected to port 1 of adder A14 and port 1 of adder A15 via AltBus1. Port 2 of adder A14 is connected to the constant 6.2832. The output of adder A14 is connected to port 1 of multiplexer Mp7. Port 2 of adder A15 is connected to the constant 0. The output of adder A15 is connected to port 2 of multiplexer Mp7. The output of multiplexer Mp7 is the output signal f(x). The connection relationship of the f(x) module is as follows. Figure 3 shown.

[0036] The circuit model of f(y) is connected as follows: the output of adder A4 is connected to port a of comparator C6 via AltBus2; port b of comparator C6 is connected to constant 6.2832; the output of comparator C6 is connected to port 0 of bus B3; the output of adder A4 is connected to port a of comparator C7 via AltBus2; port b of comparator C7 is connected to constant 0; the output of comparator C7 is connected to port 1 of bus B4; the output of bus B3 is connected to port sel of multiplexer Mp10; the output of adder A4 is connected to port a of divider D2 via AltBus2; port b of divider D2 is connected to constant 6.2832; the output q of divider D2 is connected to port a of comparator C8; the output r of divider D2 is connected to port 1 of adder A17 and port 0 of multiplexer Mp8 respectively; port b of comparator C8 is connected to port 1 of adder A17 and port 0 of multiplexer Mp8 respectively. The constant 0 is connected to port 2 of adder A17; the constant 6.2832 is connected to port 1 of multiplexer MP8; the output of multiplexer MP8 is connected to port a of comparator C9, port a of comparator C10, port 1 of adder A18, and port 1 of adder A19 respectively; the constant -4.7124 is connected to port b of comparator C9; the output of comparator C9 is connected to port 0 of bus B4; the constant -1.5708 is connected to port b of comparator C10; the output of comparator C10 is connected to port 1 of bus B4; the output of bus B4 is connected to port sel of multiplexer MP9; the constant -3.1416 is connected to port 2 of adder A18; the output of adder A18 is connected to port 0 of multiplexer MP9 via AltBus 7; the constant 6.2832; the output of adder A19 is connected to port 1 of multiplexer Mp9 through AltBus8; the output of adder A4 is connected to port 2 of multiplexer Mp9 through AltBus2; the output of multiplexer Mp9 is respectively connected to port a and port b of multiplier M11, port b of multiplier M12, port b of multiplier M13, port b of multiplier M14, port b of multiplier M15, and port b of multiplier M16 , the b port of the multiplier M17 and the b port of the multiplier M18; the output of the multiplier M11 is connected to the a port of M12; the output of the multiplier M12 is connected to the 2 port of the adder A22 through the gain G19; the a port of the multiplier M13 is connected to the output of the multiplier M12; the output of the multiplier M13 is connected to the a port of the multiplier M14; the output of the multiplier M14 is connected to the 3 port of the adder A22 through the gain G20; the a port of the multiplier M15 is connected to the The output of multiplier M14; the output of multiplier M15 is connected to port a of multiplier M16; the output of multiplier M16 is connected to port 4 of adder A22 through gain G21; the output of multiplier M17 is connected to port a of multiplier M16; the output of multiplier M17 is connected to port a of multiplier M18; the output of multiplier M18 is connected to port 5 of adder A22 through gain G22; the output of adder A22 is connected to port 4 of multiplexer Mp7 The output of adder A4 is connected to port 0 of adder A20 and port 1 of adder A21 via AltBus2. Port 2 of adder A20 is connected to the constant 6.2832. The output of adder A20 is connected to port 1 of multiplexer Mp10. Port 2 of adder A21 is connected to the constant 0. The output of adder A21 is connected to port 2 of multiplexer Mp10. The output of multiplexer Mp10 is the output signal f(y). The connection relationship of the f(y) module is as follows. Figure 4 shown.

[0037] The circuit model connection of the first equation is: the a port of multiplier M1 is connected to the output of AltBus4; the b port of multiplier M1 is connected to the output of multiplexer Mp10; the output of multiplier M1 is connected to the 1 port of adder A1 through the gain G1; the output of multiplexer Mp10 is connected to the 2 port of adder A1 through the gain G2; the output of adder A1 is connected to the 1 port of adder A3 through the gain G7; the sel port of multiplexer Mp1 is connected to the s el port; port 0 of multiplexer Mp1 is connected to the output of AltBus1; port 1 of multiplexer Mp1 is connected to the constant 3.1416 to set the system initial value; the output of multiplexer Mp1 is connected to port 2 of adder A3; the output of adder A3 is connected to port 1 of adder A7 through AltBus1; port 2 of adder A7 is connected to the constant 4 to shift the image to the first quadrant; the output of adder A7 is output to Output1 through gain G11.

[0038] The circuit model connection of the second equation is: the output end of multiplexer Mp7 is connected to port 1 of adder A4 through gain G3 and gain G8; the sel port of multiplexer Mp2 is connected to the sel port of multiplexer Mp3; the 0 port of multiplexer Mp2 is connected to the output end of AltBus2; the 1 port of multiplexer Mp1 is connected to constant 1 to set the initial value of the system; the output end of multiplexer Mp2 is connected to port 2 of adder A4; the output end of adder A4 is connected to port 1 of adder A8 through AltBus2; the 2 port of adder A8 is connected to constant 4 to shift the image to the first quadrant; the output end of adder A8 is output to Output2 through gain G12.

[0039] The circuit model connection of the third equation is: the output of adder A6 is connected to port 1 of adder A5 through AltBus4, gain G4, and gain G9; the sel port of multiplexer Mp3 is connected to the sel port of multiplexer Mp4; port 0 of multiplexer Mp3 is connected to the output of AltBus3; port 1 of multiplexer Mp1 is connected to constant 1 to set the system initial value; the output of multiplexer Mp3 is connected to port 2 of adder A5; the output of adder A5 is connected to port 1 of adder A9 through AltBus3; port 2 of adder A9 is connected to constant 4 to shift the image to the first quadrant; the output of adder A9 is output to Output3 through gain G13.

[0040] The circuit model connection of the fourth equation is: the a port of multiplier M2 is connected to the output of multiplexer Mp7; the b port of multiplier M2 is connected to the output of multiplexer Mp10; the output of multiplier M2 is connected to the 1 port of adder A2 through gain G5; the output of adder A5 is connected to the b port of adder A2 through AltBus3 and gain G6; the output of adder A2 is connected to the 1 port of adder A6 through gain G10; the sel port of multiplexer Mp4 is connected to the multiplexer The sel port of Mp1; the 0 port of multiplexer Mp4 is connected to the output of AltBus4; the 1 port of multiplexer Mp4 is connected to constant 1 to set the system initial value; the output of multiplexer Mp4 is connected to the 2 port of adder A6; the output of adder A6 is connected to the 1 port of adder A10 through AltBus4; the 2 port of adder A10 is connected to constant 4 to shift the image to the first quadrant; the output of adder A10 is output to Output4 through gain G14. The system circuit connection relationship is as follows: Figure 5 shown.

[0041] Run the designed circuit and observe it through the oscilloscope Figure 6 The experimental results shown are Figure 1 The numerical analysis results are consistent with .

[0042] In summary, this paper establishes a multi-scroll conservative chaotic system with strong pseudorandomness and ergodicity, meeting NIST testing standards. Furthermore, an FPGA circuit for this multi-scroll conservative chaotic system is developed, providing a multi-scroll conservative chaotic system model and pseudorandom signal generator for secure communication research.

Claims

1. A multi-scroll conservative chaotic system and pseudo-random signal generator, characterized in that The steps include: Step 1: Establish the following multi-scroll conservative chaotic system: Where x, y, z, w are state variables, , N1=2n1π, Q1=-2n2π, N2=2n3π, Q2=-2n4π, n1, n2, n3, n4∈N; changing the parameters n1, n2, n3, n4 can control the number of multiple volumes and the direction of expansion along the x-axis and y-axis; Step 2: Using the multi-scroll conservative chaotic system as the test system, based on the NIST test standard, we obtain three conditions that meet the NIST standard: (1) the P value of each test result is greater than the significance level α = 0.01; (2) there are 15 test sequences, and the pass rate of the test sequence falls within the confidence interval (0.9702, 1.0098); (3) the distribution of the P value should obey the uniform distribution; Step 3: Based on the above multi-scroll conservative chaotic system, the multi-scroll conservative chaotic system is implemented based on FPGA technology, and a pseudo-random signal generator is provided.

2. A multi-scroll conservative chaotic system and pseudo-random signal generator according to claim 1, characterized in that: The system described in step 1, when using a sinusoidal piecewise function, can obtain a controllable multi-scroll conservative chaotic system that expands in both directions of the x and y axes. When the parameters Q1=Q2=0, N1=N2=2π, and the initial value are (π, 1, 1, 1), a five-scroll conservative chaotic system can be observed.

3. The multi-scroll conservative chaotic system and pseudo-random signal generator according to claim 1, characterized in that: Step 2 uses the NIST SP800-22 standard.

4. The multi-scroll conservative chaotic system and pseudo-random signal generator according to claim 1, characterized in that: In step 3, the system linearization adopts the Euler method, and the FPGA implementation adopts the DSP-builder method.

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