A pixel driving circuit, method and display device

Abstract

Embodiments of the present application provide a pixel driving circuit, method and display device. The circuit includes: a reset module, a driving module, a high-frequency data writing module, and a low-frequency data writing module; the reset module is configured to provide a first initial voltage signal input from a first initial signal terminal to the driving module when receiving a reset signal; the high-frequency data writing module is configured to provide a data voltage signal at a data signal terminal to the driving module at a first frequency in a high refresh rate driving mode; the low-frequency data writing module is configured to provide the data voltage signal at the data signal terminal to the driving module at a second frequency in a low refresh rate driving mode, where the first frequency is greater than the second frequency; the driving module is configured to drive a light-emitting device in response to the input voltage signal. The switching between the high refresh rate driving mode and the low refresh rate driving mode is achieved.

Description

Technical Field

[0001] This application relates to the technical field of OLED driving circuits, and particularly to a pixel driving circuit, method, and display device. Background Art

[0002] At present, OLED (Organic Light Emitting Diode) displays have entered the era of low-frequency display energy saving. The market has high requirements for the refresh rate of dynamic videos and game screens. For static screens or scenarios with low requirements for the refresh rate, it is often necessary to switch to a low refresh rate driving mode to achieve the purpose of saving energy. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a pixel driving circuit, method, and display device to achieve the switching between a high refresh rate driving mode and a low refresh rate driving mode. The specific technical solutions are as follows:

[0004] In a first aspect, the embodiments of this application provide a pixel driving circuit, which includes:

[0005] A reset module, a driving module, a high-frequency data writing module, and a low-frequency data writing module. The reset module, the high-frequency data writing module, and the low-frequency data writing module are respectively connected to the driving module, and the driving module is connected to a light-emitting device;

[0006] The reset module is configured to provide a first initial voltage signal input from a first initial signal terminal to the driving module when receiving a reset signal;

[0007] The high-frequency data writing module is configured to provide the data voltage signal at the data signal terminal to the driving module at a first frequency in the high refresh rate driving mode;

[0008] The low-frequency data writing module is configured to provide the data voltage signal at the data signal terminal to the driving module at a second frequency in the low refresh rate driving mode, where the first frequency is greater than the second frequency;

[0009] The driving module is configured to drive the light-emitting device in response to the input voltage signal.

[0010] In a possible implementation manner, the reset module includes: a first capacitor, a first transistor, and a second transistor;

[0011] A first end of the first capacitor is connected to the positive power supply, and a second end of the first capacitor is respectively connected to a second end of the first transistor, a first end of the second transistor, and the driving module;

[0012] The gate of the first transistor is connected to the reset signal terminal, and the first end of the first transistor is connected to the first initial signal terminal, where the reset signal is input to the reset signal terminal;

[0013] The gate of the second transistor is connected to the first scan line, and the second end of the second transistor is connected to the driving module.

[0014] In a possible implementation manner, the reset module includes: a first capacitor, a first transistor, and a second transistor;

[0015] The first end of the first capacitor is connected to the positive power supply terminal, and the second end of the first capacitor is respectively connected to the second end of the first transistor, the first end of the second transistor, and the driving module;

[0016] The gate of the first transistor is connected to the reset signal terminal, and the first end of the first transistor is connected to the first initial signal terminal, where the reset signal is input to the reset signal terminal;

[0017] The gate of the second transistor is connected to the third scan line, and the second end of the second transistor is connected to the driving module.

[0018] In a possible implementation manner, the driving module includes: a fifth transistor, a third transistor, and a sixth transistor;

[0019] The gate of the fifth transistor is connected to the light emission control terminal, the first end of the fifth transistor is connected to the positive power supply terminal, and the second end of the fifth transistor is respectively connected to the second end of the third transistor, the high-frequency data writing module, and the low-frequency data writing module;

[0020] The gate of the third transistor is connected to the second end of the first capacitor, and the first end of the third transistor is respectively connected to the second end of the second transistor and the first end of the sixth transistor;

[0021] The gate of the sixth transistor is connected to the light emission control terminal, the second end of the sixth transistor is connected to the anode of the light-emitting device, and the cathode of the light-emitting device is connected to the negative power supply terminal.

[0022] In a possible implementation manner, the high-frequency data writing module includes: a fourth transistor;

[0023] The gate of the fourth transistor is connected to the first scan line, the first end of the fourth transistor is connected to the second end of the fifth transistor, and the second end of the fourth transistor is connected to the data signal terminal.

[0024] In a possible implementation, the low-frequency data writing module includes: an eighth transistor, a ninth transistor, and a second capacitor;

[0025] The gate of the eighth transistor is connected to the second scan line, the first end of the eighth transistor is connected to the second end of the fifth transistor, and the second end of the eighth transistor is respectively connected to the first end of the ninth transistor and the first end of the second capacitor;

[0026] The gate of the ninth transistor is connected to the first scan line, and the second end of the ninth transistor is connected to the data signal terminal;

[0027] The second end of the second capacitor is connected to the open-source signal terminal.

[0028] In a possible implementation, the circuit further includes: an anode potential control module;

[0029] The anode potential control module is configured to provide a second initial voltage signal of a second initial signal terminal to the anode of the light-emitting device under the control of the second scan line.

[0030] In a possible implementation, the anode potential control module includes: a seventh transistor;

[0031] The gate of the seventh transistor is connected to the second scan line, the first end of the seventh transistor is connected to the anode of the light-emitting device, and the second end of the seventh transistor is connected to the second initial signal terminal.

[0032] An embodiment of the present application provides a pixel driving method, which is applied to any one of the above pixel driving circuits. The method includes:

[0033] In the high refresh rate driving mode, controlling the high-frequency data writing module to provide the data voltage signal of the data signal terminal to the driving module at a first frequency;

[0034] In the low refresh rate driving mode, controlling the low-frequency data writing module to provide the data voltage signal of the data signal terminal to the driving module at a second frequency, where the first frequency is greater than the second frequency.

[0035] In a possible implementation, applied to the above pixel driving circuit, in the low refresh rate driving mode, in each refresh process:

[0036] When refreshing a frame, the first scan line receives a first level signal, and the second scan line receives a first level signal, so that the data voltage signal is written into the driving module and the low-frequency data writing module;

[0037] When holding a frame, a first scan line receives a second-level signal and a second scan line receives a first-level signal, so that the low-frequency data writing module provides a data voltage signal for the driving module; wherein, the first-level signal and the second-level signal are signals with opposite high and low levels.

[0038] In a possible implementation manner, the method includes:

[0039] When refreshing a frame, in a state where a second-level signal is received at a light-emitting control terminal, a first-level signal is received at a reset signal terminal, a first scan line receives the first-level signal, and a second scan line receives the first-level signal;

[0040] When holding a frame, in a state where a second-level signal is received at a light-emitting control terminal, a second-level signal is received at a reset signal terminal, a first scan line receives the second-level signal, and a second scan line receives the first-level signal.

[0041] In a possible implementation manner, the method includes:

[0042] When refreshing a frame, in a state where a second-level signal is received at a light-emitting control terminal, a first-level signal is received at a reset signal terminal, a first scan line receives the first-level signal, a second scan line receives the first-level signal, and a third scan line receives the first-level signal;

[0043] When holding a frame, in a state where a second-level signal is received at a light-emitting control terminal, a second-level signal is received at a reset signal terminal, a first scan line receives the second-level signal, a second scan line receives the first-level signal, and a third scan line receives the second-level signal.

[0044] An embodiment of the present application provides a display device, including the pixel driving circuit according to any one of the first aspects.

[0045] Advantages of the embodiment of the present application:

[0046] A pixel driving circuit, method and display device provided by an embodiment of the present application. The circuit includes a reset module, a driving module, a high-frequency data writing module, and a low-frequency data writing module. The reset module, the high-frequency data writing module, and the low-frequency data writing module are respectively connected to the driving module, and the driving module is connected to a light-emitting device. The reset module is configured to provide a first initial voltage signal input from a first initial signal terminal to the driving module when receiving a reset signal. The high-frequency data writing module is configured to provide a data voltage signal at a data signal terminal to the driving module at a first frequency in a high refresh rate driving mode. The low-frequency data writing module is configured to provide a data voltage signal at the data signal terminal to the driving module at a second frequency in a low refresh rate driving mode, where the first frequency is greater than the second frequency. The driving module is configured to drive the light-emitting device in response to the input voltage signal. Since the present application adds a low-frequency data writing module on the basis of the high-frequency data writing module, the data voltage signal at the data signal terminal is provided to the driving module at different frequencies in different driving modes, realizing the switching between the high refresh rate driving mode and the low refresh rate driving mode.

[0047] Of course, implementing any product or method of the present application does not necessarily require achieving all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments according to these drawings.

[0049] Figure 1 It is a pixel driving circuit diagram in the related art;

[0050] Figure 2 It is a first schematic diagram of the pixel driving circuit according to an embodiment of the present application;

[0051] Figure 3 It is a schematic diagram of a reset module in the pixel driving circuit according to an embodiment of the present application;

[0052] Figure 4 It is a schematic diagram of a driving module in the pixel driving circuit according to an embodiment of the present application;

[0053] Figure 5 It is a schematic diagram of a high-frequency data writing module in the pixel driving circuit according to an embodiment of the present application;

[0054] Figure 6It is a schematic diagram of a low-frequency data writing module in the pixel driving circuit according to an embodiment of the present application;

[0055] Figure 7 It is a schematic diagram of an anode potential control module in the pixel driving circuit according to an embodiment of the present application;

[0056] Figure 8 It is the second schematic diagram of the pixel driving circuit according to an embodiment of the present application;

[0057] Figure 9 It is the third schematic diagram of the pixel driving circuit according to an embodiment of the present application;

[0058] Figure 10 It is a schematic diagram of a pixel driving method according to an embodiment of the present application;

[0059] Figure 11 It is the first timing diagram of the pixel driving method according to an embodiment of the present application;

[0060] Figure 12 It is the second timing diagram of the pixel driving method according to an embodiment of the present application. Detailed implementation manners

[0061] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0062] In the related art, the pixel driving circuit of the OLED display screen usually adopts a 7T1C structure. The 7T1C structure is composed of 7 TFTs (Thin Film Transistors) and 1 capacitor. Refer to Figure 1 , in the high refresh rate driving mode, the refresh rates of the scan (scanning line) and EM (emission control terminal) signals are the same. When the EM signal is turned on in each frame, the voltage at point N2 is reset to the DATA voltage; in the low refresh rate driving mode, when the scan is not refreshed, the voltage at point N2 is the same as VDD. Therefore, there is a deviation in the voltage at point N2 in the high refresh rate driving mode and the low refresh rate driving mode. Since the voltage at point N3 is the same as that at point N2, there is also a deviation.

[0063] When switching between the high refresh rate driving mode and the low refresh rate driving mode, the difference in the refresh rate is large, which makes it extremely difficult to control the voltage consistency of point N1 and the voltages of points N2 / N3. For the control of the voltage at point N1, it is mainly required that T10 and T11 have a high voltage retention rate. Currently, the commonly used method in the industry is to use Oxide TFT (oxide thin film transistor), which can greatly reduce the leakage current and improve the voltage retention rate of point N1. For the voltage reset of points N2 / N3, in the high refresh rate driving mode, the voltages of points N2 / N3 are reset to the DATA voltage, and in the low refresh rate driving mode, the voltages of points N2 / N3 are reset to the VDD voltage. Therefore, there is a deviation in the voltages of points N2 / N3 in the high refresh rate driving mode and the low refresh rate driving mode, resulting in a deviation in the brightness of the display screen. When switching between the high refresh rate driving mode and the low refresh rate driving mode, the screen flickers, bringing a poor customer experience.

[0064] To achieve the switching between the high refresh rate driving mode and the low refresh rate driving mode, an embodiment of the present application provides a pixel driving circuit. Refer to Figure 2 , the circuit includes:

[0065] A reset module 11, a driving module 12, a high-frequency data writing module 13, and a low-frequency data writing module 14. The reset module 11, the high-frequency data writing module 13, and the low-frequency data writing module 14 are respectively connected to the driving module 12, and the driving module 12 is connected to a light-emitting device;

[0066] The reset module 11 is configured to provide a first initial voltage signal input from a first initial signal terminal to the driving module when receiving a reset signal;

[0067] The high-frequency data writing module 13 is configured to provide a data voltage signal at a data signal terminal to the driving module at a first frequency in the high refresh rate driving mode;

[0068] The low-frequency data writing module 14 is configured to provide a data voltage signal at a data signal terminal to the driving module at a second frequency in the low refresh rate driving mode, where the first frequency is greater than the second frequency;

[0069] The driving module 12 is configured to drive the light-emitting device in response to an input voltage signal.

[0070] The high refresh rate driving mode and the low refresh rate driving mode can be achieved by changing the refresh rate of the row driving signal of the array substrate, and the refresh rate of the light-emitting control signal can remain unchanged at the high refresh rate.

[0071] Both the first frequency and the second frequency can be set according to actual display requirements. For example, the first frequency can be 144Hz, 120Hz, 60Hz, etc., and the second frequency can be 10Hz, 5Hz, 1Hz, etc. The first frequency corresponds to a high refresh frequency, and the second frequency corresponds to a low refresh frequency, and the first frequency is greater than the second frequency. In one example, in the high refresh frequency driving mode, the high-frequency data writing module provides the data voltage signal DATA at the data signal terminal to the driving module at a frequency of 120Hz. In one example, in the low refresh frequency driving mode, the low-frequency data writing module provides the data voltage signal DATA at the data signal terminal to the driving module at a frequency of 1Hz.

[0072] In the embodiment of the present application, by adding a low-frequency data writing module on the basis of the high-frequency data writing module, the switching between the high refresh frequency driving mode and the low refresh frequency driving mode is realized.

[0073] In a possible implementation manner, referring to Figure 3 , the reset module 11 includes: a first capacitor C1, a first transistor T1, and a second transistor T2;

[0074] The first end of the first capacitor C1 is connected to the positive power supply VDD, and the second end of the first capacitor C1 is respectively connected to the second end of the first transistor T1, the first end of the second transistor T2, and the driving module 12;

[0075] The gate of the first transistor T1 is connected to the reset signal terminal, and the first end of the first transistor T1 is connected to the first initial signal terminal, where the reset signal Reset is accessed to the reset signal terminal;

[0076] The gate of the second transistor is connected to the first scan line scan1, and the second end of the second transistor T2 is connected to the driving module 12.

[0077] The first initial voltage signal Vinit 1 is accessed to the first initial signal terminal.

[0078] For any one transistor, the first end of the transistor is the source or the drain, and the second end of the transistor is the drain or the source corresponding to the first end. In one example, each transistor can be a TFT (Thin Film Transistor), and specifically, an N-type TFT can be selected according to the actual situation, or a P-type TFT can also be selected. In one example, each transistor in the pixel driving circuit of the present application can be a MOS transistor, and the MOS transistor can be an N-type MOS transistor or a P-type MOS transistor, and specifically, it can be selected according to the actual situation.

[0079] In an embodiment of the present application, when the reset module receives a reset signal, it provides the first initial voltage signal input from the first initial signal terminal to the driving module.

[0080] In a possible implementation manner, referring to Figure 4 , the driving module 12 includes: a fifth transistor T5, a third transistor T3, and a sixth transistor T6;

[0081] The gate of the fifth transistor T5 is connected to the light emission control terminal EM, the first end of the fifth transistor T5 is connected to the positive power supply VDD, and the second end of the fifth transistor T5 is respectively connected to the second end of the third transistor T3, the high-frequency data writing module 13, and the low-frequency data writing module 14;

[0082] The gate of the third transistor T3 is connected to the second end of the first capacitor C1, and the first end of the third transistor T3 is respectively connected to the second end of the second transistor T2 and the first end of the sixth transistor T6;

[0083] The gate of the sixth transistor T6 is connected to the light emission control terminal EM, the second end of the sixth transistor T6 is connected to the anode of the light emitting device EL, and the cathode of the light emitting device EL is connected to the negative power supply VSS.

[0084] For any one transistor, the first end of the transistor is the source or the drain, and the second end of the transistor is the drain or the source corresponding to the first end. In one example, each transistor can be a TFT (Thin Film Transistor), and specifically, an N-type TFT can be selected according to the actual situation, or a P-type TFT can also be selected. In one example, for each transistor in the pixel driving circuit of the present application, it can be a MOS transistor, and the MOS transistor can be an N-type MOS transistor or a P-type MOS transistor, and can be specifically selected according to the actual situation.

[0085] In an embodiment of the present application, the driving module drives the light emitting device to emit light in response to the input voltage signal.

[0086] In a possible implementation manner, referring to Figure 5 , the high-frequency data writing module 13 includes: a fourth transistor T4;

[0087] The gate of the fourth transistor T4 is connected to the first scan line scan1, the first end of the fourth transistor T4 is connected to the second end of the fifth transistor T5, and the second end of the fourth transistor T4 is connected to the data signal terminal.

[0088] The data signal terminal accesses the data voltage signal DATA.

[0089] In one example, in the high refresh rate driving mode, the refresh rate of the first scan line scan1 is 120 Hz, and the high-frequency data writing module provides the data voltage signal DATA at the data signal terminal to the driving module at a frequency of 120 Hz.

[0090] For any transistor, the first end of the transistor is the source or the drain, and the second end of the transistor is the drain or the source corresponding to the first end. In one example, each transistor can be a TFT (Thin Film Transistor), and specifically, an N-type TFT can be selected according to the actual situation, or a P-type TFT can also be selected. In one example, for each transistor in the pixel driving circuit of the present application, it can be a MOS transistor. The MOS transistor can be an N-type MOS transistor or a P-type MOS transistor, and specifically, it can be selected according to the actual situation.

[0091] In the embodiment of the present application, in the high refresh rate driving mode, the first scan line scan1 turns on the fourth transistor T4 and provides the data voltage signal at the data signal terminal to the driving module at a first frequency.

[0092] In a possible implementation manner, referring to Figure 6 , the low-frequency data writing module 14 includes: an eighth transistor T8, a ninth transistor T9, and a second capacitor C2;

[0093] The gate of the eighth transistor T8 is connected to the second scan line scan2. The first end of the eighth transistor T8 is connected to the second end of the fifth transistor T5. The second end of the eighth transistor T8 is respectively connected to the first end of the ninth transistor T9 and the first end of the second capacitor C2;

[0094] The gate of the ninth transistor T9 is connected to the first scan line scan1, and the second end of the ninth transistor T9 is connected to the data signal terminal;

[0095] The second end of the second capacitor C2 is connected to the open-source signal terminal.

[0096] The data voltage signal DATA is accessed at the data signal terminal. The open-source signal terminal is VDD or VSS, and the user can select the voltage signal to be connected according to actual needs.

[0097] In one example, in the low refresh rate driving mode, the refresh rate of the first scan line scan1 is 1 Hz, and the low-frequency data writing module provides the data voltage signal DATA at the data signal terminal to the driving module at a frequency of 1 Hz.

[0098] The low-frequency data writing module is connected in parallel with the high-frequency data writing module, and the low-frequency data writing module includes an eighth transistor T8, a ninth transistor T9, and a second capacitor C2. In the low refresh frequency driving mode, the working process of the low-frequency data writing module can be divided into a refresh frame and a hold frame according to different control processes of scan1 and scan2. The specific working process is as follows: In the refresh frame, by controlling scan1, the ninth transistor T9 is turned on, and the data voltage signal DATA is written to the N2 / N3 point. At the same time, the data voltage signal DATA charges the second capacitor C2 so that the second capacitor C2 is charged to the DATA voltage and stores this voltage; In the hold frame, by controlling scan1, the ninth transistor T9 is turned off, and the data voltage signal DATA is not written to the N2 / N3 point. Before the emission control terminal EM is turned on, by controlling scan2, the eighth transistor T8 is turned on. At this time, the voltage stored in C2 charges the N2 / N3 point. Before EM is turned on, the voltage of the N2 / N3 point is charged to DATA, so that the voltage of the N2 / N3 point is the same in the refresh frame and the hold frame.

[0099] In one example, each transistor can be a TFT (Thin Film Transistor), and specifically, an N-type TFT or a P-type TFT can be selected according to the actual situation. In one example, for any transistor in the pixel driving circuit of the present application, the transistor can be an N-type MOS transistor or a P-type MOS transistor, and can be specifically selected according to the actual situation; the first end of the MOS transistor is the source or the drain, and the second end of the MOS transistor is the drain or the source corresponding to the first end.

[0100] In the 7T1C structure adopted in the related technology, in the low refresh frequency driving mode, the porch area (blanking area) needs to refresh the N2 point. The voltage of the N2 point is DATA in the refresh frame and VDD in the hold frame. Since the gray level corresponding to the voltage of the N2 point cannot be determined, all gray levels cannot be taken into account. However, in the present application, by adding a low-frequency data writing module and storing the DATA voltage through the second capacitor C2, the voltage of the N2 / N3 point is the same in the refresh frame and the hold frame, and all gray levels can be taken into account.

[0101] In addition, by improving the related technology, the present application adds a low-frequency data writing module, so that the voltage of the N2 / N3 point is the same in the refresh frame and the hold frame, improves the phenomenon of screen flicker during the switching process between the high refresh frequency driving mode and the low refresh frequency driving mode, and can save the power consumption of the driving chip by switching between the high refresh frequency driving mode and the low refresh frequency driving mode.

[0102] In a possible implementation manner, refer to Figure 7, the circuit further includes: an anode potential control module 15;

[0103] The anode potential control module 15 is configured to provide a second initial voltage signal of a second initial signal terminal to an anode of the light-emitting device under the control of the second scan line.

[0104] In a possible implementation manner, refer to Figure 8 , the anode potential control module 15 includes: a seventh transistor T7;

[0105] A gate of the seventh transistor T7 is connected to the second scan line scan2, a first end of the seventh transistor T7 is connected to the anode of the light-emitting device EL, and a second end of the seventh transistor T7 is connected to the second initial signal terminal.

[0106] The second initial signal terminal accesses a second initial voltage signal Vinit 2.

[0107] In an example, each transistor can be a TFT (Thin Film Transistor). Specifically, an N-type TFT can be selected according to actual conditions, or a P-type TFT can also be selected. In an example, for any transistor in the pixel driving circuit of the present application, the transistor can be an N-type MOS transistor or a P-type MOS transistor, which can be specifically selected according to actual conditions; a first end of the MOS transistor is a source or a drain, and a second end of the MOS transistor is a drain or a source corresponding to the first end.

[0108] In the embodiment of the present application, an initial voltage signal required by the anode of the light-emitting device is provided through the anode potential control module.

[0109] The pixel driving circuit of the embodiment of the present application improves the 7T1C structure in the related art. By adding a low-frequency data writing module and using an eighth transistor, a ninth transistor, and a second capacitor, a new 9T2C structure is formed, which can improve the phenomenon of screen flicker during the switching process between the high refresh rate driving mode and the low refresh rate driving mode.

[0110] In a possible implementation manner, refer to Figure 9 , the reset module 11 includes: a first capacitor C1, a first transistor T1, and a second transistor T2;

[0111] A first end of the first capacitor C1 is connected to a positive power supply VDD, and a second end of the first capacitor C1 is respectively connected to a second end of the first transistor T1, a first end of the second transistor T2, and the driving module 12;

[0112] The gate of the first transistor T1 is connected to the reset signal terminal, and the first end of the first transistor T1 is connected to the first initial signal terminal, where the reset signal Reset is accessed at the reset signal terminal;

[0113] The gate of the second transistor is connected to the third scan line scan3, and the second end of the second transistor T2 is connected to the driving module 12.

[0114] An embodiment of the present application further provides a pixel driving method. Refer to Figure 10 , which is applied to any of the above pixel driving circuits. The method includes:

[0115] S101. In the high refresh rate driving mode, control the high-frequency data writing module to provide the data voltage signal at the data signal terminal to the driving module at a first frequency.

[0116] S102. In the low refresh rate driving mode, control the low-frequency data writing module to provide the data voltage signal at the data signal terminal to the driving module at a second frequency, where the first frequency is greater than the second frequency.

[0117] In a possible implementation manner, when applied to the above pixel driving circuit, in the low refresh rate driving mode, during each refresh process:

[0118] When refreshing the frame, the first scan line scan1 receives the first level signal, and the second scan line scan2 receives the first level signal, so that the data voltage signal is written into the driving module and the low-frequency data writing module;

[0119] When holding the frame, the first scan line scan1 receives the second level signal, and the second scan line scan2 receives the first level signal, so that the low-frequency data writing module provides the data voltage signal for the driving module; where the first level signal and the second level signal are signals with opposite high and low levels.

[0120] In an example, T1, T2, T3, T4, T5, T6, T7, T8, and T9 are all selected as P-type TFTs. In this case, when the gate signal of each transistor is at a low level, the transistor is turned on, and when the gate signal of each transistor is at a high level, the transistor is turned off. It can be understood that selecting T1, T2, T3, T4, T5, T6, T7, T8, and T9 as P-type TFTs in the present application is only for the convenience of illustration. Users can select other types of transistors, but the pixel driving method has the same concept as the present application and is within the protection scope of the present application.

[0121] When T1, T2, T3, T4, T5, T6, T7, T8, and T9 are all P-type TFTs, the first level signal is a low level signal, and the second level signal is a high level signal.

[0122] In a possible implementation, the method includes:

[0123] When refreshing a frame, in a state where the light emission control terminal EM receives the second level signal, the reset signal terminal Reset receives the first level signal, the first scan line scan1 receives the first level signal, and the second scan line scan2 receives the first level signal;

[0124] When holding a frame, in a state where the light emission control terminal EM receives the second level signal, the reset signal terminal Reset receives the second level signal, the first scan line scan1 receives the second level signal, and the second scan line scan2 receives the first level signal.

[0125] Applied to Figure 8 For the timing diagram of the pixel driving method corresponding to the pixel driving circuit, see Figure 11 , and its specific working process is as follows: In the low refresh frequency driving mode, during each refresh process: When refreshing a frame, EM is first a low level signal and then converted to a high level signal for clearing the screen. During the process when EM is a high level signal, first, Reset is set to a low level signal, T1 is turned on, the voltage at point N1 is reset to Vinit 1, then scan1 and scan2 are set to low level signals, T4 and T9 are turned on, the data voltage signal DATA is written to points N2 / N3, and at the same time, the data voltage signal DATA charges C2 so that C2 is charged to the DATA voltage and stores this voltage; When holding a frame, scan1 is set to a high level and scan2 is set to a low level, T4 and T9 are turned off, and T8 is turned on. The DATA voltage stored in C2 charges points N2 / N3. Before EM is a low level signal (turned on), the voltage at points N2 / N3 is charged to DATA, so that the voltage at points N2 / N3 is the same in the refresh frame and the hold frame.

[0126] In a possible implementation, the method includes:

[0127] When refreshing a frame, in a state where the light emission control terminal EM receives the second level signal, the reset signal terminal Reset receives the first level signal, the first scan line scan1 receives the first level signal, the second scan line scan2 receives the first level signal, and the third scan line scan3 receives the first level signal;

[0128] When holding a frame, with the emission control terminal EM receiving a second-level signal, the reset signal terminal Reset receives a second-level signal, the first scan line scan1 receives a second-level signal, the second scan line scan2 receives a first-level signal, and the third scan line scan3 receives a second-level signal.

[0129] Applied to Figure 9 The timing diagram of the pixel driving method corresponding to the pixel driving circuit, see Figure 12 The specific working process is as follows: In the low refresh frequency driving mode, during each refresh process: When refreshing a frame, EM is first a low-level signal and then converted to a high-level signal for screen clearing. During the process when EM is a high-level signal, first set Reset to a low-level signal, T1 is turned on, and the voltage at point N1 is reset to Vinit 1. Secondly, set scan3 to a low-level signal. During the process when scan3 is set to a low-level signal, then set scan1 and scan2 to low-level signals, T4 and T9 are turned on, and the data voltage signal DATA is written to points N2 / N3. At the same time, the data voltage signal DATA charges C2, so that C2 is charged to the DATA voltage and stores this voltage. Finally, set scan3 to a high-level signal again; When holding a frame, set scan1 and scan3 to high levels and scan2 to a low level, T4 and T9 are turned off, and T8 is turned on. The DATA voltage stored in C2 will charge points N2 / N3. Before EM is a low-level signal (turned on), the voltage at points N2 / N3 is charged to DATA, so as to achieve the same voltage at points N2 / N3 in the refresh frame and the hold frame. Setting scan3 to a high level when holding a frame can maintain the stability of the voltage at point N1.

[0130] The embodiment of the present application provides a display device, including the pixel driving circuit described in any one of the above.

[0131] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0132] Each embodiment in this specification is described in a related manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0133] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A pixel driving circuit, characterized in that, The circuit includes: a reset module, a driving module, a high-frequency data writing module, and a low-frequency data writing module. The reset module, the high-frequency data writing module, and the low-frequency data writing module are respectively connected to the driving module, and the driving module is connected to a light-emitting device; the reset module is configured to provide a first initial voltage signal input from a first initial signal terminal to the driving module when a reset signal is received; the high-frequency data writing module is configured to provide a data voltage signal at a data signal terminal to the driving module at a first frequency in a high refresh frequency driving mode; the low-frequency data writing module is configured to provide a data voltage signal at the data signal terminal to the driving module at a second frequency in a low refresh frequency driving mode, where the first frequency is greater than the second frequency; the driving module is configured to drive the light-emitting device in response to an input voltage signal; the reset module includes: a first capacitor, a first transistor, and a second transistor; the driving module includes: a fifth transistor, a third transistor, and a sixth transistor; the low-frequency data writing module includes: an eighth transistor, a ninth transistor, and a second capacitor; a first end of the first capacitor is connected to a positive power supply, and a second end of the first capacitor is respectively connected to a second end of the first transistor, a first end of the second transistor, and a gate of the third transistor; a gate of the first transistor is connected to a reset signal terminal, and a first end of the first transistor is connected to the first initial signal terminal, where the reset signal is input to the reset signal terminal; a gate of the second transistor is connected to a first scan line or a third scan line, and a second end of the second transistor is connected to a first end of the third transistor; a gate of the fifth transistor is connected to a light-emitting control terminal, a first end of the fifth transistor is connected to the positive power supply, and a second end of the fifth transistor is respectively connected to a second end of the third transistor, the high-frequency data writing module, and a first end of the eighth transistor; the first end of the third transistor is further connected to a first end of the sixth transistor; a gate of the sixth transistor is connected to the light-emitting control terminal, a second end of the sixth transistor is connected to an anode of the light-emitting device, and a cathode of the light-emitting device is connected to a negative power supply; a gate of the eighth transistor is connected to a second scan line, and a second end of the eighth transistor is respectively connected to a first end of the ninth transistor and a first end of the second capacitor; a gate of the ninth transistor is connected to the first scan line, and a second end of the ninth transistor is connected to the data signal terminal; a second end of the second capacitor is connected to an open-source signal terminal.

2. The pixel driving circuit according to claim 1, wherein The high-frequency data writing module includes: a fourth transistor; a gate of the fourth transistor is connected to the first scan line, a first end of the fourth transistor is connected to a second end of the fifth transistor, and a second end of the fourth transistor is connected to the data signal terminal.

3. The pixel driving circuit according to claim 1, wherein The circuit further includes: an anode potential control module; The anode potential control module is configured to provide, under the control of the second scan line, a second initial voltage signal of a second initial signal terminal to an anode of the light-emitting device.

4. The pixel driving circuit according to claim 3, wherein The anode potential control module includes: a seventh transistor; A gate of the seventh transistor is connected to the second scan line, a first end of the seventh transistor is connected to the anode of the light-emitting device, and a second end of the seventh transistor is connected to the second initial signal terminal.

5. A pixel driving method, characterized in that, Applied to the pixel driving circuit according to any one of claims 1-4, the method includes: In a high refresh rate driving mode, controlling a high-frequency data writing module to provide a data voltage signal of a data signal terminal to a driving module at a first frequency; In a low refresh rate driving mode, controlling a low-frequency data writing module to provide a data voltage signal of the data signal terminal to the driving module at a second frequency, where the first frequency is greater than the second frequency.

6. The pixel driving method according to claim 5, wherein Applied to the pixel driving circuit according to claim 4, in the low refresh rate driving mode, during each refresh process: During a refresh frame, a first scan line receives a first level signal, and a second scan line receives a first level signal, so that the data voltage signal is written into the driving module and the low-frequency data writing module; During a hold frame, the first scan line receives a second level signal, and the second scan line receives a first level signal, so that the low-frequency data writing module provides a data voltage signal to the driving module; where the first level signal and the second level signal are signals with opposite high and low levels.

7. The pixel driving method according to claim 6, wherein The method includes: During a refresh frame, in a state where a second level signal is received at a light-emitting control terminal, a first level signal is received at a reset signal terminal, a first scan line receives a first level signal, and a second scan line receives a first level signal; During a hold frame, in a state where a second level signal is received at the light-emitting control terminal, a second level signal is received at the reset signal terminal, a first scan line receives a second level signal, and a second scan line receives a first level signal.

8. The pixel driving method according to claim 6, wherein The method includes: During a refresh frame, in a state where a second level signal is received at the light-emitting control terminal, a first level signal is received at the reset signal terminal, a first scan line receives a first level signal, a second scan line receives a first level signal, and a third scan line receives a first level signal; During a hold frame, in a state where a second level signal is received at the light-emitting control terminal, a second level signal is received at the reset signal terminal, a first scan line receives a second level signal, a second scan line receives a first level signal, and a third scan line receives a second level signal.

9. A display device, characterized in that, Including the pixel driving circuit according to any one of claims 1-4.

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