A method for detecting operation of a FC port link recovery state machine

Abstract

The present invention provides an FC port link recovery state machine operation detection method. The FC port link recovery state machine operation detection method is that when the FC port link of the device to be tested is restored, the link recovery state machine in the test device automatically tests its execution status. The automatic test includes the completion judgment of the enable test of multiple operating states in the FC port, and the completion judgment of multiple primitive tests in each operating state. The FC port link recovery state machine operation detection method is the core function of the primitive sequence protocol test of the FC port, and is suitable for testing the execution status of link recovery of various types of FC ports; and the control of the link recovery state machine is clear and easy to implement in hardware logic, which can greatly improve the correctness of the automatic detection of the execution of the FC port link recovery state machine.

Description

Technical Field

[0001] The invention belongs to computer communication technology and relates to an FC port link recovery state machine operation detection method. Background Art

[0002] FC (Fibre Channel), or fiber channel technology, was first used in SAN (storage area network). FC port is a standard form of interface for fiber optic docking. As the backbone network of the new generation of avionics system, it can provide communication support for the interconnection between the subsystems of the avionics system.

[0003] During the communication process, when the FC port detects any of the following three situations: connection recovery, link timeout, and buffer overflow, the link reset protocol will be executed. The link reset protocol starts from entering the initial state, that is, the link recovery state machine jumps. However, when the FC port link recovery state machine is executed incorrectly, the link state cannot be restored. Therefore, it is necessary to detect the operation status of the FC port link recovery state machine to ensure the correctness of the FC port link recovery design and implementation. Summary of the invention

[0004] In order to accurately detect whether the FC port link recovery state machine is executed correctly when the FC port link recovery state machine is running, the present invention designs an FC port link recovery state machine operation detection method.

[0005] The present invention defines a test processing mechanism for an FC port link recovery state machine, designs an independent link recovery state machine and corresponding control logic according to the execution characteristics of the link recovery state machine under multiple operating states (such as LR1 is in the LR sending state, LR2 is in the LR receiving state, and LR3 is in the LRR receiving state) and the jump mode of the state machine. The control logic automatically tests the execution status of the FC port link recovery under the control of the state machine to ensure the correctness of its execution of the FC port link reset protocol.

[0006] The technical solution for achieving the purpose of the invention is as follows: a method for detecting the operation of a link recovery state machine of an FC port. The method for detecting the operation of a link recovery state machine of an FC port is to automatically test the execution of a link recovery state machine of an FC port of a device under test when the link is recovered. The automatic test includes completion judgment of enable tests of multiple operating states in the FC port and completion judgment of multiple primitive tests in each operating state.

[0007] Among them, the two FC ports of the device under test are directly connected in the logic, one FC port communicates with an FC test port in the test device, and the other FC port communicates with another FC test port in the test device, and the execution status of the link recovery state machine is automatically tested according to the communication between the two FC ports and the two FC test ports.

[0008] In one embodiment, the FC port link recovery state machine execution and testing method include the following steps:

[0009] S1, when powered on or reset, the link recovery state machine in the test equipment enters the initial state;

[0010] S2, the link recovery state machine enters the enable test selection state from the initial state, performs enable test completion flag judgment on various operating states of the FC port, and outputs the enable test result;

[0011] S3, judging the primitive test completion flags of the multiple primitives in each running state, and outputting the primitive test results;

[0012] S4. After all the running states of the device under test and all the primitive tests in each running state are completed, the FC port link recovery test result is determined according to the running state enabling test result and the primitive test result;

[0013] S5. According to the FC port link recovery test result, determine the link recovery state machine operation result, and place the link recovery state machine in an initial state or a test completion state.

[0014] In an improved embodiment of the above embodiment, in the above step S1, after the link recovery state machine enters the initial state, it is determined whether the power-on or reset is completed, and if not completed, it stays in the initial state.

[0015] Furthermore, the method for determining whether power-on or reset is completed is as follows:

[0016] Set the buffer-to-buffer credit value of the test device to a default value, for example, the default value can be selected as 4, and the error detection timeout value E_D_TOV, for example, the error detection timeout value can be set to 10ms;

[0017] In the initial state 0, the FC test port of the test device and the FC test port of the device under test perform synchronous operation;

[0018] When the FC test port reaches the Active state, the link recovery state machine enters and executes S3 if the power-on or reset test is passed, otherwise it stays in the initial state.

[0019] In an improved embodiment of the above embodiment, in the above step S2, the method for judging the multiple operation status enabling test completion flag of the FC port is:

[0020] S201, if the enabling test of a certain running state is not performed, then the enabling test is performed, and after the test is completed, the enabling test completion flag of the running state is set to valid;

[0021] S202, repeat step S201 until all enable tests of the running states have been performed, set the enable test completion flag of the device under test to valid, and the link recovery state machine enters the test completion state from the enable test selection state, and outputs the enable test result.

[0022] Furthermore, in the above step S201, when the enablement test of a certain operating state is not performed, the operating state that has not performed the enablement test enters the corresponding enablement test state from the enablement test selection state, and the enablement of the device under test in the operating state is tested.

[0023] Furthermore, in step S2, the multiple operating states include an LR sending state, an LR receiving state, and an LRR receiving state.

[0024] Among them, the enabling test method of the LR sending status is:

[0025] Define the buffer-to-buffer credit value as N. The first test port continuously sends N SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port. For example, N can be selected as 4. The second test port does not send the R_RDY primitive (receiver ready primitive) to the second FC port within the set time. The set time can be the E_D_TOV time.

[0026] If the LR primitive (link reset primitive sequence) sent by the second FC port is detected after the set time, it is determined that the enable test in this operating state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state and outputs the enable test result.

[0027] If the LR primitive sent by the second FC port is not detected after the set time, it is determined that the enable test in the running state has failed, and the enable test state of the running state returns to the initial state, reporting an enable error signal and setting the test completion flag to valid.

[0028] Among them, the enabling test method of the LR receiving state is:

[0029] Define the buffer-to-buffer credit value as N, the first test port continuously sends N SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port; the second test port does not send R_RDY to the second FC port within the set time; after detecting the LR primitive sent by the second FC port after the set time, the second test port sends the LR primitive to the second FC port.

[0030] If the LRR primitive (link reset response primitive sequence) sent by the second FC port is detected, it is determined that the enable test in this operating state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state and outputs the enable test result.

[0031] If the LR primitive sent by the second FC port is not detected, it is determined that the enable test in the running state has failed, and the enable test state of the running state returns to the initial state, reporting an enable error signal and setting the test completion flag to valid.

[0032] Among them, the enabling test method of the LRR receiving state is:

[0033] The first test port continuously sends N (buffer to buffer credit value) SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port; the second test port does not send R_RDY to the second FC port within a set time; after detecting the LR primitive sent by the second FC port after the set time, the second test port sends the LRR primitive to the second FC port.

[0034] If the IDLE (link valid) primitive sent by the second FC port is detected, it is determined that the enable test in this running state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state, and outputs the enable test result.

[0035] If the IDLE primitive sent by the second FC port is not detected, it is determined that the enable test in the running state has failed, and the enable test state of the running state returns to the initial state, reporting an enable error signal and setting the test completion flag to valid.

[0036] In an improved embodiment of the above embodiment, in the above step S3, the method for judging the primitive test completion flags of the plurality of primitives in the corresponding running state is:

[0037] S301, for primitives that have not been tested in the running state, enter the primitive test state corresponding to the primitive to perform primitive testing, and after the test is completed, set the primitive test completion flag of the primitive to be valid;

[0038] S302. Repeat step S301 until all primitive tests in the running state have been performed; set the primitive test completion flag of the running state to valid, and the link recovery state machine returns from the primitive test state to the primitive test selection state. If all primitive tests have been completed, return from the primitive test selection state to the enable test selection state and output the running state test result.

[0039] Furthermore, in the above step S301, the primitive test method is:

[0040] In the running state, the second test port sends the corresponding primitive to the second FC port according to the current primitive test state;

[0041] If the response made by the FC port meets the test judgment rules under the primitive test state, it indicates that the primitive test is normal under the running state, and the primitive test completion flag of the primitive is set to valid, and the link recovery state machine returns from the primitive test state to the primitive test selection state; if the corresponding primitive tests are all completed, the primitive test selection state returns to the enable test selection state and outputs the primitive test result;

[0042] Otherwise, the primitive test is abnormal in the running state, and the link recovery state machine returns from the primitive test state to the enable test state, reports an enable error signal and sets the test completion flag to be valid.

[0043] In an improved embodiment of the above embodiment, in the above step S5, the operation result of the link recovery state machine includes: outputting the corresponding test result according to the test completion flag in the corresponding state and the related primitive test completion flag; if a start test signal is received, the test completion flag is set to invalid, and the link recovery state machine returns to the initial state; otherwise, the test completion flag is set to valid, and the link recovery state machine stays in the test completion state.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows: the FC port link recovery state machine operation detection method designed by the present invention is the core function of the primitive sequence protocol test of the FC port, and is suitable for testing the execution status of link recovery of various types of FC ports; and the control of the link recovery state machine is clear and easy to implement in hardware logic, which can greatly improve the correctness of the execution of the automatic detection FC port link recovery state machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only for the purpose of more clearly illustrating the technical solutions of the embodiments of the present invention or the prior art. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 It is a link recovery state machine test model diagram of the FC port in a specific implementation mode;

[0047] Figure 2 It is a schematic diagram of the FC port link recovery state machine jump mode in a specific implementation manner. DETAILED DESCRIPTION

[0048] The present invention will be further described below in conjunction with specific embodiments, and the advantages and features of the present invention will become clearer as the description proceeds. However, these embodiments are exemplary only and do not constitute any limitation to the scope of the present invention. It should be understood by those skilled in the art that the details and forms of the technical solution of the present invention may be modified or replaced without departing from the spirit and scope of the present invention, but these modifications and replacements all fall within the scope of protection of the present invention.

[0049] In the description of this embodiment, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the invention.

[0050] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0051] This specific implementation method discloses a method for detecting the operation of a FC port link recovery state machine.

[0052] The FC port link recovery state machine operation detection method is that when the FC port link of the device under test is restored, the test device automatically tests the execution of its link recovery state machine, and the automatic test includes the completion judgment of the enable test of multiple operating states in the FC port and the completion judgment of multiple primitive tests in each operating state.

[0053] The device under test includes two FC ports with logical internal direct connection, such as Figure 1 As shown in Figure 1, N_Port1 and N_Port2 both execute the Fibre Channel link reset protocol. Figure 1 In the T1 and T2 shown in FIG. 8 , both the T1 and T2 ports implement the Fibre Channel link recovery state machine.

[0054] When the test device judges the FC port link recovery of the device under test, one FC port of the device under test communicates with an FC test port in the test device, and the other FC port communicates with another FC test port in the test device, and the execution status of the link recovery state machine is automatically tested based on the communication between the two FC ports and the two FC test ports.

[0055] The FC port link recovery state machine execution and test method include the following steps:

[0056] S1, when powered on or reset, the link recovery state machine in the test equipment enters the initial state;

[0057] S2, the link recovery state machine enters the enable test selection state from the initial state, performs enable test completion flag judgment on various operating states of the FC port, and outputs the enable test result;

[0058] S3, judging the primitive test completion flags of the multiple primitives in each running state, and outputting the primitive test results;

[0059] S4. After all the running states of the device under test and all the primitive tests in each running state are completed, the FC port link recovery test result is determined according to the running state enabling test result and the primitive test result;

[0060] S5. According to the FC port link recovery test result, determine the link recovery state machine operation result, and place the link recovery state machine in an initial state or a test completion state.

[0061] In an improved embodiment of the above embodiment, in the above step S1, after the link recovery state machine enters the initial state, it is determined whether the power-on or reset is completed, and if not completed, it stays in the initial state.

[0062] Furthermore, the method for determining whether power-on or reset is completed is as follows:

[0063] Set the buffer-to-buffer credit value of the test device to a default value, for example, the default value can be selected as 4, and the error detection timeout value E_D_TOV, for example, the error detection timeout value can be set to 10ms;

[0064] In the initial state 0, the FC test port of the test device and the FC test port of the device under test perform synchronous operation;

[0065] When the FC test port reaches the Active state, the link recovery state machine enters and executes S3 if the power-on or reset test is passed, otherwise it stays in the initial state.

[0066] In an improved embodiment of the above embodiment, in the above step S2, the method for judging the multiple operation status enabling test completion flag of the FC port is:

[0067] S201, if the enabling test of a certain running state is not performed, then the enabling test is performed, and after the test is completed, the enabling test completion flag of the running state is set to valid;

[0068] S202, repeat step S201 until all enable tests of the running states have been performed, set the enable test completion flag of the device under test to valid, and the link recovery state machine enters the test completion state from the enable test selection state, and outputs the enable test result.

[0069] Furthermore, in the above step S201, when the enablement test of a certain operating state is not performed, the operating state that has not performed the enablement test enters the corresponding enablement test state from the enablement test selection state, and the enablement of the device under test in the operating state is tested.

[0070] Furthermore, in step S2, the multiple operating states include an LR sending state, an LR receiving state, and an LRR receiving state.

[0071] Among them, the enabling test method of the LR sending status is:

[0072] Define the buffer-to-buffer credit value as N. The first test port continuously sends N SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port. For example, N can be selected as 4. The second test port does not send the R_RDY primitive (receiver ready primitive) to the second FC port within the set time. The set time can be the E_D_TOV time.

[0073] If the LR primitive (link reset primitive sequence) sent by the second FC port is detected after the set time, it is determined that the enable test in this operating state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state and outputs the enable test result.

[0074] If the LR primitive sent by the second FC port is not detected after the set time, it is determined that the enable test in the running state has failed, and the enable test state of the running state returns to the initial state, reporting an enable error signal and setting the test completion flag to valid.

[0075] Among them, the enabling test method of the LR receiving state is:

[0076] Define the buffer-to-buffer credit value as N, the first test port continuously sends N SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port; the second test port does not send R_RDY to the second FC port within the set time; after detecting the LR primitive sent by the second FC port after the set time, the second test port sends the LR primitive to the second FC port.

[0077] If the LRR primitive (link reset response primitive sequence) sent by the second FC port is detected, it is determined that the enable test in this operating state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state and outputs the enable test result.

[0078] If the LR primitive sent by the second FC port is not detected, it is determined that the enable test in the running state has failed, and the enable test state of the running state returns to the initial state, reporting an enable error signal and setting the test completion flag to valid.

[0079] Among them, the enabling test method of the LRR receiving state is:

[0080] The first test port continuously sends N (buffer to buffer credit value) SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port; the second test port does not send R_RDY to the second FC port within a set time; after detecting the LR primitive sent by the second FC port after the set time, the second test port sends the LRR primitive to the second FC port.

[0081] If the IDLE (link valid) primitive sent by the second FC port is detected, it is determined that the enable test in this running state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state, and outputs the enable test result.

[0082] If the IDLE primitive sent by the second FC port is not detected, it is determined that the enable test in the running state has failed, and the enable test state of the running state returns to the initial state, reporting an enable error signal and setting the test completion flag to valid.

[0083] In an improved embodiment of the above embodiment, in the above step S3, the method for judging the primitive test completion flags of the plurality of primitives in the corresponding running state is:

[0084] S301, for primitives that have not been tested in the running state, enter the primitive test state corresponding to the primitive to perform primitive testing, and after the test is completed, set the primitive test completion flag of the primitive to be valid;

[0085] S302. Repeat step S301 until all primitive tests in the running state have been performed; set the primitive test completion flag of the running state to valid, and the link recovery state machine returns from the primitive test state to the primitive test selection state. If all primitive tests have been completed, return from the primitive test selection state to the enable test selection state and output the running state test result.

[0086] Furthermore, in the above step S301, the primitive test method is:

[0087] In the running state, the second test port sends primitives to the second FC port according to the current primitive test state;

[0088] If the response made by the FC port meets the test judgment rules under the primitive test state, it indicates that the primitive test is normal under the running state, and the primitive test completion flag of the primitive is set to valid, and the link recovery state machine returns from the primitive test state to the primitive test selection state; if the corresponding primitive tests are all completed, the primitive test selection state returns to the enable test selection state and outputs the primitive test result;

[0089] Otherwise, the primitive test is abnormal in the running state, and the link recovery state machine returns from the primitive test state to the enable test state, reports an enable error signal and sets the test completion flag to be valid.

[0090] In an improved embodiment of the above embodiment, in the above step S5, the operation result of the link recovery state machine includes: outputting the corresponding test result according to the test completion flag in the corresponding state and the related primitive test completion flag; if a start test signal is received, the test completion flag is set to invalid, and the link recovery state machine returns to the initial state; otherwise, the test completion flag is set to valid, and the link recovery state machine stays in the test completion state.

[0091] The following uses a specific example to illustrate the FC port link recovery state machine operation detection method when the test device tests the FC port link recovery of the device under test:

[0092] The FC test port of the test device interacts and controls the FC port of the device under test with primitives, and performs automated test operations under the control of the FC port link recovery state machine (hereinafter referred to as the state machine). The state machine is as follows: Figure 2 As shown, the workflow is as follows:

[0093] 1. Initial state (i.e., state 0). The state machine enters this state when power is initially turned on or reset. In this state, the two FC test ports (T1 and T2) of the test equipment are synchronized with the two FC ports (N_Port1 and N_Port2) of the DUT. The buffer-to-buffer credit value (BB_Credit) is set to the default value of 4, and the error detection timeout value (E_D_TOV) is set to 10ms. If both T1 and T2 reach the Active state, the state machine enters state 1; otherwise, it stays in state 0.

[0094] 2. Enable test selection state (i.e. state 1). In this state, three operating states are judged, such as the enable test completion flags corresponding to the LR1, LR2, and LR3 states, and the tests of the three operating states are carried out in sequence;

[0095] If the running state test is not performed, the state machine enters the enabling test state, including state 2, state 7, and state 13. Specifically, if the LR1 state test is not performed, the state machine enters state 2; if the LR2 state test is not performed, the state machine enters state 7; if the LR3 state test is not performed, the state machine enters state 13;

[0096] If the LR1 state, LR2 state, and LR3 state are all tested, the state machine enters the test completion state (ie, state 19).

[0097] 2.1, State 2 is the LR1 enable test state. In this state, the T1 port of the test equipment is controlled to send 4 SOFi3 data frames continuously, which are transmitted through the N_Port1 and N_Port2 of the DUT and arrive at the T2 port. After receiving the 4 SOFi3 data frames, the T2 port is controlled not to send R_RDY to the N_Port2 of the DUT within the E_D_TOV time. If the LR primitive sent by N_Port2 is detected after the E_D_TOV time, it means that the LR1 enable state is normal, and the state machine enters the following state 3; otherwise, it means that the LR1 enable state is abnormal, and the state machine returns to state 0, reports the LR1 enable error, and sets the LR1 test completion flag to valid.

[0098] 2.2. State 3 is the LR1 primitive test selection state (also called the LR1 test state). In this state, the N_Port2 port of the DUT keeps sending the LR primitive.

[0099] The primitive test completion flag judgment of various primitives under LR1, including IDLE, OLS (offline primitive sequence), and NOS (non-operational primitive sequence) primitives, is carried out in three states in turn.

[0100] If the primitive test is not performed, the state machine enters the primitive test states corresponding to each primitive, including state 4, state 5, and state 6. For example, if the IDLE primitive test is not performed, the state machine enters state 4; if the OLS primitive test is not performed, the state machine enters state 5; if the NOS primitive test is not performed, the state machine enters state 6;

[0101] If the IDLE, OLS, and NOS primitive tests are all completed, the state machine returns to state 1 and sets the LR1 test completion flag to valid.

[0102] 2.2.1. State 4 is the primitive test state of the IDLE primitive in the LR1 state. In this state, T2 sends the IDLE primitive. If it is detected that the N_Port2 port of the DUT is still sending the LR primitive within the R_T_TOV time, and sends the NOS primitive after the R_T_TOV times out, the state machine returns to state 3, reporting that the IDLE primitive test received in the LR1 state is normal, and the IDLE primitive test completion flag in the LR1 state is set to valid; otherwise, the state machine returns to state 2, reporting that the IDLE primitive test received in the LR1 state is abnormal, and the IDLE primitive test completion flag in the LR1 state is set to valid.

[0103] 2.2.2. State 5 is the primitive test state of the OLS primitive in the LR1 state. In this state, T2 sends the OLS primitive. If it is detected that the N_Port2 port of the DUT sends the LR primitive, the state machine returns to state 3, reporting that the test of receiving the OLS primitive in the LR1 state is normal, and the OLS primitive test completion flag in the LR1 state is set to valid; otherwise, the state machine returns to state 2, reporting that the test of receiving the OLS primitive in the LR1 state is abnormal, and the OLS primitive test completion flag in the LR1 state is set to valid.

[0104] 2.2.3. State 6 is the primitive test state of the NOS primitive in the LR1 state. In this state, T2 sends the NOS primitive. If it is detected that the N_Port2 port of the DUT sends the OLS primitive, the state machine returns to state 3, reporting that the test of receiving the NOS primitive in the LR1 state is normal, and the NOS primitive test completion flag in the LR1 state is set to valid; otherwise, the state machine returns to state 2, reporting that the test of receiving the NOS primitive in the LR1 state is abnormal, and the NOS primitive test completion flag in the LR1 state is set to valid.

[0105] 2.3, State 7 is the LR2 enable test state. In this state, the T1 port of the test equipment is controlled to send 4 SOFi3 data frames continuously, which are transmitted through N_Port1 and N_Port2 of the DUT and arrive at the T2 port. After receiving the 4 SOFi3 data frames, the T2 port is controlled not to send R_RDY to the N_Port2 of the DUT within the E_D_TOV time. After receiving the LR primitive, T2 sends the LR primitive. If the LRR primitive sent by N_Port2 is detected, the state machine enters the following state 8; otherwise, the state machine returns to state 0, reports the LR2 enable error, and sets the LR2 test completion flag to valid.

[0106] 2.4. State 8 is the LR2 primitive test selection state (also called the LR2 test state). In this state, the N_Port2 port of the DUT keeps sending the LRR primitive.

[0107] The primitive test completion flags of various primitives under LR2 are judged, including the test completion flags corresponding to the LR, LRR, OLS, and NOS primitive tests, and tests in four states are carried out in turn.

[0108] If the primitive test is not performed, the state machine enters the primitive test states corresponding to each primitive, including state 9, state 10, state 11, and state 12. If the LR primitive test is not performed, the state machine enters state 9; if the LRR primitive test is not performed, the state machine enters state 10; if the OLS primitive test is not performed, the state machine enters state 11; if the NOS primitive test is not performed, the state machine enters state 12.

[0109] If the LR, LRR, OLS, and NOS primitive tests are all completed, the state machine returns to state 1 and sets the LR2 test completion flag to valid.

[0110] 2.4.1. State 9 is the primitive test state of the LR primitive in the LR2 state. In this state, T2 sends the LR primitive. If it is detected that the N_Port2 port of the DUT sends the LRR primitive, the state machine returns to state 8, reporting that the test of receiving the LR primitive in the LR2 state is normal, and the LR primitive test completion flag in the LR2 state is set to valid; otherwise, the state machine returns to state 7, reporting that the test of receiving the LR primitive in the LR2 state is abnormal, and the LR primitive test completion flag in the LR2 state is set to valid.

[0111] 2.4.2. State 10 is the primitive test state of the LRR primitive in the LR2 state. In this state, T2 sends the LRR primitive. If it is detected that the N_Port2 port of the DUT sends the IDLE primitive, the state machine returns to state 8, reporting that the test of receiving the LRR primitive in the LR2 state is normal, and the LRR primitive test completion flag in the LR2 state is set to valid; otherwise, the state machine returns to state 7, reporting that the test of receiving the LRR primitive in the LR2 state is abnormal, and the LRR primitive test completion flag in the LR2 state is set to valid.

[0112] 2.4.3. State 11 is the primitive test state of the OLS primitive test state in the LR2 state. In this state, T2 sends the OLS primitive. If it is detected that the N_Port2 port of the DUT sends the LR primitive, the state machine returns to state 8, reporting that the OLS primitive test received in the LR2 state is normal, and the OLS primitive test completion flag in the LR2 state is set to valid; otherwise, the state machine returns to state 7, reporting that the OLS primitive test received in the LR2 state is abnormal, and the OLS primitive test completion flag received in the LR2 state is set to valid.

[0113] 2.4.4. State 12 is the primitive test state of the NOS primitive test state in the LR2 state. In this state, T2 sends the NOS primitive. If it is detected that the N_Port2 port of the DUT sends the OLS primitive, the state machine returns to state 8, reporting that the NOS primitive test received in the LR2 state is normal, and the NOS primitive test completion flag in the LR2 state is set to valid; otherwise, the state machine returns to state 7, reporting that the NOS primitive test received in the LR2 state is abnormal, and the NOS primitive test completion flag in the LR2 state is set to valid.

[0114] 2.5, State 13 is the enable test state of the LR3 enable state. In this state, the T1 port of the test equipment is controlled to send 4 SOFi3 data frames continuously, which are transmitted through the N_Port1 and N_Port2 of the DUT and arrive at the T2 port. After receiving the 4 SOFi3 data frames, the T2 port is controlled not to send R_RDY to the N_Port2 of the DUT within the E_D_TOV time. After receiving the LR primitive, T2 sends the LRR primitive. If the IDLE primitive sent by N_Port2 is detected, the state machine enters the following state 14; otherwise, the state machine returns to state 0, reports the LR3 enable error, and sets the LR3 test completion flag to valid.

[0115] 2.6. State 14 is the primitive test selection state (also called LR3 test state. In this state, the N_Port2 port of the DUT keeps sending the IDLE primitive.

[0116] The primitive test completion flags of various primitives under LR3 are judged, including the test completion flags corresponding to the LR, LRR, OLS, and NOS primitive tests, and tests in four states are carried out in turn.

[0117] If the LR primitive test is not performed, the primitive test states corresponding to each primitive are entered respectively, including state 15, state 16, state 17, and state 18. If the LR primitive test is not performed, the state machine enters state 15; if the LRR primitive test is not performed, the state machine enters state 16; if the OLS primitive test is not performed, the state machine enters state 17; if the NOS primitive test is not performed, the state machine enters state 18.

[0118] If the LR, LRR, OLS, and NOS primitive tests are all completed, the state machine returns to state 1 and sets the LR3 test completion flag to valid.

[0119] 2.6.1. State 15 is the primitive test state of the LR primitive in the LR3 state. In this state, T2 sends the LR primitive. If it is detected that the N_Port2 port of the DUT sends the LRR primitive, the state machine returns to state 14, reporting that the test of receiving the LR primitive in the LR3 state is normal, and the LR primitive test completion flag in the LR3 state is set to valid; otherwise, the state machine returns to state 13, reporting that the test of receiving the LR primitive in the LR3 state is abnormal, and the LR primitive test completion flag in the LR3 state is set to valid.

[0120] 2.6.2. State 16 is the primitive test state of the LRR primitive in the LR3 state. In this state, T2 sends the LRR primitive. If it detects that the N_Port2 port of the DUT sends the IDLE primitive, the state machine returns to state 14, reporting that the test of receiving the LRR primitive in the LR3 state is normal, and the LRR primitive test completion flag in the LR3 state is set to valid; otherwise, the state machine returns to state 13, reporting that the test of receiving the LRR primitive in the LR3 state is abnormal, and the LRR primitive test completion flag in the LR3 state is set to valid.

[0121] 2.6.3. State 17 is the primitive test state of the OLS primitive in the LR3 state. In this state, T2 sends the OLS primitive. If it is detected that the N_Port2 port of the DUT sends the LR primitive, the state machine returns to state 14, reporting that the test of receiving the OLS primitive in the LR3 state is normal, and the OLS primitive test completion flag in the LR3 state is set to valid; otherwise, the state machine returns to state 13, reporting that the test of receiving the OLS primitive in the LR3 state is abnormal, and the OLS primitive test completion flag in the LR3 state is set to valid.

[0122] 2.6.4. State 18 is the primitive test state of the NOS primitive in the LR3 state. In this state, T2 sends the NOS primitive. If it is detected that the N_Port2 port of the DUT sends the OLS primitive, the state machine returns to state 14, reporting that the test of receiving the NOS primitive in the LR3 state is normal, and the NOS primitive test completion flag in the LR3 state is set to valid; otherwise, the state machine returns to state 13, reporting that the test of receiving the NOS primitive in the LR3 state is abnormal, and the NOS primitive test completion flag in the LR3 state is set to valid.

[0123] 2.7, State 19 is the test completion state. In this state, the LR1, LR2, LR3 test completion flags and the related primitive test completion flags received in the LR1, LR2, LR3 states are judged, and the related test results are output. If the start test signal is received, the related test completion flag is set to invalid, and the state machine returns to state 0; otherwise, the state machine stays in state 19.

[0124] The above-mentioned FC port link recovery state machine operation detection method is to test the core function of the link reset protocol of the FC port, and is suitable for testing the link recovery execution status of various types of FC ports; and the control of the link recovery state machine is clear and easy to implement in hardware logic, which can greatly improve the correctness of the automatic detection of the execution of the FC port link recovery state machine.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

[0126] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for detecting the operation of a FC port link recovery state machine, characterized in that: The FC port link recovery state machine operation detection method is that when the FC port link of the device to be tested is restored, the link recovery state machine in the test device automatically tests its execution status, and the automatic test includes the completion judgment of the enable test of multiple operation states in the FC port and the completion judgment of multiple primitive tests in each operation state; The device under test includes two FC ports that are logically directly connected internally, one of the FC ports communicates with an FC test port in the test device, and the other FC port communicates with another FC test port in the test device, and the link recovery state machine execution status is automatically tested according to the mutual communication between the two FC ports and the two FC test ports; The FC port link recovery state machine execution and test method include the following steps: S1, when powered on or reset, the link recovery state machine in the test equipment enters the initial state; S2, the link recovery state machine enters the enable test selection state from the initial state, performs enable test completion flag judgment on various operating states of the FC port, and outputs the enable test result; S3, judging the primitive test completion flags of the multiple primitives in each running state, and outputting the primitive test results; S4. After all the running states of the device under test and all the primitive tests in each running state are completed, the FC port link recovery test result is determined according to the running state enabling test result and the primitive test result; S5. According to the FC port link recovery test result, determine the link recovery state machine operation result, and place the link recovery state machine in an initial state or a test completion state.

2. The FC port link recovery state machine operation detection method according to claim 1, characterized in that: In step S1, after the link recovery state machine enters the initial state, it determines whether the power-on or reset is completed. If not, it stays in the initial state.

3. The FC port link recovery state machine operation detection method according to claim 2, characterized in that: The method to judge whether power-on or reset is completed is: Set the default values ​​for the test equipment's buffer-to-buffer credits and error detection timeout values; In the initial state 0, the FC test port of the test device and the FC test port of the device under test perform synchronous operation; When the FC test port reaches the Active state, the link recovery state machine enters and executes S3 if the power-on or reset test is passed, otherwise it stays in the initial state.

4. The FC port link recovery state machine operation detection method according to claim 1, characterized in that: In step S2, the method for judging the multiple operation status enabling test completion flag of the FC port is: S201, if the enabling test of a certain running state is not performed, then the enabling test is performed, and after the test is completed, the enabling test completion flag of the running state is set to valid; S202, repeat step S201 until all enable tests of the running states have been performed, set the enable test completion flag of the device under test to valid, and the link recovery state machine enters the test completion state from the enable test selection state, and outputs the enable test result.

5. The FC port link recovery state machine operation detection method according to claim 4, characterized in that: In step S201, when the enablement test of a certain operation state is not performed, the operation state that is not performed the enablement test enters the corresponding enablement test state from the enablement test selection state, and the enablement of the device under test in the operation state is tested.

6. The FC port link recovery state machine operation detection method according to claim 5, characterized in that: In step S2, the multiple operating states include LR sending state, LR receiving state, and LRR receiving state; Among them, the enabling test method of the LR sending state running state is: Define the buffer-to-buffer credit value as N, the first test port continuously sends N SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port; The second test port does not send R_RDY to the second FC port within the set time; If the LR primitive sent by the second FC port is detected after the set time, it is determined that the enable test in the running state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state, and outputs the enable test result; If the LR primitive sent by the second FC port is not detected after the set time, it is determined that the enable test in the running state has not passed, and the enable test state of the running state returns to the initial state, reports an enable error signal and sets the test completion flag to be valid; The method for enabling the test of the LR receiving state is: Define the buffer-to-buffer credit value as N, the first test port continuously sends N SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port; The second test port does not send R_RDY to the second FC port within the set time. After detecting the LR primitive sent by the second FC port after the set time, the second test port sends the LR primitive to the second FC port. If the LRR primitive sent by the second FC port is detected, it is determined that the enable test in the running state has passed, the link recovery state machine jumps from the enable test state to the enable test selection state, and outputs the enable test result; If the LR primitive sent by the second FC port is not detected, it is determined that the enable test in the running state has not passed, and the enable test state of the running state returns to the initial state, reports an enable error signal and sets the test completion flag to be valid; The method for enabling the test of the LRR receiving state is: Define the buffer-to-buffer credit value as N, the first test port continuously sends N SOFi3 data frames to the first FC port, which are transmitted from the first FC port to the second test port via the second FC port; The second test port does not send R_RDY to the second FC port within the set time; after detecting the LR primitive sent by the second FC port after the set time, the second test port sends the LRR primitive to the second FC port; If the IDLE primitive sent by the second FC port is detected, it is determined that the enable test in the running state has passed, and the link recovery state machine jumps from the enable test state to the enable test selection state, and outputs the enable test result; If the IDLE primitive sent by the second FC port is not detected, it is determined that the enable test in the running state has failed, and the enable test state of the running state returns to the initial state, reporting an enable error signal and setting the test completion flag to valid.

7. The FC port link recovery state machine operation detection method according to claim 1, characterized in that: In step S3, the method for judging the primitive test completion flags of multiple primitives in the corresponding running state is: S301, for primitives that have not been tested in the running state, enter the primitive test state corresponding to the primitive to perform primitive testing, and after the test is completed, set the primitive test completion flag of the primitive to be valid; S302. Repeat step S301 until all primitive tests in the running state have been performed; set the primitive test completion flag of the running state to valid, and the link recovery state machine returns from the primitive test state to the primitive test selection state. If all primitive tests have been completed, return from the primitive test selection state to the enable test selection state and output the running state test result.

8. The FC port link recovery state machine operation detection method according to claim 7, characterized in that: In step S301, the primitive test method is: In the running state, the second test port sends the corresponding primitive to the second FC port according to the current primitive test state; If the response made by the FC port meets the test judgment rules in the primitive test state, it indicates that the primitive test is normal in this running state, and the primitive test completion flag of the primitive is set to valid, and the link recovery state machine returns from the primitive test state to the primitive test selection state; If all the corresponding primitive tests are completed, the primitive test selection state returns to the enable test selection state and outputs the primitive test results; Otherwise, the primitive test is abnormal in the running state, and the link recovery state machine returns from the primitive test state to the enable test state, reports an enable error signal and sets the test completion flag to be valid.

9. The FC port link recovery state machine operation detection method according to claim 1, characterized in that: In step S5, the operation results of the link recovery state machine include: outputting the corresponding test results according to the test completion flag in the corresponding state and the related primitive test completion flag; if a start test signal is received, the test completion flag is set to invalid, and the link recovery state machine returns to the initial state; otherwise, the test completion flag is set to valid, and the link recovery state machine stays in the test completion state.

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