Display substrate and display device

Abstract

The display substrate and the display device are provided. The display substrate comprises a first sub-pixel and a third sub-pixel, the first sub-pixel comprises a first data line pattern, and the third sub-pixel comprises a third data line pattern; the first sub-pixel and the third sub-pixel each comprise a sixth transistor and an anode pattern; a second electrode of the sixth transistor is electrically connected with the corresponding anode pattern; the third sub-pixel further comprises a fourth conductive connection part, the fourth conductive connection part, the first data line pattern and the third data line pattern are located on the same layer; in the third sub-pixel, a normal projection of the anode pattern on a base at least partially overlaps with a normal projection of the third data line pattern on the base, and a normal projection of a first data line pattern adjacent to the third data line pattern in a first direction on the base at least partially overlaps with the normal projection of the third data line pattern on the base.

Description

[0001] This application is a divisional application of Chinese patent application No. 202080001756.1, filed on August 31, 2020. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0003] AMOLED (Active-matrix Organic Light-Emitting Diode) displays offer numerous advantages, including self-illumination, ultra-thinness, fast response time, high contrast, and wide viewing angles, making them a widely popular type of display device. An AMOLED display comprises multiple pixel driving circuits and multiple light-emitting elements. The pixel driving circuits drive the corresponding light-emitting elements to emit light, thereby enabling the AMOLED display to perform its display function.

[0004] When driving the light-emitting element to emit light, the pixel driving circuit includes low-frequency driving mode and high-frequency driving mode. When driving the light-emitting element with low-frequency driving mode, the data writing time of each row of pixel driving circuits to control the pixel is relatively long. When driving the light-emitting element with high-frequency driving mode, the data writing time of each row of pixels is compressed, so that the data writing time of each row of pixel driving circuits to control the pixel is shorter. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display substrate and a display device.

[0006] A first aspect of this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate, the plurality of sub-pixels comprising:

[0007] A first sub-pixel and a second sub-pixel are arranged along a second direction. The first sub-pixel includes a first data line pattern, and the second sub-pixel includes a second data line pattern. The first data line pattern is configured to provide a first data signal to the first sub-pixel, and the second data line pattern is configured to provide a second data signal to the second sub-pixel.

[0008] At least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction. The first data line pattern is located on a first side of the first sub-pixel in the same column extending along the second direction, and the second data line pattern is located on a second side of the second sub-pixel in the same column extending along the second direction. The first side and the second side are opposite to each other along a first direction, and the first direction intersects with the second direction.

[0009] The first sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0010] In the first sub-pixel, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction at least partially overlaps with the orthographic projection of the data line pattern on the substrate.

[0011] Optionally, in the first sub-pixel, the anode pattern does not overlap with the first data line pattern.

[0012] Optionally, the second sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0013] In the second sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0014] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the first data line pattern on the substrate, and the orthographic projection of the data line pattern adjacent to the first data line pattern along the first direction on the substrate at least partially overlaps with the orthographic projection of the data line pattern on the substrate.

[0015] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern on the substrate, and at least partially overlaps with the orthographic projections of the solid portion and the hollow portion on the substrate, respectively.

[0016] Optionally, the plurality of sub-pixels further include:

[0017] The third sub-pixel and the fourth sub-pixel are arranged along the second direction. Along the first direction, the third sub-pixel is located in the same row as the first sub-pixel, and the fourth sub-pixel is located in the same row as the second sub-pixel.

[0018] The third sub-pixel includes a third data line pattern, the fourth sub-pixel includes a fourth data line pattern, at least a portion of the third data line pattern and at least a portion of the fourth data line pattern both extend along a second direction, the third data line pattern is located on the second side of the same column of third sub-pixels extending along the second direction, and the fourth data line pattern is located on the first side of the same column of fourth sub-pixels extending along the second direction.

[0019] The third sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0020] In the third sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0021] The orthographic projection of the anode pattern on the substrate overlaps at least partially with the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate.

[0022] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern on the substrate, and at least partially overlaps with the orthographic projection of the data line pattern adjacent to the third data line pattern along the first direction on the substrate.

[0023] Optionally, the fourth sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0024] In the fourth sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0025] The orthographic projection of the anode pattern onto the substrate at least partially overlaps with the orthographic projection of the solid portion onto the substrate;

[0026] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern on the substrate, and at least partially overlaps with the orthographic projection of the data line pattern adjacent to the third data line pattern along the first direction on the substrate.

[0027] Optionally, in the fourth sub-pixel, the orthographic projection of the anode pattern onto the substrate does not overlap with the orthographic projection of the fourth data line pattern onto the substrate.

[0028] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include:

[0029] A power signal line pattern, at least a portion of which extends along the second direction;

[0030] A power compensation pattern, at least a portion of which extends along the first direction, wherein the power signal line pattern and the power compensation pattern are both located on the side of the first data line pattern, the second data line pattern, the third data line pattern and the fourth data line pattern close to the substrate;

[0031] The power compensation pattern is electrically connected to the power signal line pattern in its corresponding sub-pixel and the power signal line pattern in the adjacent sub-pixel along the first direction.

[0032] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: a reset signal line pattern, a gate line pattern, and a light emission control signal line pattern distributed along a second direction; at least a portion of the reset signal line pattern extends along a first direction, at least a portion of the gate line pattern extends along the first direction, and at least a portion of the light emission control signal line pattern extends along the first direction; in the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the orthographic projection of the power compensation pattern on the substrate is located between the orthographic projection of the gate line pattern on the substrate and the orthographic projection of the light emission control signal line pattern on the substrate.

[0033] Optionally, in the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel, the power signal line pattern in each sub-pixel includes: a power main body portion and a power protrusion portion electrically connected, at least a portion of the power protrusion portion extending along the second direction, and a gap between the power protrusion portion and the power main body portion;

[0034] The first end of the power compensation pattern is electrically connected to the power protrusion in its corresponding sub-pixel; the second end of the power compensation pattern is electrically connected to the main power body in the adjacent sub-pixel along the first direction.

[0035] Optionally, in the first sub-pixel, the orthographic projection of the power supply protrusion on the substrate overlaps with the orthographic projection of the first data line pattern on the substrate, and the orthographic projection of the power supply body portion on the substrate at least partially overlaps with the orthographic projection of the adjacent data line pattern along the first direction on the substrate.

[0036] Optionally, in the second sub-pixel, the orthographic projection of the power supply protrusion on the substrate does not overlap with the orthographic projection of the second data line pattern on the substrate.

[0037] Optionally, in the third sub-pixel, the orthographic projection of the power supply protrusion on the substrate does not overlap with the orthographic projection of the third data line pattern on the substrate.

[0038] Optionally, in the fourth sub-pixel, the orthographic projection of the power supply protrusion on the substrate overlaps with the orthographic projection of the fourth data line pattern on the substrate, and the orthographic projection of the power supply body portion on the substrate overlaps with the orthographic projection of the adjacent data line pattern along the first direction on the substrate.

[0039] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: an initialization signal line pattern, a second transistor, and a second conductive connection portion;

[0040] At least a portion of the initialization signal line pattern extends along the second direction, and the initialization signal line pattern is used to transmit an initialization signal;

[0041] The first terminal of the second transistor is electrically connected to the initialization signal line pattern through the second conductive connection portion, and the second terminal of the second transistor is electrically connected to the gate of the driving transistor;

[0042] In the first sub-pixel, the orthographic projection of the second conductive connection portion on the substrate overlaps with the orthographic projection of the first data line pattern on the substrate;

[0043] In the second sub-pixel, the orthographic projection of the second conductive connection portion on the substrate does not overlap with the orthographic projection of the second data line pattern on the substrate;

[0044] In the third sub-pixel, the orthographic projection of the second conductive connection portion on the substrate does not overlap with the orthographic projection of the third data line pattern on the substrate;

[0045] In the fourth sub-pixel, the orthographic projection of the second conductive connection portion on the substrate overlaps with the orthographic projection of the fourth data line pattern on the substrate.

[0046] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: an initialization signal line pattern, a shielding pattern, a driving transistor, and a second transistor;

[0047] In the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the first terminal of the second transistor is electrically connected to the initialization signal line pattern, and the second terminal of the second transistor is electrically connected to the gate of the driving transistor.

[0048] The shielding pattern is electrically connected to the power signal line pattern in the display substrate, and the orthographic projection of the shielding pattern on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second transistor on the substrate.

[0049] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: a first conductive connection portion, a fifth conductive connection portion, and a data writing transistor.

[0050] In the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the second electrode of the second transistor is electrically connected to the gate of the driving transistor through the fifth conductive connection portion;

[0051] The first conductive connection portion is electrically connected to the first terminal of the data writing transistor; the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor.

[0052] The orthographic projection of the shielding pattern on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the substrate.

[0053] Optionally, at least a portion of the shielding pattern is projected onto the substrate in an orthographic projection between the first conductive connection portion and the fifth conductive connection portion on the substrate.

[0054] Optionally, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include: a light-emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern, a light-emitting control signal line pattern, and a power signal line pattern; at least a portion of the initialization signal line pattern, at least a portion of the reset signal line pattern, at least a portion of the gate line pattern, and at least a portion of the light-emitting control signal line pattern extend along the first direction, and at least a portion of the power signal line pattern extends along the second direction;

[0055] The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each further include: a first transistor, a second transistor, a driving transistor, a data writing transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a storage capacitor;

[0056] In each sub-pixel, the gate of the driving transistor is electrically connected to the second terminal of the first transistor, the first terminal of the driving transistor is electrically connected to the second terminal of the fifth transistor, and the second terminal of the driving transistor is electrically connected to the first terminal of the first transistor.

[0057] The gate of the first transistor is electrically connected to the gate line pattern;

[0058] The gate of the second transistor is electrically connected to the reset signal line pattern, the first terminal of the second transistor is electrically connected to the initialization signal line pattern, and the second terminal of the second transistor is electrically connected to the gate of the driving transistor.

[0059] The gate of the data writing transistor is electrically connected to the gate line pattern, the first terminal of the data writing transistor is electrically connected to the data line pattern in the sub-pixel, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor.

[0060] The gate of the fifth transistor is electrically connected to the light-emitting control signal line pattern, and the first terminal of the fifth transistor is electrically connected to the power supply signal line pattern.

[0061] The gate of the sixth transistor is electrically connected to the light-emitting control signal line pattern, the first terminal of the sixth transistor is electrically connected to the second terminal of the driving transistor, and the second terminal of the sixth transistor is electrically connected to the light-emitting element.

[0062] The gate of the seventh transistor is electrically connected to the reset signal line pattern in the next sub-pixel adjacent to the second direction, the first terminal of the seventh transistor is electrically connected to the initialization signal line pattern in the next sub-pixel adjacent to the second direction, and the second terminal of the seventh transistor is electrically connected to the light-emitting element.

[0063] The first plate of the storage capacitor is reused as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line.

[0064] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate.

[0065] Based on the above-described technical solution for the display substrate, a third aspect of this disclosure provides a method for manufacturing a display substrate, comprising: fabricating an array of sub-pixels on a substrate, wherein the array of sub-pixels includes:

[0066] A first sub-pixel and a second sub-pixel are arranged along a second direction. The first sub-pixel includes a first data line pattern, and the second sub-pixel includes a second data line pattern. The first data line pattern is configured to provide a first data signal to the first sub-pixel, and the second data line pattern is configured to provide a second data signal to the second sub-pixel.

[0067] At least a portion of the first data line pattern and at least a portion of the second data line pattern both extend along a second direction. The first data line pattern is located on a first side of the first sub-pixel in the same column extending along the second direction, and the second data line pattern is located on a second side of the second sub-pixel in the same column extending along the second direction. The first side and the second side are opposite to each other along a first direction, and the first direction intersects with the second direction.

[0068] The first sub-pixel includes a sixth transistor, and a third conductive connection portion, a fourth conductive connection portion, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion;

[0069] In the first sub-pixel, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction at least partially overlaps with the orthographic projection of the data line pattern on the substrate. Attached Figure Description

[0070] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0071] Figure 1a This is a schematic diagram of sub-pixel layout in related technologies;

[0072] Figure 1b for Figure 1a A schematic diagram of the layout of the active layer;

[0073] Figure 1c for Figure 1a A schematic diagram of the layout of the first gate metal layer;

[0074] Figure 1d for Figure 1a Schematic diagram of the layout of the second gate metal layer;

[0075] Figure 1e for Figure 1a Schematic diagram of the layout of the central source drain metal layer;

[0076] Figure 1f This is a cross-sectional schematic diagram of the anode pattern in the related technology;

[0077] Figure 2 A circuit diagram of a sub-pixel driving circuit provided in an embodiment of this disclosure;

[0078] Figure 3 This is a timing diagram of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0079] Figure 4 This is a schematic diagram of the first layout of sub-pixels provided in an embodiment of the present disclosure;

[0080] Figure 5 This is a schematic diagram of the second layout of sub-pixels provided in an embodiment of the present disclosure;

[0081] Figure 6 for Figure 5 A schematic diagram showing the layout of the active layer and the first gate metal layer;

[0082] Figure 7 for Figure 5 Schematic diagram of the layout of the second gate metal layer;

[0083] Figure 8 for Figure 5 A schematic diagram of the layout of the first source / drain metal layer in the middle;

[0084] Figure 9 for Figure 5 A schematic diagram of the structure of the power supply compensation diagram;

[0085] Figure 10 for Figure 5 A schematic diagram of the layout of the first and second source / drain metal layers in the middle;

[0086] Figure 11 for Figure 5 A schematic diagram of the layout of the second source / drain metal layer in the middle;

[0087] Figure 12 This is a layout diagram for eight sub-pixels;

[0088] Figure 13a for Figure 12 A schematic diagram of the cross-section along the A1A2 direction;

[0089] Figure 13b for Figure 12 A schematic diagram of the cross-section along the B1B2 direction;

[0090] Figure 13c for Figure 12 A schematic diagram of the cross-section along the C1C2 direction;

[0091] Figure 13d for Figure 12 A schematic diagram of the cross-section along the D1D2 direction;

[0092] Figure 14 for Figure 12 A schematic diagram of the layout of the two source / drain metal layers and the anode layer;

[0093] Figure 15 This is a schematic diagram of the layout of the second source / drain metal layer and the anode layer provided in an embodiment of this disclosure;

[0094] Figure 16 for Figure 12 A schematic diagram of the layout of the active layer;

[0095] Figure 17 for Figure 12 A schematic diagram of the layout of the first gate metal layer;

[0096] Figure 18 for Figure 12 Schematic diagram of the layout of the second gate metal layer;

[0097] Figure 19 for Figure 12 A schematic diagram of the layout of the first source / drain metal layer. Detailed Implementation

[0098] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0099] The structure of an AMOLED display panel includes: a substrate, multiple sub-pixel driving circuits disposed on the substrate, and multiple light-emitting elements disposed on the side of the sub-pixel driving circuits facing away from the substrate. Each light-emitting element corresponds to a sub-pixel driving circuit, and the sub-pixel driving circuit is used to drive the corresponding light-emitting element to emit light, thereby realizing the display function of the display panel.

[0100] In related technologies, the sub-pixel driving circuit generally includes multiple thin-film transistors, such as... Figure 1a As shown, Figure 1a The diagram illustrates the specific layout of the seven thin-film transistors Q1 to Q7 in the sub-pixel driving circuit. When arranged in this manner, the sub-pixel driving circuit includes... Figure 1b The active layer shown is as follows: Figure 1c The first metal layer shown, as Figure 1d The second metal layer shown, and as shown Figure 1e The third metal layer shown; the active layer includes active patterns (such as those for forming the channel regions of each thin-film transistor) for forming the channel regions of each thin-film transistor. Figure 1b The portion within the dashed box in the image), and the doped active pattern (such as...) electrically connected to the active pattern and having conductive properties. Figure 1b The first metal layer includes the gate of each thin-film transistor, the scan signal line GATE electrically connected to the gate, one electrode CE1 of the storage capacitor in the sub-pixel driving circuit, the reset signal line RST, and the light emission control signal line EM; the second metal layer includes the initialization signal line VINT, and the other electrode CE2 of the storage capacitor in the sub-pixel driving circuit; the third metal layer includes the data line DATA, the power signal line VDD, and some conductive connections (such as those marked 341~343).

[0101] It is worth noting that, for example Figure 1a As shown, when laying out the sub-pixel driving circuit, in order to realize the electrical connection between functional graphics set in different layers, some vias (such as marked: 381~388) can also be set.

[0102] With the development of AMOLED technology, the requirements for display effects are becoming increasingly stringent. AMOLED display products have many performance specifications, and color deviation is one of the important parameters.

[0103] like Figure 1f As shown, due to the structural differences in the film layers beneath the planarization layer PLN, height differences occur at different locations above the planarization layer PLN. Furthermore, the source / drain metal pattern 344 is relatively thick, making this problem particularly pronounced at locations with the active / drain metal pattern 344. If there is no source / drain metal pattern 344 below the anode pattern 70', the anode pattern 70' will be relatively flat. If there is an active / drain metal pattern 344 on one side of the anode pattern 70' but not on the other, it will cause a height difference between the two sides of the anode pattern, causing the anode pattern 70 to "tilt," resulting in inconsistent light intensity emitted by a single sub-pixel to the left and right sides. Moreover, because the anode patterns of different color sub-pixels "tilt" in different directions, the light intensity emitted by various sub-pixels to the left and right sides is mismatched. In this case, the display panel experiences a large viewing angle color shift, appearing visually as if one side is reddish and the other bluish.

[0104] It is evident that the design of the source / drain metal pattern 344 below the anode pattern has a significant impact on the color shift of the display panel. The position of the passive drain metal pattern 344 is lower than that of the anode pattern 70, while the position of the active drain metal pattern 344 is higher. The flatness of the anode pattern directly affects pixel emission and determines the color shift characteristics of the panel.

[0105] In related technologies, the layout of the anode pattern causes it to be "tilted," resulting in color shift in the displayed product.

[0106] like Figures 12-15 As shown, this disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels arrayed on the substrate, the plurality of sub-pixels including:

[0107] A first sub-pixel M1 and a second sub-pixel M2 are arranged along a second direction. The first sub-pixel M1 includes a first data line pattern 981, and the second sub-pixel M2 includes a second data line pattern 982. The first data line pattern 981 is configured to provide a first data signal to the first sub-pixel M1, and the second data line pattern 982 is configured to provide a second data signal to the second sub-pixel M2.

[0108] At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 both extend along a second direction. The first data line pattern 981 is located on a first side of the first sub-pixel M1 in the same column extending along the second direction, and the second data line pattern 982 is located on a second side of the second sub-pixel M2 in the same column extending along the second direction. The first side and the second side are opposite to each other along a first direction, and the first direction intersects with the second direction.

[0109] The first sub-pixel M1 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964.

[0110] In the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent to the second data line pattern 982 along the first direction on the substrate.

[0111] like Figure 15 As shown in the figure, the first strip-shaped portion 9642a and the second strip-shaped portion 9642b are illustrated.

[0112] like Figure 14 As shown in the figure, the first offset portion 981a and the third offset portion 983a are illustrated.

[0113] Specifically, the display substrate includes a plurality of sub-pixels arrayed on a substrate, the plurality of sub-pixels being divisible into multiple rows of sub-pixels and multiple columns of sub-pixels. The multiple rows of sub-pixels are arranged along a second direction, and each row of sub-pixels includes a plurality of sub-pixels arranged sequentially along a first direction. The multiple columns of sub-pixels are arranged along the first direction, and each column of sub-pixels includes a plurality of sub-pixels arranged sequentially along a second direction.

[0114] For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0115] At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 both extend along the second direction. The first data line patterns 981 of each first sub-pixel M1 located in the same column of sub-pixels are sequentially electrically connected to form a single structure. The second data line patterns 982 of each second sub-pixel M2 located in the same column of sub-pixels are sequentially electrically connected to form a single structure.

[0116] For example, such as Figure 15 As shown, the first data line pattern 981 is: along the second direction, the data line portion between the current data writing position of the first sub-pixel M1 (such as the position where the data line protrusion 9802 is located) and the data writing position of the adjacent first sub-pixel M1 in the next row.

[0117] For example, in the same column of subpixels, the first subpixel M1 and the second subpixel M2 are alternately set.

[0118] For example, in the same column of sub-pixels, the first sub-pixel M1 is the odd-numbered sub-pixel, which receives a first data signal provided by the first data line pattern 981 included therein, and the second sub-pixel M2 is the even-numbered sub-pixel, which receives a second data signal provided by the second data line pattern 982 included therein.

[0119] For example, the first side is set as Figure 5 The right side of the middle, the second side is Figure 5 On the left side of the same column of sub-pixels, the first data line pattern 981 is located on the first side of the same column of sub-pixels, and the second data line pattern 982 is located on the second side of the same column of sub-pixels.

[0120] Both the first sub-pixel M1 and the second sub-pixel M2 include a sub-pixel driving circuit. The sub-pixel driving circuit includes a storage capacitor and multiple thin-film transistors, such as... Figure 2 and Figure 5 As shown, exemplarily, the sub-pixel driving circuit includes 7T1C, i.e., 7 transistors and a storage capacitor. The sub-pixel driving circuit is used to generate a driving signal to drive the light-emitting element to emit light.

[0121] For example, the sub-pixel driving circuit includes a driving transistor and a data writing transistor. In the first sub-pixel M1, the first terminal of the data writing transistor is electrically connected to the first data line pattern 981. In the second sub-pixel M2, the first terminal of the data writing transistor is electrically connected to the second data line pattern 982. In each sub-pixel, the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor, and the data writing transistor is capable of transmitting the data signal received at its first terminal to the first terminal of the driving transistor.

[0122] Within the same column of sub-pixels, the data line patterns connected to the first terminals of the data writing transistors in adjacent sub-pixels are different. More specifically, within the same column of sub-pixels, the first terminal of the data writing transistor in one of the adjacent sub-pixels is electrically connected to the first data line pattern 981, and the first terminal of the data writing transistor in the other adjacent sub-pixel is electrically connected to the second data line pattern 982.

[0123] Each sub-pixel includes a light-emitting element located on the side of the sub-pixel driving circuit facing away from the substrate. The light-emitting element comprises an anode pattern, a light-emitting functional layer, and a cathode, sequentially stacked along a direction away from the substrate. The anode pattern is electrically connected to the sub-pixel driving circuit of its corresponding sub-pixel and receives a driving signal provided by that circuit. The light-emitting functional layer includes an organic light-emitting material layer. In addition, the light-emitting functional layer may also include common layers of an entire structure such as an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL). The cathode is electrically connected to a negative power supply signal line in the display substrate and receives a negative power supply signal provided by that line. The light-emitting functional layer emits light under the combined action of the anode pattern and the cathode, realizing the display function of the display substrate.

[0124] like Figure 12 , Figure 13a and Figure 15 As shown, each sub-pixel in the display substrate includes a sixth transistor T6. The gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93. The first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor. The orthographic projection of the second electrode of the sixth transistor T6 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have a third overlapping region. The second electrode of the sixth transistor T6 and the third conductive connection portion 963 are electrically connected through a first via 61 disposed in the third overlapping region. The third conductive connection portion 963 is located in the... The orthographic projection on the substrate and the orthographic projection of the fourth conductive connection 964 on the substrate have a fourth overlapping region. The third conductive connection 963 and the fourth conductive connection 964 are electrically connected through a second via 62 provided in the fourth overlapping region. The orthographic projection of the fourth conductive connection 964 on the substrate and the orthographic projection of the anode pattern (e.g., the first anode pattern 71 to the eighth anode pattern 78) on the substrate have a fifth overlapping region. The fourth conductive connection 964 and the anode pattern are electrically connected through a third via 63 provided in the fifth overlapping region.

[0125] During the light-emitting period, the sixth transistor T6 transmits the driving signal output from the second electrode of the driving transistor to the anode of the light-emitting element through the third conductive connection 963 and the fourth conductive connection 964 in sequence.

[0126] By setting the second electrode of the sixth transistor T6 to be electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964 in sequence, the electrical connection performance between the second electrode of the sixth transistor T6 and the anode pattern is better guaranteed.

[0127] For example, such as Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in the first sub-pixel M1, the fourth conductive connection portion 964 includes a solid portion; the orthographic projection of the solid portion on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate; the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the first data line pattern 981 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate.

[0128] For example, in the first sub-pixel M1, the light-emitting element includes a first light-emitting element, which includes a first anode pattern 71, a first light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the first light-emitting element includes a red light-emitting element.

[0129] For example, in the first sub-pixel M1, the orthographic projection of the solid portion on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion on the substrate and the orthographic projection of the first anode pattern 71 on the substrate have the fifth overlapping region.

[0130] For example, the orthographic projection of the first anode pattern 71 on the substrate does not overlap with the orthographic projection of the first data line pattern 981 on the substrate, the orthographic projection of the first anode pattern 71 on the substrate does not overlap with the orthographic projection of the third data line pattern 983 adjacent along the first direction on the substrate, and the orthographic projection of the first anode pattern 71 on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 adjacent along the second direction on the substrate.

[0131] For example, the orthographic projection of the first side portion of the first anode pattern 71 on the substrate overlaps with the orthographic projection of the second data line pattern 982 adjacent along the second direction on the substrate; the orthographic projection of the second side portion of the first anode pattern 71 on the substrate overlaps with the orthographic projection of the eighth data line pattern 988 adjacent along the first direction of the second data line pattern 982 on the substrate; the first side portion and the second side portion are disposed opposite to each other along the first direction.

[0132] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, in the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate is at least partially overlapped with the orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the anode pattern on the substrate is at least partially overlapped with the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction on the substrate; so that the second data line pattern 982 and its adjacent data line patterns can compensate for the step difference generated below the anode pattern (such as the first anode pattern 71), so that the anode pattern can be formed on a relatively flat surface, thereby making the anode pattern have high flatness, ensuring that the light emission intensity of the sub-pixel is consistent in all directions, and effectively improving the color shift problem generated by the display product when the display substrate is applied to the display product.

[0133] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the first sub-pixel M1, the anode pattern does not overlap with the first data line pattern 981.

[0134] Specifically, in the first sub-pixel M1, the first anode pattern 71 and the first data line pattern 981 do not overlap.

[0135] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, the second sub-pixel M2 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964.

[0136] In the second sub-pixel M2, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0137] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the first data line pattern 981 on the substrate, and the orthographic projection of the data line pattern adjacent to the first data line pattern 981 along the first direction at least partially overlaps with the orthographic projection of the data line pattern on the substrate.

[0138] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate, and at least partially overlaps with the orthographic projections of the solid portion 9641 and the hollow portion 9642 on the substrate, respectively.

[0139] Specifically, in the second sub-pixel M2, the light-emitting element includes a second light-emitting element, which comprises a second anode pattern 72, a second light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the second light-emitting element includes a blue light-emitting element.

[0140] For example, in the second sub-pixel M2, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the second anode pattern 72 on the substrate have the fifth overlapping region.

[0141] For example, the orthographic projection of the second side portion of the second anode pattern 72 onto the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 in its corresponding sub-pixel onto the substrate; the orthographic projection of the second side portion of the second anode pattern 72 onto the substrate overlaps with the orthographic projections of the solid portion and the hollow portion onto the substrate; the orthographic projection of the first side portion of the second anode pattern 72 onto the substrate overlaps with the orthographic projection of the first data line pattern 981 adjacent along the second direction onto the substrate, and also overlaps with the orthographic projection of the third data line pattern 983 adjacent to the first data line pattern 981 along the second direction onto the substrate. The first side portion and the second side portion are disposed opposite each other along the first direction.

[0142] For example, the hollow portion 9642 is formed in a square shape, and the orthographic projection of the second side of the second anode pattern 72 on the substrate overlaps with the orthographic projections of the two opposite sides of the hollow portion 9642 along the first direction on the substrate. For example, the orthographic projection of the second side of the second anode pattern 72 on the substrate overlaps with the orthographic projections of the two opposite sides of the hollow portion 9642 along the second direction on the substrate.

[0143] In the display substrate provided in the above embodiments, the fourth conductive connection portion 964 and the second data line pattern 982 can compensate for the step difference generated below the second anode pattern 72 by the first data line pattern 981 and the adjacent data line pattern (such as the third data line pattern 983) of the first data line pattern 981, so that the second anode pattern 72 can be formed on a relatively flat surface, thereby giving the second anode pattern 72 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0144] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, the third sub-pixel M3 and the fourth sub-pixel M4 are arranged along the second direction. Along the first direction, the third sub-pixel M3 is located in the same row as the first sub-pixel M1, and the fourth sub-pixel M4 is located in the same row as the second sub-pixel M2.

[0145] The third sub-pixel M3 includes a third data line pattern 983, and the fourth sub-pixel M4 includes a fourth data line pattern 984. At least a portion of the third data line pattern 983 and at least a portion of the fourth data line pattern 984 both extend along a second direction. The third data line pattern 983 is located on the second side of the same column of third sub-pixels M3 extending along the second direction, and the fourth data line pattern 984 is located on the first side of the same column of fourth sub-pixels M4 extending along the second direction.

[0146] The third sub-pixel M3 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964.

[0147] In the third sub-pixel M3, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0148] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate.

[0149] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 on the substrate, and the orthographic projection of the data line pattern adjacent to the third data line pattern 983 along the first direction at least partially overlaps with the orthographic projection of the data line pattern on the substrate.

[0150] Specifically, at least a portion of the third data line pattern 983 and at least a portion of the fourth data line pattern 984 both extend along the second direction. The third data line patterns 983 included in each third sub-pixel M3 located in the same column of sub-pixels are sequentially electrically connected to form a single structure. The fourth data line patterns 984 included in each fourth sub-pixel M4 located in the same column of sub-pixels are sequentially electrically connected to form a single structure. The third data line pattern 983 is configured to provide a third data signal to the third sub-pixel M3, and the fourth data line pattern 984 is configured to provide a fourth data signal to the fourth sub-pixel M4.

[0151] For example, along the first direction, the third sub-pixel M3 is located in the same row as the first sub-pixel M1, and the fourth sub-pixel M4 is located in the same row as the second sub-pixel M2.

[0152] For example, in the same column of sub-pixels, the third sub-pixel M3 and the fourth sub-pixel M4 are alternately set.

[0153] Similarly, both the third sub-pixel M3 and the fourth sub-pixel M4 include sub-pixel driving circuits. In the third sub-pixel M3, the first terminal of the data writing transistor is electrically connected to the third data line pattern 983. In the fourth sub-pixel M4, the first terminal of the data writing transistor is electrically connected to the fourth data line pattern 984. In each sub-pixel, the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor, and the data writing transistor can transmit the data signal received at its first terminal to the first terminal of the driving transistor.

[0154] For example, the first side is set as Figure 5 The right side of the middle, the second side is Figure 5 The third data line pattern 983 is located on the second side of the third sub-pixel in the same column extending along the second direction, and the fourth data line pattern 984 is located on the first side of the fourth sub-pixel in the same column extending along the second direction.

[0155] For example, among sub-pixels located in the same row along the first direction, the first data line pattern 981 and the third data line pattern 983 are both located between the first sub-pixel M1 to which the first data line pattern 981 belongs and the third sub-pixel M3 to which the third data line pattern 983 belongs. Among sub-pixels located in the same row along the first direction, the second data line pattern 982 and the fourth data line pattern 984 are both located between the second sub-pixel M2 to which the second data line pattern 982 belongs and the fourth sub-pixel M4 to which the fourth data line pattern 984 belongs.

[0156] Both the third sub-pixel M3 and the fourth sub-pixel M4 include: the power signal line pattern and the power compensation pattern. The structure of the power signal line pattern is the same as that of the power signal line pattern in the first sub-pixel M1 and the second sub-pixel M2, and the structure of the power compensation pattern is the same as that of the power compensation pattern in the first sub-pixel M1 and the second sub-pixel M2.

[0157] It is worth noting that the sub-pixel driving circuits included in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 have the same structure. The difference between the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 lies in the arrangement of the data lines and the structure of the light-emitting elements.

[0158] In the third sub-pixel M3, the light-emitting element includes a third light-emitting element, which comprises a third anode pattern 73, a third light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the third light-emitting element includes a green light-emitting element.

[0159] For example, in part of the third sub-pixel M3, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third anode pattern 73 on the substrate have the fifth overlapping region.

[0160] For example, the orthographic projection of the second side of the third anode pattern 73 on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 in its corresponding sub-pixel on the substrate; the orthographic projection of the second side of the third anode pattern 73 on the substrate at least partially overlaps with the orthographic projection of the first data line pattern 981 adjacent along the first direction on the substrate; the orthographic projection of the first side of the third anode pattern 73 on the substrate overlaps with the orthographic projection of the solid portion on the substrate and the orthographic projection of the hollow portion on the substrate; the first side and the second side are disposed opposite to each other along the first direction.

[0161] For example, the hollow portion 9642 is formed in the shape of a square, and the orthographic projection of the first side of the third anode pattern 73 on the substrate overlaps with the orthographic projections of the two opposite sides of the hollow portion 9642 along the first direction on the substrate.

[0162] The above configuration enables the fourth conductive connection portion 964 to compensate for the step difference generated below the third anode pattern 73 by the first data line pattern 981 and the third data line pattern 983, so that the third anode pattern 73 can be formed on a relatively flat surface, thereby giving the fifth anode pattern 75 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0163] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, the fourth sub-pixel M4 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964.

[0164] In the fourth sub-pixel M4, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642;

[0165] The orthographic projection of the anode pattern onto the substrate at least partially overlaps with the orthographic projection of the solid portion 9641 onto the substrate;

[0166] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 on the substrate, and the orthographic projection of the data line pattern adjacent to the third data line pattern 983 along the first direction at least partially overlaps with the orthographic projection of the data line pattern on the substrate.

[0167] Specifically, in the fourth sub-pixel M4, the light-emitting element includes a fourth light-emitting element, which comprises a fourth anode pattern 74, a fourth light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the fourth light-emitting element includes a green light-emitting element.

[0168] For example, in the fourth sub-pixel M4, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the fourth anode pattern 74 on the substrate have the fifth overlapping region.

[0169] For example, the orthographic projection of the second side of the fourth anode pattern 74 on the substrate at least partially overlaps with the orthographic projection of the third data line pattern 983 adjacent to it along the second direction on the substrate; the orthographic projection of the second side of the fourth anode pattern 74 on the substrate at least partially overlaps with the orthographic projection of the first data line pattern 981 adjacent to the third data line pattern 983 along the first direction on the substrate; the orthographic projection of the first side of the fourth anode pattern 74 on the substrate overlaps with the orthographic projection of the solid portion on the substrate, but does not overlap with the orthographic projection of the hollow portion on the substrate; the first side and the second side are disposed opposite to each other along the first direction.

[0170] The above configuration enables the fourth conductive connection portion 964 to compensate for the step difference generated by the first data line pattern 981 and the third data line pattern 983 below the fourth anode pattern 74, so that the fourth anode pattern 74 can be formed on a relatively flat surface, thereby giving the fourth anode pattern 74 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0171] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the fourth sub-pixel M4, the orthographic projection of the anode pattern on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate.

[0172] The orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the fourth data line pattern 984 on the substrate, and the orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the second data line pattern 982 adjacent along the first direction on the substrate.

[0173] It needs to be explained, such as Figure 12 As shown, the plurality of sub-pixels further includes: a fifth sub-pixel M5, a sixth sub-pixel M6, a seventh sub-pixel M7, and an eighth sub-pixel M8; the fifth sub-pixel M5 and the sixth sub-pixel M6 are alternately arranged along the second direction, and the seventh sub-pixel M7 and the eighth sub-pixel M8 are alternately arranged along the second direction; along the first direction, the first sub-pixel M1, the third sub-pixel M3, the fifth sub-pixel M5, and the seventh sub-pixel M7 are located in the same row; along the first direction, the second sub-pixel M2, the fourth sub-pixel M4, the sixth sub-pixel M6, and the eighth sub-pixel M8 are located in the same row.

[0174] The fifth sub-pixel M5 includes a fifth data line pattern 985, the sixth sub-pixel M6 includes a sixth data line pattern 986, the seventh sub-pixel M7 includes a seventh data line pattern 987, and the eighth sub-pixel M8 includes an eighth data line pattern 988.

[0175] like Figure 12 The eight sub-pixels, from the first sub-pixel M1 to the eighth sub-pixel M8, form a repeating unit, and the display substrate includes a plurality of such repeating units.

[0176] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the fifth sub-pixel M5, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate both at least partially overlap with the orthographic projection of the anode pattern on the substrate; the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 adjacent along the first direction on the substrate.

[0177] Specifically, in the fifth sub-pixel M5, the light-emitting element includes a fifth light-emitting element, which comprises a fifth anode pattern 75, a fifth light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the fifth light-emitting element includes a blue light-emitting element.

[0178] For example, in the fifth sub-pixel M5, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the fifth anode pattern 75 on the substrate have the fifth overlapping region.

[0179] For example, the orthographic projection of the first side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the fifth data line pattern 985 in its sub-pixel on the substrate, and overlaps with the orthographic projection of the seventh data line pattern 987 adjacent to the fifth data line pattern 985 along the first direction on the substrate; the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projection of the hollow portion 9642 on the substrate; the first side and the second side are disposed opposite to each other along the first direction.

[0180] For example, the hollow portion 9642 is formed in a square shape, and the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projections of the two opposite sides of the hollow portion 9642 along the first direction on the substrate. For example, the orthographic projection of the second side of the fifth anode pattern 75 on the substrate overlaps with the orthographic projections of the two opposite sides of the hollow portion 9642 along the second direction on the substrate.

[0181] For example, in the hollow portion 9642, there is a first distance L3 between two opposite sides along the first direction, and in two adjacent sub-pixels along the first direction, the fifth data line pattern 985 and the seventh data line pattern 987 are close to each other and have a second distance L4 along the first direction, and the first distance L3 and the second distance L4 are equal.

[0182] The above configuration enables the fourth conductive connection portion 964 to compensate for the step difference generated by the fifth data line pattern 985 and the seventh data line pattern 987 below the fifth anode pattern 75, so that the fifth anode pattern 75 can be formed on a relatively flat surface, thereby giving the fifth anode pattern 75 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0183] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the sixth sub-pixel M6, the fourth conductive connection portion 964 includes a solid portion;

[0184] The orthographic projection of the solid portion onto the substrate at least partially overlaps with the orthographic projection of the anode pattern onto the substrate;

[0185] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the sixth data line pattern 986 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fourth data line pattern 984 adjacent along the first direction on the substrate.

[0186] Specifically, in the sixth sub-pixel M6, the light-emitting element includes a sixth light-emitting element, which comprises a sixth anode pattern 76, a sixth light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the sixth light-emitting element includes a red light-emitting element.

[0187] For example, in the sixth sub-pixel M6, the orthographic projection of the solid portion on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion on the substrate and the orthographic projection of the sixth anode pattern 76 on the substrate have the fifth overlapping region.

[0188] For example, the orthographic projection of the first side portion of the sixth anode pattern 76 onto the substrate at least partially overlaps with the orthographic projection of the sixth data line pattern 986 onto the substrate, and the orthographic projection of the second side portion of the sixth anode pattern 76 onto the substrate at least partially overlaps with the orthographic projection of the fourth data line pattern 984 adjacent along the first direction onto the substrate. The first side portion and the second side portion are disposed opposite to each other along the first direction.

[0189] The above configuration allows the sixth data line pattern 986 and the fourth data line pattern 984 to compensate for the step difference between them below the sixth anode pattern 76, enabling the sixth anode pattern 76 to be formed on a relatively flat surface. This results in the sixth anode pattern 76 having high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0190] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the seventh sub-pixel M7, the fourth conductive connection portion includes a solid portion and a hollow portion;

[0191] The orthographic projection of the solid portion on the substrate at least partially overlaps with the orthographic projection of the anode pattern on the substrate, while the orthographic projection of the hollow portion on the substrate does not overlap with the orthographic projection of the anode pattern on the substrate.

[0192] The orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent along the first direction on the substrate.

[0193] Specifically, in the seventh sub-pixel M7, the light-emitting element includes a seventh light-emitting element, which comprises a seventh anode pattern 77, a seventh light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the seventh light-emitting element includes a green light-emitting element.

[0194] For example, in the seventh sub-pixel M7, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the seventh anode pattern 77 on the substrate have the fifth overlapping region.

[0195] For example, the orthographic projection of the second side of the seventh anode pattern 77 onto the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 in its corresponding sub-pixel onto the substrate; the orthographic projection of the second side of the seventh anode pattern 77 onto the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent along the first direction onto the substrate; the orthographic projection of the first side of the seventh anode pattern 77 onto the substrate overlaps with the orthographic projection of the solid portion onto the substrate; the first side and the second side are disposed opposite to each other along the first direction.

[0196] The above configuration enables the fourth conductive connection portion 964 to compensate for the step difference generated by the seventh data line pattern 987 and the fifth data line pattern 985 below the seventh anode pattern 77, so that the seventh anode pattern 77 can be formed on a relatively flat surface, thereby giving the seventh anode pattern 77 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0197] like Figure 11 , Figure 12 , Figure 13a , Figure 14 and Figure 15 As shown, in some embodiments, in the eighth sub-pixel M8, the fourth conductive connection portion 964 includes a solid portion 9641 and a hollow portion 9642.

[0198] The orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the hollow portion 9642 on the substrate both overlap at least partially with the orthographic projection of the anodized pattern on the substrate.

[0199] The orthographic projection of the anode pattern on the substrate does not overlap with the orthographic projection of the eighth data line pattern 988 on the substrate, nor with the orthographic projection of the sixth data line pattern 986 adjacent along the first direction on the substrate.

[0200] Specifically, in the eighth sub-pixel M8, the light-emitting element includes an eighth light-emitting element, which comprises an eighth anode pattern 78, an eighth light-emitting functional layer, and a cathode sequentially stacked along a direction away from the substrate. For example, the eighth light-emitting element includes a green light-emitting element.

[0201] For example, in part of the eighth sub-pixel M8, the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the third conductive connection portion 963 on the substrate have the fourth overlapping region; the orthographic projection of the solid portion 9641 on the substrate and the orthographic projection of the eighth anode pattern 78 on the substrate have the fifth overlapping region.

[0202] For example, the orthographic projection of the second side of the eighth anode pattern 78 onto the substrate at least partially overlaps with the orthographic projection of the seventh data line pattern 987 adjacent to it along the second direction onto the substrate; the orthographic projection of the second side of the eighth anode pattern 78 onto the substrate at least partially overlaps with the orthographic projection of the fifth data line pattern 985 adjacent to the seventh data line pattern 987 along the first direction onto the substrate; the orthographic projection of the first side of the eighth anode pattern 78 onto the substrate overlaps with the orthographic projection of the solid portion onto the substrate, and also overlaps with the orthographic projection of the hollow portion onto the substrate; the first side and the second side are disposed opposite to each other along the first direction.

[0203] The above configuration enables the fourth conductive connection portion 964 to compensate for the step difference generated by the seventh data line pattern 987 and the fifth data line pattern 985 below the eighth anode pattern 78, so that the eighth anode pattern 78 can be formed on a relatively flat surface, thereby giving the eighth anode pattern 78 a high flatness and effectively reducing the color shift phenomenon generated by the display substrate during display.

[0204] It is worth noting that Figure 16 for Figure 12 A schematic diagram of the layout of the active layer; Figure 17 for Figure 12 A schematic diagram of the layout of the first gate metal layer; Figure 18 for Figure 12 Schematic diagram of the layout of the second gate metal layer; Figure 19 for Figure 12 A schematic diagram of the layout of the first source / drain metal layer. The active layer, the first gate metal layer, the second gate metal layer, and the first source / drain metal layer are stacked sequentially in a direction away from the substrate.

[0205] Please see Figures 2-4 This disclosure provides a display substrate, including: a substrate and an array of multiple sub-pixels distributed on the substrate. The multiple sub-pixels can be divided into multiple rows of sub-pixels arranged sequentially along a second direction and multiple columns of sub-pixels arranged sequentially along a first direction. Each sub-pixel includes: a light-emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92, and a light-emitting control signal line pattern 93.

[0206] The plurality of sub-pixels includes:

[0207] Alternating first and second sub-pixels along a second direction, the first sub-pixel includes a first data line pattern 981, and the second sub-pixel includes a second data line pattern 982. At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 extend along the second direction. The first data line pattern 981 is located on a first side of the same column of the first sub-pixels extending along the second direction, and the second data line pattern 982 is located on a second side of the same column of the second sub-pixels extending along the second direction. The first side and the second side are opposite to each other along the first direction, and the first direction intersects the second direction. For example, the first side is... Figure 4 The right side of the middle, the second side is Figure 4 On the left side of the middle.

[0208] Both the first sub-pixel and the second sub-pixel include a sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor (i.e., the third transistor T3) and a data writing transistor (i.e., the fourth transistor T4). In the first sub-pixel, the first terminal of the data writing transistor is electrically connected to the first data line pattern 981, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor. In the second sub-pixel, the first terminal of the data writing transistor is electrically connected to the second data line pattern 982, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor.

[0209] As can be seen from the specific structure of the display substrate described above, in the display substrate provided by this disclosure, in the same column of sub-pixels extending along the second direction, the first electrode of the data writing transistor of one of the adjacent sub-pixels is electrically connected to the first data line pattern 981, and the first electrode of the data writing transistor of the other adjacent sub-pixel is electrically connected to the second data line pattern 982. In the display substrate provided by this disclosure, by setting different data line patterns for the data writing transistors of adjacent sub-pixels in the same column of sub-pixels, data signals are provided by different data line patterns for adjacent sub-pixels in the same column of sub-pixels. This ensures that each sub-pixel has sufficient data signal writing time, thereby solving the problem of insufficient data signal writing time for each row of sub-pixels in high-frequency displays.

[0210] However, in the above-mentioned display substrate, since the power signal line patterns of each sub-pixel in each row of sub-pixels are independent of each other, the display uniformity of the display substrate is poor, which is not conducive to improving the display quality of the display substrate.

[0211] Please see Figure 5, Figure 12 , Figure 13c and Figure 13d This disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels arrayed on the substrate, the plurality of sub-pixels including:

[0212] A first sub-pixel M1 and a second sub-pixel M2 are alternately arranged along a second direction. The first sub-pixel M1 includes a first data line pattern 981, and the second sub-pixel M2 includes a second data line pattern 982. At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 extend along the second direction. The first data line pattern 981 is located on a first side of the first sub-pixel in the same column extending along the second direction, and the second data line pattern 982 is located on a second side of the second sub-pixel in the same column extending along the second direction. The first side and the second side are opposite to each other along a first direction, and the first direction intersects the second direction.

[0213] like Figure 5 ,like Figure 8 , Figure 10 , Figure 12 and Figure 19 As shown, both the first sub-pixel M1 and the second sub-pixel M2 include:

[0214] A power signal line pattern 91, at least a portion of which extends along the second direction;

[0215] A power compensation pattern 97, at least a portion of which extends along the first direction, wherein the power signal line pattern and the power compensation pattern are both located on the side of the first data line pattern and the second data line pattern close to the substrate, and the power compensation pattern 97 is electrically connected to the power signal line pattern 91 and the power signal line pattern 91 in the adjacent sub-pixel along the first direction.

[0216] Specifically, each sub-pixel includes the power signal line pattern 91, at least a portion of which extends along the second direction. Within the same column of sub-pixels, the power signal line patterns 91 of each sub-pixel are sequentially electrically connected, forming a single integrated structure.

[0217] The sub-pixel also includes a power compensation pattern 97. Both the power signal line pattern 91 and the power compensation pattern 97 are located on the side of the first data line pattern 981 and the second data line pattern 982 closest to the substrate. For example, an interlayer insulating layer (ILD) is provided on the side of the first data line pattern 981 and the second data line pattern 982 closest to the substrate, and the power compensation pattern 97 and the power signal line pattern 91 are both located on the surface of the ILD facing away from the substrate. This arrangement allows the power signal line pattern 91 and the power compensation pattern 97 to be disposed in the same layer. When the power signal line pattern 91 and the power compensation pattern 97 are made of the same material, they can be formed in the same patterning process, thereby simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0218] It should be noted that the power signal line pattern 91 and the power compensation pattern 97 can form the first source / drain metal layer in the display substrate. Of course, the first source / drain metal layer may also include other structures.

[0219] For example, such as Figure 13a As shown, the power signal line pattern 91 (including the third part 9130) is electrically connected to the second plate Cst2 of the storage capacitor Cst through the via Via.

[0220] like Figure 5 As shown, for example, the power compensation pattern 97 is electrically connected to the power signal line pattern 91 in its respective sub-pixel, and the power signal line pattern 91' in the adjacent sub-pixel along the first direction.

[0221] For example, the power compensation pattern 97 and the two power signal line patterns 91 that are electrically connected to each other are formed into an integral structure. It is worth noting that the integral structure includes: the power compensation pattern 97 and the power signal line patterns 91 are formed simultaneously in contact using the same material and through a single patterning process.

[0222] In the display substrate provided in this embodiment, by setting the power compensation pattern 97 to be electrically connected to the power signal line pattern 91 in its respective sub-pixel, and to the power signal line pattern 91' in the adjacent sub-pixel located in the same row along the first direction, the power signal line patterns 91 of each sub-pixel in the same row are electrically connected together, thereby reducing the overall resistance of the power signal line pattern 91 and thus improving the uniformity of the display substrate. Simultaneously, by setting the power signal line patterns 91 in each sub-pixel located in the same column to be sequentially electrically connected, all the power signal line patterns 91 in the display substrate are collectively formed into a mesh structure, further improving the display uniformity of the display substrate.

[0223] In the display substrate provided in this embodiment, by setting the power compensation pattern 97 and the power signal line pattern 91 to be located on the surface of the interlayer insulating layer (ILD) facing away from the substrate, and by forming the power signal line pattern 91 and the power compensation pattern 97 as the first source / drain metal layer in the display substrate, the power signal line pattern 91 and the power compensation pattern 97 can be formed in the same patterning process, thereby simplifying the manufacturing process of the display substrate and saving manufacturing costs. Furthermore, since the power compensation pattern 97 and the power signal line pattern 91 are made of the same source / drain metal material, the resistance of both the power compensation pattern 97 and the power signal line pattern 91 is relatively low, thereby improving the display uniformity of the display substrate.

[0224] In the display substrate provided in this embodiment, all the included power signal line patterns 91 are formed into a mesh structure, which effectively improves the stability of the power signal transmitted by the power signal line patterns. The power signal is used to supply the source of the driving transistor in the sub-pixel driving circuit, and the light-emitting current I generated by the sub-pixel driving circuit is... oled =k[(Vgs-Vth)] 2 Vgs = Vg - Vs, where Vg is the gate voltage of the driving transistor, Vs is the source voltage of the driving transistor, and Vth is the threshold voltage of the driving transistor. Therefore, the power supply signal, Vs, will affect the luminous current I. oled The size of the light source has an impact; therefore, the above configuration method, while improving the stability of the power signal line layer, better ensures the light-emitting current I. oled Its stability effectively avoids the occurrence of dynamic crosstalk.

[0225] like Figure 5 ,like Figure 8 , Figure 10 , Figure 12 and Figure 19As shown, further, both the third sub-pixel M3 and the fourth sub-pixel M4 include: the power signal line pattern and the power compensation pattern; the power compensation pattern included in the third sub-pixel M3 is electrically connected to the power signal line pattern included in the third sub-pixel M3 and the power signal line pattern in the first sub-pixel M1 adjacent along the first direction; the power compensation pattern included in the fourth sub-pixel M4 is electrically connected to the power signal line pattern included in the fourth sub-pixel M4 and the power signal line pattern in the second sub-pixel M2 adjacent along the first direction.

[0226] Specifically, both the third sub-pixel M3 and the fourth sub-pixel M4 include: the power signal line pattern and the power compensation pattern. The structure of the power signal line pattern is the same as that of the power signal line pattern in the first sub-pixel M1 and the second sub-pixel M2, and the structure of the power compensation pattern is the same as that of the power compensation pattern in the first sub-pixel M1 and the second sub-pixel M2.

[0227] like Figure 5 and Figure 8 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: a reset signal line pattern 95, a gate line pattern 92, and a light emission control signal line pattern 93 distributed along a second direction; at least a portion of the reset signal line pattern 95 extends along a first direction, at least a portion of the gate line pattern 92 extends along the first direction, and at least a portion of the light emission control signal line pattern 93 extends along the first direction.

[0228] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the orthographic projection of the power compensation pattern 97 on the substrate is located between the orthographic projection of the gate line pattern 92 on the substrate and the orthographic projection of the light emission control signal line pattern 93 on the substrate.

[0229] Specifically, the sub-pixel further includes: a reset signal line pattern 95, a gate line pattern 92, and a light emission control signal line pattern 93, sequentially distributed along the second direction. The reset signal line is used to transmit a reset signal, the gate line pattern 92 is used to transmit a scan signal, and the light emission control signal line pattern 93 is used to transmit a light emission control signal.

[0230] At least a portion of the reset signal line pattern 95 extends along a first direction, and the reset signal line patterns 95 included in each sub-pixel located in the same row along the first direction are sequentially electrically connected to form a single structure. At least a portion of the gate line pattern 92 extends along the first direction, and the gate line patterns 92 included in each sub-pixel located in the same row along the first direction are sequentially electrically connected to form a single structure. At least a portion of the light emission control signal line pattern 93 extends along the first direction, and the light emission control signal line patterns 93 included in each sub-pixel located in the same row along the first direction are sequentially electrically connected to form a single structure.

[0231] The specific layout of the power compensation pattern 97 varies. For example, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the orthographic projection of the power compensation pattern 97 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate, the orthographic projection of the power compensation pattern 97 on the substrate does not overlap with the orthographic projection of the gate line pattern 92 on the substrate, and the orthographic projection of the power compensation pattern 97 on the substrate does not overlap with the orthographic projection of the light emission control signal line pattern 93 on the substrate.

[0232] For example, the orthographic projection of the power compensation pattern 97 on the substrate is located between the orthographic projection of the gate line pattern 92 on the substrate and the orthographic projection of the light emission control signal line pattern 93 on the substrate.

[0233] For example, along the second direction, the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the gate line pattern 92 on the substrate is greater than the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the light emission control signal line pattern 93 on the substrate.

[0234] The power compensation pattern 97 is arranged in the manner described above, so that there is a large distance between the power compensation pattern 97 and the reset signal line pattern 95, the gate line pattern 92 and the light emission control signal line pattern 93, thereby avoiding increasing the load on the reset signal line pattern 95, the gate line pattern 92 and the light emission control signal line pattern 93.

[0235] In some embodiments, the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the gate line pattern 92 on the substrate is greater than a threshold; the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the light emission control signal line pattern 93 on the substrate is greater than the threshold.

[0236] For example, the threshold is 5 μm. The minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the gate line pattern 92 on the substrate is greater than 5 μm; the minimum distance between the orthographic projection of the power compensation pattern 97 on the substrate and the orthographic projection of the light emission control signal line pattern 93 on the substrate is greater than 5 μm.

[0237] The above configuration ensures that the power compensation pattern 97 is at a considerable distance from the reset signal line pattern 95, the gate line pattern 92, and the light emission control signal line pattern 93, thereby avoiding increasing the load on the reset signal line pattern 95, the gate line pattern 92, and the light emission control signal line pattern 93.

[0238] like Figure 5 , Figure 8 , Figure 10 , Figure 12 and Figure 19 As shown, in some embodiments, in the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4, the power signal line pattern 91 in each sub-pixel includes: a power main body portion (including a first portion 911 and a second portion 912) electrically connected to each other and a power protrusion portion 913.

[0239] The first end of the power compensation pattern 97 is electrically connected to the power protrusion 913; the second end of the power compensation pattern 97 is connected to the power body portion in the adjacent sub-pixel along the first direction (i.e., as shown in the image). Figure 8 The power signal line diagram 91' shows the main power supply part (electrical connection).

[0240] For example, at least a portion of the power protrusion 913 extends along the second direction, and the second end of the power compensation pattern 97 is electrically connected to the middle portion of the power protrusion 913.

[0241] The above-described configuration can shorten the length of the power compensation pattern 97, thereby effectively reducing the layout difficulty of the power compensation pattern 97.

[0242] like Figure 5 , Figure 8 , Figure 10 , Figure 12 and Figure 19 As shown, in some embodiments, at least a portion of the power protrusion 913 extends along the second direction, and a gap 50 exists between the power protrusion 913 and the power body portion.

[0243] More specifically, the power supply protrusion 913 includes a third portion 9130, a fourth portion 9131, and a fifth portion 9132; the third portion 9130 is electrically connected to the power compensation pattern 97 and extends along the second direction; the fourth portion 9131 is electrically connected to one end of the third portion 9130 and the power supply body portion, respectively; the fifth portion 9132 is electrically connected to the other end of the third portion 9130 and the power supply body portion, respectively; a gap 50 exists between the third portion 9130 and the power supply body portion.

[0244] Specifically, the power supply protrusion 913 has various specific structures. For example, the power supply protrusion 913 includes the third part 9130, the fourth part 9131, and the fifth part 9132, which are integral structures.

[0245] By configuring the fourth part 9131 to be electrically connected to one end of the third part 9130 and the power supply main body, and the fifth part 9132 to be electrically connected to the other end of the third part 9130 and the power supply main body, the connection performance between the power supply protrusion 913 and the power supply main body is better guaranteed, and the display uniformity of the display substrate is more effectively improved.

[0246] Additionally, the display substrate may also include a fingerprint recognition module. For example, the fingerprint recognition module is located on the side of the substrate facing away from the sub-pixel driving circuit. For example, the orthographic projection of the fingerprint recognition area of ​​the fingerprint recognition module onto the substrate overlaps with the orthographic projection of the gap 50 onto the substrate. During fingerprint recognition, a finger touches the side of the light-emitting element facing away from the substrate, and the light reflected by the finger passes through the gap 50 and is received by the fingerprint recognition module, thus realizing the fingerprint recognition function.

[0247] The aforementioned configuration provides a gap 50 between the third part 9130 and the power supply body, which improves the light transmittance of the display substrate. Therefore, when the display substrate provided in the above embodiment is compatible with optical fingerprint recognition technology, it can provide good conditions for the sensor to collect light signals, thereby effectively improving the speed and accuracy of fingerprint recognition.

[0248] In addition, in the display substrate provided in the above embodiments, the gap 50 is only formed on the power signal line pattern 91, and no operations such as narrowing the metal trace width, compressing the size of the light-emitting element, or compressing the size of the transistor or capacitor are performed except for the power signal line pattern 91. Therefore, the display substrate provided in the above embodiments is not likely to have a negative impact on the performance of the display substrate while improving the resolution.

[0249] like Figure 5 and Figure 9 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include a storage capacitor Cst and a driving transistor. In each sub-pixel, the first plate Cst1 of the storage capacitor Cst is electrically connected to the gate of the driving transistor, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power supply protrusion 913.

[0250] For example, the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the power supply protrusion 913 on the substrate, and the second plate Cst2 of the storage capacitor Cst and the power supply protrusion are electrically connected at the overlap.

[0251] For example, the third portion 9130 includes a first sub-portion 9130a and a second sub-portion 9130b, the first sub-portion 9130a being close to the fourth portion 9131 and the second sub-portion 9130b being close to the fifth portion 9132. On a plane parallel to the base and in a direction perpendicular to the second direction, the width L1 of the first sub-portion 9130a is greater than the width L2 of the second sub-portion 9130b.

[0252] The orthographic projection of the second plate Cst2 of the storage capacitor Cst onto the substrate overlaps with the orthographic projection of the first sub-part 9130a onto the substrate. The second plate Cst2 of the storage capacitor Cst and the first sub-part 9130a are electrically connected through a via provided at the overlap.

[0253] The above arrangement allows the second plate Cst2 of the storage capacitor Cst to form a large overlapping area with the first sub-part 9130a, thereby reducing the layout difficulty of the via. It should be noted that... Figure 13a The mark 40 in the figure represents the substrate and some membrane layers (such as buffer layers, isolation layers, etc.) set on the substrate.

[0254] like Figure 5 and Figure 9 As shown, in some embodiments, in a direction perpendicular to the first direction, the first end D of the power compensation pattern 97 is provided with a first width along the direction close to the power signal line pattern in the sub-pixel to which the first sub-pattern belongs (i.e., Figure 9 (The direction pointed to by the dashed line with the arrow) indicates that the first width gradually increases.

[0255] The above configuration not only improves the connection performance between the power compensation pattern 97 and the power signal line pattern 91, but also avoids the formation of a right-angle structure at the connection between the power compensation pattern 97 and the power signal line pattern 91, which could lead to electrostatic discharge risk.

[0256] like Figure 5 , Figure 8 , Figure 10 and Figure 12 As shown, in some embodiments, in the first sub-pixel M1, the orthographic projection of the power supply protrusion 913 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate, and the orthographic projection of the power supply body portion (including the first portion 911 and the second portion 912) on the substrate at least partially overlaps with the orthographic projection of the adjacent data line pattern (such as the third data line pattern 983) along the first direction on the substrate.

[0257] Specifically, in the display substrate, each sub-pixel includes the power signal line pattern 91, at least a portion of which extends along the second direction. In the same column of sub-pixels, the power signal line patterns 91 of each sub-pixel are sequentially electrically connected, forming a single integrated structure. The specific structure of the power signal line pattern 91 varies. For example, the power signal line pattern 91 includes a first portion 911 and a second portion 912 that are electrically connected, with the first portion 911 and the second portion 912 alternating. For example, the second portion 912 protrudes beyond the first portion 911 along the first direction.

[0258] For example, in the first sub-pixel M1, the orthographic projection of the first portion 911 on the substrate overlaps with the orthographic projection of the data line body portion 9801 of the third data line pattern 983 adjacent along the first direction on the substrate, and the orthographic projection of the second portion 912 on the substrate does not overlap with the orthographic projection of the data line body portion 9801 of the third data line pattern 983 on the substrate.

[0259] For example, at least a portion of the first portion 911 extends along the second direction, and at least a portion of the second portion 912 extends along the second direction. In a direction perpendicular to the second direction, the width of the first portion 911 is equal to the width of the second portion 912, or the width of the first portion 911 is greater than the width of the second portion 912, or the width of the first portion 911 is less than the width of the second portion 912.

[0260] In the display substrate provided in the above embodiments, the overlap area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, as well as the overlap area between the orthographic projection of the data line pattern adjacent to the first data line pattern 981 on the substrate along the first direction and the orthographic projection of the functional pattern with a fixed potential on the substrate, is close to that of the first data line pattern 981 and the data line pattern adjacent along the first direction. This effectively reduces the load difference between the first data line pattern 981 and the data line pattern adjacent along the first direction.

[0261] It should be noted that the functional pattern with fixed units includes: power signal line pattern 91, initialization signal line pattern 94, and conductive functional pattern (such as: second conductive connection part 962) electrically connected to the power signal line pattern 91 or the initialization signal line pattern 94.

[0262] like Figure 12 As shown, in some embodiments, in the second sub-pixel M2, the orthographic projection of the power supply protrusion 913 on the substrate does not overlap with the orthographic projection of the second data line pattern 982 on the substrate.

[0263] For example, in the second sub-pixel M2, the orthographic projection of the power protrusion 913 on the substrate overlaps with the orthographic projection of the extension of the first data line pattern 981 adjacent along the second direction on the substrate.

[0264] like Figure 12 As shown, in some embodiments, in the third sub-pixel M3, the orthographic projection of the power supply protrusion 913 on the substrate does not overlap with the orthographic projection of the third data line pattern 983 on the substrate.

[0265] For example, in the third sub-pixel M3, the orthographic projection of the power protrusion 913 on the substrate overlaps with the orthographic projection of the extension of the fourth data line pattern 984 adjacent along the second direction on the substrate.

[0266] like Figure 12 As shown, in some embodiments, in the fourth sub-pixel M4, the orthographic projection of the power supply protrusion 913 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate, and the orthographic projection of the power supply body portion on the substrate overlaps with the orthographic projection of the adjacent data line pattern (such as the second data line pattern 982) along the first direction on the substrate.

[0267] For example, in the fourth sub-pixel M4, the power supply body portion includes a first portion 911 and a second portion 912. The orthographic projection of the first portion 911 on the substrate overlaps with the orthographic projection of the data line body portion 9801 of the sixth data line pattern 986 adjacent along the first direction on the substrate. The orthographic projection of the second portion 912 on the substrate does not overlap with the orthographic projection of the data line body portion 9801 of the sixth data line pattern 986 on the substrate.

[0268] In the display substrate provided in the above embodiments, the overlap area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate is made close to the overlap area between the orthographic projection of the sixth data line pattern 986 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby effectively reducing the load difference between the fourth data line pattern 984 and the sixth data line pattern 986. It is worth noting that... Figure 12 The diagram also shows that the fifth sub-pixel M5 includes a fifth data line pattern 985, the seventh sub-pixel M7 includes a seventh data line pattern 987, and the eighth sub-pixel includes an eighth data line pattern 988.

[0269] In the display substrate provided in the above embodiments, the overlap area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, as well as the overlap area between the orthographic projection of the data line pattern adjacent to the fourth data line pattern 984 along the first direction and the orthographic projection of the functional pattern with a fixed potential on the substrate, is close to that of the fourth data line pattern 984 and the data line pattern adjacent along the first direction. This effectively reduces the load difference between the fourth data line pattern 984 and the data line pattern adjacent along the first direction.

[0270] like Figure 10 and Figure 11 As shown, in some embodiments, the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 all include a data line body portion 9801 and a data line protrusion portion 9802. The data line body portion 9801 extends along the second direction, and the data line protrusion portion 9802 protrudes from the data line body portion 9801 along the first direction.

[0271] The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include a first conductive connection portion 961 and a data writing transistor. In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the data line protrusion 9802 is electrically connected to the first electrode of the data writing transistor through the first conductive connection portion 961.

[0272] For example, at least a portion of the first conductive connection 961 extends along the second direction. The orthographic projection of a first end of the first conductive connection 961 onto the substrate has a first overlapping region with the orthographic projection of the data line protrusion 9802 onto the substrate, and the first end of the first conductive connection 961 and the data line protrusion 9802 are electrically connected through a via disposed in the first overlapping region. The orthographic projection of a second end of the first conductive connection 961 onto the substrate has a second overlapping region with the orthographic projection of the first electrode of the data writing transistor onto the substrate, and the second end of the first conductive connection 961 and the first electrode of the data writing transistor are electrically connected through a via disposed in the second overlapping region. The first electrode of the data writing transistor receives a data signal provided by the corresponding data line pattern through the first conductive connection 961.

[0273] For example, the orthographic projection of the second portion 912 of the power signal line pattern 91 onto the substrate is aligned with the first overlapping region along the first direction.

[0274] Along the first direction, the distance between the first conductive connection portion 961 and the power signal line pattern 91 is relatively large. By arranging the orthographic projection of the second part 912 of the power signal line pattern 91 on the substrate and the first overlapping area along the first direction, the second part 912 has sufficient layout space, thereby reducing the layout difficulty of the display substrate while ensuring that the second part 912 has a large area.

[0275] like Figure 5 , Figure 10 and Figure 12 As shown, in some embodiments, both the first sub-pixel M1 and the second sub-pixel M2 include: an initialization signal line pattern 94, a second transistor T2, and a second conductive connection portion 962;

[0276] At least a portion of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used to transmit an initialization signal;

[0277] The first terminal of the second transistor T2 is electrically connected to the initialization signal line pattern 94 through the second conductive connection portion 962, and the second terminal of the second transistor T2 is electrically connected to the gate of the driving transistor; in the first sub-pixel M1, the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate; in the second sub-pixel M2, the orthographic projection of the second conductive connection portion 962 on the substrate does not overlap with the orthographic projection of the second data line pattern 982 on the substrate.

[0278] like Figure 12 As shown, the third sub-pixel M3 and the fourth sub-pixel M4 both include: an initialization signal line pattern 94, a second transistor T2, and a second conductive connection portion 962;

[0279] At least a portion of the initialization signal line pattern 94 extends along the second direction, and the initialization signal line pattern 94 is used to transmit an initialization signal;

[0280] The first terminal of the second transistor T2 is electrically connected to the initialization signal line pattern 94 through the second conductive connection portion 962, and the second terminal of the second transistor T2 is electrically connected to the gate of the driving transistor.

[0281] In the third sub-pixel M3, the orthographic projection of the second conductive connection portion 962 on the substrate does not overlap with the orthographic projection of the third data line pattern 983 on the substrate;

[0282] In the fourth sub-pixel M4, the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate.

[0283] Specifically, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 all include the initialization signal line pattern 94, the second transistor T2, and the second conductive connection portion 962. For example, the orthographic projection of the first electrode of the second transistor T2 onto the substrate overlaps with the orthographic projection of the first end of the second conductive connection portion 962 onto the substrate, and the first electrode of the second transistor T2 and the first end of the second conductive connection portion 962 are electrically connected through a via located at the overlap. The orthographic projection of the second end of the second conductive connection portion 962 onto the substrate overlaps with the orthographic projection of the initialization signal line pattern 94 onto the substrate, and the second end of the second conductive connection portion 962 is electrically connected to the initialization signal line pattern 94 through a via located at the overlap.

[0284] The second transistor T2 is electrically connected to the gate of the driving transistor. During the reset period, the second transistor T2 can transmit the received initialization signal to the gate of the driving transistor to achieve gate reset of the driving transistor.

[0285] Because the second conductive connection portion 962 is electrically connected to the initialization signal line pattern 94, the initialization signal line pattern 94 has a stable potential. In the first sub-pixel M1, the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate; this makes the overlap area between the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, and the overlap area between the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, more similar, thereby further reducing the load difference between the first data line pattern 981 and the third data line pattern.

[0286] In the fourth sub-pixel M4, the above-described arrangement ensures that the orthographic projection of the second conductive connection portion 962 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate. This makes the overlap area between the orthographic projection of the second data line pattern 982 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate more similar to the overlap area between the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the functional pattern with a fixed potential on the substrate, thereby further reducing the load difference between the second data line pattern 982 and the fourth data line pattern 984.

[0287] In some embodiments, the overlapping area formed by the orthographic projection of the third data line pattern on the substrate and the orthographic projection of the first portion 911 on the substrate has a first area; the overlapping area formed by the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the power protrusion 913 on the substrate has a second area; and the orthographic projection of the first data line pattern 981 on the substrate and the orthographic projection of the second conductive connection portion 962 in the display substrate on the substrate has a third area; the sum of the second area and the third area is approximately the same as the first area. This arrangement ensures that the load on the first data line pattern 981 is substantially the same as the load on the third data line pattern, thereby improving the display uniformity of the display substrate.

[0288] In some embodiments, the overlapping area formed by the orthographic projection of the second data line pattern on the substrate and the orthographic projection of the first portion 911 on the substrate has a first area; the overlapping area formed by the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the power protrusion 913 on the substrate has a second area; the orthographic projection of the fourth data line pattern 984 on the substrate and the orthographic projection of the second conductive connection portion 962 in the display substrate on the substrate has a third area; the sum of the second area and the third area is approximately the same as the first area. This arrangement ensures that the load on the second data line pattern 982 is substantially the same as the load on the fourth data line pattern 984, thereby improving the display uniformity of the display substrate.

[0289] like Figure 5 , Figure 8 , Figure 9 , Figure 12 and Figure 19 As shown, in some embodiments, the power protrusion 913 includes a third portion 9130, a fourth portion 9131, and a fifth portion 9132; the third portion 9130 extends along the second direction, and in the first sub-pixel M1, the orthographic projection of the third portion 9130 on the substrate overlaps with the orthographic projection of the first data line pattern 981 on the substrate. In the fourth sub-pixel M4, the orthographic projection of the third portion 9130 on the substrate overlaps with the orthographic projection of the fourth data line pattern 984 on the substrate.

[0290] In the first sub-pixel M1, by setting the length of the third portion 9130 along the second direction, the overlapping area of ​​the first data line pattern 981 and the third portion 9130 can be controlled, thereby adjusting the load of the first data line pattern 981. In the third sub-pixel M3, by setting the length of the third portion 9130 along the second direction, the overlapping area of ​​the fourth data line pattern 984 and the third portion 9130 can be controlled, thereby adjusting the load of the fourth data line pattern 984.

[0291] like Figure 5 , Figure 12 and Figure 13aAs shown, in some embodiments, the display substrate further includes an interlayer insulating layer (ILD) and a first planarization layer (PLN1) sequentially stacked along a direction away from the substrate; the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 are all located on the surface of the first planarization layer (PLN1) facing away from the substrate; the power signal line pattern 91 and the power compensation pattern 97 are both located on the surface of the interlayer insulating layer (ILD) facing away from the substrate.

[0292] Specifically, the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 are all located on the surface of the first planarization layer PLN1 facing away from the substrate, so that the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 are all disposed on the same layer. When the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 are made of the same material, the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 can be formed in the same patterning process, thereby simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0293] It should be noted that the first data line pattern 981, the second data line pattern 982, the third data line pattern 983, and the fourth data line pattern 984 can form the second source / drain metal layer in the display substrate. It is also worth noting that the second source / drain metal layer may include other structures.

[0294] like Figure 5 , Figure 7 and Figure 18 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: an anode pattern, an initialization signal line pattern 94, a shielding pattern 80, a driving transistor, and a second transistor T2;

[0295] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the first terminal of the second transistor T2 is electrically connected to the initialization signal line pattern 94, and the second terminal of the second transistor T2 is electrically connected to the gate of the driving transistor.

[0296] The shielding pattern 80 is electrically connected to the power signal line pattern 91, and the orthographic projection of the shielding pattern 80 on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second transistor T2 on the substrate.

[0297] Specifically, each of the sub-pixels further includes: an anode pattern, an initialization signal line pattern 94, a shielding pattern 80, a driving transistor, a second transistor T2, and a seventh transistor T7; the gate of the second transistor T2 is electrically connected to the reset signal line pattern 95, the first terminal of the second transistor T2 is electrically connected to the initialization signal line pattern 94, the second terminal of the second transistor T2 is electrically connected to the gate of the driving transistor, and the second transistor T2 is used to reset the gate of the driving transistor.

[0298] The gate of the seventh transistor T7 is electrically connected to the reset signal line pattern 95' of the next sub-pixel adjacent to its sub-pixel along the second direction. The first electrode of the seventh transistor T7 is electrically connected to the initialization signal line pattern 94' in the next sub-pixel adjacent to its sub-pixel along the second direction. The second electrode of the seventh transistor T7 is electrically connected to the anode pattern in the sub-pixel. The seventh transistor T7 is used to reset the anode pattern.

[0299] Each sub-pixel further includes a shielding pattern 80, the orthographic projection of which overlaps with the orthographic projection of the power signal line pattern 91 on the substrate. The shielding pattern 80 and the power signal line pattern 91 are electrically connected through a via disposed at the overlap. For example, the orthographic projection of the shielding pattern 80 on the substrate overlaps with the orthographic projection of the second portion 912 of the power signal line pattern 91 on the substrate, and the shielding pattern 80 and the second portion 912 of the power signal line pattern 91 are directly electrically connected through a via disposed at the overlap.

[0300] The shielding pattern 80 is electrically connected to the power signal line pattern 91, so that the shielding pattern 80 has a stable potential. This not only helps the sub-pixel driving circuit to be in a stable working state, but also better ensures the shielding effect of the shielding pattern 80.

[0301] By setting the orthographic projection of the shielding pattern 80 on the substrate to overlap with the orthographic projection of the first electrode of the second transistor T2 on the substrate, and / or, setting the orthographic projection of the shielding pattern 80 on the substrate to overlap with the orthographic projection of the first electrode of the seventh transistor T7 in the adjacent sub-pixel along the second direction on the substrate, the shielding pattern 80 shields the influence of data signal transitions on the first electrode of the second transistor T2 and / or the first electrode of the seventh transistor T7, thereby avoiding any impact on the initialization signal transmitted on the initialization signal line pattern 94.

[0302] like Figure 5 , Figure 7 and Figure 18 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: a first conductive connection portion, a fifth conductive connection portion 965, and a data writing transistor;

[0303] In the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4, the second electrode of the second transistor T2 is electrically connected to the gate of the driving transistor through the fifth conductive connection portion 965;

[0304] The first conductive connection portion 961 is electrically connected to the first terminal of the data writing transistor; the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor.

[0305] The orthographic projection of the shielding pattern 80 on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 961 on the substrate.

[0306] Specifically, in each sub-pixel, at least a portion of the fifth conductive connection portion 965 extends along the second direction. The orthographic projection of one end of the fifth conductive connection portion 965 onto the substrate and the orthographic projection of the second electrode of the second transistor T2 onto the substrate have a sixth overlapping region. One end of the fifth conductive connection portion 965 is electrically connected to the second electrode of the second transistor T2 through a via disposed in the sixth overlapping region. The orthographic projection of the other end of the fifth conductive connection portion 965 onto the substrate overlaps with the orthographic projection of the gate of the driving transistor onto the substrate. The other end of the fifth conductive connection portion 965 is electrically connected to the gate of the driving transistor through a via disposed at the overlapping region.

[0307] Each sub-pixel further includes a first conductive connection portion 961, exemplarily, at least a portion of the first conductive connection portion 961 extending along the second direction. The orthographic projection of a first end of the first conductive connection portion 961 onto the substrate has a first overlapping region with the orthographic projection of the corresponding data line protrusion 9802 onto the substrate, and the first end of the first conductive connection portion 961 and the data line protrusion 9802 are electrically connected through a via disposed in the first overlapping region. The orthographic projection of a second end of the first conductive connection portion 961 onto the substrate has a second overlapping region with the orthographic projection of the first electrode of the data writing transistor onto the substrate, and the second end of the first conductive connection portion 961 and the first electrode of the data writing transistor are electrically connected through a via disposed in the second overlapping region. The first electrode of the data writing transistor receives data signals provided by the corresponding data line pattern through the first conductive connection portion 961.

[0308] For example, the shielding pattern 80 includes a first shielding part 801 and a second shielding part 802 that are electrically connected. The orthographic projection of the first shielding part 801 on the substrate overlaps with the orthographic projection of the power signal line pattern 91 on the substrate. The first shielding part 801 and the power signal line pattern 91 are directly electrically connected through a via provided at the overlap.

[0309] For example, the first shielding part 801 and the second shielding part 802 are formed as an integral structure.

[0310] For example, the first shielding portion 801 is a square structure extending along the first direction, and the orthographic projection of the first shielding portion 801 on the substrate overlaps with the orthographic projection of the first electrode of the second transistor T2 on the substrate, and / or, the orthographic projection of the first shielding portion 801 on the substrate overlaps with the orthographic projection of the first electrode of the seventh transistor T7 in the adjacent sub-pixel along the second direction on the substrate.

[0311] For example, the orthographic projection of the first shielding portion 801 on the substrate does not overlap with the orthographic projection of the reset signal line pattern 95 on the substrate.

[0312] For example, the orthographic projection of the first shielding portion 801 in the shielding pattern 80 onto the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 961 onto the substrate.

[0313] like Figure 5 As shown, in some embodiments, at least a portion of the shielding pattern 80 is projected onto the substrate in an orthographic projection between the first conductive connection 961 and the fifth conductive connection 965 on the substrate.

[0314] For example, such as Figure 13b As shown, the orthographic projection of the second shielding portion 802 in the shielding pattern 80 onto the substrate is located between the second overlapping region and the sixth overlapping region.

[0315] For example, the second shielding portion 802 is a square structure extending along the second direction.

[0316] The above configuration allows the second shielding portion 802 to better shield the effects of data signal changes on the second electrode of the second transistor T2, thereby preventing data signal changes from affecting the gate signal of the driving transistor. Since the gate signal of the driving transistor directly affects the brightness of the sub-pixel, the above configuration makes the gate potential of the driving transistor more stable, thus enabling the display substrate to achieve better display effects when used for display.

[0317] like Figure 5 , Figure 7 and Figure 18 As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: a first transistor T1;

[0318] In each sub-pixel, the first terminal of the first transistor T1 is electrically connected to the second terminal of the driving transistor, and the second terminal of the first transistor T1 is electrically connected to the gate of the driving transistor.

[0319] The active pattern of the first transistor T1 includes two semiconductor portions spaced apart, and a first conductor portion connecting the two semiconductor portions respectively;

[0320] The projection of the shielding pattern 80 onto the substrate also at least partially overlaps with the orthographic projection of the first conductor portion onto the substrate.

[0321] Specifically, each of the sub-pixels also includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the gate line pattern 92, the first terminal of the first transistor T1 is electrically connected to the second terminal of the driving transistor, and the second terminal of the first transistor T1 is electrically connected to the gate of the driving transistor.

[0322] The first transistor T1 is formed as a dual-gate structure. The active pattern of the first transistor T1 includes two semiconductor portions spaced apart and a first conductor portion connecting the two semiconductor portions respectively. The orthographic projection of the gate of the first transistor T1 on the substrate covers the orthographic projection of the two semiconductor portions on the substrate. The orthographic projection of the gate of the first transistor T1 on the substrate and the orthographic projection of the first conductor portion on the substrate do not overlap.

[0323] For example, the shielding pattern 80 further includes a third shielding portion 803 electrically connected to the first shielding portion 801, at least a portion of the third shielding portion 803 being a square structure extending along the second direction.

[0324] For example, the first shielding part 801 and the third shielding part 803 are formed as an integral structure.

[0325] For example, the shielding pattern 80 further includes a third shielding portion 803 electrically connected to the first shielding portion 801, wherein the orthographic projection of the third shielding portion 803 on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate.

[0326] The orthographic projection of the third shielding portion 803 on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate. This arrangement allows the third shielding pattern 80 to block the first conductor portion, preventing changes in the data signal from affecting the first transistor T1, and thus preventing changes in the data signal from affecting the gate signal of the driving transistor.

[0327] In some embodiments, the shielding pattern 80 is located between the first electrode of the second transistor T2 and the first conductive connection portion 961 in a direction perpendicular to the substrate.

[0328] For example, the display substrate further includes a second gate insulating layer located between the first electrode of the second transistor T2 and the first conductive connection portion 961, and in each sub-pixel, the initialization signal line pattern 94 and the shielding pattern 80 are both located on the surface of the second gate insulating layer facing away from the substrate.

[0329] In the above-described configuration, the initialization signal line pattern 94 and the shielding pattern 80 are both located on the surface of the second gate insulating layer facing away from the substrate, so that the initialization signal line pattern 94 and the shielding pattern 80 are disposed in the same layer. When the initialization signal line pattern 94 and the shielding pattern 80 are made of the same material, the initialization signal line pattern 94 and the shielding pattern 80 can be formed in the same patterning process, thereby simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0330] like Figure 2 , Figure 5 and Figure 12As shown, in some embodiments, the first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3, and the fourth sub-pixel M4 each include: a light-emitting element, an initialization signal line pattern 94, a reset signal line pattern 95, a gate line pattern 92, a light-emitting control signal line pattern 93, and a power signal line pattern 91; at least a portion of the initialization signal line pattern 94, at least a portion of the reset signal line pattern 95, at least a portion of the gate line pattern 92, and at least a portion of the light-emitting control signal line pattern 93 all extend along the first direction; at least a portion of the power signal line pattern 91 extends along the second direction.

[0331] The first sub-pixel M1, the second sub-pixel M2, the third sub-pixel M3 and the fourth sub-pixel M4 each include: a first transistor T1, a second transistor T2, a driving transistor (such as the third transistor), a data writing transistor (such as the fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst;

[0332] In each sub-pixel, the gate of the driving transistor is electrically connected to the second terminal of the first transistor T1, the first terminal of the driving transistor is electrically connected to the second terminal of the fifth transistor T5, and the second terminal of the driving transistor is electrically connected to the first terminal of the first transistor T1.

[0333] The gate of the first transistor T1 is electrically connected to the gate pattern 92;

[0334] The gate of the second transistor T2 is electrically connected to the reset signal line pattern 95, the first terminal of the second transistor T2 is electrically connected to the initialization signal line pattern 94, and the second terminal of the second transistor T2 is electrically connected to the gate of the driving transistor.

[0335] The gate of the data writing transistor is electrically connected to the gate line pattern 92, the first terminal of the data writing transistor is electrically connected to the data line pattern included in the sub-pixel, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor.

[0336] The gate of the fifth transistor T5 is electrically connected to the light-emitting control signal line pattern 93, and the first terminal of the fifth transistor T5 is electrically connected to the power supply signal line pattern 91.

[0337] The gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the driving transistor, and the second terminal of the sixth transistor T6 is electrically connected to the light-emitting element.

[0338] The gate of the seventh transistor T7 is electrically connected to the reset signal line pattern 95 in the next sub-pixel adjacent to the second direction, the first terminal of the seventh transistor T7 is electrically connected to the initialization signal line pattern 94 in the next sub-pixel adjacent to the second direction, and the second terminal of the seventh transistor T7 is electrically connected to the light-emitting element.

[0339] The first plate of the storage capacitor is reused as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line pattern 91.

[0340] For example, each sub-pixel in the display substrate includes a sub-pixel driving circuit, and each sub-pixel driving circuit includes: a first transistor T1, a second transistor T2, a driving transistor (such as a third transistor), a data writing transistor (such as a fourth transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, a first conductive connection 961, a second conductive connection 962, a third conductive connection 963, a fourth conductive connection 964, and a fifth conductive connection 965, etc.

[0341] Specifically, the plurality of sub-pixels can be divided into multiple rows of sub-pixels arranged sequentially along the second direction and multiple columns of sub-pixels arranged sequentially along the first direction. The initialization signal line pattern 94 of the sub-pixels in the same row is electrically connected in sequence to form a single structure; the gate line pattern 92 of the sub-pixels in the same row is electrically connected in sequence to form a single structure; the light emission control signal line pattern 93 of the sub-pixels in the same row is electrically connected in sequence to form a single structure; the reset signal line pattern 95 of the sub-pixels in the same row is electrically connected in sequence to form a single structure; the first data line pattern 981 of the sub-pixels in the same column is electrically connected in sequence to form a single structure; the second data line pattern 982 of the sub-pixels in the same column is electrically connected in sequence to form a single structure; and the power signal line pattern 91 of the sub-pixels in the same column is electrically connected in sequence to form a single structure.

[0342] like Figure 2 As shown, taking a sub-pixel driving circuit as an example, the sub-pixel driving circuit includes 7 thin-film transistors and 1 capacitor. Each transistor in the sub-pixel driving circuit is a P-type transistor, and the first electrode of each transistor includes a source electrode, and the second electrode of each transistor includes a drain electrode.

[0343] The first transistor T1 has a dual-gate structure. The gate 201g of the first transistor T1 is electrically connected to the gate line pattern 92. The source S1 of the first transistor T1 is electrically connected to the drain D3 of the third transistor T3 (i.e., the driving transistor). The drain D1 of the first transistor T1 is electrically connected to the gate 203g of the third transistor T3.

[0344] The second transistor T2 has a dual-gate structure. The gate 202g of the second transistor T2 is electrically connected to the reset signal line pattern 95, the source S2 of the second transistor T2 is electrically connected to the initialization signal line pattern 94, and the drain D2 of the second transistor T2 is electrically connected to the gate 203g of the third transistor T3.

[0345] The gate 204g of the fourth transistor T4 (i.e., the data write transistor) is electrically connected to the gate line pattern 92, the source S4 of the fourth transistor T4 is electrically connected to the first data line pattern 981 or the second data line pattern 982, and the drain D4 of the fourth transistor T4 is electrically connected to the source S3 of the third transistor T3.

[0346] The gate 205g of the fifth transistor T5 is electrically connected to the light-emitting control signal line pattern 93, the source S5 of the fifth transistor T5 is electrically connected to the power supply signal line pattern 91, and the drain D5 of the fifth transistor T5 is electrically connected to the source S3 of the third transistor T3.

[0347] The gate 206g of the sixth transistor T6 is electrically connected to the light-emitting control signal line pattern 93, the source S6 of the sixth transistor T6 is electrically connected to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL.

[0348] The gate 207g of the seventh transistor T7 is electrically connected to the reset signal line pattern 95' in the next sub-pixel adjacent to the second direction, the drain D7 of the seventh transistor T7 is electrically connected to the anode of the corresponding light-emitting element EL, and the source S7 of the seventh transistor T7 is electrically connected to the initialization signal line pattern 94' in the next sub-pixel adjacent to the second direction.

[0349] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the power signal line pattern 91.

[0350] like Figure 3 As shown, when the sub-pixel driving circuit of the above structure is working, each working cycle includes a reset period P1, a write compensation period P2, and a light emission period P3. Figure 3 In this diagram, E1 represents the light emission control signal transmitted on the light emission control signal line pattern 93 in the current sub-pixel, R1 represents the reset signal transmitted on the reset signal line pattern 95 in the current sub-pixel, D1 represents the data signal transmitted on the data line pattern in the current sub-pixel, G1 represents the gate scan signal transmitted on the gate line pattern 92 in the current sub-pixel, and R1' represents the reset signal transmitted on the reset signal line pattern 95' in the next sub-pixel adjacent to the current sub-pixel along the second direction.

[0351] During the first reset period P1, the reset signal input by the reset signal line pattern 95 is at an active level, the second transistor T2 is turned on, and the initialization signal transmitted by the initialization signal line pattern 94 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0352] During the write compensation period P2, the reset signal input to the reset signal line pattern 95 is at an inactive level, the second transistor T2 is turned off, and the gate scan signal input to the gate line pattern 92 is at an active level, controlling the first transistor T1 and the fourth transistor T4 to turn on. The corresponding data line pattern writes the data signal, which is transmitted to the source S3 of the third transistor T3 via the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, making the third transistor T3 form a diode structure. Therefore, by working together, the first transistor T1, the third transistor T3, and the fourth transistor T4 can achieve threshold voltage compensation for the third transistor T3. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to eventually reach Vdata + Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0353] During the write compensation period P2, the reset signal input to the reset signal line pattern 95' is at an active level, controlling the seventh transistor T7 to turn on. The initialization signal transmitted by the initialization signal line pattern 94' is input to the anode of the light-emitting element EL, controlling the light-emitting element EL not to emit light.

[0354] During the light-emitting period P3, the light-emitting control signal written in the light-emitting control signal line pattern 93 is at an effective level, controlling the fifth transistor T5 and the sixth transistor T6 to conduct, so that the power signal transmitted by the power signal line pattern 91 is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on. The gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power signal. The leakage current generated based on this gate-source voltage flows to the anode of the corresponding light-emitting element EL, driving the corresponding light-emitting element EL to emit light.

[0355] like Figures 6-8 , Figures 10-13a As shown, the layout of each film layer corresponding to the above sub-pixel is as follows when fabricating the sub-pixel:

[0356] An active film layer, a first gate insulating layer GI1, a first gate metal layer, a second gate insulating layer GI2, a second gate metal layer, an interlayer insulating layer ILD, a first source / drain metal layer, a first planarization layer PLN1, a second source / drain metal layer, a second planarization layer PLN2, and an anode layer are sequentially stacked along a direction away from the substrate.

[0357] like Figure 6 As shown, the active film layer is used to form the channel region (the part covered by the gate of each transistor), source (e.g., S1~S7), and drain (e.g., D1~D7) of each transistor in the sub-pixel driving circuit. Due to doping, the conductivity of the active film layer corresponding to the source and drain is better than that of the active film layer corresponding to the channel region. The active film layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain can be doped with n-type impurities or p-type impurities.

[0358] like Figure 6 As shown, the first gate metal layer is used to form the gates of each transistor in the sub-pixel driving circuit (e.g., 201g~207g), as well as the sub-pixel including the gate line pattern 92, the light emission control signal line pattern 93, the reset signal line pattern 95, and other structures. The gate 203g of the third transistor T3 in each sub-pixel driving circuit is reused as the first plate Cst1 of the second storage capacitor Cst in the sub-pixel driving circuit.

[0359] like Figure 7 As shown, the second gate metal layer is used to form the second electrode Cst2 of the second storage capacitor Cst, and the sub-pixel includes an initialization signal line pattern 94 and a shielding pattern 80.

[0360] like Figure 8 As shown, the first source / drain metal layer is used to form the power signal line pattern 91, power compensation pattern and some conductive connections included in the sub-pixel.

[0361] like Figure 11 As shown, the second source / drain metal layer is used to form the first data line pattern 981, the second data line pattern 982, and some conductive connections included in the sub-pixel.

[0362] In addition, such as Figure 5As shown, in the display substrate provided in this disclosure, in the second direction, the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gates of the seventh transistor T7, the sixth transistor T6, and the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first and second sides of the gate of the driving transistor are opposite sides along the second direction. Further, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor. The lower side, for example, is the side of the display substrate used for bonding the IC, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor further away from the IC.

[0363] In the first direction, the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor. Exemplarily, the third and fourth sides of the gate of the driving transistor are opposite sides along the first direction; further, the third side of the gate of the driving transistor can be the right side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor can be the left side of the gate of the driving transistor. For example, in the same sub-pixel, the second data line pattern 982 is located on the right side of the gate of the driving transistor, and the first data line pattern 981 is located on the left side of the gate of the driving transistor.

[0364] This disclosure also provides a display device, including the above-described display substrate.

[0365] In the display substrate provided in the above embodiments, in the first sub-pixel M1, by setting the orthographic projection of the anode pattern on the substrate to at least partially overlap with the orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the anode pattern on the substrate to at least partially overlap with the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction on the substrate, the second data line pattern 982 and its adjacent data line patterns can compensate for the step difference generated below the anode pattern (such as the first anode pattern 71), so that the anode pattern can be formed on a relatively flat surface, thereby giving the anode pattern high flatness, ensuring that the light emission intensity of the sub-pixel is consistent in all directions, and effectively improving the color shift problem generated by the display product when the display substrate is applied to the display product.

[0366] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display substrate, also has all the effects of the above-described display substrate, which will not be repeated here.

[0367] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer.

[0368] This disclosure also provides a method for manufacturing a display substrate, used to manufacture the display substrate provided in the above embodiments. The manufacturing method includes: fabricating a plurality of sub-pixels arranged in an array on a substrate, wherein the plurality of sub-pixels includes:

[0369] A first sub-pixel M1 and a second sub-pixel M2 are arranged along a second direction. The first sub-pixel M1 includes a first data line pattern 981, and the second sub-pixel M2 includes a second data line pattern 982. The first data line pattern 981 is configured to provide a first data signal to the first sub-pixel M1, and the second data line pattern 982 is configured to provide a second data signal to the second sub-pixel M2.

[0370] At least a portion of the first data line pattern 981 and at least a portion of the second data line pattern 982 both extend along a second direction. The first data line pattern 981 is located on a first side of the first sub-pixel M1 in the same column extending along the second direction, and the second data line pattern 982 is located on a second side of the second sub-pixel M2 in the same column extending along the second direction. The first side and the second side are opposite to each other along a first direction, and the first direction intersects with the second direction.

[0371] The first sub-pixel M1 includes a sixth transistor T6, and a third conductive connection portion 963, a fourth conductive connection portion 964, and an anode pattern stacked in a direction away from the substrate; the second electrode of the sixth transistor T6 is electrically connected to the anode pattern through the third conductive connection portion 963 and the fourth conductive connection portion 964.

[0372] In the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the second data line pattern 982 on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the data line pattern adjacent to the second data line pattern 982 along the first direction on the substrate.

[0373] In the display substrate manufactured using the manufacturing method provided in this embodiment, in the first sub-pixel M1, the orthographic projection of the anode pattern on the substrate is at least partially overlapped with the orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the anode pattern on the substrate is at least partially overlapped with the orthographic projection of the data line pattern adjacent to the second data line pattern along the first direction on the substrate. This allows the second data line pattern 982 and its adjacent data line patterns to compensate for the step difference generated below the anode pattern (such as the first anode pattern 71), enabling the anode pattern to be formed on a relatively flat surface. This results in the anode pattern having high flatness, ensuring consistent light emission intensity of the sub-pixel in all directions, and effectively improving the color shift problem generated by the display product when the display substrate is applied to the display product.

[0374] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0375] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0376] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0377] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0378] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A substrate and an array of sub-pixels distributed on the substrate, the sub-pixels comprising: A first sub-pixel and a third sub-pixel are arranged along a first direction. The first sub-pixel includes a first data line pattern, and the third sub-pixel includes a third data line pattern. The first data line pattern is configured to provide a first data signal to the first sub-pixel, and the third data line pattern is configured to provide a third data signal to the third sub-pixel. At least a portion of the first data line pattern and at least a portion of the third data line pattern both extend along a second direction. The first data line pattern is located on a first side of the first sub-pixel in the same column extending along the second direction, and the third data line pattern is located on a second side of the third sub-pixel in the same column extending along the second direction. The first side and the second side are opposite to each other along a first direction, and the first direction intersects with the second direction. Both the first sub-pixel and the third sub-pixel include a sixth transistor and an anode pattern; the second electrode of the sixth transistor and the corresponding anode pattern are electrically connected. The third sub-pixel also includes a fourth conductive connection portion, which is located on the same layer as the first data line pattern and the third data line pattern. In the third sub-pixel, the orthographic projection of the anode pattern on the substrate at least partially overlaps with the orthographic projection of the third data line pattern on the substrate, and the orthographic projection of the first data line pattern adjacent to the third data line pattern along the first direction at least partially overlaps with the orthographic projection of the first data line pattern on the substrate.

2. The display substrate according to claim 1, wherein, In the first sub-pixel, the anode pattern of the first sub-pixel does not overlap with the first data line pattern.

3. The display substrate according to claim 1, wherein, In the first sub-pixel, the orthographic projection of the anode pattern of the first sub-pixel on the substrate does not overlap with the orthographic projection of the first data line pattern on the substrate, and the orthographic projection of the anode pattern of the first sub-pixel on the substrate does not overlap with the orthographic projection of the third data line pattern adjacent to the first data line pattern on the substrate.

4. The display substrate according to claim 1, wherein, In the third sub-pixel, the fourth conductive connection portion includes a solid portion and a hollow portion; The orthographic projection of the anode pattern on the substrate overlaps at least partially with the orthographic projections of the solid portion and the hollow portion on the substrate.

5. The display substrate according to claim 4, wherein, The fourth conductive connection portion includes a first strip-shaped portion and a second strip-shaped portion, both of which extend along the second direction. The first data line pattern, the third data line pattern, the first strip portion and the second strip portion are arranged sequentially along the first direction, and the orthographic projection of the anodized pattern of the third sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first data line pattern on the substrate, the orthographic projection of the third data line pattern on the substrate, the orthographic projection of the first strip portion on the substrate, and the orthographic projection of the second strip portion on the substrate.

6. The display substrate according to claim 1, wherein, The first data line pattern includes a first offset portion extending in the second offset direction, and the third data line pattern includes a third offset portion extending in the second offset direction. The dimensions of the first offset portion and the third offset portion in the first direction are both smaller than the dimensions of the anodized pattern of the third sub-pixel in the first direction.

7. The display substrate according to claim 6, wherein, The maximum distance between the first offset portion and the third offset portion is greater than the minimum distance between the first data line pattern and the third data line pattern.

8. The display substrate according to claim 6, wherein, In the third sub-pixel, the orthographic projection of the anodized pattern of the third sub-pixel onto the substrate does not overlap with the orthographic projection of the first offset portion onto the substrate and the orthographic projection of the third offset portion onto the substrate.

9. The display substrate according to claim 4, wherein, The display substrate further includes: A power signal line pattern, wherein the power signal line pattern is used to receive power supply voltage; At least a portion of the power signal line pattern extends along the first direction, and the power signal line pattern is located on the side of the first data line pattern and the third data line pattern closer to the substrate. The orthographic projection of the power signal line pattern on the substrate at least partially overlaps with the orthographic projection of the first data line pattern on the substrate.

10. The display substrate according to claim 9, wherein, The first sub-pixel and the third sub-pixel each include a driving transistor, a storage capacitor, and a light-emitting element; The driving transistor is used to provide a driving signal to the light-emitting element; The storage capacitor includes a first plate and a second plate. The first plate is multiplexed as the gate of the driving transistor, and the second plate is used for patterned electrical connection with the power signal line. The second electrode is located between the power signal line pattern and the first electrode.

11. The display substrate according to claim 9, wherein, The orthographic projection of the power signal line pattern on the substrate overlaps with the orthographic projection of the first data line pattern on the substrate, as well as the orthographic projection of the third data line pattern on the substrate.

12. The display substrate according to claim 10, wherein, The power signal line pattern is electrically connected to the second plate of the storage capacitor through a via. The orthographic projection of the power signal line pattern on the substrate, the orthographic projection of the second plate of the storage capacitor on the substrate, and the orthographic projection of the first data line pattern on the substrate all at least partially overlap.

13. The display substrate according to claim 5, wherein, The first data line pattern, the third data line pattern, and the first and second stripe portions have the same spacing between their orthographic projections on the substrate.

14. The display substrate according to claim 5, wherein, The first sub-pixel and the third sub-pixel each include: a light-emitting element, an initialization signal line pattern, a reset signal line pattern, a gate line pattern, and a light-emitting control signal line pattern; at least a portion of the initialization signal line pattern, at least a portion of the reset signal line pattern, at least a portion of the gate line pattern, and at least a portion of the light-emitting control signal line pattern all extend along the first direction; The first sub-pixel and the third sub-pixel each further include: a first transistor, a second transistor, a driving transistor, a data writing transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a storage capacitor; In each sub-pixel, the gate of the driving transistor is electrically connected to the second terminal of the first transistor, the first terminal of the driving transistor is electrically connected to the second terminal of the fifth transistor, and the second terminal of the driving transistor is electrically connected to the first terminal of the first transistor. The gate of the second transistor is electrically connected to the reset signal line pattern, the first terminal of the second transistor is electrically connected to the initialization signal line pattern, and the second terminal of the second transistor is electrically connected to the gate of the driving transistor. The first terminal of the data writing transistor is electrically connected to the data line pattern in the sub-pixel, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor. The gate of the fifth transistor is electrically connected to the light-emitting control signal line pattern, and the first electrode of the fifth transistor is used to be electrically connected to the power signal line pattern in the display substrate. The gate of the sixth transistor is electrically connected to the light-emitting control signal line pattern, the first terminal of the sixth transistor is electrically connected to the second terminal of the driving transistor, and the second terminal of the sixth transistor is electrically connected to the anode of the light-emitting element. The second terminal of the seventh transistor is electrically connected to the anode of the light-emitting element and is configured to provide an initialization signal to the anode of the light-emitting element; The first plate of the storage capacitor is reused as the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to the power signal line.

15. The display substrate according to claim 14, wherein, The display substrate further includes a fifth conductive connection portion, which is disposed on the same layer as the power signal line pattern and is located between the second electrode plate of the storage capacitor and the film layer where the fourth conductive connection portion is located; the second electrode of the second transistor is electrically connected to the gate of the driving transistor through the fifth conductive connection portion.

16. The display substrate according to claim 15, wherein, The orthographic projection of the first strip portion on the substrate does not overlap with the orthographic projection of the fifth conductive connection portion on the substrate.

17. The display substrate according to claim 14, wherein, The power signal line pattern is electrically connected to the first electrode of the fifth transistor and the second electrode of the storage capacitor through at least two vias, and the at least two vias are arranged along the second direction.

18. The display substrate according to claim 17, wherein, The orthographic projection of the at least two vias arranged along the second direction on the substrate overlaps with the orthographic projection of the first data line pattern on the substrate.

19. The display substrate according to claim 1, wherein, The first sub-pixel is either a red sub-pixel or a blue sub-pixel; the third sub-pixel is a green sub-pixel.

20. A display device comprising a display substrate as claimed in any one of claims 1 to 19.

Images