Display panel, preparation method thereof and display device

Abstract

The display panel comprises a substrate substrate, a driving layer and a pixel layer which are arranged in a stacked manner; the driving layer has a pixel driving circuit for driving a sub-pixel and a common electrode parallel line. The pixel layer comprises a pixel electrode layer, an organic light-emitting layer and a common electrode layer which are arranged in a stacked manner in sequence; the pixel electrode layer is formed with a lap joint structure, a pixel electrode and a switching structure; the lap joint structure is electrically connected with the common electrode parallel line through a common electrode connection via hole and is electrically connected with the common electrode layer; the switching structure is electrically connected with the pixel driving circuit through a pixel electrode connection via hole and is electrically connected with the pixel electrode. The switching structure comprises at least a second switching layer, and the material of the second switching layer is metal; the orthographic projection of the second switching layer on the substrate substrate covers at least part of the orthographic projection of the pixel electrode connection via hole on the substrate substrate. The display panel can reduce the risk of dark spot defects.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] In some display products, a common electrode can be placed and interconnected on the driving layer. This common electrode interconnection can be electrically connected to the common electrode through a common electrode connection structure. This reduces the impedance of the common electrode and improves the uniformity of the reference voltage on the common electrode. However, such display products have a higher risk of dark spot defects.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel, a method for manufacturing the same, and a display device to reduce the risk of dark spot defects.

[0005] According to one aspect of this disclosure, a display panel is provided, comprising a substrate, a driving layer, and a pixel layer stacked thereon; the driving layer having pixel driving circuitry for driving sub-pixels and a common electrode parallel line;

[0006] The pixel layer includes a pixel electrode layer, an organic light-emitting layer, and a common electrode layer, which are sequentially stacked on the side of the driving layer away from the substrate. The pixel electrode layer has an overlap structure, a pixel electrode, and a transition structure. The overlap structure is electrically connected to the common electrode in parallel via a common electrode connection via, and is also electrically connected to the common electrode layer. The transition structure is electrically connected to the pixel driving circuit via a pixel electrode connection via, and is also electrically connected to the pixel electrode.

[0007] The adapter structure includes at least a second adapter layer, the material of which is metal; the orthographic projection of the second adapter layer on the substrate covers at least a portion of the orthographic projection of the pixel electrode connection via on the substrate.

[0008] According to one embodiment of the present disclosure, the pixel electrode layer includes a first conductive oxide pattern layer, a first metal pattern layer, a second metal pattern layer, and a second conductive oxide pattern layer sequentially stacked on the side of the driving layer away from the substrate.

[0009] The second transition layer is located in one or both of the first metal pattern layer and the second metal pattern layer.

[0010] According to one embodiment of the present disclosure, the thickness of the first metal pattern layer is greater than the thickness of the second metal pattern layer;

[0011] The second transition layer is located on the second metal pattern layer.

[0012] According to one embodiment of the present disclosure, the transition structure further includes a third transition layer located on the second conductive oxide pattern layer; the orthographic projection of the second transition layer on the substrate is located within the orthographic projection of the third transition layer on the substrate.

[0013] According to one embodiment of this disclosure, the thickness of the first metal pattern layer is greater than the thickness of the second metal pattern layer; the second transition layer is located on the first metal pattern layer.

[0014] According to one embodiment of this disclosure, the second transition layer includes a bottom metal layer of the second transition layer located on the first metal pattern layer and a top metal layer of the second transition layer located on the second metal pattern layer; the orthographic projection of the bottom metal layer of the second transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate; the orthographic projection of the top metal layer of the second transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

[0015] According to one embodiment of the present disclosure, the transition structure further includes a first transition layer located on the first conductive oxide pattern layer; the orthographic projection of the first transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

[0016] According to one embodiment of the present disclosure, the pixel electrode layer further includes a third conductive oxide pattern layer located on the side of the first conductive oxide pattern layer near the substrate; the transition structure further includes a fourth transition layer located on the third conductive oxide pattern layer; the orthographic projection of the fourth transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

[0017] According to one embodiment of this disclosure, the thickness of the second metal pattern layer is 600 to 1500 angstroms.

[0018] According to one embodiment of this disclosure, the thickness of the first metal pattern layer is 4000 to 8000 angstroms.

[0019] According to one embodiment of the present disclosure, the orthographic projection of the second transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

[0020] According to one embodiment of the present disclosure, the overlapping structure includes a first overlapping layer located in the first conductive oxide pattern layer, a bottom metal layer located in the second overlapping layer of the first metal pattern layer, a top metal layer located in the second overlapping layer of the second metal pattern layer, and a third overlapping layer located in the second conductive oxide pattern layer.

[0021] The sides of the bottom metal layer and the top metal layer of the second overlap layer are recessed relative to the edge of the third overlap layer, so that the edge portion of the third overlap layer is suspended.

[0022] According to one embodiment of the present disclosure, the pixel electrode includes a first electrode layer located in the first conductive oxide pattern layer, a second electrode layer located in at least one of the first metal pattern layer and the second metal pattern layer, and a third electrode layer located in the second conductive oxide pattern layer.

[0023] According to another aspect of this disclosure, a display device is provided, including the display panel described above.

[0024] According to another aspect of this disclosure, a method for manufacturing a display panel is provided, comprising:

[0025] A driving layer is formed on one side of a substrate. The driving layer has a pixel driving circuit for driving sub-pixels and a common electrode parallel line. The driving layer is provided with a common electrode connection via that exposes a portion of the common electrode parallel line and a pixel electrode connection via that exposes the output terminal of the pixel driving circuit.

[0026] A pixel electrode layer is formed on the side of the driving layer away from the substrate. The pixel electrode layer has an overlap structure, a pixel electrode, and a transition structure. The overlap structure is electrically connected to the common electrode in parallel via a common electrode connection via. The transition structure is electrically connected to the pixel driving circuit and the pixel electrode via the pixel electrode connection via. The transition structure includes at least a second transition layer made of metal, and the orthographic projection of the second transition layer on the substrate covers at least a portion of the orthographic projection of the pixel electrode connection via on the substrate.

[0027] An organic light-emitting layer and a common electrode layer are sequentially formed on the side of the pixel electrode layer away from the substrate; the common electrode layer is electrically connected to the overlapping structure.

[0028] According to one embodiment of this disclosure, forming a pixel electrode layer on the side of the driving layer away from the substrate includes:

[0029] A pixel electrode layer is sequentially formed on the side of the driving layer away from the substrate. The pixel electrode layer includes a first conductive oxide pattern layer, a first metal pattern layer, a second metal pattern layer, and a second conductive oxide pattern layer stacked sequentially. The second transition layer is located in at least one of the first metal pattern layer and the second metal pattern layer.

[0030] According to one embodiment of this disclosure, forming a pixel electrode layer on the side of the driving layer away from the substrate includes:

[0031] A first conductive oxide material layer and a first metal material layer are sequentially formed on the side of the driving layer away from the substrate.

[0032] The first metal material layer is patterned to form a first metal pattern layer, the first metal pattern layer including the bottom metal layer of the second overlapping layer of the overlapping structure;

[0033] A second metal material layer and a second conductive oxide material layer are sequentially formed on the side of the first metal pattern layer away from the substrate.

[0034] The second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer are patterned sequentially to form a second conductive oxide pattern layer, a second metal pattern layer, and a first conductive oxide pattern layer, respectively. The second conductive oxide pattern layer includes a third overlap layer of the overlap structure, the second metal pattern layer includes a top metal layer of the second overlap layer of the overlap structure, and the first conductive oxide pattern layer includes a first overlap layer of the overlap structure. The first overlap layer, the bottom metal layer of the second overlap layer, the top metal layer of the second overlap layer, and the third overlap layer are stacked sequentially.

[0035] According to one embodiment of the present disclosure, patterning the first metal material layer to form a first metal pattern layer includes:

[0036] The first metal material layer is patterned to form a first metal pattern layer, such that the first metal pattern layer includes the bottom metal layer of the second overlapping layer of the overlapping structure and fully exposes the pixel electrode connection via.

[0037] Patterning the second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer sequentially includes:

[0038] The second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer are patterned sequentially to form a second conductive oxide pattern layer, a second metal pattern layer, and a first conductive oxide pattern layer, respectively. The second conductive oxide pattern layer includes a third overlapping layer of the overlapping structure and a third transition layer of the transition structure. The second metal pattern layer includes a top metal layer of the second overlapping layer of the overlapping structure and a second transition layer of the transition structure. The first conductive oxide pattern layer includes a first overlapping layer of the overlapping structure and a first transition layer of the transition structure. The first overlapping layer, the bottom metal layer of the second overlapping layer, the top metal layer of the second overlapping layer, and the third overlapping layer are stacked sequentially. The first transition layer, the second transition layer, and the third transition layer are stacked sequentially, and the transition structure is not connected to the first metal pattern layer.

[0039] According to one embodiment of the present disclosure, patterning the first metal material layer to form a first metal pattern layer includes:

[0040] The first metal material layer is patterned to form a first metal pattern layer, such that the first metal pattern layer includes the bottom metal layer of the second overlapping layer of the overlapping structure and the bottom metal layer of the second transition layer of the transition structure.

[0041] Patterning the second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer sequentially includes:

[0042] The second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer are patterned sequentially to form a second conductive oxide pattern layer, a second metal pattern layer, and a first conductive oxide pattern layer, respectively. The second conductive oxide pattern layer includes a third overlapping layer of the overlapping structure and a third transition layer of the transition structure. The second metal pattern layer includes a top metal layer of the second overlapping layer of the overlapping structure and a top metal layer of the second transition layer of the transition structure. The first conductive oxide pattern layer includes a first overlapping layer of the overlapping structure and a first transition layer of the transition structure. The first overlapping layer, the bottom metal layer of the second overlapping layer, the top metal layer of the second overlapping layer, and the third overlapping layer are stacked sequentially. The first transition layer, the bottom metal layer of the second transition layer, the top metal layer of the second transition layer, and the third transition layer are stacked sequentially.

[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0045] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a display panel in one embodiment of this disclosure.

[0046] Figure 2 This is a schematic diagram of a stacked layer in which the common electrode layer is electrically connected to the common electrode in parallel via an overlapping structure, according to one embodiment of the present disclosure.

[0047] Figure 3 This is a schematic diagram of the electrical connection between the adapter structure and the drive layer in one embodiment of the present disclosure.

[0048] Figure 4 This is a schematic diagram of the planar structure of the display panel in the display area according to one embodiment of the present disclosure.

[0049] Figure 5 This is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0050] Figure 6 This is a schematic diagram showing the distribution of pixel driving circuits in a pixel region according to one embodiment of this disclosure.

[0051] Figure 7 This is a schematic diagram of the source / drain metal layer in the display area according to one embodiment of the present disclosure.

[0052] Figure 8 This is a schematic diagram of the structure of the pixel electrode layer in the display area according to one embodiment of the present disclosure.

[0053] Figure 9 This is a schematic diagram of the stacked structure of the substrate and the driving layer in one embodiment of the present disclosure.

[0054] Figure 10 This is a schematic diagram of a structure in which a third conductive oxide material layer is formed on the side of the driving layer away from the substrate in the first embodiment of this disclosure.

[0055] Figure 11 This is a schematic diagram of the structure of a third conductive oxide patterned layer formed by patterning a third conductive oxide material layer in the first embodiment of this disclosure.

[0056] Figure 12This is a schematic diagram of a structure in which a first conductive oxide material layer and a first metal material layer are sequentially formed on the side of the third conductive oxide pattern layer away from the substrate.

[0057] Figure 13 This is a schematic diagram of the structure of a first metal material layer patterned to form a first metal pattern layer in a first embodiment of this disclosure.

[0058] Figure 14 This is a schematic diagram of a structure in which a second metal material layer and a second conductive oxide material layer are sequentially formed on the side of the first metal pattern layer away from the substrate.

[0059] Figure 15 This is a schematic diagram of the structure of a second conductive oxide patterned layer formed by patterning a second conductive oxide material layer in the first embodiment of this disclosure.

[0060] Figure 16 This is a schematic diagram of the structure of a second metal pattern layer formed by patterning a second metal material layer in the first embodiment of this disclosure.

[0061] Figure 17 This is a schematic diagram of the structure of a first conductive oxide patterned layer formed by patterning a first conductive oxide material layer in a first embodiment of the present disclosure.

[0062] Figure 18 This is a schematic diagram of the structure in which the first metal pattern layer and the second metal pattern layer are etched back in the first embodiment of this disclosure.

[0063] Figure 19 This is a schematic diagram of the structure of a first metal pattern layer formed by patterning a first metal material layer in a second embodiment of this disclosure.

[0064] Figure 20 This is a schematic diagram of a structure in which a second metal material layer and a second conductive oxide material layer are sequentially formed on the side of the first metal pattern layer away from the substrate.

[0065] Figure 21 This is a schematic diagram of the structure of a second conductive oxide patterned layer formed by patterning a second conductive oxide material layer, as described in the second embodiment of this disclosure.

[0066] Figure 22 This is a schematic diagram of the structure of a second metal material layer patterned to form a second metal pattern layer, according to a second embodiment of this disclosure.

[0067] Figure 23 This is a schematic diagram of the structure of a first conductive oxide patterned layer formed by patterning a first conductive oxide material layer in a second embodiment of the present disclosure.

[0068] Figure 24 This is a schematic diagram of the structure in the second embodiment of the present disclosure, in which the first metal pattern layer and the second metal pattern layer are etched back.

[0069] Figure 25 This is a schematic diagram of the structure of the second conductive oxide pattern layer formed by patterning the second conductive oxide material layer in the third embodiment of this disclosure.

[0070] Figure 26 This is a schematic diagram of the structure of a second metal pattern layer formed by patterning a second metal material layer in a third embodiment of this disclosure.

[0071] Figure 27 This is a schematic diagram of the structure of a first conductive oxide patterned layer formed by patterning a first conductive oxide material layer, according to a third embodiment of this disclosure.

[0072] Figure 28 This is a schematic diagram of the structure in the third embodiment of this disclosure, showing the re-etching of the first metal pattern layer and the second metal pattern layer. Detailed Implementation

[0073] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0074] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0075] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0076] Structural layer A is located on the side of structural layer B that faces away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the substrate serves as the height reference.

[0077] This disclosure provides a method for manufacturing a display panel and the manufactured display panel, thereby improving the yield of the display panel. See also: Figure 1 and Figures 8 to 28 The method for manufacturing this display panel includes:

[0078] Step S110: A driving layer F100 is formed on one side of the substrate BP. The driving layer F100 has a pixel driving circuit for driving sub-pixels and a common electrode parallel line VSSL. The driving layer F100 is provided with a common electrode connection via HA that exposes a portion of the common electrode parallel line VSSL and a pixel electrode connection via HB that exposes the output terminal of the pixel driving circuit.

[0079] In step S120, a pixel electrode layer PP is formed on the side of the driving layer F100 away from the substrate BP. The pixel electrode layer PP has an overlap structure RIB, a pixel electrode PIXP, and a transition structure TRP. The overlap structure RIB is electrically connected to the parallel line VSSL of the common electrode through the common electrode connection via HA. ​​The transition structure TRP is electrically connected to the pixel driving circuit through the pixel electrode connection via HB and is also electrically connected to the pixel electrode PIXP. The transition structure TRP includes at least a second transition layer TRB. The material of the second transition layer TRB is metal, and the orthographic projection of the second transition layer TRB on the substrate BP covers at least a portion (e.g., completely covers) the orthographic projection of the pixel electrode connection via HB on the substrate BP.

[0080] In step S130, an organic light-emitting layer EL and a common electrode layer COML are sequentially formed on the side of the pixel electrode layer PP away from the substrate BP; the common electrode layer COML is electrically connected to the overlapping structure RIB.

[0081] Thus, see Figure 2 and Figure 3 The display panel fabricated by the method of this disclosure includes a substrate BP, a driving layer F100, and a pixel layer F200 stacked together. The driving layer F100 has a pixel driving circuit for driving sub-pixels and a common electrode parallel line VSSL. The pixel layer F200 includes a pixel electrode layer PP, an organic light-emitting layer EL, and a common electrode layer COML stacked sequentially on the side of the driving layer F100 away from the substrate BP; the pixel electrode layer PP forms an overlap structure RIB, a pixel electrode PIXP, and a transition structure TRP; the overlap structure RIB is electrically connected to the common electrode parallel line VSSL through a common electrode connection via HA, and is also electrically connected to the common electrode layer COML; the transition structure TRP is electrically connected to the pixel driving circuit through a pixel electrode connection via HB, and is also electrically connected to the pixel electrode PIXP. The transition structure TRP includes at least a second transition layer TRB, which is made of metal. The orthographic projection of the second transition layer TRB onto the substrate BP covers at least a portion of the orthographic projection of the pixel electrode connection via HB onto the substrate BP. Further, in one example, the orthographic projection of the second transition layer TRB onto the substrate BP completely covers the orthographic projection of the pixel electrode connection via HB onto the substrate BP.

[0082] In this embodiment, the display panel has a common electrode parallel line VSSL on the driving layer F100, and this common electrode parallel line VSSL is electrically connected to the common electrode layer COML through the overlapping structure RIB. This reduces the impedance of the common electrode layer COML and improves its uniformity. Especially for display panels using transparent electrodes in the common electrode layer COML and large-size display panels, it can significantly improve the uniformity of the reference voltage VSS on the common electrode layer COML, thereby improving display uniformity.

[0083] In related technologies, the material of the transition structure TRP is a conductive metal oxide, such as indium tin oxide. Such display panels are prone to dark spot defects. Analysis and verification of the dark spot defects revealed that the TRP's shielding effect on the pixel electrode connection via HB is insufficient; the etching solution during the patterning process of the pixel electrode layer PP can penetrate through the TRP itself or from its edges into the pixel electrode connection via HB, leading to corrosion of the portion where the pixel driving circuit is electrically connected to the TRP, resulting in poor electrical connection between the pixel driving circuit and the pixel electrode PIXP. In the display panel fabrication method provided in this disclosure, the TRP includes a second transition layer TRB covering the pixel electrode connection via HB. The second transition layer TRB is made of metal and therefore has high density, effectively preventing the etching solution from penetrating through the TRB into the pixel electrode connection via HB, thereby reducing or eliminating the corrosion of the source / drain metal layer SD by the etching solution, improving the electrical connection yield between the pixel driving circuit and the pixel electrode PIXP, and thus eliminating or reducing dark spot defects.

[0084] The following is a further illustrative description of the manufacturing method and structure of the display panel in the embodiments of this disclosure, in conjunction with the accompanying drawings.

[0085] Figure 2 This is a schematic diagram of a stacked structure in which the common electrode layer COML is electrically connected to the common electrode parallel line VSSL through the overlapping structure RIB. Figure 3 This is a schematic diagram showing the stacked electrical connection between the transition structure TRP and the driving layer F100 in one embodiment of this disclosure. See also... Figure 2 and Figure 3 The display panel includes a substrate BP, a driving layer F100, and a pixel layer F200 stacked sequentially. The pixel layer F200 contains sub-pixels for display, and the driving layer F100 contains pixel driving circuits for driving the sub-pixels.

[0086] The substrate BP can be an inorganic material substrate BP, an organic material substrate BP, or a substrate BP composed of alternating layers of organic and inorganic materials. Further, the substrate BP can be a transparent substrate BP. For example, in one embodiment of this disclosure, the material of the substrate BP can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In another embodiment of this disclosure, the material of the substrate BP can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In another embodiment of this disclosure, the substrate BP can also be a flexible substrate BP, for example, the material of the substrate BP can be polyimide.

[0087] In some examples, the display panel may also include a back film layer located on the side of the substrate BP away from the driving layer F100 to protect and support the substrate BP. For example, when the display panel is a flexible display panel, the back side of the substrate BP (the surface away from the driving layer F100) may be attached with a back film layer.

[0088] In some examples, the substrate BP can be a multilayer structure, for example, it may include multiple polyimide layers and inorganic material layers sandwiched between the polyimide layers to improve the mechanical strength of the substrate BP.

[0089] The driving layer F100 is provided with pixel driving circuits for driving sub-pixels. In the driving layer F100, any pixel driving circuit may include a transistor and a storage capacitor. Further, the transistor can be a thin-film transistor (TFT), which can be selected from top-gate TFTs, bottom-gate TFTs, or dual-gate TFTs; the material of the active layer of the TFT can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, carbon nanotube semiconductor material, organic semiconductor material, or other types of semiconductor material; the TFT can be an N-type TFT or a P-type TFT.

[0090] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. For example, in one embodiment, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in another embodiment of this disclosure, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor material.

[0091] In one example, each transistor in the pixel driving circuit is a low-temperature polycrystalline silicon thin-film transistor.

[0092] In some embodiments of this disclosure, see Figure 2 The driving layer F100 may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, and a source / drain metal layer SD, stacked between the substrate BP and the pixel layer F200. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer SEMI, gate insulating layer GI, gate layer GT, and source / drain metal layer SD. The positional relationship of each layer can be determined based on the thin-film transistor's layer structure. Further, the semiconductor layer SEMI can be used to form the channel region of the transistor; the gate layer GT can be used to form the scan trace L of the display panel, the gate of the transistor, or part or all of the electrode plates of the storage capacitor; the source / drain metal layer SD can be used to form data voltage traces, driving voltage traces DataL, and other source / drain metal layer traces, or part of the electrode plates of the storage capacitor. Further, the driving layer F100 may also include an interlayer dielectric layer ILD located between the semiconductor layer SEMI and the source / drain metal layer SD, with the source / drain metal layer SD electrically connected to the semiconductor layer SEMI through vias penetrating the interlayer dielectric layer ILD.

[0093] In some embodiments of this disclosure, the driving layer F100 may include a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, and a source / drain metal layer SD, which are stacked sequentially, thus forming a top-gate thin-film transistor. It is understood that the stacked structure of the display panel of this disclosure may also be... Figure 2 Other feasible structures besides those mentioned above.

[0094] In some other embodiments of this disclosure, the driving layer F100 may include a gate layer GT, a gate insulating layer GI, a semiconductor layer SEMI, an interlayer dielectric layer ILD, and a source / drain metal layer SD stacked sequentially, thus forming a bottom-gate thin-film transistor.

[0095] In some embodiments of the display panel disclosed herein, the gate layer GT can be a single layer, or it can be configured as two or three layers as needed. In one example, the gate layer GT may include a first gate layer and a second gate layer, and the gate insulating layer GI may include a first gate insulating layer for isolating the semiconductor layer SEMI and the first gate layer, and a second gate insulating layer for isolating the first gate layer and the second gate layer. For example, the driving layer F100 may include a semiconductor layer SEMI, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer ILD, and a source / drain metal layer SD, which are sequentially stacked on one side of the substrate BP. In one example, the gate layer GT may include a first gate layer and a second gate layer, and the semiconductor layer SEMI may be sandwiched between the first gate layer and the second gate layer; the gate insulating layer GI may include a first gate insulating layer for isolating the semiconductor layer SEMI and the first gate layer, and a second gate insulating layer for isolating the second gate layer and the semiconductor layer SEMI. For example, the driving layer F100 may include a first gate layer, a first gate insulating layer, a semiconductor layer SEMI, a second gate insulating layer, a second gate layer, an interlayer dielectric layer ILD, and a source / drain metal layer SD, sequentially stacked on one side of the substrate BP. This allows the formation of a transistor with a dual-gate structure. In one example, the semiconductor layer SEMI may include a low-temperature polysilicon semiconductor layer and a metal-oxide semiconductor layer; the gate layer GT includes a first gate layer and a second gate layer; and the gate insulating layer includes first to third gate insulating layers. The driving layer F100 may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a metal-oxide semiconductor layer, a third gate insulating layer, a second gate layer, an interlayer dielectric layer ILD, and a source / drain metal layer SD, sequentially stacked on one side of the substrate BP. In one example, the semiconductor layer SEMI may include a low-temperature polysilicon semiconductor layer and a metal-oxide semiconductor layer; the gate layer GT includes first to third gate layers GT; and the gate insulating layer includes first to third gate insulating layers. The driving layer F100 may include a low-temperature polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, an insulating buffer layer, a second gate layer, a second gate insulating layer, a metal oxide semiconductor layer, a third gate insulating layer, a third gate layer GT, an interlayer dielectric layer ILD, and a source / drain metal layer SD, which are sequentially stacked on one side of the substrate BP.

[0096] In the display panel of some embodiments of this disclosure, the source / drain metal layer SD can be a single layer, or it can be configured as two or three layers as needed. In one example, the source / drain metal layer SD may include a first source / drain metal layer SD and a second source / drain metal layer SD sequentially stacked on the side of the interlayer dielectric layer ILD away from the substrate BP. An insulating layer, such as a passivation layer PVX and / or a planarization layer PLN, may be sandwiched between the first source / drain metal layer SD and the second source / drain metal layer SD. In another example, the source / drain metal layer SD may include a first source / drain metal layer SD, a second source / drain metal layer SD, and a third source / drain metal layer SD sequentially stacked on the side of the interlayer dielectric layer ILD away from the substrate BP. An insulating layer, such as a passivation layer PVX and / or a resin layer, may be sandwiched between the first source / drain metal layer SD and the second source / drain metal layer SD. An insulating layer, such as a passivation layer PVX and / or a planarization layer PLN, may be sandwiched between the second source / drain metal layer SD and the third source / drain metal layer SD.

[0097] Optional, see Figure 2 The driving layer F100 may also include a passivation layer PVX, which may be disposed on the surface of the source / drain metal layer SD away from the substrate BP, in order to protect the source / drain metal layer SD.

[0098] Optionally, see Figure 2 The driving layer F100 may further include an inorganic buffer layer Buff disposed between the substrate BP and the semiconductor layer SEMI, wherein the semiconductor layer SEMI, the gate layer GT, etc., are all located on the side of the inorganic buffer layer Buff away from the substrate BP. The material of the inorganic buffer layer Buff may be an inorganic insulating material such as silicon oxide or silicon nitride. The inorganic buffer layer Buff may be a single inorganic material layer or a multilayer stacked inorganic material layer.

[0099] Optionally, see Figure 2 The driving layer F100 may further include a planarization layer PLN located between the source / drain metal layer SD and the pixel layer F200. The planarization layer PLN can provide a planarized surface for the pixel electrode PIXP. Optionally, the material of the planarization layer PLN can be an organic material.

[0100] Optional, see Figure 2The driving layer F100 may further include a light-shielding metal layer BHL located between the semiconductor layer SEMI and the substrate BP. The light-shielding metal layer BHL may be formed directly on the surface of the substrate BP or within the inorganic buffer layer Buff. The light-shielding metal layer BHL may overlap with the channel region of the transistor in the semiconductor layer SEMI to shield light illuminating the channel region. Furthermore, the light-shielding metal layer BHL may form wiring structures and be electrically connected to at least one of the gate layer GT, the semiconductor layer SEMI, and the source / drain metal layer SD to form a capacitor and / or serve as an electrical connection adapter.

[0101] by Figure 2 Taking the example display panel as an example, the driving layer F100 of this display panel includes a light-shielding metal layer BHL, an inorganic buffer layer Buff, a semiconductor layer SEMI, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, a passivation layer PVX, and a planarization layer PLN, stacked sequentially. In this example, the semiconductor layer SEMI is made of low-temperature polycrystalline silicon semiconductor material, and the transistors used in the pixel driving circuit are top-gate type low-temperature polycrystalline silicon thin-film transistors. Figure 2 In the example, the source / drain metal layer SD has a common electrode parallel line VSSL formed, and the passivation layer PVX and the planarization layer PLN have a common electrode connection via HA that exposes at least a portion of the common electrode parallel line VSSL (see [reference]). Figure 7 The overlapping structure RIB, located on the pixel electrode layer PP, can be electrically connected to the common electrode parallel line VSSL via the common electrode connection via HA.

[0102] exist Figure 2 In the example, the electrical connection between the pixel electrode PIXP and the pixel driving circuit is not shown. See also Figure 3 The pixel electrode layer PP can also be provided with a pixel electrode PIXP and a transition structure TRP, which are electrically connected to each other (e.g., through a conductive connection structure located in the pixel electrode layer PP). The source / drain metal layer SD is provided with an electrode transition portion SDP as the output terminal of the pixel driving circuit; the planarization layer PLN and the passivation layer PVX are provided with pixel electrode connection vias HB that expose at least a portion of the electrode transition portion SDP; the transition structure TRP is electrically connected to the electrode transition portion SDP through the pixel electrode connection vias HB. In some examples, the area around the electrode transition portion SDP in the display panel can be removed (cut out) to reduce the step difference between the transition structure TRP and the electrode transition portion SDP, improving the stability of the electrical connection between the transition structure TRP and the electrode transition portion SDP. Thus, the passivation layer PVX is provided with pixel electrode connection vias HB that expose at least a portion of the electrode transition portion SDP. Further, in one example, see... Figure 3 The electrical path between the electrode junction (SDP) and the thin-film transistor is provided with traces located in the light-shielding metal layer (BHL) to improve the flexibility of the SDP layout. It is understandable that... Figure 1 The film structure of the driving layer F100 shown in the example is only one feasible way of display panel in the embodiments of this disclosure; as needed, the display panel of the embodiments of this disclosure may also adopt other driving layers F100.

[0103] In this embodiment, the pixel layer F200 may be provided with light-emitting elements electrically connected to the pixel driving circuit, and the light-emitting elements may serve as sub-pixels of the display panel. Thus, the pixel layer F200 is provided with an array of light-emitting elements, and each light-emitting element emits light under the control of the pixel driving circuit. In this disclosure, the light-emitting elements may be organic light-emitting diodes (OLEDs), polymer organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), or other types of current-driven light-emitting elements. Exemplarily, in one embodiment of this disclosure, the light-emitting element is an organic light-emitting diode (OLED). Below, taking an organic light-emitting diode as an example, a feasible structure of the pixel layer F200 will be described exemplarily.

[0104] In this example, the pixel layer F200 can be disposed on the side of the driving layer F100 away from the substrate BP, and it can include a pixel electrode layer PP, a pixel definition layer PDL, an organic light-emitting layer EL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PP has multiple pixel electrodes PIXP in the display area of ​​the display panel; the pixel definition layer PDL has multiple through-holes in the display area corresponding to the multiple pixel electrodes PIXP, with each pixel opening exposing at least a portion of the corresponding pixel electrode PIXP. The organic light-emitting layer EL at least covers the pixel electrodes PIXP exposed by the pixel definition layer PDL. The organic light-emitting layer EL can include an organic electroluminescent material layer, and can include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. Optionally, the various film layers of the organic light-emitting layer EL can be prepared by a vapor deposition process, and a fine metal mask or an open mask can be used to define the pattern of each film layer during vapor deposition. The common electrode layer COML can cover the organic light-emitting layer EL in the display area. Thus, the pixel electrode PIXP, the common electrode layer COML, and the organic light-emitting layer EL located between the pixel electrode PIXP and the common electrode layer COML form an organic light-emitting diode, and any one of the organic light-emitting diodes can serve as a sub-pixel of the display panel.

[0105] Optionally, in some examples, the pixel layer F200 may also be provided with a support pillar layer on the side of the pixel definition layer PDL away from the substrate BP. The support pillar layer is formed with multiple support pillars to support the fine metal mask during the evaporation process.

[0106] Optionally, in some examples, the pixel layer F200 may also include a light extraction layer located on the side of the common electrode layer COML away from the substrate BP to enhance the light extraction efficiency of the organic light-emitting diode.

[0107] Optionally, the display panel may further include a thin-film encapsulation layer. The thin-film encapsulation layer is disposed on the surface of the pixel layer F200 away from the substrate BP, and may include alternately stacked inorganic and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting layer EL and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area of ​​the display panel. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer includes a first inorganic encapsulation layer CVDA, an organic encapsulation layer INJ, and a second inorganic encapsulation layer CVDB, sequentially stacked on the side of the pixel layer F200 away from the substrate BP.

[0108] Optionally, the display panel may also include a touch layer, which is disposed on the side of the thin-film encapsulation layer away from the substrate BP, for realizing touch operation of the display panel.

[0109] Optionally, the display panel may also include an anti-reflection layer, which may be disposed on the side of the thin-film encapsulation layer away from the pixel layer F200, to reduce the reflection of ambient light by the display panel, thereby reducing the impact of ambient light on the display effect.

[0110] See Figure 2 and Figure 3 In the display area of ​​the display panel, the pixel electrode layer (PP) may further include an overlapping structure (RIB) and a transition structure (TRP). The transition structure (TRP) is electrically connected to the pixel driving circuit via a pixel electrode connection via (HB), and the overlapping structure (RIB) is electrically connected to the common electrode parallel line (VSSL) via a common electrode connection via (HA). See also... Figure 2The overlapping structure RIB can be configured as a T-shaped structure (especially an I-shaped structure), meaning the edge of the top film layer (the film layer furthest from the substrate BP) of the overlapping structure RIB is suspended. Thus, when the organic light-emitting layer EL and the common electrode layer COML are fabricated via vapor deposition, the organic light-emitting layer EL is discontinuous due to the suspended edge of the top film layer of the overlapping structure RIB, allowing the cross-section of the common electrode layer COML to be electrically connected to the portion below the top film layer of the overlapping structure RIB. In this way, the parallel common electrode line VSSL can be connected in parallel with the common electrode layer COML through the overlapping structure RIB.

[0111] exist Figure 3 In the previous example, the conductive connection between the pixel electrode PIXP and the transition structure TRP was not shown due to the cutting position. In the examples of this disclosure, the pixel electrode PIXP and the transition structure TRP are electrically connected to each other, and their film structures may be the same or different, with the transition structure TRP having a second transition layer TRB composed of a metallic material.

[0112] Understandable, Figure 2 and Figure 3 The illustrated pixel layer F200 structure is a feasible pixel layer F200 structure for a display panel according to an embodiment of this disclosure. Depending on the needs, other types of pixel layer F200 structures may also be used in embodiments of this disclosure, as long as they enable the common electrode layer COML to be electrically connected to the common electrode parallel line VSSL via the overlapping structure RIB, and the pixel electrode PIXP to be electrically connected to the pixel driving circuit via the adapter structure TRP.

[0113] From the perspective of the planar distribution of various structures, the display panel includes a display area and a peripheral area located on at least one side of the display area, such as a peripheral area surrounding the display area. The pixel driving circuit and the sub-pixels driven by the pixel driving circuit can be disposed within the display area.

[0114] Figure 4 A schematic diagram illustrating the planar structure of the display panel in the display area is provided as an example of one embodiment of this disclosure. See also... Figure 4 The display panel includes an array of pixel regions AA. Each pixel region AA contains multiple sub-pixels and a corresponding pixel driving circuit; the pixel driving circuit drives the corresponding sub-pixels to display an image on the display panel. Furthermore, the display area also includes a transparent region BB; along the row direction DH, the transparent region BB and the pixel regions AA are alternately arranged. At least a portion of the transparent region BB is not made of opaque materials such as metal, allowing light to pass through. Thus, the display panel can be a transparent display panel.

[0115] For example, see Figure 4In one example, the display panel includes a column of pixel regions and a column of transparent regions arranged sequentially at intervals along the row direction DH in the display area; the column of pixel regions includes a plurality of pixel regions AA arranged sequentially along the column direction DV; the column of transparent regions includes a plurality of transparent regions BB arranged sequentially along the column direction DV. Pixel regions AA are provided with pixel driving circuits and sub-pixels driven by the pixel driving circuits; at least part of the metal layer and organic layer can be removed from the transparent regions BB to improve the light transmittance of the transparent regions BB, enabling the display panel to achieve transparent display. Of course, it is understood that in some other embodiments of this disclosure, the display panel may not have transparent regions BB in the display area.

[0116] See Figure 4 For example, in each pixel region column, a column trace VL extending along the column direction DV is provided. These column traces VL include, but are not limited to, a drive power supply trace VDDL for loading the drive power supply voltage VDD, a drive voltage trace DataL for loading the data voltage Data, etc. When the pixel driving circuit needs to detect the characteristics of the driving transistor (e.g., when a sensing unit is provided), the column trace VL may also include a sensing trace SSL for transmitting the detection signal. In at least some pixel region columns, the column trace VL may also include a common electrode parallel line VSSL; for example, the column trace VL in each pixel region column also includes a common electrode parallel line VSSL. In this way, the driving layer F100 can provide multiple common electrode parallel lines VSSL and connect them in parallel with the common electrode layer COML, improving the uniformity of the reference voltage VSS on the common electrode layer COML.

[0117] In some examples, the drive power trace VDDL for loading the drive power supply voltage VDD, the drive voltage trace DataL for loading the data voltage Data, the common electrode parallel trace VSSL for parallel connection with the common electrode layer COML, and the sensing trace SSL for receiving the sensing signal SS are grouped together and set on the same layer, located between adjacent transparent areas BB, and arranged sequentially along the row direction; this makes the distribution of the common electrode parallel trace VSSL more uniform and improves the uniformity of the reference voltage VSS on the common electrode layer COML.

[0118] See Figure 4 For example, the display panel may also include walkways HL extending along the row direction DH, which may include scan traces L for driving pixel driving circuitry. Of course, if the pixel driving circuitry requires other traces, corresponding traces, such as reset lines, initial signal lines, etc., may be added to the walkways HL or column traces VL.

[0119] Figure 5An equivalent circuit diagram of a pixel driving circuit in one embodiment of this disclosure is illustrated. See also Figure 5 The pixel driving circuit includes a data writing transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst. The source of the data writing transistor T1 is used to load a data voltage Data. The drain of the data writing transistor T1, the gate of the driving transistor T2, and the first electrode plate of the storage capacitor are electrically connected to a first node N1. The gate of the data writing transistor T1 is used to load a light-emitting scanning signal G1. The source of the driving transistor T2 is used to load a driving power supply voltage VDD. The drain of the driving transistor T2, the source of the sensing transistor T3, and the pixel electrode PIXP of the sub-pixel are electrically connected to a second node N2. The gate of the sensing transistor T3 is used to load a sensing scanning signal G2, and the drain of the sensing transistor T3 is used to output a sensing signal SS. During the display phase, a light-emitting scan signal G1 can be applied to the gate of the data writing transistor T1, and a data voltage Data can be applied to the source of the data writing transistor T1. The data writing transistor T1 is turned on in response to the light-emitting scan signal G1, and the data voltage Data is applied to the first node N1. Under the control of the voltage on the first node N1, the driving transistor T2 outputs a driving current to the sub-pixel CC so that the sub-pixel CC emits light. During this display phase, a signal that turns off the sensing transistor T3 can be applied to the gate of the sensing transistor T3. During the sensing phase, a sensing scan signal G2 can be applied to the gate of the sensing transistor T3 so that the sensing transistor T3 is turned on. The driving module of the display device can receive the sensing signal SS through the sensing transistor T3, and then determine the threshold voltage and mobility of the driving transistor T2. It is understood that, as needed, the pixel driving circuit can also be a pixel driving circuit with other architectures, such as a 7T1C (7 transistors, 1 capacitor) or 8T1C (8 transistors, 1 capacitor) architecture.

[0120] Figure 6 A schematic diagram illustrating the distribution of pixel driving circuits (PDCs) in pixel region AA is provided as an example in one embodiment of this disclosure. See also... Figure 6The pixel region AA contains four pixel driving circuits PDC: a first pixel driving circuit PDC1, a second pixel driving circuit PDC2, a third pixel driving circuit PDC3, and a fourth pixel driving circuit PDC4. These four pixel driving circuits PDC can be arranged in a 2×2 configuration. In this disclosure, the area where the transistors and storage capacitors Cst of the pixel driving circuits PDC are set is defined as the pixel arrangement area pixel driving circuit PDCA. Thus, the pixel region AA has four pixel arrangement area pixel driving circuits PDCA: a first pixel arrangement area pixel driving circuit PDCA1 for setting the transistors and storage capacitors Cst of the first pixel driving circuit PDC1, a second pixel arrangement area pixel driving circuit PDCA2 for setting the transistors and storage capacitors Cst of the second pixel driving circuit PDC2, a third pixel arrangement area pixel driving circuit PDCA3 for setting the transistors and storage capacitors Cst of the third pixel driving circuit PDC3, and a fourth pixel arrangement area pixel driving circuit PDCA4 for setting the transistors and storage capacitors Cst of the fourth pixel driving circuit PDC4. Accordingly, four sub-pixels are set in the pixel area AA, and four pixel driving circuits PDC drive the sub-pixels respectively, such as red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. In this disclosure, the color of the sub-pixel is determined based on the color of the final light emitted from the display panel, rather than based on the color of the light emitted from the sub-pixel.

[0121] Thus, in each pixel region AA, the column trace VL includes driving voltage traces DataL for loading data voltage Data, driving voltage traces DataL corresponding to each pixel driving circuit PDC (i.e., the first driving voltage trace Data1L for driving the first pixel driving circuit PDC1, the second driving voltage trace Data2L for driving the second pixel driving circuit PDC2, the third driving voltage trace Data3L for driving the third pixel driving circuit PDC3, the fourth driving voltage trace Data4L for driving the fourth pixel driving circuit PDC4, etc.), sensing traces SSL for receiving sensing signals SS, and common electrode parallel trace VSSL for parallel connection with the common electrode layer COML, etc. The walkline HL can include two scan traces GL that drive the two rows of pixel driving circuits PDC respectively, namely the second scan trace G2L driving the first pixel driving circuit PDC1 and the third pixel driving circuit PDC3 and the first scan trace G1L driving the second pixel driving circuit PDC2 and the fourth pixel driving circuit PDC4.

[0122] In one example, each sub-pixel emits white light. The display panel has a color filter layer with color resist units corresponding to each sub-pixel. The light emitted by the sub-pixel passes through the corresponding color resist unit, thus producing colored light. For example, the color filter layer has a red color resist unit corresponding to the red sub-pixel; the white light emitted by the red sub-pixel passes through the red color resist unit and is ultimately emitted as red light from the display panel. The color filter layer has a green color resist unit corresponding to the green sub-pixel; the white light emitted by the green sub-pixel passes through the green color resist unit and is ultimately emitted as green light from the display panel. The color filter layer has a blue color resist unit corresponding to the blue sub-pixel; the white light emitted by the blue sub-pixel passes through the blue color resist unit and is ultimately emitted as blue light from the display panel. The color filter layer may also have colorless color resist units corresponding to white sub-pixels, or the positions corresponding to white sub-pixels may be filled with other colorless materials (such as optical adhesive), thus preventing the color filter layer from filtering light from the white sub-pixels.

[0123] In another example, different subpixels can emit different colors of light. For instance, a red subpixel can emit red light; a green subpixel can emit green light; a blue subpixel can emit blue light; and a white subpixel can emit white light.

[0124] It is understood that the descriptions of the number and distribution of pixel driving circuits (PDCs) in pixel region AA, as well as the number and color of sub-pixels, in the above embodiments are merely examples of embodiments of this disclosure. In other embodiments of this disclosure, pixel region AA may be provided with other numbers of pixel driving circuits (PDCs) and sub-pixels, may be provided with sub-pixels of other colors, and may be arranged in other ways.

[0125] In one embodiment of this disclosure, the column trace VL is disposed on the source / drain metal layer SD. For example, the common electrode parallel line VSSL is disposed on the source / drain metal layer SD and extends along the column direction DV. In a further embodiment, the gate layer GT may be provided with a parallel structure overlapping the common electrode parallel line VSSL. The parallel structure is connected in parallel with the overlapping common electrode parallel line VSSL through multiple vias to further reduce the impedance of the common electrode parallel line VSSL, thereby further improving the uniformity of the reference voltage VSS distribution on the display panel. Furthermore, the parallel structure may be discontinuous to avoid other structures on the gate layer GT, such as scan traces on the gate layer GT.

[0126] Figure 7 This is a schematic diagram of the source / drain metal layer SD in the display area in one embodiment of the present disclosure. Figure 8 This is a schematic diagram of the pixel electrode layer PP in the display area according to one embodiment of this disclosure. See also... Figure 7 The common electrode parallel line VSSL extends along the column direction DV, and the common electrode connection via HA exposes at least a portion of the common electrode parallel line VSSL. The overlap structure RIB located on the pixel electrode layer PP is electrically connected to the common electrode parallel line VSSL via the common electrode connection via HA. Figure 7 In the example, the common electrode parallel line VSSL includes a body trace extending along the column direction DV and multiple side branch VSSMs connected to the body trace. The common electrode connection via HA can expose a portion of the body trace and / or a portion of the side branch VSSMs. Of course, in other embodiments of this disclosure, the common electrode parallel line VSSL can also have other routing arrangements, for example, it may not have side branch VSSMs.

[0127] In one example, the common electrode connection via HA includes a first common electrode connection via HA1, which exposes a portion of the body trace of the common electrode parallel line VSSL. The overlap structure RIB includes a first overlap structure RIB1 corresponding to the first common electrode connection via HA1, which is electrically connected to the body trace of the common electrode parallel line VSSL via the corresponding first common electrode connection via HA1. Furthermore, one first common electrode connection via HA1 is provided in each pixel region AA. Of course, some pixel regions AA may not have a first common electrode connection via HA1, or multiple first common electrode connection vias HA1 may be provided in some pixel regions AA.

[0128] In one example, the common electrode parallel line VSSL includes a main trace and a side branch VSSM connected to the main trace; the common electrode connection via HA includes a second common electrode connection via HA2, which exposes at least a portion of the side branch VSSM; the overlap structure RIB includes a second overlap structure RIB2 corresponding to the second common electrode connection via HA2; the second overlap structure RIB2 is electrically connected to the side branch VSSM of the common electrode parallel line VSSL through the corresponding second common electrode connection via HA2. Further, the side branch VSSM extends into the transparent area BB. Further, each transparent area BB has multiple side branch VSSMs (e.g., four) of the same common electrode parallel line VSSL, and each side branch VSSM overlaps with the corresponding second common electrode connection via HA2.

[0129] In one example, such as Figure 7 and 8As shown, the second common electrode connection via HA2 is located in the transparent area BB, and the first common electrode connection via HA1 is located in the pixel area AA. The unit density of the second common electrode connection via HA2 is greater than that of the first common electrode connection via HA1. This design helps to avoid short circuits caused by excessively small spacing between holes and reduces the impact of the second common electrode connection via HA2 on the pixel circuit in the pixel area AA.

[0130] In one example, such as Figure 8 As shown, at least some of the second common electrode connection vias HA2 are staggered in the transparent area BB, which is beneficial for the second overlapping structure RIB2 to be electrically connected to the side branch VSSM of the common electrode parallel line VSSL from different positions through the corresponding second common electrode connection vias HA2, thereby improving stability.

[0131] In one example, such as Figure 8 As shown, at least a portion of the second common electrode connection via HA2 is located at a distance less than the distance between the first common electrode connection via HA1 and the pixel electrode connection via HB. Furthermore, the projection points of at least a portion of the second common electrode connection via HA2 in the row direction, the projection points of the pixel electrode connection via HB in the row direction, and the projection points of the first common electrode connection via HA1 in the row direction do not coincide. This ensures appropriate spacing between vias, simplifies the process, and guarantees device stability.

[0132] In one example, the reference voltage VSS includes a main trace and a side branch VSSM connected to the main trace, the side branch VSSM extending into a transparent region BB adjacent to the main trace. The common electrode connection via HA includes a first common electrode connection via HA1 and a second common electrode connection via HA2; the overlap structure RIB includes a first overlap structure RIB1 corresponding to the first common electrode connection via HA1 and a second overlap structure RIB2 corresponding to the second common electrode connection via HA2. The first common electrode connection via HA1 exposes a portion of the main trace of the common electrode parallel line VSSL and is located in pixel region AA; the first overlap structure RIB1 is electrically connected to the main trace of the common electrode parallel line VSSL through the corresponding first common electrode connection via HA1. The second common electrode connection via HA2 exposes at least a portion of the side branch VSSM and is located in transparent region BB; the second overlap structure RIB2 is electrically connected to the side branch VSSM of the common electrode parallel line VSSL through the corresponding second common electrode connection via HA2.

[0133] In one example, see Figure 3 and Figure 7The source / drain metal layer SD has an electrode transition portion SDP located in the transparent region BB. The electrode transition portion SDP serves as the output terminal of the pixel driving circuit PDC and is electrically connected to the trace located in the light-shielding metal layer BHL via a via, thereby connecting to the pixel driving circuit PDC. The pixel electrode connection via HB is located in the transparent region BB and overlaps with the corresponding electrode transition portion SDP. Thus, the transition structure TRP located in the pixel electrode layer PP is located in the transparent region BB and is electrically connected to the corresponding electrode transition portion SDP via the corresponding pixel electrode connection via HB. Of course, in other embodiments of this disclosure, the pixel electrode connection via HB may also be located in the pixel region AA, so that the transition structure TRP can be electrically connected to the pixel driving circuit PDC via the pixel electrode connection via HB.

[0134] In one example, see Figure 8 Each sub-pixel may include two pixel electrodes (PIXPs) electrically connected to the same transition structure (TRP). Thus, a sub-pixel may include two parallel sub-parts. When either sub-part malfunctions, it can be repaired by closing that sub-part (severing the electrical connection between the pixel electrodes (PIXPs) of that sub-part and the transition structure (TRP), while the normal display of the sub-pixel is ensured through light emission compensation of the other sub-part. Of course, in other embodiments of this disclosure, a sub-pixel may also have only one pixel electrode (PIXP), or more than three pixel electrodes (PIXPs).

[0135] In one example, see Figure 8 The pixel electrode is connected to the via HB at a distance of two pixel electrodes in the row and / or column directions.

[0136] In some embodiments of this disclosure, see Figure 2 The pixel electrode layer PP includes a first conductive oxide patterned layer POA, a first metal patterned layer PMB1, a second metal patterned layer PMB2, and a second conductive oxide patterned layer POC, which are sequentially stacked on the side of the driving layer F100 away from the substrate BP. This facilitates edge etching of the overlapping structure RIB (the middle film portion on the side is etched and shrank inward), so that the common electrode layer COML is electrically connected to the overlapping structure RIB. The second transition layer TRB is located in one or both of the first metal patterned layer PMB1 and the second metal patterned layer PMB2. Thus, the fabrication of the second transition layer TRB in the transition structure TRP can be achieved without adding a new patterning process, which can reduce the manufacturing cost of the display panel while improving the yield of the display panel.

[0137] In this embodiment, the pixel electrode layer PP can be prepared by the following method:

[0138] See Figures 12-28 A first conductive oxide material layer POAX, a first metal material layer PMB1X, a second metal material layer PMB2X, and a second conductive oxide material layer POCX are sequentially formed on the side of the driving layer F100 away from the substrate BP. The first conductive oxide material layer POAX, the first metal material layer PMB1X, the second metal material layer PMB2X, and the second conductive oxide material layer POCX are patterned to form the pixel electrode layer PP. The second transition layer TRB is formed by patterning at least one of the first metal material layer PMB1X and the second metal material layer PMB2X.

[0139] It is understandable that when patterning the first conductive oxide material layer POAX, the first metal material layer PMB1X, the second metal material layer PMB2X, and the second conductive oxide material layer POCX, the various film layers required for the overlapping structure RIB and the pixel electrode PIXP are also formed.

[0140] In one embodiment of this disclosure, the pixel electrode layer PP can be prepared using the following further preparation method:

[0141] See Figure 12 A first conductive oxide material layer POAX and a first metal material layer PMB1X are sequentially formed on the side of the driving layer F100 away from the substrate BP.

[0142] See Figure 13 The first metal material layer PMB1X is patterned to form a first metal pattern layer PMB1, the first metal pattern layer PMB1 including the bottom metal layer VSSB1 of the second overlapping layer of the overlapping structure RIB.

[0143] See Figure 14 A second metal material layer PMB2X and a second conductive oxide material layer POCX are sequentially formed on the side of the first metal pattern layer PMB1 away from the substrate BP.

[0144] See Figures 15-17 The second conductive oxide material layer POCX, the second metal material layer PMB2X, and the first conductive oxide material layer POAX are patterned sequentially to form the second conductive oxide patterned layer POC, the second metal patterned layer PMB2, and the first conductive oxide patterned layer POA, respectively; see [link to previous section]. Figure 15 The second conductive oxide patterned layer POC includes the third overlapping layer VSSC of the overlapping structure RIB; see also Figure 16The second metal pattern layer PMB2 includes the top metal layer VSSB2 of the second overlap layer of the overlap structure RIB; see also Figure 17 The first conductive oxide patterned layer POA includes the first overlap layer VSSA of the overlap structure RIB; the first overlap layer VSSA, the bottom metal layer VSSB1 of the second overlap layer, the top metal layer VSSB2 of the second overlap layer, and the third overlap layer VSSC are stacked in sequence.

[0145] Thus, the overlapping structure RIB includes a first overlapping layer VSSA located in the first conductive oxide patterned layer POA, a bottom metal layer VSSB1 located in the second overlapping layer of the first metal patterned layer PMB1, a top metal layer VSSB2 located in the second overlapping layer of the second metal patterned layer PMB2, and a third overlapping layer VSSC located in the second conductive oxide patterned layer POC. Furthermore, by using an etching solution with a high etching ratio for the bottom metal layer VSSB1 and the top metal layer VSSB2 of the second overlapping layer, the sides of the bottom metal layer VSSB1 and the top metal layer VSSB2 of the second overlapping layer can be recessed relative to the edge of the third overlapping layer VSSC, so that the edge portion of the third overlapping layer VSSC is suspended (see...). Figure 18 ).

[0146] In one example, after patterning the second conductive oxide material layer POCX, the second metal material layer PMB2X is patterned using the second conductive oxide patterned layer POC as a mask. Then, the first conductive oxide material layer POAX is patterned using the second metal patterned layer PMB2 and the first metal patterned layer PMB1 as masks. Thus, in the fabrication of the pixel electrode layer PP in this embodiment, patterning the first metal material layer PMB1X requires one mask, patterning the second conductive oxide material layer POCX requires one mask, but patterning the second metal layer PMB2X and the first conductive oxide layer POAX does not require masks. This reduces the number of masks required, thereby lowering the fabrication cost.

[0147] Optionally, after patterning the second conductive oxide material layer POCX, the second metal material layer PMB2X, and the first conductive oxide material layer POAX in sequence, the second metal pattern layer PMB2 and the first metal pattern layer PMB1 can be etched back to further etch the bottom metal layer VSSB1 of the second overlap layer and the top metal layer VSSB2 of the second overlap layer, further improving the overhang degree of the edge of the third overlap layer VSSC (see...). Figure 18This improves the tomographic effect of the RIB (Ribbed Integral) structure on the organic light-emitting layer (EL), ensuring that the common electrode layer (COML) is electrically connected to the RIB structure during the EL tomographic break. Alternatively, when etching the second metal material layer (PMB2X), it can be over-etched, resulting in the side surfaces of the bottom metal layer (VSSB1) and the top metal layer (VSSB2) of the second overlap layer being etched, achieving a shrinkage effect for both layers. This eliminates the need for re-etching the bottom metal layer (VSSB1) and the top metal layer (VSSB2) of the second overlap layer after patterning the material layer of the first conductive oxide pattern layer (POA), or reduces the re-etching time.

[0148] In this embodiment, the metal layer between the first conductive oxide patterned layer POA and the second conductive oxide patterned layer POC of the overlapping structure RIB is prepared in two separate steps. This allows the pixel electrode PIXP and the transition structure TRP to flexibly choose whether or not to include a metal layer, and to adjust the thickness of the metal layer as needed when it is included. Furthermore, the two-step preparation of the metal layer between the first conductive oxide patterned layer POA and the second conductive oxide patterned layer POC allows for a larger thickness of the metal layer in the overlapping structure RIB, which facilitates the formation of the side etching structure of the overlapping structure RIB, ensuring the electrical connection between the common electrode layer COML and the overlapping structure RIB.

[0149] In one embodiment of this disclosure, the first metal pattern layer PMB1 and the second metal pattern layer PMB2 have different thicknesses, particularly that the thickness of the first metal pattern layer PMB1 is greater than that of the second metal pattern layer PMB2. This facilitates the formation and maintenance of the side etching structure of the overlapping structure RIB, and also allows the pixel electrode PIXP and the transition structure TRP to select suitable metal layers based on their structural characteristics, such as using thinner metal layers.

[0150] Optionally, the thickness of the first metal pattern layer PMB1 is 4000–8000 angstroms. For example, the thickness of the first metal pattern layer PMB1 is 5000 angstroms. Of course, the thickness of the first metal pattern layer PMB1 can be greater or less as needed.

[0151] Optionally, the first metal pattern layer PMB1 may include a single metal layer or multiple stacked metal layers. For example, in one embodiment, the first metal pattern layer PMB1 includes a first protective metal layer and a first main metal layer stacked together. The conductivity of the first main metal layer is greater than that of the first protective metal layer, and the first main metal layer is located on the side of the first protective metal layer away from the substrate BP. For instance, the first metal pattern layer PMB1 may include a stacked molybdenum-niobium alloy layer (first protective metal layer) and a copper layer (first main metal layer). The copper layer is located on the side of the molybdenum-niobium alloy layer away from the substrate BP. Further, the thickness of the molybdenum-niobium alloy layer is 300–500 angstroms. Of course, it is understood that the first metal pattern layer PMB1 may also employ other metal film layer structures, such as a stacked titanium / aluminum layer, or a molybdenum layer.

[0152] Optionally, the thickness of the second metal pattern layer PMB2 is 600 to 1500 angstroms. For example, the thickness of the second metal pattern layer PMB2 is 1000 angstroms.

[0153] Optionally, the second metal pattern layer PMB2 may include a single metal layer or multiple stacked metal layers. For example, in one embodiment, the second metal pattern layer PMB2 includes a stacked second main metal layer and a second protective metal layer, wherein the conductivity of the second main metal layer is greater than that of the second protective metal layer, and the second protective metal layer is located on the side of the second main metal layer away from the substrate BP. For instance, the second metal pattern layer PMB2 may include a stacked copper layer (second main metal layer) and a molybdenum-niobium alloy layer (second protective metal layer). The copper layer is located on the side of the molybdenum-niobium alloy layer closest to the substrate BP. Further, the thickness of the molybdenum-niobium alloy layer is 300–500 angstroms. Of course, it is understood that the second metal pattern layer PMB2 may also employ other metal film layer structures, such as a stacked aluminum / titanium nitride layer, or a molybdenum layer.

[0154] In one example, the thickness of the first metal pattern layer PMB1 is greater than the thickness of the second metal pattern layer PMB2. The first metal pattern layer PMB1 includes a first protective metal layer and a first main metal layer stacked together, with the first main metal layer located on the side of the first protective metal layer away from the substrate BP. The second metal pattern layer PMB2 includes a second main metal layer and a second protective metal layer stacked together, with the second protective metal layer located on the side of the second main metal layer away from the substrate BP. The conductivity of the first main metal layer is greater than that of the first protective metal layer; the conductivity of the second main metal layer is greater than that of the second protective metal layer.

[0155] Furthermore, the materials of the first main metal layer and the second main metal layer are the same; the materials of the first protective metal layer and the second protective metal layer are also the same. For example, the materials of both the first and second main metal layers are copper, and the materials of both the first and second protective metal layers are molybdenum-niobium alloys. Thus, in the overlapping structure RIB, the boundary between the bottom metal layer VSSB1 and the top metal layer VSSB2 of the second overlapping layer can be indistinct or merged; for example, the first and second main metal layers can be merged into a single metal layer.

[0156] Optionally, the materials of the first conductive oxide patterned layer POA and the second conductive oxide patterned layer POC can be conductive metal oxides, such as ITO (indium tin oxide). Thus, the material types of the first conductive oxide patterned layer POA and the second conductive oxide patterned layer POC are different from the material types of the first metal patterned layer PMB1 and the second metal patterned layer PMB2, which facilitates selective etching, allowing the overlapping structure RIB to be etched laterally, thereby leaving the edge of the third overlapping layer VSSC suspended.

[0157] See Figure 3 In one embodiment of this disclosure, the transition structure TRP further includes a first transition layer TRA located on the first conductive oxide patterned layer POA. The orthographic projection of the first transition layer TRA on the substrate BP completely covers the orthographic projection of the pixel electrode connection via HB on the substrate BP.

[0158] During the fabrication of the transition structure TRP, when the first metal material layer PMB1X and / or the second metal material layer PMB2X are patterned, the first conductive oxide material layer POAX has not yet been patterned. Therefore, the complete first conductive oxide material layer POAX can protect the pixel electrode connection via HB, thereby reducing the risk of etching solution leakage into the pixel electrode connection via HB, especially eliminating the risk of etching solution penetrating into the pixel electrode connection via HB through the edge of the transition structure TRP. When the first conductive oxide material layer POAX is patterned, the patterning operations of the first metal material layer PMB1X and the second metal material layer PMB2X have been completed. Therefore, during the patterning process of the first conductive oxide material layer POAX, a second transition layer TRB for protecting the pixel electrode connection via HB has already been formed on the first conductive oxide material layer POAX. Thus, the patterning process of the first conductive oxide material layer POAX will not cause the electrode transition portion SDP in the pixel electrode connection via HB to be corroded, resulting in black spot defects. Even in some examples, the first metal patterned layer PMB1 and the second metal patterned layer PMB2 are etched back after the first conductive oxide material layer POAX is patterned (e.g. Figure 18However, at this time, the pixel electrode connection via HB is already under the shielding of the adapter structure TRP, so the risk of the etching solution penetrating into the pixel electrode connection via HB is very low.

[0159] It is understandable that, in the manufacturing method of the display panel, see... Figure 17 When the first conductive oxide material layer POAX is patterned, in addition to forming the first overlapping layer VSSA located on the first conductive oxide patterned layer POA, a first transition layer TRA located on the first conductive oxide patterned layer POA is also formed.

[0160] In one embodiment of this disclosure, the thickness of the first metal patterned layer PMB1 is greater than the thickness of the second metal patterned layer PMB2. The second transition layer TRB is located on the second metal patterned layer PMB2. In other words, see [link to relevant documentation]. Figure 17 During the patterning operation of the second metal material layer PMB2X, a second transition layer TRB is formed, thus giving the second metal patterned layer PMB2 the second transition layer TRB. During the patterning operation of the first metal material layer PMB1X (see...), Figure 13 As shown, this allows the first metal pattern layer PMB1 to expose the area where the first transition layer TRA is located. In this way, the second transition layer TRB located on the second metal pattern layer PMB2 can be directly stacked on the first transition layer TRA located on the first conductive oxide pattern layer POA. This arrangement allows for a thinner metal layer in the transition structure TRP and improves the uniformity and thickness controllability of the transition structure TRP.

[0161] Further, see Figure 18 The transition structure TRP further includes a third transition layer TRC located on the side of the second transition layer TRB away from the substrate BP. The third transition layer TRC is located on the second conductive oxide patterned layer POC, which is formed during the patterning process of the second conductive oxide material layer POCX. The orthographic projection of the second transition layer TRB onto the substrate BP lies within the orthographic projection of the third transition layer TRC onto the substrate BP. Furthermore, the orthographic projection of the second transition layer TRB onto the substrate BP lies within the orthographic projection of the third transition layer TRC onto the substrate BP, and the edge of the third transition layer TRC is suspended. Thus, the transition structure TRP includes a first transition layer TRA, a second transition layer TRB, and a third transition layer TRC sequentially stacked on the side of the driving layer F100 away from the substrate BP.

[0162] Figures 12-18 An exemplary method for fabricating the pixel electrode layer PP in this embodiment is illustrated. The fabrication method includes:

[0163] Step S210, see Figure 12On the side of the driving layer F100 away from the substrate BP, a first conductive oxide material layer POAX and a first metal material layer PMB1X are sequentially formed.

[0164] Step S221, see Figure 13 The first metal material layer PMB1X is patterned to form a first metal pattern layer PMB1. The first metal pattern layer PMB1 has a bottom metal layer VSSB1 of the second overlapping layer as part of the overlapping structure RIB (the orthographic projection of the bottom metal layer VSSB1 of the second overlapping layer on the substrate BP covers the orthographic projection of the common electrode connection via HA on the substrate BP), and is cut out in the area used to form the pixel electrode PIXP and the transition structure TRP.

[0165] Step S231, see Figure 14 On the side of the first metal pattern layer PMB1 away from the substrate BP, a second metal material layer PMB2X and a second conductive oxide material layer POCX are sequentially formed.

[0166] Step S241, see Figure 15 The second conductive oxide material layer POCX is patterned to form a second conductive oxide patterned layer POC. The second conductive oxide patterned layer POC has a third overlapping layer VSSC (the orthographic projection of the third overlapping layer VSSC on the substrate BP, covering the orthographic projection of the common electrode connection via HA on the substrate BP) as part of the overlapping structure RIB, a third electrode layer PIXC as part of the pixel electrode PIXP, and a third transition layer TRC (the orthographic projection of the third transition layer TRC on the substrate BP, covering the orthographic projection of the pixel electrode connection via HB on the substrate BP) as part of the transition structure TRP. Thus, the second conductive oxide patterned layer POC can serve as a mask for subsequent patterning operations.

[0167] Step S251, see Figure 16Using the second conductive oxide patterned layer POC as a mask, the second metal material layer PMB2X is patterned to form the second metal patterned layer PMB2. The second metal patterned layer PMB2 has a top metal layer VSSB2 (the orthographic projection of the top metal layer VSSB2 on the substrate BP, which is part of the overlap structure RIB, and is located within the orthographic projection of the third overlap layer VSSC on the substrate BP), a second electrode layer PIXB (the orthographic projection of the second electrode layer PIXB on the substrate BP, which is part of the pixel electrode PIXP, and is located within the orthographic projection of the third electrode layer PIXC on the substrate BP), and a second transition layer TRB (the orthographic projection of the second transition layer TRB on the substrate BP, which is located within the orthographic projection of the third transition layer TRC on the substrate BP, which is part of the transition structure TRP).

[0168] Step S261, see Figure 17 Using the second conductive oxide patterned layer POC, the second metal patterned layer PMB2, and the first metal patterned layer PMB1 as a mask, the first conductive oxide material layer POAX is patterned to form a first conductive oxide patterned layer POA. The first conductive oxide patterned layer POA has a first overlapping layer VSSA (part of the overlapping structure RIB), a first electrode layer PIXA (part of the pixel electrode PIXP), and a first transition layer TRA (part of the transition structure TRP). Thus, the overlapping structure RIB includes the first overlapping layer VSSA, the bottom metal layer VSSB1 of the second overlapping layer, the top metal layer VSSB2 of the second overlapping layer, and the third overlapping layer VSSC, stacked sequentially. The pixel electrode PIXP includes the first electrode layer PIXA, the second electrode layer PIXB, and the third electrode layer PIXC, stacked sequentially. The transition structure TRP includes the first transition layer TRA, the second transition layer TRB, and the third transition layer TRC, stacked sequentially. In this example, the second electrode layer PIXB is located on the second metal pattern layer PMB2. This allows the second electrode layer PIXB to have a smaller thickness, which in turn helps to improve the stability of the pixel electrode PIXP and the light emission effect of the sub-pixels.

[0169] Step S271, see Figure 18 The second metal pattern layer PMB2 and the first metal pattern layer PMB1 are etched back, so that the sides of the bottom metal layer VSSB1 of the second overlap layer and the top metal layer VSSB2 of the second overlap layer are etched and retracted into the range of the third overlap layer VSSC, so that the edge of the third overlap layer VSSC is suspended.

[0170] In another embodiment of this disclosure, see [link to relevant documentation]. Figure 24 The thickness of the first metal patterned layer PMB1 is greater than the thickness of the second metal patterned layer PMB2; the second transition layer TRB is located on the first metal patterned layer PMB1. In other words, when the first metal material layer PMB1X is patterned, the first metal material layer PMB1X forms the second transition layer TRB. Further, when the second conductive oxide material layer POCX and the second metal material layer PMB2X are patterned, the second conductive oxide patterned layer POC and the second metal patterned layer PMB2 can expose the second transition layer TRB. Thus, the transition structure TRP includes the first transition layer TRA located on the first conductive oxide patterned layer POA and the second transition layer TRB located on the first metal patterned layer PMB1, and the transition structure TRP does not include the structure located on the second metal patterned layer PMB2 and the second conductive oxide patterned layer POC. In this embodiment, from the start of patterning of the first metal material layer PMB1X, a metal layer is already present above the pixel electrode connection via HB for shielding, which can better shield the etching solution in subsequent etching processes. It is understandable that in this embodiment, during the etching process of the second metal material layer PMB2X and the etching back of the second metal pattern layer PMB2 and the first metal pattern layer PMB1, the etching solution will etch the upper surface (the surface away from the substrate BP) of the second transition layer TRB. This may result in the thickness of the second transition layer TRB being thinner than the thickness of the bottom metal layer VSSB1 of the second overlapping layer in the overlapping structure RIB, and may also result in insufficient surface flatness of the second transition layer TRB.

[0171] Figure 12 , Figures 19-24 An exemplary method for fabricating the pixel electrode layer PP in this embodiment is illustrated. The fabrication method includes:

[0172] Step S210, see Figure 12 On the side of the driving layer F100 away from the substrate BP, a first conductive oxide material layer POAX and a first metal material layer PMB1X are sequentially formed.

[0173] Step S222, see Figure 19The first metal material layer PMB1X is patterned to form a first metal pattern layer PMB1. The first metal pattern layer PMB1 has a bottom metal layer VSSB1 (the orthographic projection of the bottom metal layer VSSB1 on the substrate BP, which covers the orthographic projection of the common electrode connection via HA on the substrate BP) as part of the overlap structure RIB, and a second transition layer TRB (the orthographic projection of the second transition layer TRB on the substrate BP, which covers the orthographic projection of the pixel electrode connection via HB on the substrate BP) as part of the transition structure TRP. The first metal pattern layer PMB1 is cut out in the area used to form the pixel electrode PIXP.

[0174] Step S232, see Figure 20 On the side of the first metal pattern layer PMB1 away from the substrate BP, a second metal material layer PMB2X and a second conductive oxide material layer POCX are sequentially formed.

[0175] Step S242, see Figure 21 The second conductive oxide material layer POCX is patterned to form a second conductive oxide patterned layer POC. The second conductive oxide patterned layer POC has a third overlap layer VSSC (the orthographic projection of the third overlap layer VSSC onto the substrate BP, covering the orthographic projection of the common electrode connection via HA onto the substrate BP) as part of the overlap structure RIB, and a third electrode layer PIXC as part of the pixel electrode PIXP. Thus, the second conductive oxide patterned layer POC can serve as a mask for subsequent patterning operations.

[0176] Step S252, see Figure 22 Using the second conductive oxide patterned layer POC as a mask, the second metal material layer PMB2X is patterned to form a second metal patterned layer PMB2. This second metal patterned layer PMB2 has a top metal layer VSSB2 (the orthographic projection of the top metal layer VSSB2 on the substrate BP, located within the orthographic projection of the third overlap layer VSSC on the substrate BP), which is part of the overlap structure RIB, and a second electrode layer PIXB (the orthographic projection of the second electrode layer PIXB on the substrate BP, located within the orthographic projection of the third electrode layer PIXC on the substrate BP), which is part of the pixel electrode PIXP. In the region used to form the transition structure TRP, due to the lack of masking by the second conductive oxide patterned layer POC, the second metal material layer PMB2X is completely removed, exposing the second transition layer TRB.

[0177] Step S262, see Figure 23 Using the second conductive oxide patterned layer POC, the second metal patterned layer PMB2, and the first metal patterned layer PMB1 as a mask, the first conductive oxide material layer POAX is patterned to form a first conductive oxide patterned layer POA. The first conductive oxide patterned layer POA has a first overlapping layer VSSA (part of the overlapping structure RIB), a first electrode layer PIXA (part of the pixel electrode PIXP), and a first transition layer TRA (part of the transition structure TRP). Thus, the overlapping structure RIB includes the first overlapping layer VSSA, the bottom metal layer VSSB1 of the second overlapping layer, the top metal layer VSSB2 of the second overlapping layer, and the third overlapping layer VSSC, stacked sequentially. The pixel electrode PIXP includes the first electrode layer PIXA, the second electrode layer PIXB, and the third electrode layer PIXC, stacked sequentially. The transition structure TRP includes the first transition layer TRA, the second transition layer TRB, and the third transition layer TRC, stacked sequentially. In this example, the second electrode layer PIXB is located on the second metal pattern layer PMB2. This allows the second electrode layer PIXB to have a smaller thickness, which in turn helps to improve the stability of the pixel electrode PIXP and the light emission effect of the sub-pixels.

[0178] Step S272, see Figure 24 The second metal pattern layer PMB2 and the first metal pattern layer PMB1 are etched back, so that the sides of the bottom metal layer VSSB1 of the second overlap layer and the top metal layer VSSB2 of the second overlap layer are etched and retracted into the range of the third overlap layer VSSC, so that the edge of the third overlap layer VSSC is suspended.

[0179] In another embodiment of this disclosure, see [link to relevant documentation]. Figure 28 The second transition layer TRB includes a bottom metal layer TRB1 located in the second transition layer of the first metal pattern layer PMB1 and a top metal layer TRB2 located in the second transition layer of the second metal pattern layer PMB2. The orthographic projection of the bottom metal layer TRB1 on the substrate BP completely covers the orthographic projection of the pixel electrode connection via HB on the substrate BP; the orthographic projection of the top metal layer TRB2 on the substrate BP completely covers the orthographic projection of the pixel electrode connection via HB on the substrate BP. In other words, the second transition layer TRB can be fabricated using the metals of both the first metal material layer PMB1X and the second metal material layer PMB2X. Furthermore, the transition structure TRP may also include a third transition layer TRC located in the second conductive oxide pattern layer POC.

[0180] Figure 12, Figures 19-24 An exemplary method for fabricating the pixel electrode layer PP in this embodiment is illustrated. The fabrication method includes:

[0181] Step S210, see Figure 12 On the side of the driving layer F100 away from the substrate BP, a first conductive oxide material layer POAX and a first metal material layer PMB1X are sequentially formed.

[0182] Step S222, see Figure 19 The first metal material layer PMB1X is patterned to form a first metal pattern layer PMB1. The first metal pattern layer PMB1 has a bottom metal layer VSSB1 of the second overlapping layer as part of the overlapping structure RIB (the orthographic projection of the bottom metal layer VSSB1 of the second overlapping layer on the substrate BP covers the orthographic projection of the common electrode connection via HA on the substrate BP), and a bottom metal layer TRB1 of the second transition layer as part of the transition structure TRP (the orthographic projection of the bottom metal layer TRB1 of the second transition layer on the substrate BP covers the orthographic projection of the pixel electrode connection via HB on the substrate BP). The first metal pattern layer PMB1 is cut out in the area used to form the pixel electrode PIXP.

[0183] Step S232, see Figure 20 On the side of the first metal pattern layer PMB1 away from the substrate BP, a second metal material layer PMB2X and a second conductive oxide material layer POCX are sequentially formed.

[0184] Step S243, see Figure 25 The second conductive oxide material layer POCX is patterned to form a second conductive oxide patterned layer POC. The second conductive oxide patterned layer POC has a third overlap layer VSSC (the orthographic projection of the third overlap layer VSSC on the substrate BP, covering the orthographic projection of the common electrode connection via HA on the substrate BP) as part of the overlap structure RIB, a third electrode layer PIXC as part of the pixel electrode PIXP, and a third transition layer TRC (the orthographic projection of the third transition layer TRC on the substrate BP, covering the orthographic projection of the pixel electrode connection via HB on the substrate BP) as part of the transition structure TRP. Thus, the second conductive oxide patterned layer POC can serve as a mask for subsequent patterning operations.

[0185] Step S253, see Figure 26Using the second conductive oxide patterned layer POC as a mask, the second metal material layer PMB2X is patterned to form the second metal patterned layer PMB2. The second metal patterned layer PMB2 has a top metal layer VSSB2 (the orthographic projection of the top metal layer VSSB2 on the substrate BP, which is part of the RIB overlap structure, and lies within the orthographic projection of the third overlap layer VSSC on the substrate BP) as part of the RIB overlap structure, a second electrode layer PIXB (the orthographic projection of the second electrode layer PIXB on the substrate BP, which lies within the orthographic projection of the third electrode layer PIXC on the substrate BP) as part of the PIXP pixel electrode, and a top metal layer TRB2 (the orthographic projection of the top metal layer TRB2 on the substrate BP, which lies within the orthographic projection of the third transition layer TRC on the substrate BP) as part of the TRP transition structure.

[0186] Step S263, see Figure 27 Using the second conductive oxide patterned layer POC, the second metal patterned layer PMB2, and the first metal patterned layer PMB1 as a mask, the first conductive oxide material layer POAX is patterned to form a first conductive oxide patterned layer POA. The first conductive oxide patterned layer POA has a first overlap layer VSSA (part of the overlap structure RIB), a first electrode layer PIXA (part of the pixel electrode PIXP), and a first transition layer TRA (part of the transition structure TRP). Thus, the overlap structure RIB includes the first overlap layer VSSA, the bottom metal layer VSSB1 of the second overlap layer, the top metal layer VSSB2 of the second overlap layer, and the third overlap layer VSSC, stacked sequentially. The pixel electrode PIXP includes the first electrode layer PIXA, the second electrode layer PIXB, and the third electrode layer PIXC, stacked sequentially. The transition structure TRP includes a first transition layer TRA, a second transition layer TRB (including a bottom metal layer TRB1 and a top metal layer TRB2 of the stacked second transition layer), and a third transition layer TRC, which are stacked sequentially. In this example, the second electrode layer PIXB is located on the second metal pattern layer PMB2. This allows the second electrode layer PIXB to have a smaller thickness, which in turn helps to improve the stability of the pixel electrode PIXP and the light emission effect of the sub-pixel.

[0187] Step S273, see Figure 28The second metal pattern layer PMB2 and the first metal pattern layer PMB1 are etched back, so that the sides of the bottom metal layer VSSB1 of the second overlap layer and the top metal layer VSSB2 of the second overlap layer are etched and retracted into the range of the third overlap layer VSSC, so that the edge of the third overlap layer VSSC is suspended.

[0188] In one embodiment of this disclosure, the pixel electrode PIXP includes a first electrode layer PIXA located in the first conductive oxide patterned layer POA, a second electrode layer PIXB located in at least one of the first metal patterned layer PMB1 and the second metal patterned layer PMB2, and a third electrode layer PIXC located in the second conductive oxide patterned layer POC. Thus, when the first conductive oxide material layer POA is patterned, the first electrode layer PIXA can be formed; and when the second conductive oxide material layer POC is patterned, the third electrode layer PIXC can be formed.

[0189] In one example, the second electrode layer PIXB is located on the second metal pattern layer PMB2. Since the thickness of the second metal pattern layer PMB2 is less than that of the first metal pattern layer PMB1, placing the second electrode layer PIXB on the second metal pattern layer PMB2 reduces the thickness of the second electrode layer PIXB, decreases the overhang of the edge of the third electrode layer PIXC, and improves the luminous efficacy and yield of the sub-pixels. In this example, when the first metal material layer PMB1X is patterned, the first metal pattern layer PMB1 may not cover the area where the pixel electrode PIXP is located, ensuring that the pixel electrode PIXP does not have a film layer located on the first metal pattern layer PMB1. When the second metal material layer PMB2X is patterned using the third electrode layer PIXC as a mask, the second electrode layer PIXB can be formed in the area where the pixel electrode PIXP is located. Furthermore, during the patterning process of the second metal material layer PMB2X and / or the etch-back process of the second metal pattern layer PMB2, the edge of the second electrode layer PIXB (the side is etched) can be recessed relative to the edge of the third electrode layer PIXC, thereby making the edge of the third electrode layer PIXC suspended.

[0190] Of course, the second electrode layer PIXB can also be located simultaneously in the first metal pattern layer PMB1 and the second metal pattern layer PMB2. For example, in one example, the second electrode layer PIXB includes a bottom metal layer PIXB1 located in the second electrode layer of the first metal pattern layer PMB1 and a top metal layer PIXB2 located in the second electrode layer of the second metal pattern layer PMB2. Thus, the pixel electrode PIXP includes a first electrode layer PIXA (located in the first conductive oxide pattern layer POA), a bottom metal layer PIXB1 (located in the first metal pattern layer PMB1), a top metal layer PIXB2 (located in the second metal pattern layer PMB2), and a third electrode layer PIXC (located in the second conductive oxide pattern layer POC) stacked sequentially. When the first metal material layer PMB1X is patterned, the first metal pattern layer PMB1 forms the bottom metal layer PIXB1 of the second electrode layer; when the second metal material layer PMB2X is patterned, the second metal pattern layer PMB2 forms the top metal layer PIXB2 of the second electrode layer.

[0191] In other embodiments of this disclosure, see [link to relevant documentation]. Figure 18 The pixel electrode layer PP further includes a third conductive oxide patterned layer POD located on the side of the first conductive oxide patterned layer POA near the substrate BP; in other words, the pixel electrode layer PP includes a third conductive oxide patterned layer POD, a first conductive oxide patterned layer POA, a first metal patterned layer PMB1, a second metal patterned layer PMB2, and a second conductive oxide patterned layer POC stacked sequentially. The third conductive oxide patterned layer POD can form at least a portion of the structure of the pixel electrode layer PP, for example, such that the overlapping structure RIB has a fourth overlapping layer VSSD located on the third conductive oxide patterned layer POD, and / or such that the pixel electrode PIXP has a fourth electrode layer PIXD located on the third conductive oxide patterned layer POD, and / or such that the transition structure TRP has a fourth transition layer TRD located on the third conductive oxide patterned layer POD.

[0192] In one example, the overlap structure RIB has a fourth overlap layer VSSD located on the third conductive oxide patterned layer POD; the pixel electrode PIXP has a fourth electrode layer PIXD located on the third conductive oxide patterned layer POD; and the transition structure TRP has a fourth transition layer TRD located on the third conductive oxide patterned layer POD. The fourth overlap layer VSSD is electrically connected to the common electrode parallel line VSSL via a common electrode connection via HA, and the fourth transition layer TRD is electrically connected to the pixel drive circuit PDC via a pixel electrode connection via HB, for example, to the electrode transition section SDP.

[0193] In one example, when fabricating the pixel electrode layer PP, a third conductive oxide material layer PODX can be formed first on the side of the driving layer F100 away from the substrate BP (see [link to documentation]). Figure 9 and Figure 10 Then, the third conductive oxide material layer PODX is patterned to form the third conductive oxide patterned layer POD (see...). Figure 11 Next, a first conductive oxide material layer POAX is formed on the side of the third conductive oxide patterned layer POD away from the substrate BP. Further, after the third conductive oxide patterned layer PODX is patterned to form the third conductive oxide patterned layer POD, and before the first conductive oxide material layer POAX is prepared, the substrate with the third conductive oxide patterned layer POD can be inspected, for example, by performing an array test (AT test). This allows for the timely removal of defective substrates or the repair of substrates with repairable defects, ensuring that substrates entering subsequent processes (such as forming the first conductive oxide patterned layer POA) are inspected or repaired, thereby eliminating waste and reducing costs. Of course, it is understood that in other examples of this disclosure, array inspection and defect repair can be performed after the pixel electrode layer PP is prepared.

[0194] In one example, the material of the third conductive oxide patterned layer POD is a conductive metal oxide, such as ITO.

[0195] In one embodiment of this disclosure, see Figure 2 The orthographic projection of the fourth lap layer VSSD onto the substrate BP is at least partially outside the orthographic projection of the first lap layer VSSA onto the substrate BP; for example, the orthographic projection of the first lap layer VSSA onto the substrate BP is completely within the orthographic projection of the fourth lap layer VSSD onto the substrate BP and there is a gap between it and the edge of the orthographic projection of the fourth lap layer VSSD. Thus, from a top view, the fourth lap layer VSSD at least partially extends beyond the first lap layer VSSA, which ensures that the common electrode layer COML can be electrically connected at the fault location to either the bottom metal layer VSSB1 or the top metal layer VSSB2 of the second lap layer during deposition.

[0196] In one embodiment of this disclosure, after forming the pixel electrode layer PP, the method for fabricating the display panel may further include sequentially forming a pixel definition layer PDL, an organic light-emitting layer EL (e.g., formed using a vapor deposition process), and a common electrode layer COML (e.g., formed using a vapor deposition process), wherein the pixel definition layer PDL exposes at least a portion of the edge of the third overlap layer VSSC. Thus, the common electrode layer COML is discontinuous at the exposed edge of the third overlap layer VSSC, thereby partially entering the suspended space (side etching space) of the transition structure TRP and electrically connecting with the bottom metal layer VSSB1 and / or the top metal layer VSSB2 of the second overlap layer supporting the third overlap layer VSSC.

[0197] Optionally, the pixel definition layer PDL covers the edge of the fourth overlap layer VSSD and has a gap between it and the edge of the third overlap layer VSSC.

[0198] In one embodiment of this disclosure, the pixel definition layer (PDL) covers the edge of the pixel electrode (PIXP) to define the light emission position and light emission area of ​​the sub-pixel.

[0199] In one embodiment of this disclosure, the pixel definition layer PDL covers the transition structure TRP and the electrical connection structure between the pixel electrode PIXP and the transition structure TRP, thereby defining the light-emitting area of ​​the sub-pixel on the one hand, and preventing the pixel electrode PIXP and the transition structure TRP from short-circuiting with the common electrode layer COML on the other hand.

[0200] In one example, the electrical connection structure between the pixel electrode PIXP and the transition structure TRP is located in the pixel electrode layer PP, and its film structure is identical to that of either the pixel electrode PIXP or the transition structure TRP. In a further example, the pixel electrode PIXP and the transition structure TRP have identical film structures, for example, both including portions located in the third conductive oxide patterned layer POD, the first conductive oxide patterned layer POA, the second metal patterned layer PMB2, and the second conductive oxide patterned layer POC.

[0201] This disclosure also provides a display device, which includes any of the display panels described in the above-described display panel embodiments. The display device can be a television set, an advertising screen, a billboard, a transparent shop window display, or other types of display devices. Since this display device has any of the display panels described in the above-described display panel embodiments, it has the same beneficial effects, and will not be repeated here.

[0202] It is understood that the display panel provided in this disclosure can be used not only in the display field, but also as a light-emitting substrate for use in the lighting field, such as as a light-emitting substrate for lighting devices such as lamps, vehicle lights, and ambient lights.

[0203] It should be noted that although the steps of the method for preparing the display panel in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0204] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a substrate, a driving layer, and a pixel layer stacked thereon; characterized in that, The driving layer has a pixel driving circuit for driving sub-pixels and a common electrode parallel line; The pixel layer includes a pixel electrode layer, an organic light-emitting layer, and a common electrode layer, which are sequentially stacked on the side of the driving layer away from the substrate. The pixel electrode layer has an overlap structure, a pixel electrode, and a transition structure. The overlap structure is electrically connected to the common electrode in parallel via a common electrode connection via, and is also electrically connected to the common electrode layer. The transition structure is electrically connected to the pixel driving circuit via a pixel electrode connection via, and is also electrically connected to the pixel electrode. The transition structure includes at least a second transition layer, the material of which is metal; the orthographic projection of the second transition layer on the substrate covers at least a portion of the orthographic projection of the pixel electrode connection via on the substrate. The pixel electrode layer includes a first conductive oxide pattern layer, a first metal pattern layer, a second metal pattern layer, and a second conductive oxide pattern layer, which are sequentially stacked on the side of the driving layer away from the substrate. The second transition layer is located in one or both of the first metal pattern layer and the second metal pattern layer; The display panel further includes: the thickness of the first metal pattern layer is greater than the thickness of the second metal pattern layer; the second transition layer is located on the second metal pattern layer; Alternatively, the transition structure may further include a third transition layer located on the second conductive oxide patterned layer; the orthographic projection of the second transition layer on the substrate is located within the orthographic projection of the third transition layer on the substrate. Alternatively, the thickness of the first metal pattern layer is greater than the thickness of the second metal pattern layer; the second transition layer is located on the first metal pattern layer. Alternatively, the pixel electrode layer may further include a third conductive oxide pattern layer located on the side of the first conductive oxide pattern layer near the substrate; the transition structure may further include a fourth transition layer located on the third conductive oxide pattern layer; the orthographic projection of the fourth transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

2. The display panel according to claim 1, characterized in that, The second transition layer includes a bottom metal layer of the second transition layer located on the first metal pattern layer and a top metal layer of the second transition layer located on the second metal pattern layer; the orthographic projection of the bottom metal layer of the second transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate; the orthographic projection of the top metal layer of the second transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

3. The display panel according to claim 1, characterized in that, The adapter structure further includes a first adapter layer located on the first conductive oxide pattern layer; the orthographic projection of the first adapter layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

4. The display panel according to claim 1, characterized in that, The thickness of the second metal pattern layer is 600 to 1500 angstroms; and / or the thickness of the first metal pattern layer is 4000 to 8000 angstroms.

5. The display panel according to claim 1, characterized in that, The orthographic projection of the second transition layer on the substrate completely covers the orthographic projection of the pixel electrode connection via on the substrate.

6. The display panel according to claim 1, characterized in that, The overlapping structure includes a first overlapping layer located in the first conductive oxide pattern layer, a bottom metal layer located in the second overlapping layer of the first metal pattern layer, a top metal layer located in the second overlapping layer of the second metal pattern layer, and a third overlapping layer located in the second conductive oxide pattern layer. The sides of the bottom metal layer and the top metal layer of the second overlap layer are recessed relative to the edge of the third overlap layer, so that the edge portion of the third overlap layer is suspended.

7. The display panel according to claim 1, characterized in that, The pixel electrode includes a first electrode layer located in the first conductive oxide pattern layer, a second electrode layer located in at least one of the first metal pattern layer and the second metal pattern layer, and a third electrode layer located in the second conductive oxide pattern layer.

8. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 7.

9. A method for manufacturing a display panel, characterized in that, include: A driving layer is formed on one side of a substrate. The driving layer has a pixel driving circuit for driving sub-pixels and a common electrode parallel line. The driving layer is provided with a common electrode connection via that exposes a portion of the common electrode parallel line and a pixel electrode connection via that exposes the output terminal of the pixel driving circuit. A pixel electrode layer is formed on the side of the driving layer away from the substrate. The pixel electrode layer has an overlap structure, a pixel electrode, and a transition structure. The overlap structure is electrically connected to the common electrode in parallel through the common electrode connection via. The transition structure is electrically connected to the pixel driving circuit and the pixel electrode through the pixel electrode connection via. The transition structure includes at least a second transition layer, the second transition layer being made of metal, and the orthographic projection of the second transition layer on the substrate covers at least a portion of the orthographic projection of the pixel electrode connection via on the substrate; wherein forming a pixel electrode layer on the side of the driving layer away from the substrate includes: sequentially forming a pixel electrode layer on the side of the driving layer away from the substrate, the pixel electrode layer including a first conductive oxide pattern layer, a first metal pattern layer, a second metal pattern layer, and a second conductive oxide pattern layer stacked sequentially; wherein the second transition layer is located at at least one of the first metal pattern layer and the second metal pattern layer; the thickness of the first metal pattern layer is greater than the thickness of the second metal pattern layer; the second transition layer is located on the second metal pattern layer, or the second transition layer is located on the first metal pattern layer; An organic light-emitting layer and a common electrode layer are sequentially formed on the side of the pixel electrode layer away from the substrate; the common electrode layer is electrically connected to the overlapping structure.

10. The method for manufacturing a display panel according to claim 9, characterized in that, Forming a pixel electrode layer on the side of the driving layer away from the substrate includes: A first conductive oxide material layer and a first metal material layer are sequentially formed on the side of the driving layer away from the substrate. The first metal material layer is patterned to form a first metal pattern layer, the first metal pattern layer including the bottom metal layer of the second overlapping layer of the overlapping structure; A second metal material layer and a second conductive oxide material layer are sequentially formed on the side of the first metal pattern layer away from the substrate. The second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer are patterned sequentially to form a second conductive oxide pattern layer, a second metal pattern layer, and a first conductive oxide pattern layer, respectively. The second conductive oxide pattern layer includes a third overlap layer of the overlap structure, the second metal pattern layer includes a top metal layer of the second overlap layer of the overlap structure, and the first conductive oxide pattern layer includes a first overlap layer of the overlap structure. The first overlap layer, the bottom metal layer of the second overlap layer, the top metal layer of the second overlap layer, and the third overlap layer are stacked sequentially.

11. The method for manufacturing a display panel according to claim 10, characterized in that, Patterning the first metal material layer to form a first metal pattern layer includes: The first metal material layer is patterned to form a first metal pattern layer, such that the first metal pattern layer includes the bottom metal layer of the second overlapping layer of the overlapping structure and fully exposes the pixel electrode connection via. Patterning the second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer sequentially includes: The second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer are patterned sequentially to form a second conductive oxide pattern layer, a second metal pattern layer, and a first conductive oxide pattern layer, respectively. The second conductive oxide pattern layer includes a third overlapping layer of the overlapping structure and a third transition layer of the transition structure. The second metal pattern layer includes a top metal layer of the second overlapping layer of the overlapping structure and a second transition layer of the transition structure. The first conductive oxide pattern layer includes a first overlapping layer of the overlapping structure and a first transition layer of the transition structure. The first overlapping layer, the bottom metal layer of the second overlapping layer, the top metal layer of the second overlapping layer, and the third overlapping layer are stacked sequentially. The first transition layer, the second transition layer, and the third transition layer are stacked sequentially, and the transition structure is not connected to the first metal pattern layer.

12. The method for manufacturing a display panel according to claim 10, characterized in that, Patterning the first metal material layer to form a first metal pattern layer includes: The first metal material layer is patterned to form a first metal pattern layer, such that the first metal pattern layer includes the bottom metal layer of the second overlapping layer of the overlapping structure and the bottom metal layer of the second transition layer of the transition structure. Patterning the second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer sequentially includes: The second conductive oxide material layer, the second metal material layer, and the first conductive oxide material layer are patterned sequentially to form a second conductive oxide pattern layer, a second metal pattern layer, and a first conductive oxide pattern layer, respectively. The second conductive oxide pattern layer includes a third overlapping layer of the overlapping structure and a third transition layer of the transition structure. The second metal pattern layer includes a top metal layer of the second overlapping layer of the overlapping structure and a top metal layer of the second transition layer of the transition structure. The first conductive oxide pattern layer includes a first overlapping layer of the overlapping structure and a first transition layer of the transition structure. The first overlapping layer, the bottom metal layer of the second overlapping layer, the top metal layer of the second overlapping layer, and the third overlapping layer are stacked sequentially. The first transition layer, the bottom metal layer of the second transition layer, the top metal layer of the second transition layer, and the third transition layer are stacked sequentially.

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