Decomposed switch control path with direct connection scheduling
By employing pass-through interface technology in the server host accelerator system, the transmission paths of data and configuration packets are separated, solving the latency and bandwidth issues in PCIe and CXL topologies, and achieving low-latency, high-bandwidth data transmission and hot-plugging capabilities.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XILINX INC
- Filing Date
- 2021-02-18
- Publication Date
- 2026-06-12
AI Technical Summary
In existing technologies, PCIe and CXL topologies of server host accelerator systems suffer from increased latency, reduced bandwidth, and inefficient switch resources due to their tree-like topology, especially under cache coherence protocols.
By employing a pass-through interface technology, the transmission paths of data packets and configuration packets are separated. Data packets bypass the embedded switch via a direct path, while configuration packets are forwarded through the switch, thus avoiding the impact of the switch's bandwidth, resources, and latency.
It reduces latency, improves bandwidth utilization, and enhances system performance, especially by reducing latency during cache consistency operations, and supports software compatibility for hot-plugging and configuration operations.
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Figure CN115836282B_ABST